Wire harness layout optimization method based on three-dimensional simulation

Abstract

The invention discloses a wire harness layout optimization method based on three-dimensional simulation, relates to the technical field of wire harness layout optimization, and solves the technical problem that layout is unreasonable due to the fact that interference between wire harness layouts is not considered by comprehensively considering various factors. Whether space interference exists in a preliminarily planned route is judged based on a model and an electrical schematic diagram, if interference exists, interference areas and reasons are analyzed and obtained, the number of reasons is judged, single or multiple types of reason signals are generated, optimization information is generated according to the single reason signals and the obtained information, and whether reason interaction exists or not is judged according to the multiple types of reason signals; if yes, generating optimization information, if not, generating a path analysis signal, analyzing the path analysis signal, obtaining all planned paths, calculating the planning priority value of each path, generating optimization information by taking the maximum planning priority value as a standard, properly solving the problem through system analysis, and reducing design change and cost increase.

Description

Technical Field

[0001] The invention relates to the technical field of wiring harness layout optimization, and in particular to a wiring harness layout optimization method based on three-dimensional simulation. Background Art

[0002] With the widespread application of electronic equipment and electrical systems in various products, the layout of wire harnesses, as a key part connecting various electrical components, becomes critical. Traditional wire harness layout design often relies on manual experience. In a complex physical space, it is difficult to fully consider multiple factors such as space utilization, electrical performance, and assembly process. With the trend of product miniaturization and integration, more wire harnesses need to be arranged in a limited physical space. Manual design can easily lead to interference problems between wire harnesses and between wire harnesses and other components, affecting product performance and reliability.

[0003] When using some existing harness layout optimization methods, manual design can easily lead to interference problems between harnesses and between harnesses and other components, affecting product performance and reliability. At the same time, as the complexity of electrical systems increases, the requirements for electrical performance become more stringent, and manual design is difficult to accurately ensure that parameters such as resistance, capacitance, and inductance meet design standards. In addition, manually designed harness layouts may bring many inconveniences to assembly work, reduce assembly efficiency, and increase assembly costs. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a wiring harness layout optimization method based on three-dimensional simulation, which solves the problem of unreasonable layout caused by failure to comprehensively consider the interference between wiring harness layouts due to multiple factors.

[0005] To achieve the above objectives, the present invention is implemented by the following technical solutions: Based on a three-dimensional simulation wiring harness layout optimization method, the method specifically includes the following steps: Determine the physical space and create a 3D model of the physical space through 3D modeling software, while defining the specification parameters of the wiring harness; Based on the three-dimensional model and in combination with the electrical system schematic diagram of the physical space, a preliminary planned route is obtained, and whether there is spatial interference on the preliminary planned route is judged, and a judgment result is generated, including a result of interference or a result of non-interference; Analyze the generated interference results, obtain the interference area and its interference reasons, and judge the number of interference reasons, generate a single reason signal or multiple types of reason signals, analyze the generated single reason signal, obtain the corresponding single reason information, and generate corresponding optimization information based on the single reason information; Analyze the generated multi-type cause signals, obtain the corresponding multi-type cause information, and determine whether there is cause interaction in the multi-type cause information. If so, generate corresponding optimization information based on the multi-type cause information as a standard, otherwise generate a path analysis signal; Analyze the generated path analysis signal, obtain all planned routes, and calculate the space utilization value according to the effective occupied space volume of the planned path. Analyze the satisfied quantity of resistance, capacitance and inductance to calculate the parameter ratio value, assign the operation convenience to obtain the assembly process value, and calculate the planning priority value of the planned path. According to the interference situation of the planned paths, the interference paths and non-interference paths are classified, and the interference paths corresponding to the interference reasons less than the preset values ​​are selected as the paths to be analyzed. At the same time, the maximum planning priority value among the paths to be analyzed and the non-interference paths is selected as the standard to generate optimization information.

[0006] As a further solution of the present invention, the specific method of generating the judgment result is: Based on the obtained three-dimensional model, the preliminary planned route is obtained in combination with the electrical system schematic diagram of the physical space, and it is determined whether there is spatial interference in the preliminary planned route. The preliminary planned route and the physical space are obtained, and the models of the wiring harness and surrounding components in the preliminary planned route are checked. If there is interference between the wiring harness and other objects, an interference result is generated. Otherwise, if there is no interference between the wiring harness and other objects, a non-interference result is generated.

[0007] As a further solution of the present invention, the specific method of analyzing the generated interference results and generating corresponding optimization information based on the single cause information is as follows: Obtain the corresponding interference area and its corresponding interference cause in the preliminary planned path, determine the number of interference causes, generate a single cause signal or multiple types of cause signals, and analyze the two; Analyze the generated single cause signal to obtain corresponding single cause information, and generate corresponding optimization information based on the single cause information; As a further solution of the present invention, the specific method of analyzing the generated multi-type cause signals is: Obtain the corresponding multi-type cause information, and then determine whether there is any cause interaction in the multi-type cause information. If so, generate corresponding optimization information based on the multi-type cause information. Otherwise, re-plan and analyze the preliminary planned path and generate a path analysis signal.

[0008] As a further solution of the present invention, the specific method of calculating the space utilization value according to the effective occupied space volume of the planned path is: Get the volume Vz of the physical space, and get the effective occupied space volume Vi corresponding to the planned path i, and calculate it according to the formula Calculate the space utilization rate corresponding to the planned path i, and then quantify the space utilization rate to obtain the corresponding space utilization value.

[0009] As a further solution of the present invention, the specific method of analyzing and calculating the parameter proportion value of the satisfied quantity of resistance, capacitance and inductance is: According to the formula The resistance R corresponding to the planned path i is calculated, where l is the length of the planned path, S is the cross-sectional area of ​​the harness, is the resistivity; According to the formula The capacitance C corresponding to the planned path i is calculated, where is the dielectric constant, S x is the area facing the plates, and d is the distance between the plates; According to the formula The inductance L corresponding to the planned path i is calculated, where Magnetic permeability, l is the length of the wire, D is the distance between the two wires, and r is the radius of the wire; The obtained resistance, capacitance and inductance are compared with the corresponding design standards respectively, and the number of parameters that meet the design standards is determined. At the same time, the corresponding parameter proportion values ​​are calculated and recorded as electrical performance values.

[0010] As a further solution of the present invention, the specific method of calculating the planning priority value of the planned path is: According to the formula The planning priority value Q corresponding to the planned path is calculated, where K is the space utilization value, H is the electrical performance value, and A is the assembly process value. , and are the weight coefficients corresponding to the space utilization value, electrical performance value and assembly process value, respectively, and + + =1; Similarly, the planning priority value Q of all planned paths i is calculated and recorded as Qi.

[0011] As a further solution of the present invention, the specific method of selecting the maximum planning priority value in the path to be analyzed and the non-interference path as the standard to generate the optimization information is: The classified interference path is recorded as a, and a=1, 2, ..., n, where n represents the number of interference paths. Then, the interference cause corresponding to the interference path a is obtained, and the interference path corresponding to the interference cause less than the preset value is screened and recorded as the path to be analyzed. Then, the non-interference path is obtained and labeled as b, and b=1, 2, ..., m, where m represents the number of non-interference paths. At the same time, all the paths to be analyzed are obtained, and the path with the largest planning priority value is selected as the standard based on the two, and the optimization information is generated.

[0012] The present invention provides a wiring harness layout optimization method based on three-dimensional simulation. Compared with the prior art, it has the following beneficial effects: The present invention can comprehensively and meticulously check the interference between the wiring harness and the surrounding component models in the preliminary planned route by using professional 3D modeling and analysis tools, which improves the accuracy and efficiency of interference detection compared to traditional manual judgment. In the case of interference, by systematically analyzing the interference area and cause, effective optimization measures can be put forward in a targeted manner. Whether the interference is caused by a single reason or multiple types of reasons, it can be properly resolved, reducing design changes and cost increases caused by interference.

[0013] The electrical performance of the planned path is deeply analyzed, and parameters such as resistance, capacitance, and inductance are calculated through precise formulas. These parameters are then strictly compared with the design standards to detect potential electrical problems in advance and ensure the stable operation of the electrical system. Compared with traditional empirical judgment, this quantitative analysis method can more accurately meet electrical performance requirements and improve the electrical reliability of the product.

[0014] From the perspective of operational convenience, the assembly processability of the planned path is quantitatively assigned according to the volume of the operating space, making the evaluation of the assembly process more scientific and objective. The wiring harness layout designed in this way can improve assembly efficiency, reduce assembly difficulty, reduce manual operation errors, and thus reduce production costs.

[0015] A mathematical model that comprehensively considers space utilization, electrical performance, and assembly process values ​​was established, and multiple groups of planned paths were sorted and screened by calculating planning priority values. This multi-factor comprehensive consideration method can optimize the wiring harness layout plan as a whole, and the selected optimal path can achieve a balance in terms of space utilization, electrical performance, and assembly process, thereby improving the overall performance and quality of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a diagram of the steps of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] For example, see Figure 1 The present application provides a wiring harness layout optimization method based on three-dimensional simulation, which specifically includes the following steps: Step S1, first determine the scope of the physical space, and create a three-dimensional model of the entire physical space, and here the model is created through professional three-dimensional modeling software, such as CATIA, UG, SolidWorks, etc., and the specification parameters of the wire harness are defined, and the specification parameters here include the diameter, quantity, material of the wire, thickness and characteristics of the insulation layer, etc.

[0019] Step S2: Based on the constructed accurate three-dimensional model, closely associate the electrical system schematic diagram in the physical space to obtain the preliminary planned route. In this process, it is necessary to strictly judge whether there is spatial interference in the preliminary planned route and generate corresponding accurate judgment results. The judgment results are clearly divided into two categories: interference results and non-interference results. The specific judgment method is as follows: Comprehensively obtain the preliminary planned route and the physical space information in which it is located, use professional 3D analysis tools, and conduct meticulous inspections on the models of the wiring harness and surrounding components in the preliminary planned route. Take the automobile wiring harness layout as an example. In the 3D model of the automobile engine compartment, the preliminary planned wiring harness is connected from the battery to various electrical devices, such as the engine control unit, headlights, etc. When the planned route is checked for interference, if it is found that the wiring harness overlaps with a protruding component of the engine, such as the intake manifold, in spatial position, it indicates that there is interference between the wiring harness and other objects. At this time, an interference result should be generated immediately. On the contrary, if after a comprehensive inspection, the wiring harness and all components in the engine compartment, including the engine body, radiator, various pipelines, etc., maintain a safe distance in spatial position and there is no overlapping part, then a non-interference result is generated, and the generated non-interference result is not processed.

[0020] Step S3, when the interference result is generated, it is necessary to carry out systematic and in-depth analysis. First, with the help of professional 3D model analysis software, the specific area where interference occurs in the preliminary planned path is accurately located. Taking the car engine compartment as an example, in this complex three-dimensional space, if a section of the wiring harness connecting the battery to the engine control unit is found to be interfering, the spatial range where this section of the wiring harness is located is the interference area.

[0021] Next, thoroughly investigate the reasons that caused the interference in this interference area. There may be various reasons for interference, such as unreasonable design of the wiring harness itself, which fails to effectively avoid surrounding components in a limited space; or because the actual installation position of some components in the engine compartment deviates from the original design, occupying the space originally planned for the wiring harness; or the selected wiring harness is too thick, exceeding the capacity of the reserved space, etc. After clarifying all the reasons for interference, carefully count the number of reasons. If there is only one reason causing interference, the system will generate a single reason signal; If there are two or more different reasons causing interference, multiple types of cause signals are generated. After that, targeted analysis and optimization measures are implemented for the two different types of signals respectively.

[0022] When a single cause signal is received, the signal is analyzed in depth to obtain accurate and detailed single cause information. Assume that in the wiring harness layout of the automobile engine compartment, the single cause signal shows that the interference is caused by a certain section of the wiring harness running directly through the engine's intake manifold installation area. Based on this single cause information, corresponding optimization information can be formulated, such as re-planning the wiring harness path so that it is arranged along the wire trough or bracket at the edge of the engine compartment to avoid the intake manifold. If multiple types of cause signals are generated, further careful analysis is required to grasp the comprehensive multiple types of cause information, and then determine whether there is cause interaction between these multiple types of cause information. The so-called cause interaction refers to the existence of intersection correlation between different interference causes.

[0023] For example, in the engine compartment of a car, after analyzing the multi-type cause information, it was found that, on the one hand, some wire harnesses were concentrated in a small space due to poor early design; on the other hand, in order to meet the power demand of the newly added electronic equipment, thicker wire harnesses were selected, and these thickened wire harnesses happened to be concentrated in the area where the early design was poor, resulting in serious lack of space and interference, which is a cause interaction. In response to this situation, the corresponding optimization information is generated based on the multi-type cause information, which may include re-planning the direction of the wire harness, dispersing the concentrated wire harnesses, and re-evaluating the wire harness specifications. On the premise of meeting the electrical performance requirements, a more suitable wire harness is selected to relieve space pressure. If it is judged that there is no cause interaction in the multi-type cause information, for example, part of the interference is due to the addition of a large cooling auxiliary device in the engine compartment, which changes the original space layout; the other part is that the position design of several wire harness fixing points is unreasonable, resulting in the inability to effectively fix the wire harness during installation and easy to collide with surrounding components, but there is no direct correlation between the two reasons. At this point, it is necessary to comprehensively re-plan and analyze the entire preliminary planned path and generate a path analysis signal to provide a strong basis for the subsequent redesign of a more reasonable wiring harness layout solution that is more suitable for the current complex environment of the engine compartment.

[0024] Step S4, analyzing the generated path analysis signal, generating multiple groups of planned paths based on the physical space and in combination with the schematic diagram of the electrical system, and labeling them as i, and i=1, 2, ..., j, where j represents the number of planned routes, and the generation method here divides the entire system into different functional areas according to the function and location of the electrical equipment. In each area, first preliminarily determine the basic path of the wiring harness from the power supply to each electrical device, and try to make the equipment connection lines in the same functional area relatively concentrated, and then separately analyze the space utilization, electrical performance and assembly processability corresponding to the planned route i; The specific method of analyzing the space utilization rate of the planned path i is to obtain the space volume Vz of the physical space and the effective occupied space volume Vi corresponding to the planned path i. The effective occupied space volume is obtained through the specification parameters in the three-dimensional model and is calculated according to the formula Calculate the space utilization rate corresponding to the planned path i, and then quantify the space utilization rate to obtain the corresponding space utilization value. The quantization process here specifically converts the obtained percentage to obtain the corresponding value. For example, if the calculated space utilization rate is 80%, the space utilization value after quantization is 0.8.

[0025] The specific method for analyzing the electrical performance of the planned path i is to calculate the resistance, capacitance and inductance corresponding to the planned path i respectively. The method for calculating the resistance is as follows: The resistance R corresponding to the planned path i is calculated, where l is the length of the planned path, S is the cross-sectional area of ​​the harness, is the resistivity; The way to calculate the capacitance is, according to the formula The capacitance C corresponding to the planned path i is calculated, where is the dielectric constant, S x is the area facing the plates, and d is the distance between the plates; The inductance is calculated according to the formula The inductance L corresponding to the planned path i is calculated, where Magnetic permeability, l is the length of the wire, D is the distance between the two wires, and r is the radius of the wire; The obtained resistance, capacitance and inductance are compared with the corresponding design standards respectively, and the design standards here correspond to the resistance, capacitance and inductance, and the number of parameters that meet the design standards is determined, and the corresponding parameter proportion is calculated, and the proportion is recorded as the electrical performance value, and the parameter proportion here is specifically expressed as the proportion of qualified parameters. For example, after comparison, the resistance and capacitance are the same as the design standard, and the parameter proportion obtained by further calculation is 2 / 3.

[0026] The specific method for analyzing the assembly processability of the planned path i is to assign a value to the operational convenience of the planned path i to obtain the assembly process value, and the method for assigning the operational convenience is to obtain the corresponding operating space and perform corresponding rating processing based on the volume of the operating space. The rating levels include narrow (the operating space volume is less than 0.05 cubic meters), normal (the operating space volume is between 0.05 cubic meters and 0.2 cubic meters), and wide (the operating space volume is greater than 0.2 cubic meters), and the values ​​are assigned as 1, 2, and 3 respectively.

[0027] Then substitute the obtained space utilization value, electrical performance value and assembly process value into the formula The planning priority value Q corresponding to the planned path is calculated, where K is the space utilization value of the planned path, H is the electrical performance value of the planned path, and A is the assembly process value of the planned path. , and are the weight coefficients corresponding to the space utilization value, electrical performance value and assembly process value, respectively, and + + =1, for example, the electrical performance weight is 0.4, the space utilization weight is 0.3, and the assembly process weight is 0.3. Similarly, the planning priority value Q of all planned paths i is calculated and recorded as Qi, and sorted from large to small according to the value; the specific planning priority value Q is between 0 and 1, and the closer the value is to 1, the more reasonable the planned path is.

[0028] Step S5, obtaining the sorted planned paths, performing interference analysis on the planned paths, and classifying them into interference paths and non-interference paths, and analyzing the two in combination; The interference path after classification is obtained and recorded as a, and a=1, 2, ..., n, where n represents the number of interference paths. Then, the interference cause corresponding to the interference path a is obtained, and the interference path corresponding to the interference cause less than the preset value is screened, and the specific value of the preset value is set by the operator. For the interference path whose interference cause is greater than the preset value, it is directly eliminated and recorded as the path to be analyzed. Then, the non-interference path is obtained and labeled as b, and b=1, 2, ..., m, where m represents the number of non-interference paths. At the same time, all the paths to be analyzed are obtained, and the path with the largest planning priority value is selected as the standard based on the two, and optimization information is generated.

[0029] Embodiment 2: This embodiment is implemented on the basis of Embodiment 1, and the difference from Embodiment 1 is as follows: In step S4, the space utilization rate of the planned path i can also be calculated by projecting the area. The specific calculation formula is: Specifically, the wiring harness and layout space are projected onto a plane. For example, in circuit board routing, the wiring harness and the wiring area of ​​the circuit board are usually projected onto the plane of the circuit board. The area of ​​the wiring harness on the projection plane can be obtained by measuring or calculating the projection shape of the wiring harness, and the area of ​​the layout space on the projection plane is the area of ​​the circuit board that can be used for routing.

[0030] Embodiment 3: This embodiment is implemented on the basis of Embodiment 1, and the difference between this embodiment and Embodiment 1 and Embodiment 2 is as follows: In step S4, the space utilization rate of the planned path i can also be calculated by the total volume method. The specific calculation formula is: Specifically, the total volume of the wire harness refers to the sum of the volumes occupied by all wire harnesses in three-dimensional space, which can be calculated by measuring or modeling the shape and size of the wire harness. The total volume of the layout space refers to the volume of the three-dimensional space reserved for the wire harness, such as the space volume inside a cabinet for wiring, the space volume in the engine compartment of a car that can be used to arrange the wire harness, etc.

[0031] Embodiment 4, as the fourth embodiment of the present invention, focuses on combining the implementation processes of Embodiment 1, Embodiment 2 and Embodiment 3 for implementation.

[0032] Some of the data in the above formulas are calculated by taking their numerical values, and are not substituted into parameter units for calculation. At the same time, the contents not described in detail in this specification belong to the existing technologies known to those skilled in the art.

[0033] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A wiring harness layout optimization method based on three-dimensional simulation, characterized in that: The method specifically comprises the following steps: Determine the physical space and create a 3D model of the physical space through 3D modeling software, while defining the specification parameters of the wiring harness; Based on the three-dimensional model and in combination with the electrical system schematic diagram of the physical space, a preliminary planned route is obtained, and whether there is spatial interference on the preliminary planned route is judged, and a judgment result is generated, including a result of interference or a result of non-interference; Analyze the generated interference results, obtain the interference area and its interference reasons, and judge the number of interference reasons, generate a single reason signal or multiple types of reason signals, analyze the generated single reason signal, obtain the corresponding single reason information, and generate corresponding optimization information based on the single reason information; Analyze the generated multi-type cause signals, obtain the corresponding multi-type cause information, and determine whether there is cause interaction in the multi-type cause information. If so, generate corresponding optimization information based on the multi-type cause information as a standard, otherwise generate a path analysis signal; Analyze the generated path analysis signal, obtain all planned routes, and calculate the space utilization value according to the effective occupied space volume of the planned path. Analyze the satisfied quantity of resistance, capacitance and inductance to calculate the parameter ratio value, assign the operation convenience to obtain the assembly process value, and calculate the planning priority value of the planned path. According to the interference situation of the planned paths, the interference paths and non-interference paths are classified, and the interference paths corresponding to the interference reasons less than the preset values ​​are selected as the paths to be analyzed. At the same time, the maximum planning priority value among the paths to be analyzed and the non-interference paths is selected as the standard to generate optimization information.

2. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of generating the judgment result is: Based on the obtained three-dimensional model, the preliminary planned route is obtained in combination with the electrical system schematic diagram of the physical space, and it is determined whether there is spatial interference in the preliminary planned route. The preliminary planned route and the physical space are obtained, and the models of the wiring harness and surrounding components in the preliminary planned route are checked. If there is interference between the wiring harness and other objects, an interference result is generated. Otherwise, if there is no interference between the wiring harness and other objects, a non-interference result is generated.

3. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1 is characterized in that: The specific method of analyzing the generated interference results and generating corresponding optimization information based on the single cause information is as follows: Obtain the corresponding interference area and its corresponding interference cause in the preliminary planned path, determine the number of interference causes, generate a single cause signal or multiple types of cause signals, and analyze the two; The generated single-cause signal is analyzed to obtain corresponding single-cause information, and corresponding optimization information is generated based on the single-cause information.

4. The wiring harness layout optimization method based on three-dimensional simulation according to claim 3 is characterized in that: The specific method of analyzing the generated multi-type cause signals is as follows: Obtain the corresponding multi-type cause information, and then determine whether there is any cause interaction in the multi-type cause information. If so, generate corresponding optimization information based on the multi-type cause information. Otherwise, re-plan and analyze the preliminary planned path and generate a path analysis signal.

5. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of calculating the space utilization value according to the effective occupied space volume of the planned path is: Get the volume Vz of the physical space, and get the effective occupied space volume Vi corresponding to the planned path i, and calculate it according to the formula Calculate the space utilization rate corresponding to the planned path i, and then quantify the space utilization rate to obtain the corresponding space utilization value.

6. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of analyzing and calculating the parameter proportion values ​​of the satisfied quantities of resistance, capacitance and inductance is as follows: According to the formula The resistance R corresponding to the planned path i is calculated, where l is the length of the planned path, S is the cross-sectional area of ​​the harness, is the resistivity; According to the formula The capacitance C corresponding to the planned path i is calculated, where is the dielectric constant, S x is the area facing the plates, and d is the distance between the plates; According to the formula The inductance L corresponding to the planned path i is calculated, where Magnetic permeability, l is the length of the wire, D is the distance between the two wires, and r is the radius of the wire; The obtained resistance, capacitance and inductance are compared with the corresponding design standards respectively, and the number of parameters that meet the design standards is determined. At the same time, the corresponding parameter proportion values ​​are calculated and recorded as electrical performance values.

7. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1 is characterized in that: The specific method of calculating the planning priority value of the planned path is: According to the formula The planning priority value Q corresponding to the planned path is calculated, where K is the space utilization value, H is the electrical performance value, and A is the assembly process value. , and are the weight coefficients corresponding to the space utilization value, electrical performance value and assembly process value, respectively, and + + =1; Similarly, the planning priority value Q of all planned paths i is calculated and recorded as Qi.

8. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of selecting the maximum planning priority value in the path to be analyzed and the non-interference path as the standard to generate the optimization information is: The classified interference path is recorded as a, and a=1, 2, ..., n, where n represents the number of interference paths. Then, the interference cause corresponding to the interference path a is obtained, and the interference path corresponding to the interference cause less than the preset value is screened and recorded as the path to be analyzed. Then, the non-interference path is obtained and labeled as b, and b=1, 2, ..., m, where m represents the number of non-interference paths. At the same time, all the paths to be analyzed are obtained, and the path with the largest planning priority value is selected as the standard based on the two, and the optimization information is generated.

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