Gate driving circuit and its driving method, display device

Abstract

This application provides a gate driving circuit and its driving method, as well as a display device. The gate driving circuit includes: a node control module configured to control the potentials of a first node and a second node according to a clock signal and an input signal; an output control module configured to provide the voltage of the first node or a first voltage signal to a third node and to a fourth node according to a control signal; and an output module configured to alternately output a first voltage signal and a second voltage signal according to the potentials of the second, third, and fourth nodes. The technical solution provided by this application can improve the stability of the gate driving circuit output and reduce problems such as uneven display caused by output voltage fluctuations.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and in particular to a gate driving circuit and its driving method, and a display device. Background Technology

[0002] In today's rapidly developing display technology, the gate drive circuit, as a core component of display devices such as Active Matrix Organic Light-Emitting Diode (AMOLED) displays, is crucial for ensuring display uniformity through its output stability. However, current display devices suffer from unstable output voltage in their gate drive circuits, which can easily lead to noticeable uneven brightness and color inconsistencies on the display panel. This not only impairs the user's visual experience but also limits the further application of display technology in the field of high-precision displays. Summary of the Invention

[0003] In view of this, the embodiments of this application aim to provide a gate driving circuit and its driving method, and a display device, so as to solve the problem of uneven display caused by unstable output voltage of the gate driving circuit.

[0004] The first aspect of this application provides a gate driving circuit, including: a node control module configured to control the potentials of a first node and a second node according to a clock signal and an input signal; an output control module configured to provide the voltage of the first node or a first voltage signal to a third node and to a fourth node according to a control signal; and an output module configured to alternately output a first voltage signal and a second voltage signal according to the potentials of the second node, the third node and the fourth node.

[0005] In one embodiment, the output module includes a first output unit and a second output unit. The first output unit is configured to output a second voltage signal based on the potential of a third node, and the second output unit is configured to output a second voltage signal based on the potential of a fourth node. Optionally, the first output unit and the second output unit alternately output the second voltage signal. Optionally, the first output unit outputs the second voltage signal during at least a portion of a first time period, and the second output unit outputs the second voltage signal during at least a portion of a second time period. Optionally, the first output unit includes a first transistor, the control electrode of which is connected to the third node, the first electrode of which is connected to the second voltage signal, and the second electrode of which is connected to the gate signal output terminal. The second output unit includes a second transistor, the control electrode of which is connected to the fourth node, the first electrode of which is connected to the second voltage signal, and the second electrode of which is connected to the gate signal output terminal. Optionally, the first transistor and the second transistor alternately conduct.

[0006] In one embodiment, the output module further includes a third output unit configured to output a first voltage signal according to the potential of the second node; optionally, the third output unit includes a third transistor, the control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first voltage signal, and the second electrode of the third transistor is connected to the gate signal output terminal; optionally, the first time period includes a first sub-time period and a second sub-time period, in which the third output unit outputs the first voltage signal to the gate signal output terminal, and in the second sub-time period, the first output unit outputs a second voltage signal to the gate signal output terminal; the second time period includes a third sub-time period and a fourth sub-time period, in which the third output unit outputs the first voltage signal to the gate signal output terminal, and in the fourth sub-time period, the second output unit outputs... The second voltage signal is sent to the gate signal output terminal; optionally, the first time period and the second time period are alternately set; optionally, in the first sub-time period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the second sub-time period, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned off; in the third sub-time period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the fourth sub-time period, the first transistor is turned off, the second transistor is turned on, and the third transistor is turned off; optionally, one of the first voltage signal and the second voltage signal is at a low potential, and the other is at a high potential; optionally, the first voltage signal is at a high potential, and the second voltage signal is at a low potential; optionally, the gate drive circuit further includes a third capacitor, the two ends of which are respectively connected to the control electrode of the third transistor and the first electrode of the third transistor.

[0007] In one embodiment, the output control module includes a first control unit and a second control unit, and the control signals include a first control signal and a second control signal. The first and second control units are configured to control the first output unit and the second output unit to alternately output a second voltage signal according to the first control signal and the second control signal. Optionally, the first control unit is configured to provide the voltage of the first node to the third node according to the first control signal and to provide the first voltage signal to the third node according to the second control signal; the second control unit is configured to provide the voltage of the first node to the fourth node according to the second control signal and to provide the first voltage signal to the fourth node according to the first control signal. Optionally, in the first time period and the second time period, one of the first control signal and the second control signal is at a high potential and the other is at a low potential; one of the potentials of the first control signal in the first time period and the second time period is at a high potential and the other is at a low potential; one of the potentials of the second control signal in the first time period and the second time period is at a high potential and the other is at a low potential.

[0008] In one embodiment, the first control unit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is connected to a first control signal, and the first electrode of the fourth transistor is connected to a first node. The control electrode of the fifth transistor is connected to a second control signal, and the first electrode of the fifth transistor is connected to a first voltage signal. The second electrodes of the fourth and fifth transistors are connected to a third node. The second control unit includes a sixth transistor and a seventh transistor. The control electrode of the sixth transistor is connected to the second control signal, and the first electrode of the sixth transistor is connected to the first node. The control electrode of the seventh transistor is connected to the first control signal, and the first electrode of the seventh transistor is connected to the first voltage signal. The second electrodes of the sixth and seventh transistors are connected to a fourth node. Optionally, in a first time period, the fourth transistor is turned on, the fifth transistor is turned off, the sixth transistor is turned off, and the seventh transistor is turned on; in a second time period, the fourth transistor is turned off, the fifth transistor is turned on, the sixth transistor is turned on, and the seventh transistor is turned off.

[0009] In one embodiment, the node control module includes an input unit, and the clock signal includes a first clock signal. The input unit is configured to provide an input signal to a first node according to the first clock signal. Optionally, the input unit includes an eighth transistor, with the first terminal of the eighth transistor connected to the input signal, the control terminal of the eighth transistor connected to the first clock signal, and the second terminal of the eighth transistor connected to the first node.

[0010] Optionally, the input unit also includes a ninth transistor, the second terminal of the eighth transistor and the first terminal of the ninth transistor are connected, the control terminal of the ninth transistor is connected to a second voltage signal, and the second terminal of the ninth transistor is connected to the first node.

[0011] In one embodiment, the node control module further includes a third control unit.

[0012] The third control unit and the input unit are connected to the first node. The third control unit is configured to provide a first voltage signal to the second node according to the potential of the first node.

[0013] Alternatively, the third control unit and the input unit are connected to the fifth node, the input unit is further configured to provide an input signal to the fifth node according to the first clock signal, and the third control unit is configured to provide a first voltage signal to the second node according to the potential of the fifth node; optionally, the third control unit includes a tenth transistor, the control electrode of the tenth transistor is connected to the fifth node or the first node, the first electrode of the tenth transistor is connected to the first voltage signal, and the second electrode of the tenth transistor is connected to the second node; optionally, the second electrode of the eighth transistor and the first electrode of the ninth transistor are connected to the fifth node.

[0014] In one embodiment, the node control module further includes a fourth control unit, and the clock signal further includes a second clock signal. The fourth control unit is configured to control the potential of the first node according to the input signal, the first clock signal, and the second clock signal. Optionally, the fourth control unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The first terminal of the eleventh transistor is connected to a first voltage signal, the second terminals of the eleventh transistor and the twelfth transistor are connected, the first terminal of the twelfth transistor is connected to a second clock signal, the control terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor, the second terminal of the thirteenth transistor is connected to the first node, the first terminal of the thirteenth transistor and the control terminal of the thirteenth transistor are connected to the second terminal of the fourteenth transistor, the control terminal of the fourteenth transistor is connected to a second voltage signal, the first terminal of the fourteenth transistor and the second terminal of the fifteenth transistor are connected, the control terminal of the fifteenth transistor is connected to the first clock signal, and the first terminal of the fifteenth transistor is connected to an input signal. Optionally, the fourth control unit further includes a first capacitor, the two ends of which are respectively connected to the control terminal of the twelfth transistor and the second terminal of the twelfth transistor. Optionally, the node control module further includes a fifth control unit, configured to control the potential of the second node according to a first clock signal and a second clock signal; optionally, the fifth control unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor, wherein the first terminal of the sixteenth transistor is connected to a second voltage signal, the second terminal of the sixteenth transistor and the first terminal of the seventeenth transistor are connected to the control terminal of the eleventh transistor, the control terminal of the sixteenth transistor is connected to the first clock signal, the control terminal of the seventeenth transistor is connected to the second voltage signal, the second terminal of the seventeenth transistor is connected to the control terminal of the eighteenth transistor, the first terminal of the eighteenth transistor is connected to the second clock signal, the second terminal of the eighteenth transistor is connected to the first terminal of the nineteenth transistor, the second terminal of the nineteenth transistor is connected to the second node, the control terminal of the nineteenth transistor is connected to the second clock signal, the first terminal of the twentieth transistor is connected to the first clock signal, the control terminal of the twentieth transistor is connected to the second terminal of the eighth transistor, and the second terminal of the twentieth transistor is connected to the second terminal of the sixteenth transistor; optionally, the fifth control unit further includes a second capacitor, the two ends of which are respectively connected to the control terminal of the eighteenth transistor and the second terminal of the eighteenth transistor; optionally, the first clock signal and the second clock signal have the same frequency but different phases.

[0015] A second aspect of this application provides a driving method for a gate driving circuit, applicable to the gate driving circuit mentioned in any of the above embodiments. The driving method includes: a first time period, inputting a first control signal in a first level state and a second control signal in a second level state to an output control module, so that a first control unit provides a voltage of a first node to a third node according to the first control signal, and a second control unit provides a first voltage signal to a fourth node according to the first control signal; a second time period, inputting a first control signal in a second level state and a second control signal in a first level state to the output control module, so that the first control unit provides a first voltage signal to the third node according to the second control signal, and the second control unit provides a voltage of the first node to the fourth node according to the second control signal.

[0016] A third aspect of this application provides a display device, including a gate driving circuit as mentioned in any of the above embodiments.

[0017] The technical solution provided in this application, by setting up an output control module, controls the transmission of the first node voltage according to the control signal, enabling the output module to alternately output a second voltage signal based on the potentials of the third and fourth nodes. This configuration avoids the problem in related technologies where the output transistor is subjected to negative bias stress over a long period, causing threshold voltage drift and resulting in unstable output voltage. Therefore, the technical solution provided in this application can improve the stability of the gate drive circuit output and reduce problems such as uneven display caused by output voltage fluctuations.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The diagram shown is a schematic diagram of the gate driving circuit provided in an embodiment of this application.

[0021] Figure 2 The figure shown is a simulation waveform diagram of a gate driving circuit provided in an embodiment of this application.

[0022] Figure 3 The diagram shown is a schematic diagram of the gate drive circuit provided in another embodiment of this application.

[0023] Figure 4 The diagram shown is a schematic diagram of the gate drive circuit provided in another embodiment of this application.

[0024] Figure 5 The diagram shown is a schematic diagram of the gate drive circuit provided in another embodiment of this application.

[0025] Figure 6 The diagram shown is a schematic diagram of the gate drive circuit provided in another embodiment of this application.

[0026] Figure 7 The diagram shown is a schematic diagram of the gate drive circuit provided in another embodiment of this application.

[0027] Figure 8 The diagram shown is a schematic flowchart of a control method for a gate drive circuit provided in an embodiment of this application.

[0028] Figure 9 The figure shown is a simulation waveform diagram of a gate drive circuit provided in another embodiment of this application. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Connections may include direct or indirect connections.

[0031] As mentioned in the background section, AMOLED display devices utilize gate driver integrated circuits to drive the switching devices in the pixels. However, the inventors discovered that due to the circuit structure, a "step" appears during the low-level output process, the height of which is related to the threshold voltage of the output transistor. Because the output transistor is subjected to negative bias stress for a long time, its threshold voltage drifts, causing output voltage instability and resulting in uneven display.

[0032] In view of this, the embodiments of this application aim to provide a gate driving circuit and its driving method, and a display device, so as to solve the problem of uneven display caused by unstable output voltage of the gate driving circuit.

[0033] Figure 1 The diagram shown is a schematic representation of a gate drive circuit according to an embodiment of this application. Figure 1 As shown, the gate drive circuit includes: a node control module 101 configured to control the potentials of the first node N1 and the second node N2 according to a clock signal and an input signal EIN; an output control module 102 configured to provide the voltage of the first node N1 or a first voltage signal VGH to the third node N3 and to the fourth node N4 according to a control signal; and an output module 103 configured to alternately output the first voltage signal VGH and the second voltage signal VGL according to the potentials of the second node N2, the third node N3 and the fourth node N4.

[0034] Specifically, the node control module 101 is used to control the potentials of the first node N1 and the second node N2 according to the clock signal and the input signal EIN, so as to provide the output module 103 with the turn-on (or turn-off) voltage. For example, Figure 2 The image shown is a simulation waveform diagram of a gate drive circuit provided in an embodiment of this application. See also... Figure 1 and Figure 2 The input signal EIN can be either a gate high voltage (VGH) or a gate low voltage (VGL). The first voltage signal VGH is the gate high voltage, and the second voltage signal VGL is the gate low voltage.

[0035] Output module 103 alternately outputs a first voltage signal VGH and a second voltage signal VGL based on the potentials of the second node N2, the third node N3, and the fourth node N4. However, in related technologies, output module 103 suffers from unstable output voltage when outputting the second voltage signal VGL. This solution includes an output control module 102 connected to output module 103 at the third node N3 and the fourth node N4. Output control module 102 controls the transmission of the voltage of the first node N1 and the first voltage signal VGH according to a control signal. For example, during certain time periods, such as at least a portion of the first time period, output control module 102 transmits the voltage of the first node N1 to the third node N3 and simultaneously transmits the first voltage signal VGH to the fourth node N4 according to the control signal. Similarly, during certain time periods, such as at least a portion of the second time period, output control module 102 transmits the voltage of the first node N1 to the fourth node N4 and simultaneously transmits the first voltage signal VGH to the third node N3 according to the control signal. For example, when the third node N3 receives the voltage from the first node N1, the fourth node N4 receives the first voltage signal VGH, and the output module 103 outputs the second voltage signal VGL according to the potential of the third node N3. When the fourth node N4 receives the voltage from the first node N1, the third node N3 receives the first voltage signal VGH, and the output module 103 outputs the second voltage signal VGL according to the potential of the fourth node N4. By controlling the control period of the control signals (e.g., including the first control signal XT1 and the second control signal XT2), the output module 103 can be controlled to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4.

[0036] The technical solution of this embodiment, by setting an output control module 102 to control the transmission of the voltage of the first node N1 according to the control signal, enables the output module 103 to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4. This configuration avoids the problem in related technologies where the output transistor is subjected to negative bias stress over a long period, causing threshold voltage drift and resulting in unstable output voltage. Therefore, the technical solution provided by this application embodiment can improve the stability of the gate drive circuit output and reduce problems such as uneven display caused by output voltage fluctuations.

[0037] Figure 3 The diagram shown is a schematic representation of a gate drive circuit according to another embodiment of this application. Figure 3As shown, the output module 103 includes a first output unit 1031 and a second output unit 1032. The first output unit 1031 is configured to output a second voltage signal VGL based on the potential of the third node N3, and the second output unit 1032 is configured to output a second voltage signal VGL based on the potential of the fourth node N4. Optionally, the first output unit 1031 and the second output unit 1032 alternately output the second voltage signal VGL; or, the first output unit 1031 and the second output unit 1032 output the second voltage signal VGL in a time-sharing manner. Optionally, the first output unit 1031 outputs the second voltage signal VGL during at least a portion of the first time period t1, and the second output unit 1032 outputs the second voltage signal VGL during at least a portion of the second time period t2. The first output unit 1031 includes a first transistor T1, the control electrode of which is connected to a third node N3. The first electrode of the first transistor T1 is connected to a second voltage signal VGL and / or to a second power supply line (capable of transmitting the second voltage signal VGL). The second electrode of the first transistor T1 is connected to the gate signal output terminal EM_OUT. The second output unit 1032 includes a second transistor T2, the control electrode of which is connected to a fourth node N4. The first electrode of the second transistor T2 is connected to a second voltage signal VGL and / or to a second power supply line. The second electrode of the second transistor T2 is connected to the gate signal output terminal EM_OUT. Optionally, the first transistor T1 and the second transistor T2 are alternately turned on, or the first transistor T1 and the second transistor T2 are turned on in a time-division multiplexing manner. For example, the first transistor T1 is turned on during at least a portion of the first time period t1, and the second transistor T2 is turned on during at least a portion of the second time period t2.

[0038] For example, the first transistor T1 and the second transistor T2 have the same channel type, such as the first transistor T1 and the second transistor T2 being N-type transistors, or the first transistor T1 and the second transistor T2 being P-type transistors.

[0039] Specifically, the gate signal output terminal EM_OUT of the gate drive circuit can be used to output the gate drive signal. By controlling the control period of the control signals (e.g., including the first control signal XT1 and the second control signal XT2), the output control module 102 can control the first output unit 1031 and the second output unit 1032 to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4, respectively. For example, the first output unit 1031 outputs the second voltage signal VGL during at least a portion of the first time period t1, and the second output unit 1032 outputs the second voltage signal VGL during at least a portion of the second time period t2. For example, the first time period t1 may be one or more, the second time period t2 may be one or more, and the first time period t1 and the second time period t2 may be alternately set.

[0040] The control gate of the first transistor T1 is connected to the third node N3 to receive the voltage of the first node N1 or the first voltage signal VGH, controlling the on / off state of the first transistor T1. The first source of the first transistor T1 is connected to the second voltage signal VGL, and the second drain of the first transistor T1 is connected to the gate signal output terminal EM_OUT. When the first transistor T1 is turned on, the second terminal of the first transistor T1 outputs the second voltage signal VGL. The control gate of the second transistor T2 is connected to the fourth node N4 to receive the voltage of the first node N1 or the first voltage signal VGH, controlling the on / off state of the second transistor T2. The first source of the second transistor T2 is connected to the second voltage signal VGL, and the second drain of the second transistor T2 is connected to the gate signal output terminal EM_OUT. When the second transistor T2 is turned on, the second terminal of the second transistor T2 outputs the second voltage signal VGL. For example, during at least a portion of the first time period t1, the first transistor T1 is turned on and the second transistor T2 is turned off; during at least a portion of the second time period t2, the first transistor T1 is turned off and the second transistor T2 is turned on.

[0041] In this embodiment, by controlling the control electrodes of the first transistor T1 and the second transistor T2 respectively, the first output unit 1031 and the second output unit 1032 can be precisely controlled to output the second voltage signal VGL according to a preset control cycle. Since the first output unit 1031 and the second output unit 1032 can work independently, they can alternately output the second voltage signal VGL according to the control signal (e.g., including the first control signal XT1 and the second control signal XT2), avoiding the problem of the first transistor T1 or the second transistor T2 being affected by negative bias stress for a long time, causing the threshold voltage to drift and resulting in unstable output voltage.

[0042] Figure 4 The diagram shown is a structural schematic of a gate drive circuit provided in another embodiment of this application. Figure 4 As shown, the output module 103 further includes a third output unit 1033, which is configured to output a first voltage signal VGH according to the potential of the second node N2. Optionally, the third output unit 1033 includes a third transistor T3, the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first voltage signal VGH and / or connected to the first power line (which can transmit the first voltage signal VGH), and the second electrode of the third transistor T3 is connected to the gate signal output terminal EM_OUT.

[0043] Optionally, the first time period t1 includes a first sub-time period t11 and a second sub-time period t12. In the first sub-time period t11, the third output unit 1033 outputs a first voltage signal VGH to the gate signal output terminal EM_OUT. In the second sub-time period t12, the first output unit 1031 outputs a second voltage signal VGL to the gate signal output terminal EM_OUT. Optionally, the second time period t2 includes a third sub-time period t13 and a fourth sub-time period t14. In the third sub-time period t13, the third output unit 1033 outputs the first voltage signal VGH to the gate signal output terminal EM_OUT. In the fourth sub-time period t14, the second output unit 1032 outputs the second voltage signal VGL to the gate signal output terminal EM_OUT.

[0044] Optionally, the first time period t1 and the second time period t2 are set alternately. Optionally, in the first sub-time period t11, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on; in the second sub-time period t12, the first transistor T1 is turned on, the second transistor T2 is turned off, and the third transistor T3 is turned off; in the third sub-time period t13, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on; in the fourth sub-time period t14, the first transistor T1 is turned off, the second transistor T2 is turned on, and the third transistor T3 is turned off.

[0045] Optionally, one of the first voltage signal VGH and the second voltage signal VGL is at a low potential, and the other is at a high potential; alternatively, the first voltage signal VGH is at a high potential, and the second voltage signal VGL is at a low potential. The first voltage signal VGH and the second voltage signal VGL can be DC potentials.

[0046] Optionally, the gate drive circuit also includes a third capacitor C3, the two ends of which are connected to the control electrode of the third transistor T3 and the first electrode of the third transistor T3, respectively.

[0047] Specifically, the third output unit 1033 outputs a first voltage signal VGH based on the potential of the second node N2. The third output unit 1033 and the first output unit 1031 (or the second output unit 1032) operate alternately. The control electrode (gate) of the third transistor T3 is connected to the second node N2 to receive the voltage of the second node N2 and control the on / off state of the third transistor T3. The first electrode (source) of the third transistor T3 is connected to the first voltage signal VGH, and the second electrode (drain) of the third transistor T3 is connected to the output node EM_OUT. When the third transistor T3 is turned on, the second electrode of the third transistor T3 outputs the first voltage signal VGH.

[0048] For example, in the first sub-time period t11, the first transistor T1 and the second transistor T2 are off, the third transistor T3 is on, and the second terminal of the third transistor T3 outputs the first voltage signal VGH. In the second sub-time period t12, the first transistor T1 is on, and the second terminal of the first transistor T1 outputs the second voltage signal VGL, while the second transistor T2 and the third transistor T3 are off. In the third sub-time period t13, the first transistor T1 and the second transistor T2 are off, the third transistor T3 is on, and the second terminal of the third transistor T3 outputs the first voltage signal VGH. In the fourth sub-time period t14, the first transistor T1 is off, the second transistor T2 is on, and the second terminal of the second transistor T2 outputs the second voltage signal VGL, while the third transistor T3 is off.

[0049] In this embodiment, by providing a third output unit 1033, the output module 103 can output a first voltage signal VGH based on the potential of the second node N2. This allows the gate driving circuit to alternately output the first voltage signal VGH and the second voltage signal VGL in time intervals, controlling the on / off state of the transistors in the pixel circuit. Furthermore, this enhances the reliability of the circuit and helps improve the problem of uneven display.

[0050] Figure 5 The diagram shown is a structural schematic of a gate drive circuit provided in another embodiment of this application. Figure 5 As shown, the output control module 102 includes a first control unit 1021 and a second control unit 1022. The control signals include a first control signal XT1 and a second control signal XT2. The first control unit 1021 and the second control unit 1022 are configured to control the first output unit 1031 and the second output unit 1032 to alternately output a second voltage signal VGL according to the first control signal XT1 and the second control signal XT2. Optionally, the first control unit 1021 is configured to provide the voltage of the first node N1 to the third node N3 according to the first control signal XT1 and to provide the first voltage signal VGH to the third node N3 according to the second control signal XT2. The second control unit 1022 is configured to provide the voltage of the first node N1 to the fourth node N4 according to the second control signal XT2 and to provide the first voltage signal VGH to the fourth node N4 according to the first control signal XT1.

[0051] Optionally, in the first time period t1 and the second time period t2, one of the first control signal XT1 and the second control signal XT2 is at a high potential and the other is at a low potential; one of the potentials of the first control signal XT1 in the first time period t1 and the second time period t2 is at a high potential and the other is at a low potential; one of the potentials of the second control signal XT2 in the first time period t1 and the second time period t2 is at a high potential and the other is at a low potential.

[0052] Specifically, the first control unit 1021 controls the operating state of the first output unit 1031 according to the first control signal XT1 and the second control signal XT2. The second control unit 1022 controls the operating state of the second output unit 1032 according to the first control signal XT1 and the second control signal XT2. For example, the first control signal XT1 is at a low potential in the first time period t1 and at a high potential in the second time period t2; the second control signal XT2 is at a high potential in the first time period t1 and at a low potential in the second time period t2. For instance, the first control unit 1021 transmits the voltage of the first node N1 to the third node N3 according to the first control signal XT1 and the second control signal XT2, and the second control unit 1022 transmits the first voltage signal VGH to the fourth node N4 according to the first control signal XT1 and the second control signal XT2. When the third node N3 receives the voltage of the first node N1, the fourth node N4 receives the first voltage signal VGH, and the first output unit 1031 outputs the second voltage signal VGL according to the potential of the third node N3. For example, the second control unit 1022 transmits the voltage of the first node N1 to the fourth node N4 according to the first control signal XT1 and the second control signal XT2, and the first control unit 1021 transmits the first voltage signal VGH to the third node N3 according to the first control signal XT1 and the second control signal XT2. When the fourth node N4 receives the voltage of the first node N1, the third node N3 receives the first voltage signal VGH, and the second output unit 1032 outputs the second voltage signal VGL according to the potential of the fourth node N4. Therefore, by controlling the control period of the first control signal XT1 and the second control signal XT2, the first output unit 1031 and the second output unit 1032 can be controlled to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4.

[0053] In this embodiment, by configuring the first control unit 1021 and the second control unit 1022, the first output unit 1031 and the second output unit 1032 can alternately output the second voltage signal VGL, reducing output voltage fluctuations in the drive circuit, thereby improving display uniformity and reducing or eliminating display problems caused by voltage unevenness. Furthermore, the first control unit 1021 and the second control unit 1022 respectively control the first output unit 1031 and the second output unit 1032, making the operation logic of the output control module 102 simpler and easier to implement and maintain.

[0054] Figure 6 The diagram shown is a structural schematic of a gate drive circuit provided in another embodiment of this application. Figure 6As shown, the first control unit 1021 includes a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is connected to a first control signal XT1, and its first electrode is connected to a first node N1. The control electrode of the fifth transistor T5 is connected to a second control signal XT2, and its first electrode is connected to a first voltage signal VGH and / or a first power supply line. The second electrodes of both transistors T4 and T5 are connected to a third node N3. The control electrodes of the fourth transistor T4 and T5 can be connected to different control signals, i.e., different control signal lines. For example, the channel types of the fourth transistor T4 and T5 can be the same, such as N-type transistors, or P-type transistors. For example, the switching states of the fourth transistor T4 and T5 can be opposite.

[0055] In other embodiments, the control electrode of the fourth transistor T4 and the control electrode of the fifth transistor T5 can be connected to the same control signal, that is, connected to the same control signal line. For example, the channel types of the fourth transistor T4 and the fifth transistor T5 can be different. For example, the fourth transistor T4 is a P-type transistor and the fifth transistor T5 is an N-type transistor, or the fourth transistor T4 is an N-type transistor and the fifth transistor T5 is a P-type transistor.

[0056] Optionally, the second control unit 1022 includes a sixth transistor T6 and a seventh transistor T7. The control electrode of the sixth transistor T6 is connected to a second control signal XT2, and the first electrode of the sixth transistor T6 is connected to a first node N1. The control electrode of the seventh transistor T7 is connected to the first control signal XT1, and the first electrode of the seventh transistor T7 is connected to a first voltage signal VGH and / or a first power supply line. The second electrodes of the sixth transistor T6 and the seventh transistor T7 are connected to a fourth node N4. For example, the channel types of the sixth transistor T6 and the seventh transistor T7 can be the same, such as N-type transistors, or P-type transistors. For example, the switching states of the sixth transistor T6 and the seventh transistor T7 can be opposite.

[0057] In other embodiments, the control electrode of the sixth transistor T6 and the control electrode of the seventh transistor T7 can be connected to the same control signal. For example, the channel types of the sixth transistor T6 and the seventh transistor T7 can be different. For example, the sixth transistor T6 is a P-type transistor and the seventh transistor T7 is an N-type transistor, or the sixth transistor T6 is an N-type transistor and the seventh transistor T7 is a P-type transistor.

[0058] For example, the switching states of the fourth transistor T4 and the sixth transistor T6 are opposite. For example, the channel types of the fourth transistor T4 and the sixth transistor T6 can be the same. The fourth transistor T4 and the sixth transistor T6 can be connected to different control signals, that is, connected to different control signal lines.

[0059] For example, the fourth transistor T4 and the sixth transistor T6 can have different channel types. The fourth transistor T4 and the sixth transistor T6 can be connected to the same control signal, that is, connected to the same control signal line.

[0060] Optionally, in the first time period t1, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned off, and the seventh transistor T7 is turned on; in the second time period t2, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off.

[0061] Specifically, the gate of the fourth transistor T4 is connected to the first control signal XT1 to control the on / off state of the fourth transistor T4. The source of the fourth transistor T4 is connected to the first node N1 and is connected to the voltage of the first node N1. The drain of the fourth transistor T4 is connected to the third node N3. When the fourth transistor T4 is turned on, it transfers the voltage of the first node N1 to the third node N3 to control the operation of the first transistor T1.

[0062] The gate of the fifth transistor T5 is connected to the second control signal XT2, which controls the on / off state of the fifth transistor T5. The source of the fifth transistor T5 is connected to the first voltage signal VGH. The drain of the fifth transistor T5 is connected to the third node N3. When the fifth transistor T5 is turned on, it transmits the first voltage signal VGH to the third node N3 to control the first transistor T1 to stop working.

[0063] The gate of the sixth transistor T6 is connected to the second control signal XT2, controlling the on / off state of the sixth transistor T6. The source of the sixth transistor T6 is connected to the first node N1, receiving the voltage of the first node N1. The drain of the sixth transistor T6 is connected to the fourth node N4. When the sixth transistor T6 is turned on, it transfers the voltage of the first node N1 to the fourth node N4 to control the operation of the second transistor T2.

[0064] The gate of the seventh transistor T7 is connected to the first control signal XT1, controlling the on / off state of the seventh transistor T7. The source of the seventh transistor T7 is connected to the first voltage signal VGH. The drain of the seventh transistor T7 is connected to the fourth node N4. When the seventh transistor T7 is turned on, it transmits the first voltage signal VGH to the fourth node N4 to control the second transistor T2 to stop working.

[0065] For example, in the first time period t1, the fourth transistor T4 is turned on, transmitting the voltage of the first node N1 to the third node N3; the fifth transistor T5 is turned off, controlling the first transistor T1 to operate; the sixth transistor T6 is turned off, and the seventh transistor T7 is turned on, transmitting the first voltage signal VGH to the fourth node N4, controlling the second transistor T2 to stop operating. In the second time period t2, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, transmitting the first voltage signal VGH to the third node N3, controlling the first transistor T1 to stop operating; the sixth transistor T6 is turned on, transmitting the voltage of the first node N1 to the fourth node N4; the seventh transistor T7 is turned off, controlling the second transistor T2 to operate.

[0066] In this embodiment, through the combination of the fourth transistor T4 and the fifth transistor T5, the first control unit 1021 can precisely switch the voltage of the third node N3 according to the first control signal XT1 and the second control signal XT2, thereby controlling the operating state of the first output unit 1031. Through the combination of the sixth transistor T6 and the seventh transistor T7, the second control unit 1022 can precisely switch the voltage of the fourth node N4 according to the first control signal XT1 and the second control signal XT2, thereby controlling the operating state of the second output unit 1032. This configuration avoids the first transistor T1 or the second transistor T2 being subjected to negative bias stress for a long time, causing threshold voltage drift and resulting in unstable output voltage, further improving the display unevenness problem.

[0067] Figure 7 The diagram shown is a structural schematic of a gate drive circuit provided in another embodiment of this application. Figure 7 As shown, the node control module 101 includes an input unit, and the clock signal includes a first clock signal CK1. The input unit is configured to provide an input signal EIN to the first node N1 according to the first clock signal CK1. Optionally, the input unit includes an eighth transistor T8, the first terminal of the eighth transistor T8 is connected to the input signal EIN, the control terminal of the eighth transistor T8 is connected to the first clock signal CK1, and the second terminal of the eighth transistor T8 is connected to the first node N1.

[0068] Optionally, the input unit further includes a ninth transistor T9, with the second terminal of the eighth transistor T8 and the first terminal of the ninth transistor T9 connected; the control terminal of the ninth transistor T9 is connected to the second voltage signal VGL and / or to the second power supply line, and the second terminal of the ninth transistor T9 is connected to the first node N1. That is, the second terminal of the eighth transistor T8 is indirectly connected to the first node N1.

[0069] Specifically, the gate of the eighth transistor T8 is connected to the first clock signal CK1, controlling its on / off state. The source of the eighth transistor T8 is connected to the input signal EIN, and its drain is connected to the first terminal of the ninth transistor T9 or the first node N1. For example, when the first clock signal CK1 is low, the eighth transistor T8 is turned on, transmitting the input signal EIN to the ninth transistor T9. The gate of the ninth transistor T9 is connected to the second voltage signal VGL, controlling its on / off state. For example, the ninth transistor T9 is a P-type transistor. The ninth transistor T9 is a normally open transistor in the gate drive circuit. The second terminal of the ninth transistor T9 is connected to the first node N1, transmitting the received input signal EIN to the first node N1.

[0070] In this embodiment, by using the first clock signal CK1 to control the eighth transistor T8, it can be ensured that the input signal EIN is delivered to the first node N1 at the correct time, thereby achieving synchronization with the clock of the entire display system. The switching characteristics of the transistor reduce signal loss and interference during transmission, improving the reliability of signal transmission. Using transistors as input units simplifies circuit layout, reduces the number of components, and lowers the complexity and manufacturing cost of the circuit board.

[0071] In one embodiment, see Figure 7 The node control module 101 also includes a third control unit.

[0072] The third control unit and the input unit are connected to the first node N1. The third control unit is configured to provide the first voltage signal VGH to the second node N2 according to the potential of the first node N1.

[0073] Alternatively, the third control unit and the input unit are connected to the fifth node N5, the input unit is further configured to provide the input signal EIN to the fifth node N5 according to the first clock signal CK1, and the third control unit is configured to provide the first voltage signal VGH to the second node N2 according to the potential of the fifth node N5.

[0074] Optionally, the third control unit includes a tenth transistor T10, the control electrode of which is connected to the fifth node N5 (e.g., Figure 7 (as shown) or the first node N1 (as shown) Figure 8As shown), the first terminal of the tenth transistor T10 is connected to the first voltage signal VGH, and the second terminal of the tenth transistor T10 is connected to the second node N2; for example, the second terminal of the eighth transistor T8 and the first terminal of the ninth transistor T9 are connected to the fifth node N5.

[0075] Specifically, the input unit not only provides the input signal EIN to the first node N1, but also provides the input signal EIN to the fifth node N5 according to the first clock signal CK1. The third control unit and the input unit are connected to the fifth node N5 or the first node N1, and determine whether to provide the first voltage signal VGH to the second node N2 according to the potential of the fifth node N5 or the first node N1. The control electrode (gate) of the tenth transistor T10 is connected to the fifth node N5 or the first node N1, and controls the on / off state of the tenth transistor T10 according to the potential of the fifth node N5 or the first node N1. The first electrode (source) of the tenth transistor T10 is connected to the first voltage signal VGH, and the second electrode (drain) is connected to the second node N2. For example, when the potential of the fifth node N5 or the first node N1 is low, the tenth transistor T10 is turned on, transmitting the input signal EIN to the second node N2 to control the third transistor T3 to stop working.

[0076] In this embodiment, when the fifth node N5 or the first node N1 is at a low level, the tenth transistor T10 is turned on, providing the first voltage signal VGH to the second node N2, thereby implementing the pull-up function of the gate level of the third transistor T3. This configuration further improves the reliability of the circuit, simplifies the circuit design, reduces the need for additional pull-up resistors or other pull-up components, and lowers the complexity and cost of the circuit.

[0077] In one embodiment, see Figure 7The node control module 101 further includes a fourth control unit, and the clock signal further includes a second clock signal CK2. The fourth control unit is configured to control the potential of the first node N1 according to the input signal EIN, the first clock signal CK1, and the second clock signal CK2; for example, the fourth control unit is configured to provide the input signal EIN to the first node N1 according to the first clock signal CK1 and the second clock signal CK2. Optionally, the fourth control unit includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The first terminal of the eleventh transistor T11 is connected to the first voltage signal VGH and / or connected to the first power supply line. The second terminal of the eleventh transistor T11 is connected to the second terminal of the twelfth transistor T12. The first terminal of the twelfth transistor T12 is connected to the second clock signal CK2. The control terminal of the twelfth transistor T12 is connected to the first terminal of the thirteenth transistor T13. The second terminal of the thirteenth transistor T13 is connected to the first node N1. The first terminal of transistor T13 and the control terminal of transistor T13 are connected to the second terminal of transistor T14. The control terminal of transistor T14 is connected to the second voltage signal VGL and / or the second power supply line. The first terminal of transistor T14 and the second terminal of transistor T15 are connected. The control terminal of transistor T15 is connected to the first clock signal CK1. The first terminal of transistor T15 is connected to the input signal EIN. Optionally, the fourth control unit also includes a first capacitor C1. The two ends of the first capacitor C1 are connected to the control terminal of transistor T12 and the second terminal of transistor T12, respectively.Optionally, the node control module 101 further includes a fifth control unit, configured to control the potential of the second node N2 according to the first clock signal CK1 and the second clock signal CK2; optionally, the fifth control unit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20. The first terminal of the sixteenth transistor T16 is connected to the second voltage signal VGL and / or connected to the second power supply line. The second terminal of the sixteenth transistor T16 and the first terminal of the seventeenth transistor T17 are connected to the control terminal of the eleventh transistor T11. The control terminal of the sixteenth transistor T16 is connected to the first clock signal CK1. The control terminal of the seventeenth transistor T17 is connected to the second voltage signal VGL and / or connected to the second power supply line. The second terminal of the seventeenth transistor T17 and the first terminal of the eighteenth transistor T18... The control electrode of the 18th transistor T18 is connected to the first electrode of the 19th transistor T19, and the second electrode of the 18th transistor T18 is connected to the first electrode of the 19th transistor T19. The second electrode of the 19th transistor T19 is connected to the second node N2, and the control electrode of the 19th transistor T19 is connected to the second clock signal CK2. The first electrode of the 20th transistor T20 is connected to the first clock signal CK1, and the control electrode of the 20th transistor T20 is connected to the second electrode of the 8th transistor T8. The second electrode of the 20th transistor T20 is connected to the second electrode of the 16th transistor T16. Optionally, the fifth control unit also includes a second capacitor C2, the two ends of which are connected to the control electrode of the 18th transistor T18 and the second electrode of the 18th transistor T18, respectively. Optionally, the first clock signal CK1 and the second clock signal CK2 have the same frequency but different phases, for example, opposite phases.

[0078] Specifically, the fourth control unit includes eleventh to fifteenth transistors T15 and a first capacitor C1. These components work together to provide the input signal EIN to the first node N1 according to the first clock signal CK1 and the second clock signal CK2. The circuit composed of eleventh to fifteenth transistors T15 can realize the fourth control function of the potential of the first node N1, that is, under the control of the first clock signal CK1 and the second clock signal CK2, pull the potential of the first node N1 low.

[0079] The fifth control unit includes sixteenth transistors T16 to twentieth transistors T20, a second capacitor C2, and a third capacitor C3. These components work together to provide a second voltage signal VGL to the second node N2 according to the first clock signal CK1 and the second clock signal CK2, thereby controlling the operation of the third transistor T3. The fifth control unit is used to maintain the stability of the voltage at the second node N2, unaffected by external interference or fluctuations during signal transmission.

[0080] In this embodiment, the fourth control unit ensures that the potential of the first node N1 can be pulled low when needed, thereby increasing the conduction level of the first transistor T1 and improving the stability of signal transmission. The fifth control unit, through a combination of transistors and capacitors, can effectively maintain the voltage stability of the second node N2, which is crucial for the normal operation of the entire circuit. The design of the fifth and fourth control units increases circuit redundancy, further improving the reliability of the circuit in the face of voltage fluctuations and external interference.

[0081] In one embodiment, see Figure 7 The node control module 101 further includes a reset unit configured to control the potential of the fifth node N5 according to the reset signal REST. Exemplarily, the reset unit includes a twenty-first transistor T21. The first terminal of the twenty-first transistor T21 is connected to a first voltage signal VGH and / or a first power supply line. The control terminal of the twenty-first transistor T21 is connected to the reset signal REST. The second terminal of the twenty-first transistor T21, the control terminal of the tenth transistor T10, and the first terminal of the ninth transistor T9 are connected to the fifth node. The second terminal of the twenty-first transistor T21 is connected to the second terminal of the eighth transistor T8. Exemplarily, when the twenty-first transistor T21 is turned on, the second terminal of the twenty-first transistor T21 outputs the first voltage signal VGH to the fifth node N5 to reset the gate drive circuit.

[0082] Each transistor in the above embodiments may include a P-type transistor or an N-type transistor, such as... Figure 7 As shown, each transistor may include a P-type transistor.

[0083] Figure 8 The diagram shown is a schematic flowchart of a driving method for a gate driving circuit according to an embodiment of this application, applicable to driving the gate driving circuit mentioned in any of the above embodiments. Figure 8 As shown, the driving method includes:

[0084] S110, in the first time period, a first control signal in a first level state and a second control signal in a second level state are input to the output control module, so that the first control unit provides the voltage of the first node to the third node according to the first control signal, and the second control unit provides the first voltage signal to the fourth node according to the first control signal.

[0085] For example, in the first level state and the second level state, one is a low level state and the other is a high level state. For example, the first level state is a low level state and the second level state is a high level state.

[0086] For example, Figure 9 The diagram shown is a simulation waveform of a gate drive circuit provided in another embodiment of this application. Figure 9As shown, during the first time period t1, a first control signal XT1 in a low-level state and a second control signal XT2 in a high-level state are input to the output control module 102. For example, the fourth transistor T4 and the seventh transistor T7 are connected to the on level, and the fifth transistor T5 and the sixth transistor T6 are connected to the off level, so that the first control unit 1021 provides the voltage of the first node N1 to the third node N3 according to the first control signal XT1, and the potential of the third node N3 is low. The second control unit 1022 provides the first voltage signal VGH to the fourth node N4 according to the first control signal XT1, and the potential of the fourth node N4 is high. Then the first output unit 1031 receives the low-level control signal and turns on and outputs the second voltage signal VGL, and the second output unit 1032 receives the high-level control signal and turns off. The first transistor T1 is in a negative bias stress (NBS) state, and the second transistor T2 is in a positive bias stress (PBS) state.

[0087] For example, in the first sub-time period t11, the potential of the third node N3 is high, and the potential of the fourth node N4 is high. Therefore, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the second terminal of the third transistor T3 outputs the first voltage signal VGH. In the second sub-time period t12, the potential of the third node N3 is low, and the potential of the fourth node N4 is high. Therefore, the first transistor T1 is turned on, the second terminal of the first transistor T1 outputs the second voltage signal VGL, and the second transistor T2 and the third transistor T3 are turned off.

[0088] S120, Second Time Period: Input a first control signal and a second control signal at a second level to the output control module, so that the first control unit provides a first voltage signal to the third node according to the second control signal, and the second control unit provides the voltage of the first node to the fourth node according to the second control signal.

[0089] Specifically, during the second time period t2, a high-level first control signal XT1 and a low-level second control signal XT2 are input to the output control module 102. For example, the fourth transistor T4 and the seventh transistor T7 are connected to the off level, and the fifth transistor T5 and the sixth transistor T6 are connected to the on level. This causes the first control unit 1021 to provide the first voltage signal VGH to the third node N3 according to the second control signal XT2, and the potential of the third node N3 is high. The second control unit 1022 provides the voltage of the first node N1 to the fourth node N4 according to the second control signal XT2, and the potential of the fourth node N4 is low. Then, the second output unit 1032 receives the low-level control signal, turns on, and outputs the second voltage signal VGL. The first output unit 1031 receives the high-level control signal, turns off, and the second transistor T2 is in the NBS state, while the first transistor T1 is in the PBS state.

[0090] For example, in the third sub-time period t13, the potential of the third node N3 is high, and the potential of the fourth node N4 is high. Therefore, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the second terminal of the third transistor T3 outputs the first voltage signal VGH. In the fourth sub-time period t14, the potential of the third node N3 is high, and the potential of the fourth node N4 is low. Therefore, the first transistor T1 is turned off, the second transistor T2 is turned on, the second terminal of the second transistor T2 outputs the second voltage signal VGL, and the third transistor T3 is turned off.

[0091] The technical solution of this embodiment, by switching the level states of the first control signal and the second control signal at different stages, enables the first control unit and the second control unit to control the first output unit and the second output unit to alternately output the second voltage signal. During this control cycle, both the first transistor and the second transistor periodically switch between two states, avoiding the problem of threshold voltage drift and output voltage instability caused by the first transistor and the second transistor being affected by negative bias stress for a long time. Therefore, the technical solution provided by this application embodiment can improve the stability of the gate drive circuit output and reduce problems such as uneven display caused by output voltage fluctuations.

[0092] This application also provides a display device, including a gate driving circuit as mentioned in any of the above embodiments. This display device has the beneficial effects of the gate driving circuit mentioned in any of the above embodiments; its technical principle and the resulting effects are similar, and will not be repeated here. The display device may include electronic products such as mobile phones, tablets, laptops, wearable devices, in-vehicle devices, and smartwatches.

[0093] The gate drive circuit can be connected to a first clock line and a second clock line. The first clock line can be used to provide a first clock signal to the odd-numbered gate drive circuits, and the second clock line can be used to provide a second clock signal to the odd-numbered gate drive circuits. The first clock line can be used to provide a second clock signal to the even-numbered gate drive circuits, and the second clock line can be used to provide a first clock signal to the even-numbered gate drive circuits.

[0094] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A gate driving circuit, characterized in that, include: The node control module is configured to control the potential of the first node and the second node based on the clock signal and the input signal; The output control module is configured to provide the voltage of the first node or the first voltage signal to the third node and to the fourth node according to the control signal. An output module is configured to alternately output a first voltage signal and a second voltage signal based on the potentials of the second node, the third node, and the fourth node; the output module includes a first output unit and a second output unit, the first output unit being configured to output the second voltage signal based on the potential of the third node, and the second output unit being configured to output the second voltage signal based on the potential of the fourth node; The first output unit and the second output unit alternately output the second voltage signal; The first output unit outputs the second voltage signal during at least a portion of the first time period, and the second output unit outputs the second voltage signal during at least a portion of the second time period; The first output unit includes a first transistor, the control electrode of the first transistor is connected to the third node, the first electrode of the first transistor is connected to the second voltage signal, and the second electrode of the first transistor is connected to the gate signal output terminal; the second output unit includes a second transistor, the control electrode of the second transistor is connected to the fourth node, the first electrode of the second transistor is connected to the second voltage signal, and the second electrode of the second transistor is connected to the gate signal output terminal; the first transistor and the second transistor are alternately turned on; The output module further includes a third output unit, which is configured to output the first voltage signal according to the potential of the second node; the third output unit includes a third transistor, the control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first voltage signal, and the second electrode of the third transistor is connected to the gate signal output terminal; The first time period includes a first sub-time period and a second sub-time period. During the first sub-time period, the third output unit outputs the first voltage signal to the gate signal output terminal. During the second sub-time period, the first output unit outputs the second voltage signal to the gate signal output terminal. The second time period includes a third sub-time period and a fourth sub-time period. During the third sub-time period, the third output unit outputs the first voltage signal to the gate signal output terminal. During the fourth sub-time period, the second output unit outputs the second voltage signal to the gate signal output terminal. The first time period and the second time period are alternately set. During the first sub-period, the first transistor and the second transistor are turned off, and the third transistor is turned on; during the second sub-period, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned off. In the third sub-period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the fourth sub-period, the first transistor is turned off, the second transistor is turned on, and the third transistor is turned off.

2. The gate driving circuit according to claim 1, characterized in that, One of the first voltage signal and the second voltage signal is at a low potential, and the other is at a high potential.

3. The gate driving circuit according to claim 1, characterized in that, The first voltage signal is at a high potential, and the second voltage signal is at a low potential.

4. The gate driving circuit according to claim 1, characterized in that, The gate drive circuit also includes a third capacitor, the two ends of which are respectively connected to the control electrode of the third transistor and the first electrode of the third transistor.

5. The gate driving circuit according to claim 1, characterized in that, The output control module includes a first control unit and a second control unit. The control signal includes a first control signal and a second control signal. The first control unit and the second control unit are configured to control the first output unit and the second output unit to alternately output the second voltage signal according to the first control signal and the second control signal.

6. The gate driving circuit according to claim 5, characterized in that, The first control unit is configured to provide the voltage of the first node to the third node according to the first control signal, and to provide the first voltage signal to the third node according to the second control signal; the second control unit is configured to provide the voltage of the first node to the fourth node according to the second control signal, and to provide the first voltage signal to the fourth node according to the first control signal.

7. The gate driving circuit according to claim 5, characterized in that, During the first time period and the second time period, one of the first control signal and the second control signal is at a high potential, and the other is at a low potential; The first control signal has a high potential in one of the first time period and a low potential in the second time period; The second control signal has a high potential in one of the first time period and a low potential in the second time period.

8. The gate driving circuit according to claim 5, characterized in that, The first control unit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is connected to the first control signal, the first electrode of the fourth transistor is connected to the first node, the control electrode of the fifth transistor is connected to the second control signal, the first electrode of the fifth transistor is connected to the first voltage signal, and the second electrodes of the fourth transistor and the second electrodes of the fifth transistor are connected to the third node. The second control unit includes a sixth transistor and a seventh transistor. The control electrode of the sixth transistor is connected to the second control signal, the first electrode of the sixth transistor is connected to the first node, the control electrode of the seventh transistor is connected to the first control signal, the first electrode of the seventh transistor is connected to the first voltage signal, and the second electrodes of the sixth transistor and the seventh transistor are connected to the fourth node.

9. The gate driving circuit according to claim 8, characterized in that, During the first time period, the fourth transistor is turned on, the fifth transistor is turned off, the sixth transistor is turned off, and the seventh transistor is turned on; during the second time period, the fourth transistor is turned off, the fifth transistor is turned on, the sixth transistor is turned on, and the seventh transistor is turned off.

10. The gate driving circuit according to claim 1, characterized in that, The node control module includes an input unit, the clock signal includes a first clock signal, and the input unit is configured to provide the input signal to the first node according to the first clock signal.

11. The gate driving circuit according to claim 10, characterized in that, The input unit includes an eighth transistor, the first terminal of which is connected to the input signal, the control terminal of which is connected to the first clock signal, and the second terminal of which is connected to the first node.

12. The gate driving circuit according to claim 11, characterized in that, The input unit further includes a ninth transistor, the second terminal of the eighth transistor and the first terminal of the ninth transistor are connected, the control terminal of the ninth transistor is connected to the second voltage signal, and the second terminal of the ninth transistor is connected to the first node.

13. The gate driving circuit according to claim 12, characterized in that, The node control module also includes a third control unit. The third control unit and the input unit are connected to the first node, and the third control unit is configured to provide the first voltage signal to the second node according to the potential of the first node; Alternatively, the third control unit and the input unit are connected to the fifth node, the input unit is further configured to provide the input signal to the fifth node according to the first clock signal, and the third control unit is configured to provide the first voltage signal to the second node according to the potential of the fifth node.

14. The gate driving circuit according to claim 13, characterized in that, The third control unit includes a tenth transistor, the control electrode of which is connected to the fifth node or the first node, the first electrode of which is connected to the first voltage signal, and the second electrode of which is connected to the second node.

15. The gate driving circuit according to claim 13, characterized in that, The second terminal of the eighth transistor and the first terminal of the ninth transistor are connected to the fifth node.

16. The gate driving circuit according to claim 11, characterized in that, The node control module further includes a fourth control unit, and the clock signal further includes a second clock signal. The fourth control unit is configured to control the potential of the first node according to the input signal, the first clock signal, and the second clock signal.

17. The gate driving circuit according to claim 16, characterized in that, The fourth control unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The first terminal of the eleventh transistor is connected to the first voltage signal. The second terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor. The first terminal of the twelfth transistor is connected to the second clock signal. The control terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor. The second terminal of the thirteenth transistor is connected to the first node. The first terminal of the thirteenth transistor and the control terminal of the thirteenth transistor are connected to the second terminal of the fourteenth transistor. The control terminal of the fourteenth transistor is connected to the second voltage signal. The first terminal of the fourteenth transistor is connected to the second terminal of the fifteenth transistor. The control terminal of the fifteenth transistor is connected to the first clock signal. The first terminal of the fifteenth transistor is connected to the input signal.

18. The gate driving circuit according to claim 17, characterized in that, The fourth control unit further includes a first capacitor, the two ends of which are respectively connected to the control electrode of the twelfth transistor and the second electrode of the twelfth transistor.

19. The gate driving circuit according to claim 17, characterized in that, The node control module further includes a fifth control unit, which is configured to control the potential of the second node according to the first clock signal and the second clock signal.

20. The gate driving circuit according to claim 19, characterized in that, The fifth control unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor. The first terminal of the sixteenth transistor is connected to the second voltage signal. The second terminal of the sixteenth transistor and the first terminal of the seventeenth transistor are connected to the control terminal of the eleventh transistor. The control terminal of the sixteenth transistor is connected to the first clock signal. The control terminal of the seventeenth transistor is connected to the second voltage signal. The second terminal of the seventeenth transistor is connected to the control terminal of the eighteenth transistor. The first terminal of the eighteenth transistor is connected to the second clock signal. The second terminal of the eighteenth transistor is connected to the first terminal of the nineteenth transistor. The second terminal of the nineteenth transistor is connected to the second node. The control terminal of the nineteenth transistor is connected to the second clock signal. The first terminal of the twentieth transistor is connected to the first clock signal. The control terminal of the twentieth transistor is connected to the second terminal of the eighth transistor. The second terminal of the twentieth transistor is connected to the second terminal of the sixteenth transistor.

21. The gate driving circuit according to claim 20, characterized in that, The fifth control unit further includes a second capacitor, the two ends of which are respectively connected to the control electrode of the eighteenth transistor and the second electrode of the eighteenth transistor.

22. The gate driving circuit according to claim 16, characterized in that, The first clock signal and the second clock signal have the same frequency but different phases.

23. A driving method for a gate driving circuit, characterized in that, The gate driving circuit applicable to any one of claims 5 to 9, the driving method comprising: In the first time period, the first control signal in the first level state and the second control signal in the second level state are input to the output control module, so that the first control unit provides the voltage of the first node to the third node according to the first control signal, and the second control unit provides the first voltage signal to the fourth node according to the first control signal. In the second time period, the first control signal and the second control signal of the second level state are input to the output control module, so that the first control unit provides the first voltage signal to the third node according to the second control signal, and the second control unit provides the voltage of the first node to the fourth node according to the second control signal.

24. A display device, characterized in that, include: The gate drive circuit as described in any one of claims 1 to 22.

Images