Display panel, preparation method thereof and display device

Abstract

The embodiment of the invention provides a display panel, a preparation method thereof and a display device. The display panel comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel circuit and a light-emitting device which are electrically connected with each other; the pixel circuit comprises a plurality of transistors, the plurality of transistors comprise a driving transistor and a data write-in transistor, the driving transistor is used for generating light-emitting driving current, the data write-in transistor is located between the driving transistor and a data signal line, and the data write-in transistor is used for transmitting data voltage transmitted by the data signal line to the driving transistor; wherein the data writing transistor comprises a first channel, the first channel comprises a first doping element and a second doping element, and the electron number of the first doping element is different from that of the second doping element. The threshold voltage of the data write-in transistor can be adjusted to be negative, and the problem of display abnormity caused by the fact that the data write-in transistor cannot be effectively turned off can be solved while the flicker problem of the display panel is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] The display panel includes a pixel circuit and a light-emitting device, wherein the pixel circuit includes a driving transistor and a plurality of switching transistors. Based on the cooperation between the driving transistor and the switching transistor, the pixel circuit transmits a light-emitting driving current to the light-emitting device to drive the light-emitting device to emit light.

[0003] However, in the prior art, when the display panel performs low-frequency display, the off-state leakage current of the switching transistor close to the gate of the driving transistor will greatly affect the gate potential of the driving transistor, which can easily cause the gate potential of the driving transistor to continuously increase within a display frame, causing the brightness within the display frame to continuously decrease, and thus easily causing the picture displayed by the display panel to show obvious flickering, seriously affecting the display effect under low-frequency driving. Summary of the invention

[0004] In view of this, embodiments of the present application provide a display panel and a method for manufacturing the same, and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including a plurality of sub-pixels, wherein the sub-pixels include a pixel circuit and a light-emitting device electrically connected to each other; the pixel circuit includes a plurality of transistors, wherein the plurality of transistors include:

[0006] A driving transistor, the driving transistor is used to generate a light-emitting driving current;

[0007] A data writing transistor is located between the driving transistor and the data signal line, and is used to transmit the data voltage transmitted by the data signal line to the driving transistor;

[0008] The data writing transistor includes a first channel, the first channel includes a first doping element and a second doping element, and the number of electrons in the first doping element is different from the number of electrons in the second doping element.

[0009] In an implementation manner of the first aspect, the first doping element includes at least one of boron, gallium, and indium, and the second doping element includes at least one of phosphorus, arsenic, and antimony.

[0010] In an implementation manner of the first aspect, in the first channel, a concentration of the second doping element is less than a concentration of the first doping element.

[0011] In an implementation manner of the first aspect, the driving transistor includes a second channel, and the second channel includes a first doping element.

[0012] In an implementation manner of the first aspect, the type of majority carriers in the first channel is the same as the type of majority carriers in the second channel.

[0013] In an implementation of the first aspect, a concentration of majority carriers in the first channel is less than a concentration of majority carriers in the second channel.

[0014] In an implementation manner of the first aspect, the data writing transistor is a P-type transistor.

[0015] In an implementation of the first aspect, a first electrode of a data write transistor is electrically connected to a data signal line, a second electrode is electrically connected to a first electrode of a driving transistor, and a gate is electrically connected to a first control line; the multiple transistors include a threshold grabbing transistor, a first electrode of the threshold grabbing transistor is electrically connected to a second electrode of the driving transistor, a second electrode is electrically connected to a gate of the driving transistor, and the gate is electrically connected to the first control line; wherein the data write transistor and the threshold grabbing transistor have the same channel type.

[0016] In an implementation of the first aspect, the threshold grabbing transistor includes a first sub-transistor and a second sub-transistor, the first electrode of the first sub-transistor is electrically connected to the second electrode of the driving transistor, the second electrode is electrically connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is electrically connected to the gate of the driving transistor; the gate of the first sub-transistor and the gate of the second sub-transistor are both electrically connected to the first control line.

[0017] In a second aspect, an embodiment of the present application provides a method for preparing a display panel, which is used to prepare the display panel provided in the first aspect, and the preparation method includes:

[0018] Providing a substrate, and preparing a semiconductor layer of a transistor on one side of the substrate;

[0019] implanting a first doping element into a semiconductor layer of the transistor;

[0020] A second doping element is implanted into the channel of the data writing transistor.

[0021] In an implementation manner of the second aspect, before the second doping element is implanted into the channel of the data writing transistor, the method further includes:

[0022] A protective material is provided on the semiconductor layer, the protective material covering channels of transistors other than the data writing transistor.

[0023] In an implementation manner of the second aspect, after the second doping element is implanted into the channel of the data writing transistor, the method further includes:

[0024] Remove protective material.

[0025] In an implementation manner of the second aspect, the protective material is photoresist.

[0026] In a third aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0027] In an embodiment of the present application, a first channel of a data writing transistor is set, including a first doping element and a second doping element with different electron numbers. The difference in the number of electrons between the first doping element and the second doping element can be used to adjust the concentration of carriers in the first channel, which is conducive to making the threshold voltage of the data writing transistor negative.

[0028] By making the threshold voltage of the data write transistor negative, the absolute value of the threshold voltage of the data write transistor can be increased. According to the transistor shutdown principle, even if the potential of the high-level signal VGH in the display panel is lowered, it is easier to control the data write transistor to turn off. While improving the flickering problem of the display panel, it is helpful to avoid the problem of display abnormality caused by the inability to effectively shut down the data write transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0030] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0031] Figure 2 for Figure 1 A timing diagram of the pixel circuit shown;

[0032] Figure 3 A schematic diagram of a relationship between a potential of a high-level signal and a screen flicker value provided in an embodiment of the present application;

[0033] Figure 4 A schematic plan view of a display panel provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0037] Figure 8 A process flow chart of manufacturing a display panel provided in an embodiment of the present application;

[0038] Fig. 9 A process flow chart of another display panel manufacturing method provided in an embodiment of the present application;

[0039] Fig.10 A process flow chart of another display panel manufacturing method provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0043] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0044] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0045] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0046] Before describing the technical solutions provided by the embodiments of the present application, Figure 1 Taking the pixel circuit shown in FIG. 1 as an example, the working principle of the pixel circuit is explained.

[0047] like Figure 1 As shown, the pixel circuit 11 may include a driving transistor Td, a gate reset transistor T1, a data writing transistor T2, a threshold grabbing transistor T3, a bias transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a reset transistor T7 and a storage capacitor Cst.

[0048] The driving transistor Td is used to generate a light-emitting driving current. The gate reset transistor T1, the data writing transistor T2, the threshold grabbing transistor T3, the bias transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the reset transistor T7 can be switch transistors.

[0049] The gate of the driving transistor Td is electrically connected to the first node N1. The gate of the gate reset transistor T1 is electrically connected to the gate reset scanning line S1, the first electrode is electrically connected to the gate reset signal line Vref1, and the second electrode is electrically connected to the first node N1.

[0050] The data writing transistor T2 has a gate electrically connected to the first control line SP, a first electrode electrically connected to the data signal line Data, and a second electrode electrically connected to the first electrode of the driving transistor Td.

[0051] The threshold grabbing transistor T3 includes a first sub-transistor T31 and a second sub-transistor T32. The first electrode of the first sub-transistor T31 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the second node N2, and the gate is electrically connected to the first control line SP. The first electrode of the second sub-transistor T32 is electrically connected to the second node N2, the second electrode is electrically connected to the first node N1, and the gate is electrically connected to the first control line SP. The switching states of the first sub-transistor T31 and the second sub-transistor T32 can be the same.

[0052] The bias transistor T4 has a gate electrically connected to the second control line SP*, a first electrode electrically connected to the bias signal line VDH, and a second electrode electrically connected to the first electrode of the driving transistor Td.

[0053] The gate of the first light emission control transistor T5 is electrically connected to the light emission control line EM, the first electrode is electrically connected to the power signal line PVDD, and the second electrode is electrically connected to the first electrode of the driving transistor Td. The gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line EM, the first electrode is electrically connected to the second electrode of the driving transistor Td, and the second electrode is electrically connected to the first electrode of the light emitting device 12, and the first electrode of the light emitting device 12 can be its anode. The switching states of the first light emission control transistor T5 and the second light emission control transistor T6 can be the same.

[0054] The reset transistor T7 has a gate electrically connected to the second control line SP*, a first electrode electrically connected to the reset signal line Vref2 , and a second electrode electrically connected to the first electrode of the light emitting device 12 .

[0055] One plate of the storage capacitor Cst is electrically connected to the power signal line PVDD, and the other plate of the storage capacitor Cst is electrically connected to the first node N1.

[0056] Combination Figure 2 As shown, Figure 2 for Figure 1 A timing diagram of the pixel circuit shown in FIG. 1 , a driving cycle of the pixel circuit 11 includes a writing frame Z01 and a holding frame Z02, the writing frame Z01 includes an initialization phase Z1, a data writing phase Z2, a light emitting phase Z3, and an adjustment phase Z4, the adjustment phase Z4 can be executed before the initialization phase Z1, and is executed between the data writing phase Z2 and the light emitting phase Z3. The holding frame Z02 includes the light emitting phase Z3 and the adjustment phase Z4 executed before the light emitting phase Z3, and the holding frame does not include the initialization phase Z1 and the data writing phase Z2.

[0057] In the initialization stage Z1, the gate reset scan line S1 provides an enable signal (such as a low-level signal), the gate reset transistor T1 is turned on, and the gate reset transistor T1 writes the gate reset voltage provided by the gate reset signal line Vref1 into the first node N1 to initialize the potential of the first node N1. Since the first node N1 is electrically connected to the gate of the driving transistor Td, the gate potential of the driving transistor Td can be initialized.

[0058] In the data writing stage Z2, the first control line SP provides an enable signal (such as a low-level signal), the data writing transistor T2 and the threshold grabbing transistor T3 are turned on, the data writing transistor T2 and the threshold grabbing transistor T3 write the data voltage provided by the data signal line Data into the first node N1, and realize the threshold compensation of the driving transistor Td.

[0059] In the adjustment stage Z4, the second control line SP* provides an enable signal (such as a low level signal), the bias transistor T4 and the reset transistor T7 are turned on, the bias transistor T4 writes the bias voltage provided by the bias signal line VDH into the first electrode of the driving transistor Td, and adjusts the bias state of the driving transistor Td. The reset transistor T7 writes the reset voltage provided by the reset signal line Vref2 into the first electrode of the light emitting device 12, and resets the first electrode of the light emitting device 12.

[0060] In the light-emitting stage Z3, the light-emitting control signal line EM provides an enable signal (such as a low-level signal), the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting drive current converted according to the data voltage and the power supply voltage provided by the power signal line PVDD is transmitted to the light-emitting device 12 to control the light-emitting device 12 to emit light.

[0061] During the operation of the pixel circuit 11 , the enable signal provided by the gate reset scan line S1 , the first control line SP, the second control line SP*, and the light emitting control signal line EM may be a low level signal VGL, and the disable signal provided may be a high level signal VGH.

[0062] The inventors of the present application discovered during the research process that when the display panel performs low-frequency display, the pixel circuit 11 maintains a longer frame time, and the off-state leakage current of the switching transistor will have a greater impact on the gate potential of the driving transistor Td.

[0063] Specifically, when the signal on the first control line SP jumps from the low-level signal VGL to the high-level signal VGH, due to the coupling between the gate and source of the threshold capture transistor T3, the potential of the second node N2 will be pulled up, and the potential of the second node N2 will leak to the first node N1 through the second sub-transistor T32, causing the potential of the first node N1 to increase, thereby causing the brightness within a display frame to continuously decrease, causing the picture displayed by the display panel to flicker significantly.

[0064] Since the increase in the potential of the second node N2 is caused by the signal jump on the first control line SP, the inventor proposes to improve the flicker problem of the display panel during low-frequency display by reducing the potential of the high-level signal VGH.

[0065] like Figure 3 As shown, Figure 3 A schematic diagram of the relationship between the potential of a high-level signal and the screen flicker value provided in an embodiment of the present application, when the potential of the high-level signal VGH is 4V, the flicker value Flicker is -44.46dB, when the potential of the high-level signal VGH is 5V, the flicker value Flicker is -43.58dB, when the potential of the high-level signal VGH is 6V, the flicker value Flicker is -42.67dB, when the potential of the high-level signal VGH is 7V, the flicker value Flicker is -41.74dB, when the potential of the high-level signal VGH is 8V, the flicker value Flicker is -40.75dB.

[0066] On the scale of the flicker value Flicker, the larger the absolute value of the number is, the lower the degree of flicker is. Therefore, it can be seen that the lower the potential of the high-level signal VGH is, the better the effect of improving the flicker problem of the display panel is.

[0067] However, the inventors discovered through further research that when the potential of the high-level signal VGH is reduced to a certain level, the data write transistor T2 may not be able to be turned off, resulting in the data write transistor T2 leaking the data voltage on the data signal line Data to the first node N1 during the period when the light-emitting control signal line EM transmits a non-enable signal (high-level signal), thereby causing display abnormalities.

[0068] Specifically, if the data write transistor T2 is completely turned off, |Vgs|=|VH-VGMP|<|Vth|, Vgs is the gate-source voltage of the data write transistor T2, and Vth is the threshold voltage of the data write transistor T2. Here, VH is the potential of the non-enable signal (high level signal VGH) provided by the first control line SP, and VGMP is the maximum data voltage received by the data write transistor T2. When the potential of the high level signal VGH decreases, VH is usually less than VGMP, and the smaller VH is, the larger |VH-VGMP| will be, and it will be more difficult to achieve |VH-VGMP|<|Vth|, which makes it difficult to turn off the data write transistor T2.

[0069] Moreover, in a high temperature environment, the threshold voltage of the data write transistor T2 is easily positive, that is, |Vth| is too small, which further makes it difficult to achieve |VH-VGMP|<|Vth|, and the data write transistor T2 is easily unable to be turned off.

[0070] In view of this, an embodiment of the present application further provides a display panel 01, which can reduce the potential of the high-level signal VGH and improve the flickering problem of the display panel while improving the ability to turn off the data writing transistor, thereby further improving the display effect.

[0071] like Figure 4 As shown, Figure 4 A schematic plan view of a display panel provided in an embodiment of the present application, wherein the display panel 01 includes a plurality of sub-pixels 10, wherein the sub-pixels 10 include a pixel circuit 11 and a light-emitting device 12 electrically connected to each other, and the circuit structure of the pixel circuit 11 can be as follows: Figure 1 As shown, the pixel circuit 11 includes multiple transistors, including a driving transistor Td and a data writing transistor T2. The driving transistor Td is used to generate a light-emitting driving current. The data writing transistor T2 is coupled between the driving transistor Td and the data signal line Data. The data writing transistor T2 is used to transmit the data voltage transmitted by the data signal line Data to the driving transistor Td.

[0072] It should be noted that if Figure 1 The connection mode of the data writing transistor T2 shown is only for illustration, and other transistors may be provided between the data writing transistor T2 and the driving transistor Td. Of course, other transistors may also be provided between the data writing transistor T2 and the data signal line Data, and the embodiment of the present application does not make any specific limitation, as long as the data voltage needs to be transmitted to the driving transistor Td through the data writing transistor T2.

[0073] Combination Figure 5 As shown, Figure 5A schematic diagram of the structure of a display panel provided in an embodiment of the present application, the display panel 01 includes a substrate 20 and an array layer 30 located on one side of the substrate 20, the array layer 30 includes a pixel circuit 11, that is, the pixel circuit 11 can be located in the array layer 30 of the display panel 01. The pixel circuit 11 includes a plurality of transistors T, the transistor T includes a semiconductor layer 31, and the semiconductor layer 31 includes a channel C. The semiconductor layer 31 may include a material silicon.

[0074] The plurality of transistors T include a data writing transistor T2, and the semiconductor layer 31 of the data writing transistor T2 includes a first channel C1, that is, the channel of the data writing transistor T2 may be the first channel C1. The first channel C1 includes a first doping element m1 and a second doping element m2, and the number of electrons of the first doping element m1 is different from the number of electrons of the second doping element m2.

[0075] In the manufacturing process of the display panel, the channel type of the transistor can be determined by controlling the doping elements in the transistor channel and affecting the threshold voltage of the transistor.

[0076] In the embodiment of the present application, a first channel C1 of the data writing transistor T2 is provided, including a first doping element m1 and a second doping element m2 with different electron numbers. The difference in the number of electrons between the first doping element m1 and the second doping element m2 can be utilized to adjust the concentration of carriers in the first channel C1, which is conducive to making the threshold voltage of the data writing transistor T2 negative.

[0077] From the above analysis, it can be seen that by making the threshold voltage of the data write transistor T2 negative, |Vth| can be increased. Even if the potential VH of the high-level signal VGH is reduced, it is easier to make |VH-VGMP|<|Vth|, that is, it is easier to achieve |Vgs|=|VH-VGMP|<|Vth|, which is beneficial to control the data write transistor T2 to be better turned off. While improving the flicker problem of the display panel, it is beneficial to avoid the problem of display abnormality caused by the inability to effectively turn off the data write transistor T2.

[0078] like Figure 5 As shown, the semiconductor layer 31 further includes a first heavily doped region a1 and a second heavily doped region a2, and the first heavily doped region a1 and the second heavily doped region a2 are located on opposite sides of the channel C. The transistor T further includes a gate G located on a side of the semiconductor layer 31 away from the substrate 10, and a first electrode S and a second electrode D. An inter-gate insulating layer GI is provided between the gate G and the semiconductor layer 31. The gate G may cover the channel C of the transistor T along a direction H perpendicular to the plane where the display panel 01 is located.

[0079] In the process of the display panel, after a certain dose of the first doping element m1 is injected into the semiconductor layer 31 of the transistor T, a certain dose of the second doping element m2 is injected into the first channel C1 of the data writing transistor T2 to negatively adjust the threshold voltage of the data writing transistor T2 so that the threshold voltage of the data writing transistor T2 is biased negative. After that, subsequent film layers such as the inter-gate insulating layer GI, the gate G, the first electrode S, and the second electrode D can be prepared in sequence. The first heavily doped region a1 and the second heavily doped region a2 can be prepared after the preparation of the gate G is completed.

[0080] Optionally, the first doping element m1 includes at least one of boron, gallium, and indium, and the second doping element m2 includes at least one of phosphorus, arsenic, and antimony.

[0081] Among them, the outermost layer of atoms in the first doping element m1 includes 3 electrons, and the outermost layer of atoms in the second doping element m2 includes 5 electrons. Taking the semiconductor layer 31 including material silicon as an example, the outermost layer of silicon atoms includes 4 electrons. When the first doping element m1 is injected into the silicon material, the atoms in the first doping element m1 can replace some silicon atoms, and one electron in the original silicon atom jumps to the vacancy to form a hole. When the second doping element m2 is injected into the silicon material, the second doping element m2 will replace some silicon atoms, and the excess electrons in the second doping element m2 will become active free electrons. Due to diffusion movement, the free electrons will form a composite pair with the holes, reducing the concentration of effective holes in the channel, thereby requiring a larger electric field to form an effective conductive channel, making the threshold voltage of the data writing transistor T2 negative.

[0082] Optionally, in the first channel C1, the concentration of the second doping element m2 is less than the concentration of the first doping element m1. Based on this setting, it can be ensured that the carriers in the first channel C1 are mainly generated by the injection of the first doping element m1, which is conducive to avoiding the problem that the injection of the second doping element m2 causes too few carriers in the first channel C1, resulting in excessive reduction in the performance of the data writing transistor T2.

[0083] Moreover, setting the concentration of the second doping element m2 to be smaller than the concentration of the first doping element m1 is also beneficial to avoid changing the channel type of the first channel C1, resulting in a situation where the channel type of the data writing transistor T2 is different from the channel type of other transistors, such as causing the channel types of the data writing transistor T2 and the threshold grabbing transistor T3 connected to the same first control line SP to be different, thereby helping to avoid control failure of the pixel circuit 11.

[0084] Exemplarily, the data writing transistor T2 is a P-type transistor.

[0085] Please continue to refer to Figure 5In one embodiment of the present application, the driving transistor Td includes a second channel C2, and the second channel C2 is located in the semiconductor layer 31 of the driving transistor Td. The second channel C2 and the first channel C1 may be located in the same layer.

[0086] The second channel C2 includes a first doping element m1.

[0087] In the embodiment of the present application, the first channel C1 and the second channel C2 are both doped with the first doping element m1. On the one hand, it is beneficial to make the types of carriers in the first channel C1 and the second channel C2 the same, so that the channel type of the driving transistor Td is the same as the channel type of the data writing transistor T2, which is beneficial to reduce the structural complexity of the pixel circuit 11, thereby reducing the difficulty of preparing and controlling the pixel circuit 11; on the other hand, the first channel C1 and the second channel C2 are both doped with the first doping element m1. Then, in the process of the display panel, a certain dose of the first doping element m1 can be injected into the first channel C1 and the second channel C2 at the same time, which is beneficial to simplify the preparation process of the display panel and reduce the preparation cost.

[0088] Exemplarily, the driving transistor Td is a P-type transistor.

[0089] Optionally, the second doping element m2 is not provided in the second channel C2. In the process of the display panel, after the first doping element m1 is injected, a certain dose of the second doping element m2 can be injected into the first channel C1 of the data writing transistor T2 alone, without injecting the second doping element m2 into the second channel C2.

[0090] In this way, only the threshold voltage of the data writing transistor T2 can be adjusted to be negative biased, without affecting the threshold voltage of the driving transistor Td, which is conducive to achieving targeted adjustment of the threshold voltage of the data writing transistor T2.

[0091] Furthermore, in the pixel circuit 11, except for the data writing transistor T2 and the driving transistor Td, the channels of other transistors may be doped with only the first doping element m1, without doping with the second doping element m2. In this way, the channel types of each transistor in the pixel circuit 11 are the same, further reducing the structural complexity of the pixel circuit. In addition, the first doping element m1 can be injected into the channels of each transistor at the same time, which is conducive to further simplifying the manufacturing process of the display panel.

[0092] In the process of the display panel, before injecting the second doping element m2 into the data writing transistor T2, a protective material can be used to cover the channels of other transistors in the pixel circuit, so that the second doping element m2 can be injected into the data writing transistor T2 alone without causing the channels of other transistors to be injected with the second doping element m2.

[0093] Optionally, the type of majority carriers in the first channel C1 is the same as the type of majority carriers in the second channel C2. For example, the majority carriers in the first channel C1 and the majority carriers in the second channel C2 are both holes.

[0094] Based on this configuration, it can be ensured that the channel type of the driving transistor Td is the same as the channel type of the data writing transistor T2, which is beneficial to reduce the structural complexity of the pixel circuit 11, and further reduce the difficulty of manufacturing and controlling the pixel circuit 11.

[0095] Optionally, the concentration of majority carriers in the first channel C1 is less than that in the second channel C2. For example, the majority carriers in the first channel C1 and the majority carriers in the second channel C2 are holes, and the concentration of holes in the first channel C1 is less than that in the second channel C2.

[0096] This is because the first channel C1 is doped with the second doping element m2, and the second doping element m2 and the first doping element m1 are injected into the semiconductor layer 31 to generate different types of carriers, and two different types of carriers (such as holes and free electrons) neutralize each other, thereby reducing the concentration of the majority carriers in the first channel C1. The embodiment of the present application can adjust the threshold voltage of the data writing transistor T2 by adjusting the concentration of the majority carriers in the first channel C1.

[0097] In addition, in some other embodiments, the threshold voltage of the data writing transistor T2 may be made negative by not doping elements into the first channel C1. That is, after the semiconductor layer 31 is formed, the first channel C1 is no longer doped.

[0098] For example, after the semiconductor layer 31 of the transistor T is prepared, a certain dose of the first doping element m1 is injected into the channels of the other transistors except the data writing transistor T2, and then the inter-gate insulating layer GI, the gate G and other film layers are sequentially prepared. The inventors of the present application have found through research that based on this setting, the threshold voltage of the data writing transistor T2 can be made negative by about 0.7V.

[0099] Please continue to refer to Figure 1 In one embodiment of the present application, a first electrode of the data writing transistor T2 is electrically connected to the data signal line Data, a second electrode is electrically connected to the first electrode of the driving transistor Td, and a gate is electrically connected to the first control line SP.

[0100] The plurality of transistors include a threshold grabbing transistor T3 , a first electrode of the threshold grabbing transistor T3 is electrically connected to a second electrode of the driving transistor Td, a second electrode of the threshold grabbing transistor T3 is electrically connected to a gate of the driving transistor Td, and a gate of the threshold grabbing transistor T3 is electrically connected to a first control line SP.

[0101] The data writing transistor T2 and the threshold grabbing transistor T3 have the same channel type, and the signal provided by the first control line SP controls the data writing transistor T2 and the threshold grabbing transistor T3 to have the same switching state.

[0102] Exemplarily, both the data writing transistor T2 and the threshold grabbing transistor T3 are P-type transistors.

[0103] Optional, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present application, wherein the channel of the threshold grabbing transistor T3 includes the first doping element m1 but does not include the second doping element m2.

[0104] In addition, it can be known from the working process of the aforementioned pixel circuit 11 that the threshold capture transistor T3 can cooperate with the data writing transistor T2 to write the data voltage into the gate of the driving transistor Td. Therefore, the threshold voltage of the threshold capture transistor T3 can also be negatively adjusted to improve the ability of the non-enable signal (high level signal VGH) transmitted by the first control line SP to turn off the threshold capture transistor T3.

[0105] Optional, such as Figure 7 As shown, Figure 7 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, wherein the channel of the threshold capture transistor T3 includes a first doping element m1 and a second doping element m2. In this way, the threshold voltage of the threshold capture transistor T3 can be made negative, which is beneficial to improving the ability of the display panel to turn off the threshold capture transistor T3, thereby further preventing the data voltage from being transmitted to the gate of the driving transistor, which causes display abnormality, while improving the flicker problem of the display panel.

[0106] In the process of the display panel, a certain dose of the first doping element m1 can be simultaneously injected into the channels of the data writing transistor T2 and the threshold grabbing transistor T3, and then a certain dose of the second doping element m2 can be simultaneously injected into the channels of the data writing transistor T2 and the threshold grabbing transistor T3.

[0107] Please continue to refer to Figure 1 In one embodiment of the present application, the threshold grabbing transistor T3 includes a first sub-transistor T31 and a second sub-transistor T32, the first electrode of the first sub-transistor T31 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the first electrode of the second sub-transistor T32, and the second electrode of the second sub-transistor T32 is electrically connected to the gate of the driving transistor Td. A second node N2 is provided between the second electrode of the first sub-transistor T31 and the first electrode of the second sub-transistor T32. The first sub-transistor T31 and the second sub-transistor T32 are connected in series.

[0108] The gate of the first sub-transistor T31 and the gate of the second sub-transistor T32 are both electrically connected to the first control line SP.

[0109] Exemplarily, the first sub-transistor T31 and the second sub-transistor T32 have the same channel type, and the signal provided by the first control line SP controls the first sub-transistor T31 and the second sub-transistor T32 to have the same switching state.

[0110] In the embodiment of the present application, the threshold capture transistor T3 is set to include a first sub-transistor T31 and a second sub-transistor T32 connected in series. Then, during the period when the first control line SP provides a non-enable signal, the first sub-transistor T31 and the second sub-transistor T32 connected in series can increase the difficulty of the second pole of the driving transistor Td to leak the gate of the driving transistor Td, which is beneficial to improving the stability of the gate potential of the driving transistor Td, thereby helping to improve the display effect of the display panel 01.

[0111] Figure 8 A process flow chart of a display panel manufacturing method provided in an embodiment of the present application.

[0112] The present application also provides a method for preparing a display panel, which is used to prepare the display panel 01 provided in the above embodiment. The structure of the display panel 01 can be as follows: Figure 4-Figure 7 As shown, Figure 8 As shown, the preparation method comprises:

[0113] Step B1: providing a substrate 10 , and preparing a semiconductor layer 31 of a transistor T on one side of the substrate 10 .

[0114] Illustratively, the semiconductor layer 31 includes silicon.

[0115] Step B2: implanting the first doping element m1 into the semiconductor layer 31 of the transistor T.

[0116] Exemplarily, the first doping element m1 includes at least one of boron, gallium, and indium.

[0117] Step B3: injecting a second doping element m2 into the channel of the data writing transistor T2.

[0118] That is, the second doping element m2 is implanted into the first channel C1. Exemplarily, the second doping element m2 includes at least one of phosphorus, arsenic, and antimony.

[0119] In the preparation method provided in the embodiment of the present application, a first channel C1 of the data writing transistor T2 is set, including a first doping element m1 and a second doping element m2 with different electron numbers. The difference in the number of electrons between the first doping element m1 and the second doping element m2 can be utilized to adjust the concentration of carriers in the first channel C1, which is conducive to making the threshold voltage of the data writing transistor T2 negative.

[0120] From the above analysis, it can be seen that by making the threshold voltage of the data write transistor T2 negative, |Vth| can be increased. Even if the potential VH of the high-level signal VGH is reduced, it is easier to make |VH-VGMP|<|Vth|, that is, it is easier to achieve |Vgs|=|VH-VGMP|<|Vth|, which is beneficial to control the data write transistor T2 to be better turned off. While improving the flicker problem of the display panel, it is beneficial to avoid the problem of display abnormality caused by the inability to effectively turn off the data write transistor T2.

[0121] Fig. 9 A flow chart of a manufacturing process of another display panel provided in an embodiment of the present application.

[0122] In one embodiment of the present application, Fig. 9 As shown, before the second doping element m2 is implanted into the channel of the data writing transistor T2, the method further includes:

[0123] Step B31 : a protective material PR is disposed on the semiconductor layer 31 , and the protective material PR covers the channels of the transistors T except the data writing transistor T2 .

[0124] like Fig. 9 As shown, step B31 can be performed after step B2 and before step B3.

[0125] Exemplarily, the protective material PR is a photoresist, which can prevent the second doping element m2 from penetrating and is relatively easy to be stripped in subsequent processes, thereby reducing the difficulty of manufacturing the display panel.

[0126] In the embodiment of the present application, a protective material PR is first provided to cover the channels of other transistors T except the data writing transistor T2, and then the second doping element m2 is injected into the channel of the data writing transistor T2. This can prevent the second doping element m2 from being injected into the channels of other transistors and affecting the threshold voltages of other transistors, and is conducive to achieving targeted adjustment of the threshold voltage of the data writing transistor T2.

[0127] Fig.10 A flow chart of a manufacturing process of another display panel provided in an embodiment of the present application.

[0128] In one embodiment of the present application, Fig.10 As shown, after the second doping element m2 is implanted into the channel of the data writing transistor T2, the method further includes:

[0129] Step B4: Removing the protective material PR.

[0130] Further, such as Fig.10 As shown, after completing step 4, the preparation method further includes:

[0131] Step B5: forming an inter-gate insulating layer GI on the semiconductor layer 31 .

[0132] Step B6: Prepare the gate G of the transistor on the inter-gate insulating layer GI.

[0133] From the above analysis, it can be seen that the protective material PR is a transition material used in the display panel manufacturing process. Removing the protective material PR can prevent the protective material PR from affecting the fit of the display panel film layer, such as affecting the fit between the inter-gate insulating layer GI and the semiconductor layer 31, thereby avoiding affecting the display panel yield. In the embodiment of the present application, the protective material PR can be stripped by ultrasound or chemical solvent.

[0134] Fig.11 A schematic diagram of a display device provided in an embodiment of the present application.

[0135] The present application embodiment provides a display device 02, such as Fig.11 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. Exemplarily, the display device 02 can be an electronic device such as a mobile phone, a computer, a television, a car display, etc., which is not specifically limited in this application.

[0136] In the display device, a first channel C1 of a data writing transistor T2 is provided, including a first doping element m1 and a second doping element m2 having different electron numbers. The difference in the electron numbers between the first doping element m1 and the second doping element m2 can be utilized to adjust the concentration of carriers in the first channel C1, which is conducive to making the threshold voltage of the data writing transistor T2 negative.

[0137] From the above analysis, it can be seen that by making the threshold voltage of the data write transistor T2 negative, |Vth| can be increased. Even if the potential VH of the high-level signal VGH is reduced, it is easier to make |VH-VGMP|<|Vth|, that is, it is easier to achieve |Vgs|=|VH-VGMP|<|Vth|, which is beneficial to control the data write transistor T2 to be better turned off. While improving the flicker problem of the display panel, it is beneficial to avoid the problem of display abnormality caused by the inability to effectively turn off the data write transistor T2.

[0138] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: comprising a plurality of sub-pixels, each of which comprises a pixel circuit and a light-emitting device electrically connected to each other; The pixel circuit includes a plurality of transistors, wherein the plurality of transistors include: A driving transistor, the driving transistor is used to generate a light-emitting driving current; A data writing transistor, coupled between the driving transistor and the data signal line, the data writing transistor being used to transmit the data voltage transmitted by the data signal line to the driving transistor; The data writing transistor includes a first channel, the first channel includes a first doping element and a second doping element, and the number of electrons in the first doping element is different from the number of electrons in the second doping element.

2. The display panel according to claim 1, characterized in that: The first doping element includes at least one of boron, gallium, and indium, and the second doping element includes at least one of phosphorus, arsenic, and antimony.

3. The display panel according to claim 1, characterized in that: In the first channel, a concentration of the second doping element is lower than a concentration of the first doping element.

4. The display panel according to claim 1, characterized in that: The driving transistor includes a second channel including the first doping element.

5. The display panel according to claim 4, characterized in that: The type of majority carriers in the first channel is the same as the type of majority carriers in the second channel.

6. The display panel according to claim 4, characterized in that: The concentration of majority carriers in the first channel is less than the concentration of majority carriers in the second channel.

7. The display panel according to claim 1, characterized in that: The data writing transistor is a P-type transistor.

8. The display panel according to claim 1, characterized in that: The data writing transistor has a first electrode electrically connected to the data signal line, a second electrode electrically connected to the first electrode of the driving transistor, and a gate electrically connected to the first control line; The plurality of transistors include a threshold grabbing transistor, wherein a first electrode of the threshold grabbing transistor is electrically connected to a second electrode of the driving transistor, a second electrode of the threshold grabbing transistor is electrically connected to a gate of the driving transistor, and a gate of the threshold grabbing transistor is electrically connected to the first control line; The data writing transistor and the threshold grabbing transistor have the same channel type.

9. The display panel according to claim 8, characterized in that: The threshold grabbing transistor includes a first sub-transistor and a second sub-transistor, wherein the first electrode of the first sub-transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the first sub-transistor is electrically connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is electrically connected to the gate of the driving transistor; The gate of the first sub-transistor and the gate of the second sub-transistor are both electrically connected to the first control line.

10. A method for preparing a display panel, characterized in that: Used to prepare a display panel according to any one of claims 1 to 9; the preparation method comprises: Providing a substrate, and preparing a semiconductor layer of the transistor on one side of the substrate; injecting the first doping element into the semiconductor layer of the transistor; The second doping element is implanted into the channel of the data writing transistor.

11. The method according to claim 10, characterized in that Before implanting the second doping element into the channel of the data writing transistor, the method further includes: A protection material is disposed on the semiconductor layer, and the protection material covers channels of the transistors other than the data writing transistor.

12. The method according to claim 11, characterized in that After implanting the second doping element into the channel of the data writing transistor, the method further includes: The protective material is removed.

13. The method according to claim 11, characterized in that The protective material is photoresist.

14. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-9.

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