Solar cell and preparation method thereof

Abstract

The invention discloses a preparation method of a solar cell. The preparation method comprises the following steps: selecting an N-type monocrystalline silicon substrate; depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface; the method comprises the following steps of: flatly placing the front surface of a silicon substrate on a carrier plate, coating a liquid dopant on the back surface, drying and annealing to form an N-type doped poly layer; laser grooving is used to obtain a P region in which a P + doped region is to be formed; texturing is carried out; sequentially depositing an intrinsic amorphous silicon layer and an anti-reflection film on the front surface; sequentially depositing an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the back surface; partially splitting the film by using laser to expose the PSG layer on the N region; pickling the PSG layer, and exposing the N-type doped poly layer below the PSG layer; depositing a TCO conductive film layer on the whole back surface; and performing laser grooving, forming an isolation groove, insulating the N region and the P region, preparing a metal electrode, and performing sintering and curing to obtain the BC battery. According to the method, the winding plating is directly removed before annealing, and the technological process is greatly simplified.

Description

Technical Field

[0001] The invention relates to the technical field of photovoltaic cell manufacturing, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Solar cells are devices that convert solar energy into electrical energy. The current mainstream solar cells include PERC cells, TOPCON cells, and BC cells. The conversion efficiency of solar cells determines the power generation capacity of solar cells, and the preparation process of solar cells determines the production cost of solar cells. The conversion efficiency of the current mainstream solar cells still has room for further improvement, and the preparation cost also has room for further reduction. Summary of the invention

[0003] The object of the present invention is to provide a solar cell and a method for preparing the same, combining the respective advantages of HBC and TBC, improving the passivation and hot spot resistance capabilities, and improving the conversion efficiency of the solar cell, while simplifying the preparation process, avoiding the risk of bypass expansion, enhancing the process controllability, and reducing the preparation cost of the solar cell.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for preparing a BC battery, comprising the following steps:

[0005] Step S1: Select an N-type single crystal silicon substrate; perform pre-cleaning and double-sided polishing;

[0006] Step S2: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon substrate;

[0007] Step S3: firstly, the front side of the silicon substrate is placed flat on a carrier, and then a liquid dopant is coated on the back side and dried and annealed to crystallize the amorphous silicon and activate the impurities to form an N-type doped poly layer;

[0008] The annealing temperature is 600-700°C and the annealing time is 1-3 minutes;

[0009] The carrier plate fixes the silicon substrate flatly on the carrier plate by negative pressure adsorption;

[0010] Step S4: using a laser to groove the N-type doped poly layer, and etching and cleaning to obtain a P region to be formed as a P+ doped region; the region not grooved is the N region;

[0011] Step S5: performing texturing on the front side of the silicon substrate;

[0012] Step S6: depositing an intrinsic amorphous silicon layer and an anti-reflection film in sequence on the front surface of the silicon substrate;

[0013] Step S7: depositing an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on the back side of the silicon substrate;

[0014] Step S8: using a laser to partially open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer on the N region on the back side of the silicon substrate to expose the PSG layer on the N region;

[0015] Step S9: pickling the PSG layer on the exposed N region to expose the N-type doped poly layer thereunder;

[0016] Step S10: depositing a TCO conductive thin film layer on the entire back surface of the silicon substrate;

[0017] Step S11: using a laser to open a groove on the back side of the silicon substrate to expose the PSG layer and form an isolation groove to insulate the N region and the P region to prevent leakage caused by the interconnection of the N / P regions;

[0018] Step S12: Prepare metal electrodes in the P region and the N region on the back side of the silicon substrate, sinter and solidify them, and then obtain the BC battery.

[0019] Preferably, in step S4: use a laser to groove the N-type doped poly layer, etch and clean it, and when the silicon substrate is exposed, continue to etch 2-5 microns into the silicon substrate to etch away the inwardly expanded phosphorus) to obtain a P region to be formed as a P+ doped region, the P region is recessed 2-5 microns inwardly relative to the N region, the width of the P region is greater than that of the N region, and there is no requirement for thickness.

[0020] The anti-reflection film in step S6 is preferably SiNx with a thickness of 80-100 nm.

[0021] Preferably, in step S2: the thickness of the tunneling oxide layer is 1-3 nm; the thickness of the intrinsic amorphous silicon layer is 280-330 nm.

[0022] Preferably, in step S3, the liquid dopant contains a Group V element, and the Group V element is selected from one or more of N, P, As, Sb, and Bi.

[0023] Preferably, in step S3: the carrier has a heating function, and the liquid dopant is dried by heating the carrier.

[0024] Preferably, in step S3, the annealing temperature is 610-630° C., and the annealing time is 80-100 seconds.

[0025] Preferably, in step S4: the etching cleaning is performed by immersion or floating on a solution, and the reagent used for the etching cleaning is a KOH solution or a HF / HCl mixed solution.

[0026] Preferably, in step S10: a TCO conductive thin film layer is deposited on the back side of the silicon substrate using a PVD method, and the thickness of the TCO conductive thin film layer is 70-100 nm.

[0027] Preferably, in step S3, the coating is performed by spin coating, roll coating or spray coating.

[0028] Preferably, in step S3: the annealing is performed in a tube furnace or a chain furnace.

[0029] The present invention also claims protection for a BC battery prepared by the above preparation method. The battery combines the respective advantages of HBC and TBC, is a new BC battery structure, and has better conversion efficiency.

[0030] Preferably, the BC cell comprises an N-type single crystal silicon substrate, the N-type single crystal silicon substrate has a front side and a back side opposite to each other, and a plurality of first regions and second regions are alternately arranged on the back side of the N-type single crystal silicon substrate along a first direction;

[0031] The first direction intersects with the thickness direction of the N-type single crystal silicon substrate;

[0032] The first region includes a tunneling oxide layer and an N-type doped poly layer sequentially arranged in a direction away from the back side of the substrate, and the second region includes a back intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, and a TCO conductive film layer sequentially arranged in a direction away from the back side of the substrate;

[0033] The surface of the N-type doped poly layer has a third region and a fourth region arranged at both ends of the third region along the first direction; the fourth region is divided into two sub-regions and a spacing region between the two sub-regions, and the two sub-regions are arranged at intervals along the first direction;

[0034] The sub-region includes a back intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, and a TCO conductive film layer arranged in sequence in a direction away from the back side of the substrate, and the P-type doped amorphous silicon layer of the second region is in contact with the back intrinsic amorphous silicon layer of the adjacent sub-region;

[0035] A TCO conductive film layer is disposed on the third region of the surface of the N-type doped poly layer;

[0036] The TCO conductive film layer of the sub-region is connected with the TCO conductive film layers of the adjacent third region and the second region respectively.

[0037] Preferably, the front side of the N-type single crystal silicon substrate is provided with a textured structure, a front intrinsic amorphous silicon layer and an anti-reflection layer in sequence in the direction away from the front side of the substrate. The textured structure and anti-reflection layer of the front side are both prior art and will not be described in detail.

[0038] Preferably, it further comprises a first electrode and a second electrode, wherein the first electrode is printed on the TCO conductive film layer located in the third area, and the second electrode is printed on the TCO conductive film layer located in the second area.

[0039] Due to the application of the above technical solution, the beneficial effects of the present application compared with the prior art are:

[0040] 1. The present application adopts a single-sided coating of liquid dopants to introduce doping elements on the back side of the silicon wafer, and first places the front side of the silicon substrate flat on a carrier. The front side of the silicon wafer is adsorbed and shielded by the carrier, avoiding the risk of dopants being coated around the front side of the silicon wafer, and the carrier has a heating function, which can complete the curing in one step of coating and drying, and then annealing is used for crystallization + doping of phosphorus atoms (impurity promotion and activation). Since the front side is protected by a barrier layer BSG with a thickness of 50 to 120 nm, and the diffusion rate of phosphorus atoms in the barrier layer BSG is very low, the present application controls the annealing time to prevent the phosphorus atoms from penetrating the barrier layer BSG and spreading around to the front side, ultimately avoiding the risk of spreading around. It can be seen that the present application realizes the direct removal of plating before annealing, thereby greatly simplifying the process flow.

[0041] 2. In step S4 of the present application, a laser is used to groove the N-type doped poly layer to expose the P-type doped layer. Compared with the existing HBC battery preparation process, it does not require multiple use of masking and demasking technology to form patterning, which reduces the process difficulty and improves production efficiency.

[0042] 3. The present application can control the doping concentration by adjusting the concentration of the liquid dopant, and control the degree of crystallization and the inward expansion of the oxide layer through the annealing process, thereby achieving enhanced process controllability.

[0043] 4. In the battery structure of the present application, a P-type passivation contact area is stacked on the first area adjacent to the N-type passivation contact area and the P-type passivation contact area, and a spacer area (isolation groove or gap) is used to isolate the N-type area and the P-type area. The spacer area is located on the first area, and penetrates the TCO conductive film covering the P area and the N area and the P-type passivation contact area stacked on the first area until the N-type passivation contact area. Through the above-mentioned structural setting, it is possible to avoid damaging the N-poly of the N-type passivation contact area when processing the spacer area. In addition, a P-type passivation contact area is stacked on the first area and partially contacts the P-type area. The contact area forms multiple leakage points, which reduces the reverse breakdown voltage of the battery. When the battery cell is reversely cut off, more leakage generates less heat, which is beneficial to reduce the impact of hot spots. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figures 1 to 11 This is a process flow chart for preparing the BC battery of the present invention.

[0046] Fig.12 It is a schematic diagram of the cross-sectional structure of the BC battery in Example 2 of the present disclosure.

[0047] Among them: 1. N-type single crystal silicon substrate; 2. tunneling oxide layer; 3. intrinsic amorphous silicon layer; 4. N-type doped poly layer; 5. anti-reflection film; 6. intrinsic amorphous silicon layer; 7. P-type doped amorphous silicon layer; 8. TCO conductive film layer; 9. metal electrode; 20. first electrode; 30. second electrode; 40. spacer area. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0051] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0052] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] See also Figures 1 to 11 , a method for preparing a BC battery, comprising the following steps:

[0055] Step S1: Select an N-type single crystal silicon substrate 1 with a thickness of 150 μm; perform pre-cleaning and double-sided polishing; it can be understood that the silicon substrate can also be a P-type single crystal silicon substrate, which is not limited in the present disclosure, and this embodiment is described by taking an N-type single crystal silicon substrate as an example;

[0056] Polishing and cleaning: Place the above-mentioned N-type single crystal silicon substrate into a tank-type alkaline polishing machine for polishing and cleaning: First, pre-clean the silicon wafer to remove organic and other contaminants generated during the silicon wafer cutting and transportation process: Place it in a hydrogen peroxide alkaline solution with a concentration of 0.2-1% to clean the surface oil stains; Wash the residual chemicals with water and then perform alkaline polishing: The alkaline solution is a KOH solution with a concentration of 5-20%, a temperature of 70°C, and a time of 300 seconds; Then perform SC1 cleaning, ozone cleaning, and finally acid washing and dehydration to complete polishing and cleaning;

[0057] Step S2: depositing a tunnel oxide layer 2 and an intrinsic amorphous silicon layer 3 on the back side of the silicon substrate; Figure 2 , specifically as follows: put the cleaned polished wafer into the LPCVD equipment, grow a 1-3nm tunneling oxide layer at 500-700℃; grow an intrinsic poly layer at 550-650℃, with a thickness of 280-330nm;

[0058] Step S3: First, place the front side of the silicon substrate flat on a carrier, then coat the back side with a phosphorus-containing liquid dopant, and dry it at 100-200°C for 10-120s; then anneal it in a tube furnace to crystallize the amorphous silicon and promote and activate the impurities (phosphorus) to form an N-type doped poly layer 4; see Figure 3 ;

[0059] The annealing temperature is 650° C., the annealing time is 1.5 min, the pressure is normal, and the atmosphere is nitrogen;

[0060] The carrier plate fixes the silicon substrate flatly on the carrier plate by negative pressure adsorption;

[0061] Step S4: Use laser to groove the N-type doped poly layer, etch and clean it, expose the silicon substrate (or etch 2-5 microns into the silicon substrate to etch away the inwardly expanded phosphorus), and obtain the P region to be formed into the P+ doped region, the P region is concave 2-5 microns inward relative to the N region, and the width of the P region is greater than that of the N region; the area not grooved is the N region; see Figure 4 ;

[0062] The laser adopts green nanosecond laser with a wavelength of 532nm and a pulse width of nanosecond level; the etching and cleaning is immersion type or solution floating type, and the reagents used in the etching and cleaning are KOH solution and HF / HCl mixed solution;

[0063] Step S5: Texturing is performed on the front side of the silicon substrate; see Figure 5 ;

[0064] In this embodiment, the front surface is textured by RIE plasma etching method. The process of the RIE plasma etching method is as follows: placing a silicon wafer in a carrier for plasma etching and sending it into a plasma etching equipment cavity; evacuating the equipment, maintaining the vacuum degree of the equipment at 100-1000mtorr at room temperature 25°C, maintaining a stable pressure, introducing 100-1000sccmSF6, 100-5000sccmO2 and 100-2000sccmCl2, and performing selective corrosion plasma etching, and the etching time is 1-100min;

[0065] Post-RIE cleaning: Use a mixed solution with a volume ratio of BOE:H2O2:H2O=1:2:3 to optimize the texture of the silicon wafer after RIE, with a reaction time of 6-8 minutes and a reaction temperature of 40°C, and then perform water washing-HF washing-water washing-HCl washing-water washing in sequence to remove the oxide layer or metal impurities on the surface of the silicon wafer;

[0066] Step S6: depositing an intrinsic amorphous silicon layer 6 and an anti-reflection film 5 on the front side of the silicon substrate in sequence; Figure 6 ;

[0067] In this embodiment, PECVD is used to sequentially deposit an intrinsic hydrogenated amorphous silicon layer a-si:H with a thickness of 6-10nm and a SiNx layer with a thickness of 80-100nm on the front side of a single crystal silicon substrate; the deposition temperature of the a-si:H layer is 180-220°C, and the deposition temperature of the SiNx layer is 500-550°C;

[0068] Step S7: depositing an intrinsic amorphous silicon layer 6 and a P-type doped amorphous silicon layer 7 on the back side of the silicon substrate in sequence, see Figure 7 ;

[0069] In this embodiment, a-si:H with a thickness of 10 nm and a-si:H(P) with a thickness of 20-25 nm (i.e., a P-type doped hydrogenated amorphous silicon layer pa-Si) are deposited on the back of the silicon wafer using a CVD device; the deposition temperature of a-si:H is 180-220°C, and the deposition temperature of a-si:H(P) is 200-220°C;

[0070] Step S8: using a laser to partially open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer on the N region on the back of the silicon substrate to expose the PSG layer on the N region; Figure 8 ;

[0071] Specifically, a nanosecond laser is used to open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer in the N region to expose the PSG layer on the N region, and the laser power is 10-14W;

[0072] Specifically, the N-region is partially opened, specifically, the amorphous silicon layer and the P-type doped intrinsic amorphous silicon layer in the first region adjacent to the P region are retained, so that in step S11, when the TCO film is laser grooved, the amorphous silicon layer and the P-type doped intrinsic amorphous silicon layer in the first region can be used as a laser mask to avoid laser damage to the N-poly layer corresponding to the isolation groove GAP;

[0073] Step S9: pickling the PSG layer on the exposed N region to expose the N-type doped poly layer thereunder;

[0074] In this embodiment, a chain machine is used to remove the exposed PSG: 5% wt hydrofluoric acid is used to clean the exposed PSG layer, thereby removing the PSG layer in the grooved area to expose the portion of the N-type doped crystalline silicon layer n-poly-Si;

[0075] Step S10: Depositing a TCO conductive film layer 8 on the entire back surface of the silicon substrate; see Fig. 9 ;

[0076] Use PVD to deposit a TCO conductive film layer on the back with a thickness of 70-100nm;

[0077] Step S11: Use laser to open grooves on the back side of the silicon substrate to expose the PSG layer and form isolation grooves to insulate the N region and the P region to prevent leakage caused by the interconnection of the N / P regions; see Fig.10 ;

[0078] Use ultraviolet picosecond laser to open grooves to expose the PSG layer and form isolation grooves to insulate the N region and P region to prevent leakage caused by the interconnection of the N / P regions; the insulation resistance of the insulation region is tested to be >10MΩ, and the laser width is 75 microns;

[0079] Specifically, the isolation groove divides the first area into two parts, wherein the first part of the P-type area close to the P area forms a first contact area, and the first contact area forms multiple leakage points, which reduces the reverse breakdown voltage of the battery. When the battery cell is reversely cut off, more leakage generates less heat, and the temperature of the hot spot is naturally low (for example, the battery cell is blocked by shadows, bird droppings, etc.), which is conducive to reducing the impact of the hot spot on the system;

[0080] Step S12: Prepare metal electrodes 9 in the P region and N region on the back of the silicon substrate, see Fig.11 ; After sintering and solidification, the BC battery can be obtained.

[0081] It can be understood that the above embodiment is described by taking the first conductive region as an N-type tunnel passivation contact (N-topcon) and the second conductive region as a P-type heterojunction structure as an example. It can be understood that the first conductive region can also be a P-topcon and the second conductive region can be an N-type heterojunction structure, which will not be repeated in the present disclosure.

[0082] Comparative Example 1

[0083] The N-type crystalline silicon TBC solar cell prepared according to the method disclosed in Chinese invention patent application CN116387369A was subjected to performance tests with the battery product of the embodiment of the present invention. The test results are shown in the following table, wherein Voc represents the open circuit voltage, Jsc represents the short circuit current density, FF represents the fill factor, and EFF represents the battery conversion efficiency.

[0084] Voc(mV) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) EFF(%) Comparative Example 1 730.1 41.677 83.3 25.35 Example 1 738.3 41.768 83.33 25.44

[0085] By comparing the test data, it can be seen that the BC battery cell with a new structure prepared by the method of the present invention has improved open circuit voltage and short circuit current density compared with TBC batteries, and the battery cell conversion efficiency is improved by 0.09%, achieving excellent results.

[0086] Example 2

[0087] See also Fig.12 , a solar BC cell, this embodiment is explained by taking the substrate as an N-type substrate, the first region as an N-type topcon structure, and the second region as a P-type heterojunction structure as an example. It can be understood that the first region can be a P-type topcon structure and the second region can be an N-type heterojunction structure, and the present disclosure does not limit it.

[0088] The invention comprises an N-type single crystal silicon substrate 1, wherein the N-type single crystal silicon substrate has a front side and a back side opposite to each other, and a plurality of first regions and second regions are alternately arranged on the back side of the N-type single crystal silicon substrate along a first direction; it can be understood that the single crystal silicon substrate 1 can also be a P-type, which is not limited in this embodiment;

[0089] The first direction intersects with the thickness direction of the N-type single crystal silicon substrate;

[0090] The first region includes a first passivation contact layer and a first conductive layer arranged in a direction away from the back side of the substrate, wherein the first passivation contact layer includes a stacked tunneling oxide layer 2 and an N-type doped poly layer 4. It can be understood that the doped poly layer can also be a P-type doped poly layer.

[0091] The second region includes a second passivation contact layer and a second conductive layer sequentially arranged in a direction away from the back side of the substrate, and the second passivation contact layer includes a stacked intrinsic amorphous silicon layer 3 and a P-type doped amorphous silicon layer 7; it can be understood that the doped amorphous silicon layer 7 can also be an N-type doped amorphous silicon layer, and the corresponding doped poly layer 4 is a P-type doped poly layer,

[0092] Preferably, the first conductive layer and the second conductive layer are TCO conductive film layers 8. It can be understood that the conductive layer can also be other types of conductive film layers.

[0093] A first region of the first region close to the second region further includes a second passivation contact layer stacked on the first passivation contact layer;

[0094] The first region includes a first sub-region, a spacing region, and a second sub-region sequentially distributed along a first direction, wherein the spacing region penetrates the conductive layer, the second passivation contact layer and the first passivation contact layer, wherein the second sub-region is close to the second region;

[0095] The spacer isolates the first region from the second region to prevent the first region from being electrically connected to the second region;

[0096] By stacking the second passivation contact layer on the first passivation contact layer, the damage to the first passivation contact layer can be reduced when the spacer is formed in the first region, thereby improving the passivation effect of the battery.

[0097] At the same time, the second sub-region and the second region are adjacent to form a partial conductive contact point, which can effectively reduce the reverse breakdown voltage of the battery. When the battery cell is reversely cut off, more leakage current will generate less heat, which is beneficial to reducing the impact of hot spots.

[0098] In this embodiment, the front side of the battery is provided with a velvet structure, a front intrinsic amorphous silicon layer and an anti-reflection layer in sequence in a direction away from the front side of the substrate.

[0099] In this embodiment, the solar cell further includes a first electrode 20 and a second electrode 30. The first electrode is printed on the conductive layer in the first region other than the first region, and the second electrode is printed on the conductive layer in the second region.

[0100] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: The solar cell comprises a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, and a plurality of first conductive regions and second conductive regions are alternately arranged on the back side of the silicon substrate along a first direction, wherein the first conductive regions and the second conductive regions have opposite conductive types; The first direction intersects with the thickness direction of the silicon substrate; The first conductive region includes a first passivation contact layer and a first conductive layer sequentially arranged in a direction away from the back surface, and the first passivation contact layer includes a stacked tunneling oxide layer and a doped poly layer; The second region includes a second passivation contact layer and a second conductive layer sequentially arranged in a direction away from the back surface, and the second passivation contact layer includes a stacked intrinsic amorphous silicon layer and a doped amorphous silicon layer; A first region of the first region close to the second region further includes a second passivation contact layer stacked on the first passivation contact layer; The first region includes a first sub-region, a spacer region, and a second sub-region distributed in sequence along a first direction, wherein the spacer region runs through the conductive layer of the first region, the second passivation contact layer and the first passivation contact layer, and the second sub-region is close to the second conductive region and contacts the second conductive region at a first position.

2. The solar cell according to claim 1, wherein: The front side is provided with a velvet structure, an intrinsic amorphous silicon layer and an anti-reflection layer in sequence in a direction away from the front side of the substrate.

3. The solar cell according to claim 1, wherein: The device further includes a first electrode and a second electrode. The first electrode is located on the conductive layer of the first conductive region other than the first region, and the second electrode is located on the conductive layer of the second conductive region.

4. The solar cell according to claim 1, wherein: The conductive layer is a TCO conductive film layer.

5. A method for preparing a solar cell according to any one of claims 1 to 4, characterized in that: The steps include: Step S1: Select a silicon substrate; perform pre-cleaning and double-sided polishing; Step S2: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon substrate; Step S3: firstly, the front side of the silicon substrate is placed flat on a carrier, and then a liquid dopant is coated on the back side and dried, followed by annealing to crystallize the amorphous silicon and activate the impurities to form a doped poly layer; The annealing temperature is 600-700°C and the annealing time is 1-3 minutes; Step S4: using laser to groove the doped poly layer, and etching and cleaning to obtain the second conductive area to be formed; the area not grooved is the first conductive area; Step S5: performing texturing on the front side of the silicon substrate; Step S6: depositing an intrinsic amorphous silicon layer and an anti-reflection film in sequence on the front surface of the silicon substrate; Step S7: depositing an intrinsic amorphous silicon layer and a doped amorphous silicon layer in sequence on the back side of the silicon substrate; Step S8: using a laser to partially open the doped amorphous silicon layer and the intrinsic amorphous silicon layer on the first conductive region on the back side of the silicon substrate to expose the protective layer on the first conductive region; Step S9: pickling the exposed protective layer to expose the doped poly layer underneath; Step S10: depositing a conductive layer on the entire back surface of the silicon substrate; Step S11: using a laser to open a groove on the back side of the silicon substrate to expose the protective layer and form an isolation groove to insulate the first conductive area and the second conductive area; Step S12: preparing metal electrodes on the first conductive region and the second conductive region on the back side of the silicon substrate.

6. The method according to claim 5, characterized in that In the step S2: the thickness of the tunnel oxide layer is 1-3 nm; the thickness of the intrinsic amorphous silicon layer is 280-330 nm.

7. The method according to claim 5, characterized in that: In step S3: the liquid dopant contains a Group V element, and the Group V element is selected from one or more of N, P, As, Sb, and Bi.

8. The method according to claim 5, characterized in that In the step S3: the carrier has a heating function, and the liquid dopant is dried by heating the carrier.

9. The preparation method according to claim 5, characterized in that: In the step S3, the annealing temperature is 610-630° C., and the annealing time is 80-100 seconds.

10. The method according to claim 5, characterized in that: In the step S10: a TCO conductive thin film layer is deposited on the back side of the silicon substrate using a PVD method, and the thickness of the TCO conductive thin film layer is 70-100 nm.

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