Full-function reconfigurable digital array radar brick based on SOC chip

Abstract

The invention provides a full-function reconfigurable digital array radar brick based on an SOC chip, and relates to the technical field of wireless signals. According to the invention, a framework is composed of full-function independent bricks and comprises a structure mounting piece, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit; wherein each brick comprises a structure mounting part, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit, a complete radar front-end function is realized through multi-layer layered architecture integration, and each brick can be matched with a signal processing plug-in box to realize a complete radar; in addition, when two or more full-function reconfigurable digital array radar bricks carry out radar reconstruction, interdigital splicing is carried out through the staggered arrangement structure of the full-function reconfigurable digital array radar bricks; therefore, the integration level of the sub-array architecture is improved, and the sub-array architecture has a complete radar front-end function and has a flexible system reconstruction capability.

Description

Technical Field

[0001] The invention relates to the technical field of wireless signals, in particular to a full-function reconfigurable digital array radar brick based on a SOC chip. Background Art

[0002] Existing digital array radars are implemented using a modular subarray architecture, with solid-state active phased array and digital array technology as core features. Typical implementations such as the US SPY-6 radar system use a digital subarray structure, whose subarrays are mainly composed of digital TR components, which need to be combined with peripheral analog TR components and antenna arrays to build a radar front-end system.

[0003] The existing technology has three significant defects, which seriously restrict the rapid deployment capability and multi-mission adaptability of the radar system:

[0004] First, the integration of the subarray architecture is limited. When analog TR components need to be integrated, the physical size and weight will increase significantly, making it difficult to achieve a compact layout.

[0005] Second, a single subarray does not have complete radar front-end functions and must rely on external antennas, power supplies, and signal processing systems to work together;

[0006] Third, the system reconstruction capability is insufficient. The existing sub-arrays only support beamforming reconstruction at the signal level and cannot achieve radar system-level functional reconstruction through physical combination, resulting in the need to redesign the hardware platform for different application scenarios.

[0007] Therefore, it is necessary to provide a fully functional reconfigurable digital array radar brick based on SOC chip to solve the technical problems of limited integration of sub-array architecture, lack of complete radar front-end functions and insufficient system reconstruction capability. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a fully functional reconfigurable digital array radar brick based on a SOC chip, thereby improving the integration of the subarray architecture, enabling it to have complete radar front-end functions and flexible system reconstruction capabilities.

[0009] To achieve the above purpose, the present application proposes a fully functional reconfigurable digital array radar brick based on a SOC chip, including a structural mounting part, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit; wherein,

[0010] The structural mounting member comprises a front cover plate, a shielding plate and a rear back plate; wherein the front cover plate and the rear back plate are both staggered structures, wherein the staggered structure is composed of a plurality of rectangular areas arranged equidistantly and staggeredly on the same plane, and two spaced rectangular areas are arranged parallel to each other;

[0011] The digital processing board includes an FPGA chip and a digital processing circuit board; wherein the FPGA chip is arranged on the digital processing circuit board, the digital processing circuit board is arranged in a geometric contraction according to the staggered arrangement structure, and the digital processing circuit board is placed on the inner side of the back plate, and the FPGA chip is electrically connected to the upper computer;

[0012] The transmitting / receiving digital integrated board is composed of a plurality of digital TR boards; wherein the digital TR board includes a SOC chipset and a digital integrated circuit board; the digital TR board is arranged to be proportionally contracted corresponding to the rectangular area and is placed inside the digital processing circuit board; the SOC chipset is arranged on the digital integrated circuit board and is electrically connected to the digital processing board respectively;

[0013] The RF transmitting / receiving board is composed of multiple RF TR boards; wherein the RF TR board is provided with multiple RF transceiver channels, power supply and communication control modules; the RF TR board is arranged in equal proportion to the corresponding rectangular area, is placed inside the digital TR board and places the shielding board in the middle for isolation, and is electrically connected to the corresponding antenna board respectively;

[0014] The antenna unit is composed of multiple antenna boards; wherein, the antenna boards are arranged corresponding to the rectangular area and arranged in a staggered structure, the front cover plate and the back plate encapsulate the digital processing board, the transmitting / receiving digital integrated board, and the radio frequency transmitting / receiving board inside, and the antenna unit is arranged to fit the outer side of the front cover plate.

[0015] As a further solution, the antenna board is configured using a patch radiation array element, including a top PCB board, a first structural film layer, a PMI foam layer, a second structural film layer, a bottom PCB board, an adhesive film layer and an antenna floor, which are sequentially arranged, and edge packaging is performed using 3M tape, a sealing ring and silicone rubber.

[0016] As a further solution, the RF transceiver channel includes a transmitting channel, a receiving channel and a switching channel; wherein,

[0017] The transmitting channel includes a transmitting input interface, a first amplifier and a second amplifier; wherein the transmitting input interface is electrically connected to the first amplifier, the first amplifier is electrically connected to the power supply and communication control module and the second amplifier, and the second amplifier is electrically connected to the power supply and communication control module;

[0018] The receiving channel includes a limiter, a low noise amplifier and a receiving output interface; wherein the limiter is electrically connected to the low noise amplifier, and the low noise amplifier is electrically connected to the receiving output interface;

[0019] The switching channel includes a transceiver switching switch and a filter; wherein the transceiver switching switch is electrically connected to the second amplifier, the limiter, the filter, the power supply and the pass control module respectively, and the other end of the filter is electrically connected to the antenna board.

[0020] As a further solution, the power supply and communication control module includes a power management module and a communication control management module; wherein, the power management module is set through a power management chip, and the communication control management module is set through an MCU, and the power management module is electrically connected to each RF TR board, digital TR board and digital processing circuit board respectively.

[0021] As a further solution, the SOC chipset includes a first SOC chip and a second SOC chip, and the digital integrated circuit board includes a first radio frequency transceiver chip, a second radio frequency transceiver chip and a wire-to-board connector; wherein,

[0022] The first SOC chip is electrically connected to the first RF transceiver chip; wherein, bidirectional JESD204B channel 1, JESD204B channel 2, SPI*2 channel and GPIO*10 channel are arranged between the first SOC chip and the first RF transceiver chip, and a unidirectional synchronization signal input channel, synchronization signal output channel and reference clock channel are arranged between the first SOC chip and the first RF transceiver chip;

[0023] The second SOC chip is electrically connected to the second RF transceiver chip, and adopts the same electrical connection relationship as the first SOC chip and the first RF transceiver chip; the first RF transceiver chip and the second RF transceiver chip are electrically connected to the transmitting channel and the receiving channel of each RF transceiver channel respectively;

[0024] One end of the wire-to-board connector is electrically connected to the power supply and communication control module, the first SOC chip is connected to the I2C interface of the wire-to-board connector, and the second SOC chip is respectively connected to the RF_INHB interface, RF_TX_DRAIN interface and RF_TXRX_SWITCH interface of the wire-to-board connector.

[0025] As a further solution, a clock synchronization adapter and a power adapter are also provided; wherein the clock synchronization adapter is electrically connected to the FPGA chip, and the power adapter is electrically connected to the power management module.

[0026] As a further solution, when two or more fully-functional reconfigurable digital array radar bricks are reconstructing the radar, the staggered arrangement structure of each fully-functional reconfigurable digital array radar brick is used for interleaving, and the clock synchronization adapters are electrically connected to each other, and the power adapters are electrically connected to each other.

[0027] As a further solution, the digital processing circuit board includes a clock management unit, an Ethernet PHY module, a DDR4 module, a FLASH module, a driver interface chipset module, a digital processing interface group and a high-speed signal transmission interface; wherein,

[0028] The FPGA chip is electrically connected to the Ethernet PHY module, the DDR4 module, the FLASH module and the drive interface chipset module respectively, and the Ethernet PHY module is electrically connected to the high-speed signal transmission interface;

[0029] The clock management unit includes a CLK clock driver and a clock crystal oscillator; wherein the CLK clock driver is electrically connected to the clock crystal oscillator, the FPGA chip, the high-speed signal transmission interface and the digital processing interface group respectively;

[0030] The high-speed signal transmission interface is provided through a plurality of SEAF8-20 board-to-board connectors, and is electrically connected to the FPGA chip, the driver interface chipset module, the CLK clock driver and the high-speed signal transmission interface respectively;

[0031] The high-speed signal transmission interface includes an ERF8-035 board-to-board connector and a power connector; wherein the board-to-board connector is electrically connected to the FPGA chip, the CLK clock driver, the SEAF8-20 board-to-board connector and the ERF8-035 board-to-board connector respectively, and the ERF8-035 board-to-board connector is electrically connected to the SEAF8-20 board-to-board connector and the power management module.

[0032] Compared with the related art, the present invention can provide a fully functional reconfigurable digital array radar brick based on SOC chip, which has the following advantages:

[0033] The present invention adopts a fully functional independent brick composition architecture, including structural mounting parts, digital processing boards, transmitting / receiving digital integrated boards, radio frequency transmitting / receiving boards and antenna units; wherein each brick contains a structural mounting part, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit, and realizes complete radar front-end functions through multi-layer layered architecture integration, and each brick can be matched with a signal processing plug-in box to realize a complete radar; in addition, when two or more fully functional reconfigurable digital array radar bricks are used for radar reconstruction, interdigital splicing is performed through the staggered arrangement structure of each fully functional reconfigurable digital array radar brick; therefore, the present invention improves the integration of the subarray architecture, so that it has complete radar front-end functions and flexible system reconstruction capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 A schematic diagram of the structure of a fully functional reconfigurable digital array radar brick based on a SOC chip provided by the present invention;

[0037] Figure 2 A schematic diagram of the vertical interconnection structure provided by the present invention;

[0038] Figure 3 A schematic diagram of the external structure of the antenna board provided by the present invention;

[0039] Figure 4 A schematic structural diagram of a static sealing structure provided by the present invention;

[0040] Figure 5 A schematic diagram of the internal connection structure of the antenna board provided by the present invention;

[0041] Figure 6 A schematic diagram of the structure of the radio frequency transceiver channel provided by the present invention;

[0042] Figure 7 A schematic diagram of the structure of a digital integrated circuit board provided by the present invention;

[0043] Figure 8 This is a structural schematic diagram of the digital processing circuit board provided by the present invention.

[0044] Among them, the figure markings are: 1. back plate; 2. digital processing board; 3. digital TR board; 4. RF TR board; 5. shielding plate; 6. front cover; 7. antenna unit; 8. clock synchronization adapter; 9. power adapter; 10. vertical interconnection; 11. 3M tape; 12. top PCB board; 13. first structural film layer; 14. PMI foam layer; 15. second structural film layer; 16. bottom PCB board; 17. adhesive film layer; 18. antenna floor; 19. silicone rubber; 20. sealing ring.

[0045] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] See also Figure 1 The embodiment of the present application provides a fully functional reconfigurable digital array radar brick based on a SOC chip, including a structural mounting part, a digital processing board 2, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit 7; wherein,

[0048] The structural mounting part includes a front cover plate 6, a shielding plate 5 and a back plate 1; wherein the front cover plate 6 and the back plate 1 are both staggered structures, and the staggered structure is composed of a plurality of rectangular areas arranged equidistantly and staggered in the same plane, and the two spaced rectangular areas are arranged parallel to each other;

[0049] The digital processing board 2 includes an FPGA chip and a digital processing circuit board; wherein the FPGA chip is arranged on the digital processing circuit board, the digital processing circuit board is arranged in a geometric contraction according to the staggered arrangement structure, and the digital processing circuit board is placed on the inner side of the back plate 1, and the FPGA chip is electrically connected to the upper machine;

[0050] The transmitting / receiving digital integrated board is composed of a plurality of digital TR boards 3; wherein the digital TR board 3 includes a SOC chipset and a digital integrated circuit board; the digital TR board 3 is arranged to be proportionally contracted corresponding to the rectangular area and is placed inside the digital processing circuit board; the SOC chipset is arranged on the digital integrated circuit board and is electrically connected to the digital processing board 2 respectively;

[0051] The RF transmitting / receiving board is composed of a plurality of RF TR boards 4; wherein the RF TR board 4 is provided with a plurality of RF transceiver channels, a power supply and a communication control module; the RF TR board 4 is arranged in a proportional contraction corresponding to the rectangular area, is placed inside the digital TR board 3 and places the shielding board 5 in the middle for isolation, and is electrically connected to the corresponding antenna board respectively;

[0052] The antenna unit 7 is composed of multiple antenna boards; wherein, the antenna boards are arranged corresponding to the rectangular area and arranged in a staggered structure, the front cover plate 6 and the back plate 1 encapsulate the digital processing board 2, the transmitting / receiving digital integrated board, and the radio frequency transmitting / receiving board inside, and the antenna unit 7 is arranged to fit the outer side of the front cover plate 6.

[0053] It should be noted that: this embodiment adopts a fully functional independent brick composition architecture, each brick includes a structural mounting part, a digital processing board 2, a transmit / receive digital integrated board, a radio frequency transmit / receive board and an antenna unit 7, and realizes the complete radar front-end function through a multi-layer layered architecture integration; each brick can be matched with a signal processing plug-in box to realize a complete radar. In addition, multiple bricks can be reconstructed to build a new radar to realize the reconstruction of the radar function.

[0054] Multi-layered architecture: Figure 1 As shown, the layering and placement order between the layers inside the bricks have been designed and optimized many times, and are connected by vertical interconnection 10 structures as shown in Figure 2 As shown, this design can simultaneously reduce inter-board transmission loss, reduce electromagnetic compatibility impact, and increase vibration stability; and can ensure that all boards and devices can be placed in a compact space.

[0055] In a specific embodiment, the antenna board is configured with a patch radiation array element, which is a double patch radiation array element structure. Each group of four radiation array elements is packaged as a group and is installed on the front housing of the brick by screw connection. Each group of four radiation array elements packaged as a group should have sufficient structural rigidity and should not be easily scratched or damaged.

[0056] In order to ensure that each group of radiation units is blindly plugged into the RF TR board 4, the front cover plate 6 of the brick is designed with positioning pins for blind plugging and positioning of the patch radiation array elements, and the electrical connection between the patch radiation array elements and the RF TR board 4 is considered to adopt a full-escapement or semi-escapement socket adapter with a tolerance of ≤0.1mm.

[0057] Based on structural requirements such as structural vibration resistance, heat conduction and electromagnetic shielding, a shielding plate 5 is installed between the RF TR board 4 and the digital TR board 3 to isolate the two sides. A single board is installed with 8 screws of no less than M2.5 specification and is directly installed on the shielding plate 5.

[0058] The digital processing board 2 is directly mounted on the back plate 1 of the brick. Similar to the radiating element communication structure, the RF TR board 4, the digital TR board 3 and the digital processing board 2 are installed as blind plug vertical interconnection 10; the communication connection preferably has a certain amount of floating plug and socket.

[0059] like Figure 3 As shown, the radiating element mounting surface includes 4 connectors. On the basis of ensuring waterproofness, in order to reasonably utilize the limited structural space, the following Figure 4 The static sealing structure of "rectangular groove + formed filler" shown in the figure; the waterproofing measures between the front cover plate 6 and the back plate 1 are similar to the waterproofing of the radiation array element structure, and also adopt the static sealing structure of "rectangular groove + formed filler".

[0060] like Figure 5As shown, the antenna board includes a top PCB board 12, a first structural film layer 13, a PMI foam layer 14, a second structural film layer 15, a bottom PCB board 16, an adhesive film layer 17 and an antenna floor 18, which are arranged in sequence, and are edge-encapsulated by 3M tape 11, a sealing ring 20 and silicone rubber 19.

[0061] The antenna board processing mainly involves the following parts: reflector board processing, printed circuit board processing, printed circuit board and connector welding SMT production line, reflector printed circuit board and PMI foam lamination.

[0062] The reflector printed board and PMI foam lamination process uses adhesive film CF3350 and structural adhesive film AF126-2 to pressurize and bond the printed board and PMI foam into one piece in a high temperature box.

[0063] like Figure 6 As shown, the RF transceiver channel includes a transmitting channel, a receiving channel and a switching channel; wherein,

[0064] The transmitting channel includes a transmitting input interface, a first amplifier and a second amplifier; wherein the transmitting input interface is electrically connected to the first amplifier, the first amplifier is electrically connected to the power supply and communication control module and the second amplifier, and the second amplifier is electrically connected to the power supply and communication control module;

[0065] The receiving channel includes a limiter, a low noise amplifier and a receiving output interface; wherein the limiter is electrically connected to the low noise amplifier, and the low noise amplifier is electrically connected to the receiving output interface;

[0066] The switching channel includes a transceiver switching switch and a filter; wherein the transceiver switching switch is electrically connected to the second amplifier, the limiter, the filter, the power supply and the pass control module respectively, and the other end of the filter is electrically connected to the antenna board.

[0067] In a specific embodiment, the RF TR board 4 includes 4 RF transceiver channels; wherein the receiving channel and the transmitting channel work in time sharing; when the transmitting channel works, the transceiver switching switch selects the transmitting channel, and the RF signal sent from the front-stage board is amplified to more than 10W through a two-stage amplifier, and is transmitted to the rear-end antenna through the transceiver switch to radiate energy into space, and a low-pass filter is designed after the transceiver switch to improve the harmonic suppression capability of the transmitting signal. When the receiving channel works, the transceiver switching switch selects the receiving channel, and the signal received from the antenna is sent to the limiter by the selection switch after passing through the filter, and then amplified by the low-noise amplifier and sent to the back-end board for sampling and processing.

[0068] The +48V DC power supplied by the power supply is converted into different voltages through the power supply and communication control module to provide power for the first amplifier, the second amplifier and the low noise amplifier. In order to ensure the time-sharing operation of the RF TR board 4, the power supply and communication control module generates a corresponding timing control signal to control the conduction state of the transceiver switch; when the transmitting channel is working, a control signal is generated to enable the transceiver switch to select the transmitting channel, enable the second amplifier, and turn off the low noise amplifier; when the receiving channel is working, a control signal is generated to enable the transceiver switch to select the receiving channel, and turn off the second amplifier and enable the low noise amplifier.

[0069] The power supply and communication control module includes a power management module and a communication control management module; wherein, the power management module is set through the power management chip, and the communication control management module is set through the MCU, and the power management module is electrically connected to each RF TR board 4, digital TR board 3 and digital processing circuit board respectively.

[0070] When in use, the communication control management module can realize temperature monitoring, current and voltage monitoring, monitor the working status of the RFTR board at all times, and transmit status information to the superior system through the I2C or UART communication interface, thereby improving the health management capabilities of the RF TR board 4.

[0071] like Figure 7 As shown, the SOC chipset includes a first SOC chip and a second SOC chip, and the digital integrated circuit board includes a first radio frequency transceiver chip, a second radio frequency transceiver chip and a wire-to-board connector; wherein,

[0072] The first SOC chip is electrically connected to the first RF transceiver chip; wherein, bidirectional JESD204B channel 1, JESD204B channel 2, SPI*2 channel and GPIO*10 channel are arranged between the first SOC chip and the first RF transceiver chip, and a unidirectional synchronization signal input channel, synchronization signal output channel and reference clock channel are arranged between the first SOC chip and the first RF transceiver chip;

[0073] The second SOC chip is electrically connected to the second RF transceiver chip, and adopts the same electrical connection relationship between the first SOC chip and the first RF transceiver chip; the first RF transceiver chip and the second RF transceiver chip are electrically connected to the transmitting channel and the receiving channel of each RF transceiver channel respectively;

[0074] One end of the wire-to-board connector is electrically connected to the power supply and communication control module, the first SOC chip is connected to the I2C interface of the wire-to-board connector, and the second SOC chip is respectively connected to the RF_INHB interface, RF_TX_DRAIN interface and RF_TXRX_SWITCH interface of the wire-to-board connector.

[0075] The digital TR board 3 is based on two RF SOC chips, which mainly complete the digital-to-analog conversion of digital signals from the digital processing board 2, and receive the analog-to-digital conversion of signals from ports P1 to P8. The SOC chip has a built-in phase-locked loop and a basic signal preprocessing unit, and each RF SOC has two data channels. The two SOC chips introduce control signals, configuration signals, reference clocks, and data signals through ports P20 and P21, respectively. Therefore, the configuration of the SOC chip is mainly realized through the digital processing board 2.

[0076] Ports P1 to P8 are mainly used to receive and transmit RF signals. When the system is working, the transceiver switch needs to be switched according to the working mode. Therefore, the digital TR board 3 provides power to the RF TR board 4 and transfers the control signal of the digital processing board 2 through the P9 port; and an I2C interface is designed for uploading the status information of the RF TR board 4.

[0077] like Figure 8 As shown, the digital processing circuit board includes a clock management unit, an Ethernet PHY module, a DDR4 module, a FLASH module, a driver interface chipset module, a digital processing interface group and a high-speed signal transmission interface; wherein,

[0078] The FPGA chip is electrically connected to the Ethernet PHY module, the DDR4 module, the FLASH module and the driver interface chipset module respectively, and the Ethernet PHY module is electrically connected to the high-speed signal transmission interface;

[0079] The clock management unit includes a CLK clock driver and a clock crystal oscillator; wherein the CLK clock driver is electrically connected to the clock crystal oscillator, the FPGA chip, the high-speed signal transmission interface and the digital processing interface group respectively;

[0080] The high-speed signal transmission interface is provided through a plurality of SEAF8-20 board-to-board connectors, and is electrically connected to the FPGA chip, the driver interface chipset module, the CLK clock driver and the high-speed signal transmission interface respectively;

[0081] The high-speed signal transmission interface includes an ERF8-035 board-to-board connector and a power connector; wherein the board-to-board connector is electrically connected to the FPGA chip, CLK clock driver, SEAF8-20 board-to-board connector and ERF8-035 board-to-board connector respectively, and the ERF8-035 board-to-board connector is electrically connected to the SEAF8-20 board-to-board connector and the power management module.

[0082] like Figure 1 As shown, a clock synchronization adapter 8 and a power adapter 9 are also provided; wherein the clock synchronization adapter 8 is electrically connected to the FPGA chip, and the power adapter 9 is electrically connected to the power management module.

[0083] When two or more fully functional reconfigurable digital array radar bricks are reconstructing the radar, they are interleaved through the staggered arrangement structure of each fully functional reconfigurable digital array radar brick, and the clock synchronization adapters 8 are electrically connected to each other, and the power adapters 9 are electrically connected to each other, so that we can unify the power supply and synchronize the clock.

[0084] The above are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A fully functional reconfigurable digital array radar brick based on SOC chip, characterized by: It comprises a structural mounting part, a digital processing board (2), a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit (7); wherein: The structural mounting member comprises a front cover plate (6), a shielding plate (5) and a rear back plate (1); wherein the front cover plate (6) and the rear back plate (1) are both staggered structures, wherein the staggered structure comprises a plurality of rectangular areas which are staggered and arranged at equal intervals on the same plane, and two spaced rectangular areas are arranged parallel to each other; The digital processing board (2) comprises an FPGA chip and a digital processing circuit board; wherein the FPGA chip is arranged on the digital processing circuit board, the digital processing circuit board is arranged in a geometric contraction manner according to the staggered arrangement structure, and the digital processing circuit board is placed on the inner side of the back plate (1), and the FPGA chip is electrically connected to the upper computer; The transmitting / receiving digital integrated board is composed of a plurality of digital TR boards (3); wherein the digital TR board (3) comprises a SOC chipset and a digital integrated circuit board; the digital TR board (3) is arranged in a proportional manner corresponding to the rectangular area and is placed inside the digital processing circuit board; the SOC chipset is arranged on the digital integrated circuit board and is electrically connected to the digital processing board (2) respectively; The radio frequency transmitting / receiving board is composed of a plurality of radio frequency TR boards (4); wherein the radio frequency TR board (4) is provided with a plurality of radio frequency transmitting and receiving channels, a power supply and a communication control module; the radio frequency TR board (4) is arranged in a proportional contraction manner corresponding to the rectangular area, is placed inside the digital TR board (3) and places a shielding board (5) in the middle for isolation, and is electrically connected to the corresponding antenna board respectively; The antenna unit (7) is composed of a plurality of antenna panels; wherein the antenna panels are arranged corresponding to the rectangular area and arranged in a staggered arrangement structure; the front cover plate (6) and the back plate (1) encapsulate the digital processing board (2), the transmitting / receiving digital integrated board, and the radio frequency transmitting / receiving board inside; and the antenna unit (7) is arranged to fit the outer side of the front cover plate (6).

2. A fully functional reconfigurable digital array radar brick based on a SOC chip according to claim 1, characterized in that: The antenna board is arranged by using a patch radiation array element, comprising a top PCB board (12), a first structural adhesive film layer (13), a PMI foam layer (14), a second structural adhesive film layer (15), a bottom PCB board (16), an adhesive film layer (17) and an antenna floor (18) arranged in sequence, and edge packaging is performed by using 3M adhesive tape (11), a sealing ring (20) and silicone rubber (19).

3. A fully functional reconfigurable digital array radar brick based on a SOC chip according to claim 2, characterized in that: The radio frequency transceiver channel includes a transmitting channel, a receiving channel and a switching channel; wherein, The transmitting channel includes a transmitting input interface, a first amplifier and a second amplifier; wherein the transmitting input interface is electrically connected to the first amplifier, the first amplifier is electrically connected to the power supply and communication control module and the second amplifier, and the second amplifier is electrically connected to the power supply and communication control module; The receiving channel includes a limiter, a low noise amplifier and a receiving output interface; wherein the limiter is electrically connected to the low noise amplifier, and the low noise amplifier is electrically connected to the receiving output interface; The switching channel includes a transceiver switching switch and a filter; wherein the transceiver switching switch is electrically connected to the second amplifier, the limiter, the filter, the power supply and the pass control module respectively, and the other end of the filter is electrically connected to the antenna board.

4. A fully functional reconfigurable digital array radar brick based on a SOC chip according to claim 3, characterized in that: The power supply and communication control module comprises a power management module and a communication control management module; wherein the power management module is set by a power management chip, and the communication control management module is set by an MCU, and the power management module is electrically connected to each radio frequency TR board (4), a digital TR board (3) and a digital processing circuit board.

5. A fully functional reconfigurable digital array radar brick based on a SOC chip according to claim 4, characterized in that: The SOC chipset includes a first SOC chip and a second SOC chip, and the digital integrated circuit board includes a first radio frequency transceiver chip, a second radio frequency transceiver chip and a wire-to-board connector; wherein, The first SOC chip is electrically connected to the first RF transceiver chip; wherein, bidirectional JESD204B channel 1, JESD204B channel 2, SPI*2 channel and GPIO*10 channel are arranged between the first SOC chip and the first RF transceiver chip, and a unidirectional synchronization signal input channel, synchronization signal output channel and reference clock channel are arranged between the first SOC chip and the first RF transceiver chip; The second SOC chip is electrically connected to the second RF transceiver chip, and adopts the same electrical connection relationship as the first SOC chip and the first RF transceiver chip; the first RF transceiver chip and the second RF transceiver chip are electrically connected to the transmitting channel and the receiving channel of each RF transceiver channel respectively; One end of the wire-to-board connector is electrically connected to the power supply and communication control module, the first SOC chip is connected to the I2C interface of the wire-to-board connector, and the second SOC chip is respectively connected to the RF_INHB interface, RF_TX_DRAIN interface and RF_TXRX_SWITCH interface of the wire-to-board connector.

6. A fully functional reconfigurable digital array radar brick based on a SOC chip according to claim 4, characterized in that: A clock synchronization adapter (8) and a power adapter (9) are also provided; wherein the clock synchronization adapter (8) is electrically connected to the FPGA chip, and the power adapter (9) is electrically connected to the power management module.

7. A fully functional reconfigurable digital array radar brick based on a SOC chip according to claim 6, characterized in that: When two or more fully functional reconfigurable digital array radar bricks are reconstructing the radar, the staggered arrangement structure of each fully functional reconfigurable digital array radar brick is used for interdigital splicing, and each clock synchronization adapter (8) is electrically connected to each other, and each power adapter (9) is electrically connected to each other.

8. The fully functional reconfigurable digital array radar brick based on SOC chip according to claim 1 is characterized in that: The digital processing circuit board includes a clock management unit, an Ethernet PHY module, a DDR4 module, a FLASH module, a driver interface chipset module, a digital processing interface group and a high-speed signal transmission interface; wherein, The FPGA chip is electrically connected to the Ethernet PHY module, the DDR4 module, the FLASH module and the drive interface chipset module respectively, and the Ethernet PHY module is electrically connected to the high-speed signal transmission interface; The clock management unit includes a CLK clock driver and a clock crystal oscillator; wherein the CLK clock driver is electrically connected to the clock crystal oscillator, the FPGA chip, the high-speed signal transmission interface and the digital processing interface group respectively; The high-speed signal transmission interface is provided through a plurality of SEAF8-20 board-to-board connectors, and is electrically connected to the FPGA chip, the driver interface chipset module, the CLK clock driver and the high-speed signal transmission interface respectively; The high-speed signal transmission interface includes an ERF8-035 board-to-board connector and a power connector; wherein the board-to-board connector is electrically connected to the FPGA chip, the CLK clock driver, the SEAF8-20 board-to-board connector and the ERF8-035 board-to-board connector respectively, and the ERF8-035 board-to-board connector is electrically connected to the SEAF8-20 board-to-board connector and the power management module.

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