SCI (Serial Communication Interface) communication method applicable to double DSP (Digital Signal Processor) architectures of aviation starter generator controller

Abstract

The invention belongs to the field of information communication, and particularly relates to an SCI (Serial Communication Interface) communication method applicable to double DSP (Digital Signal Processor) architectures of an aviation starter generator controller, which comprises the following steps of: sending logic: packaging data sent by a main DSP or an auxiliary DSP; judging the data in the sending register: if the data do not exist, storing the data sent by the main DSP or the auxiliary DSP into the SCITXBUF and then jumping out of the operation function of the period, and if the data exist, continuing to judge until the data in the sending register is completely sent; receiving logic: judging the data in the receiving register, if the data is greater than or equal to the byte number of the sent data, judging the packet header of the received data, and if the packet header is correct, executing the judgment checksum; if not, discarding the data; judging the checksum: judging whether the cumulative sum of all data after the packet tail is removed is 0 or not, and if the cumulative sum is correct, saving the array and jumping out of the operation function of the period; and analyzing and using the received data.

Description

Technical Field

[0001] The present application belongs to the field of information communication, and in particular relates to an SCI communication method between dual DSP architectures applicable to an aviation starter generator controller. Background Art

[0002] In order to meet the throughput requirements, non-similar heterogeneity requirements and I / O requirements of the aviation starter generator system architecture, more and more aviation starter generator controller CPU components adopt dual processor architecture, one DSP is used as the main control chip for mode conversion, state detection, etc., and the other DSP is used as the auxiliary control chip for starting and power generation control. Compared with a single DSP, it ensures sufficient content, CPU budget and hardware I / O port number for subsequent expansion. In short, the dual DSP architecture can effectively cope with complex control requirements in aviation starter generator controllers while ensuring high reliability and flexibility.

[0003] At present, in the field of aviation starter generator control, there are two types of communication methods between the mainstream dual DSP architectures. The first transmission method is GPIO, but it requires multiple data lines, which may lead to complex hardware design, and high-speed parallel communication is prone to interference, requiring strict design of PCB wiring. The second transmission method is SPI communication, which has high hardware complexity and requires at least 4 signal lines. The master device must continuously provide a clock signal, and the quality of the clock signal directly affects the stability of communication. In the aviation starter generator controller based on the dual DSP architecture, the use of SCI communication hardware wiring is simple, requiring only two signal lines (Tx and Rx), and the software driver layer code configuration is also simple. In practical applications, the maximum rate of SCI can usually reach about 10Mbps. Based on the consideration of aircraft safety, a rate of 1Mbps or less is generally selected to balance the rate and reliability. Summary of the invention

[0004] In order to solve the above problems, the present application provides an SCI communication method between dual DSP architectures applicable to an aviation starter generator controller, wherein the dual DSP architecture includes a main DSP and an auxiliary DSP, including:

[0005] The main DSP or auxiliary DSP sending logic is divided into the following steps:

[0006] Step S1: After entering the periodic operation function, the main DSP or the auxiliary DSP packages the data sent by the main DSP or the auxiliary DSP;

[0007] Step S2: Determine the data in the sending register: if there is no data, proceed to step S3; if there is data, continue to determine until the data in the sending register is sent completely;

[0008] Step S3: After storing the data sent by the main DSP or the auxiliary DSP into SCITXBUF, jump out of the current cycle running function;

[0009] The receiving logic of the auxiliary DSP or the main DSP is divided into the following steps:

[0010] Step K1: After entering the cycle running function, the data in the receiving register is judged. If it is greater than or equal to the number of data bytes sent, the packet header of the received data is judged. If it is correct, step K2 is executed; if it is incorrect, the data is discarded;

[0011] Step K2: Check the checksum. The checksum is determined by whether the cumulative sum of all data after removing the packet tail is 0. If it is correct, save the array and jump out of the current cycle running function.

[0012] Step K3: Parse and use the received data.

[0013] Preferably, the packet group includes a packet header, a packet trailer, a checksum and some data.

[0014] Preferably, before data is sent, an interface communication protocol is established in the communication between the main DSP and the auxiliary DSP.

[0015] Preferably, the main DSP or the auxiliary DSP sends data periodically.

[0016] Preferably, the main DSP or the auxiliary DSP receives data periodically.

[0017] Preferably, the main DSP and the auxiliary DSP are initialized and configured before data is sent.

[0018] This design takes engineering application as the starting point. The aviation starter generator controller adopts a dual DSP intercommunication architecture system, and uses its own DSP chip internal and external devices to realize inter-chip communication between the master and slave DSPs, greatly improving the efficiency of inter-chip communication and solving the technical bottleneck problem of difficult inter-chip data interaction. It saves DSP chip resources and enhances system reliability. This technology broadens the scope of engineering application of the dual DSP architecture of aviation starter generator controllers. At the same time, it has reference and reference value for promotion and application in other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a SCI communication logic diagram of a preferred implementation mode of the present application;

[0020] Figure 2 This is a SCI communication protocol diagram of a preferred implementation mode of the present application;

[0021] Figure 3 This is a logic flow chart of the master / slave DSP sending in a preferred implementation mode of the present application;

[0022] Figure 4 This is a main / auxiliary DSP receiving logic flow chart of a preferred implementation mode of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the implementation of this application clearer, the technical scheme in the implementation of this application will be described in more detail in combination with the drawings in the implementation of this application. In the drawings, the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The described implementation is a part of the implementation of this application, not all of the implementations. The implementation described below with reference to the drawings is exemplary and is intended to be used to explain this application, and cannot be understood as a limitation on this application. Based on the implementation in this application, all other implementations obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The implementation of this application is described in detail below in combination with the drawings.

[0024] As shown in the figure, the present invention proposes an SCI communication method suitable for dual DSP architectures of aviation starter generator controllers.

[0025] Based on the dual DSP architecture framework of the aviation starter generator controller, the SCI communication is verified. The SCI communication setting is divided into the following parts:

[0026] The first part is initialization configuration: the main DSP and auxiliary DSP are initialized and the following registers are configured.

[0027] 1) Communication Control Register (SCICCR): The character length control bit of the main DSP and auxiliary DSP is configured to 8, the SCI multi-processing mode control bit is configured to the idle line mode protocol, the loopback test mode enable is configured to disable, the SCI parity enable bit is configured to enable, the parity bit selection is configured to even polarity, and the SCI end bit unit is configured to 1 end bit;

[0028] 2) Control register 1 (SCICTL1): The transmitter enable bit is configured to start the transmitter operation, and the receiver enable bit is configured to send the received characters to SCIRXEMU and SCIRXBUF;

[0029] 3) Data transfer rate register (SCIHBAUD, SCILBAUD): The baud rate is set to 115200.

[0030] 4) FIFO transmit register (SCIFFTX): The main DSP and auxiliary DSP set the 16-level receive FIFO depth and do not enable the transmit FIFO interrupt;

[0031] 5) FIFO receive register (SCIFFRX): The master DSP and slave DSP set the 16-level receive FIFO depth and enable the receive FIFO interrupt;

[0032] 6)FIFO control register (SCIFFCT): set to 0.

[0033] The second part is the setting of SCI communication protocol: In the design, data is sent in packets. The header of the data sent by the main DSP is set to 0xBB and 0xBB, and the tail of the packet is set to 0xFF and 0xFF. In the aviation starter generator controller, the data content sent by the main DSP to the slave DSP is shown in Table 1, which are control instructions and test instructions. The header of the data sent by the slave DSP is 0xAA and 0xAA, and the tail of the packet is 0x55 and 0x55. The data sent back from the DSP to the main DSP is shown in Table 2, including speed and fault signals. The checksum in the communication packet is the result of the cumulative sum of the data excluding the tail of the packet, the inverse of the sum and the addition of one.

[0034] The third part is the sending logic design of the main DSP: using 1ms period to send, the sending logic of the main DSP is divided into the following steps:

[0035] Step 1: After entering the cycle run function, the data sent by the main DSP is packaged.

[0036] Step 2: Determine the data in the transmit FIFO. If there is no data, proceed to step 3. If there is data, continue to determine until the data in the transmit FIFO is completely sent.

[0037] Step 3: After storing the data sent by the main DSP into SCITXBUF, jump out of the current cycle running function.

[0038] The fourth part is the receiving logic design of the auxiliary DSP: using 1ms period reception. The receiving logic of the auxiliary DSP is divided into the following steps:

[0039] Step 1: After entering the cycle running function, the data in the receive FIFO is judged. If it is greater than or equal to the number of data bytes sent by the main DSP, the packet header of the received data is judged. If correct, step 2 is executed; if incorrect, the data is discarded.

[0040] Step 2: Determine the checksum. The checksum is determined by whether the sum of the previous 5 bytes of data is 0. If it is correct, save the array and exit the current cycle running function.

[0041] Step 3: Parse and use the data received by the auxiliary DSP.

[0042] Part 5, the sending logic design of the auxiliary DSP: using 1ms period to send, the sending logic of the auxiliary DSP is divided into the following steps:

[0043] Step 1: After entering the periodic run function, the data sent by the auxiliary DSP is packaged.

[0044] Step 2: Determine the data in the transmit FIFO. If there is no data, proceed to step 3. If there is data, continue to determine until the data in the transmit FIFO is completely sent.

[0045] Step 3: After storing the data sent by the auxiliary DSP into SCITXBUF, jump out of the current cycle running function.

[0046] Part 6, the receiving logic design of the main DSP: using 1ms period reception. The receiving logic of the main DSP is divided into the following steps:

[0047] Step 1: After entering the cycle running function, the data in the receive FIFO is judged. If it is greater than or equal to the number of data bytes sent by the auxiliary DSP, the packet header of the received data is judged. If correct, step 2 is executed; if incorrect, the data is discarded.

[0048] Step 2: Determine the checksum. The checksum is determined by whether the sum of the previous 7 bytes of data is 0. If it is correct, save the array and exit the current cycle running function.

[0049] Step 3: Parse and use the data received by the main DSP.

[0050] Through the above settings of the communication logic, the main DSP receives the same array as the content in Table 2, and the auxiliary DSP receives the same number as Table 1. The SCI communication of the dual DSP architecture of the aviation starter generator controller is verified.

[0051] Table 1 Main DSP packet data communication content

[0052]

[0053] Table 2 Auxiliary DSP group data communication content

[0054]

[0055]

[0056] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A SCI communication method between dual DSP architectures of an aviation starter generator controller, wherein the dual DSP architecture includes a main DSP and an auxiliary DSP, characterized in that: include: The main DSP or auxiliary DSP sending logic is divided into the following steps: Step S1: After entering the periodic operation function, the main DSP or the auxiliary DSP packages the data sent by the main DSP or the auxiliary DSP; Step S2: Determine the data in the sending register: if there is no data, proceed to step S3; if there is data, continue to determine until the data in the sending register is sent completely; Step S3: After storing the data sent by the main DSP or the auxiliary DSP into SCITXBUF, jump out of the current cycle running function; The receiving logic of the auxiliary DSP or the main DSP is divided into the following steps: Step K1: After entering the cycle running function, the data in the receiving register is judged. If it is greater than or equal to the number of data bytes sent, the packet header of the received data is judged. If it is correct, step K2 is executed; if it is incorrect, the data is discarded; Step K2: Check the checksum. The checksum is determined by whether the cumulative sum of all data after removing the packet tail is 0. If it is correct, save the array and jump out of the current cycle running function. Step K3: Parse and use the received data.

2. The SCI communication method between dual DSP architectures of an aviation starter generator controller as claimed in claim 1, characterized in that: The packet group includes a packet header, a packet trailer, a checksum and some data.

3. The SCI communication method between dual DSP architectures of an aviation starter generator controller as claimed in claim 1, characterized in that: Before data is sent, an interface communication protocol is established between the main DSP and the auxiliary DSP.

4. The SCI communication method between dual DSP architectures of an aviation starter generator controller as claimed in claim 1, characterized in that: The main DSP or auxiliary DSP sends data periodically.

5. The SCI communication method between dual DSP architectures of an aviation starter generator controller as claimed in claim 1, characterized in that: The main DSP or auxiliary DSP receives data periodically.

6. The SCI communication method between dual DSP architectures of an aviation starter generator controller as claimed in claim 1, characterized in that: Before data is sent, the main DSP and auxiliary DSP are initialized and configured.

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