Multi-core heterogeneous SOC reset method, electronic equipment and chip

Abstract

The invention discloses a multi-core heterogeneous SOC local reset method, electronic equipment and a chip, the SOC is applied to a data acquisition terminal and comprises a security domain, an application domain and a resource management domain which are used for inter-core communication, and the data acquisition terminal is connected with an upper computer through PCIe. The method comprises the following steps: mapping a reset parameter register of a data acquisition terminal and a register of an interface controller to an upper computer; when the upper computer monitors that data transmission of the application domain is interrupted, a reset preparation signal is sent to the security domain; the security domain feeds back a reset confirmation signal to the upper computer and sends a reset instruction to the resource management domain and the application domain; in the process of resetting the application domain, the resource management domain closes resources of the application domain and clears data of the interface controller; after the application domain is reset, the application domain sends a clock resource initialization request to the security domain; and the security domain sends a reset completion signal to the upper computer. According to the method, the problems of important data loss, long reset time and the like caused by global reset can be solved.

Description

Technical Field

[0001] The present application relates to the field of industrial data acquisition, and in particular to a multi-core heterogeneous SOC reset method, electronic device and chip. Background Art

[0002] In the field of industrial data acquisition, multi-core heterogeneous SOCs are widely used. They are hard-isolated into multiple domains with different security levels and run multiple systems. When a certain application domain fails or there is a need for system maintenance and update, a global reset method is usually used in related technologies. However, this reset method is prone to the loss of important data, and the reset time is long, which seriously affects the continuity and accuracy of data acquisition, bringing inconvenience and potential risks to industrial production. In addition, the related technology also uses an external reset button reset method or a power-off reset method. However, the external reset button reset method requires additional hardware circuit design, which undoubtedly increases the hardware cost. In the connection mode between the Windows switchboard and the data acquisition device using a multi-core heterogeneous SOC, although the power-off reset can be achieved by operating the PCIe reset pin, it still cannot solve the key problems such as the loss of important data caused by the global reset and the long reset time. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a multi-core heterogeneous SOC reset method, electronic device and chip, which can realize local reset of the multi-core heterogeneous SOC to overcome key problems such as loss of important data caused by global reset and long reset time.

[0004] In order to achieve the above-mentioned object, an embodiment of the present application provides a multi-core heterogeneous SOC reset method, wherein the multi-core heterogeneous SOC is applied to a data acquisition terminal, the data acquisition terminal is connected to a host computer via PCIe, the multi-core heterogeneous SOC includes a security domain, an application domain and a resource management domain, and an inter-core communication channel is set between the security domain, the application domain and the resource management domain, and the method includes:

[0005] When the system starts, the reset parameter register of the data acquisition terminal and the register of the interface controller are mapped to the host computer;

[0006] The host computer monitors the data transmission of the data acquisition terminal, and when it is detected that the data transmission of part or all of the application domains is interrupted, the host computer sends a reset preparation signal to the security domain;

[0007] In response to the reset preparation signal, the security domain feeds back a reset confirmation signal to the host computer, and sends a reset instruction to the resource management domain and the application domain through the inter-core communication channel, preparing to perform a partial reset on the multi-core heterogeneous SOC;

[0008] In the process of resetting the application domain, the resource management domain closes the resources of the application domain and clears the interface controller data;

[0009] After the application domain is reset, the application domain sends a clock resource initialization request to the security domain to start the corresponding application; the security domain sends a reset completion signal to the host computer to enable the data acquisition device to transmit data to the host computer again.

[0010] Optionally, when the host computer does not receive a reset confirmation signal fed back after the security domain responds to a reset preparation signal within a preset period of time, a global reset process is initiated, or the data acquisition terminal is powered on again to perform a global reset.

[0011] Optionally, after the security domain feeds back a reset confirmation signal to the host computer, it sends a resource release signal to the resource management domain; in response to the resource release signal, the resource management domain feeds back a release completion signal to the security domain, and the security domain resets the application domain.

[0012] Optionally, the resource management domain releases the resources of the application domain in response to the resource release signal, which includes:

[0013] Control the corresponding interface controller of the application domain to stop accessing the external device;

[0014] When it is detected that the external device is in a non-working state, the external device is controlled to stop;

[0015] The memory management configuration information and hardware resource configuration information of the application domain are obtained and transmitted to the security domain, and the security domain resets the application domain according to the configuration information to release the resources of the application domain.

[0016] Optionally, the security domain resetting the application domain according to the configuration information includes:

[0017] Initialize the relevant resources of the application domain according to the configuration information;

[0018] Restarting the application domain;

[0019] Feedback the normal working signal of the application domain to the security domain.

[0020] Optionally, after receiving the normal working signal of the application domain, the security domain feeds back a reset completion signal to the host computer to notify the host computer to restart data transmission.

[0021] Optionally, the reset parameter register in the data acquisition terminal and the register of the interface controller are mapped to the address space of the host computer through the base address register space.

[0022] Optionally, the base address register space is allocated according to the memory address space size or I / O address space size required by the data acquisition terminal set by the base address register in the data acquisition terminal configuration space.

[0023] An embodiment of the present application further provides an electronic device, which includes a processor and a memory, wherein an executable program is stored in the memory, and the processor executes the executable program to perform the steps of the method described above.

[0024] The embodiment of the present application further provides a chip, which adopts a multi-core heterogeneous SOC. The multi-core heterogeneous SOC adopts the method as described above to achieve partial reset of the multi-core heterogeneous SOC by resetting the application domain.

[0025] In the multi-core heterogeneous SOC reset method provided in the embodiment of the present application, the multi-core heterogeneous SOC is applied to a data acquisition terminal, the data acquisition terminal is connected to a host computer via PCIe, the multi-core heterogeneous SOC includes a security domain, an application domain and a resource management domain, and an inter-core communication channel is set between the security domain, the application domain and the resource management domain. The method provides a basis for local reset of the multi-core heterogeneous SOC by mapping the reset parameter register of the data acquisition terminal and the register of the interface controller to the host computer when the system starts. Through the interaction between the host computer and the security domain, the application domain and the resource management domain, as well as the inter-core interaction between the security domain, the application domain and the resource management domain, the application domain where data transmission is interrupted can be reset to achieve local reset of the multi-core heterogeneous SOC. The local reset can overcome key problems such as loss of important data caused by global reset and long reset time.

[0026] In addition, the multi-core heterogeneous SOC reset method provided by the embodiment of the present application does not require additional reset buttons and hardware circuits. In the case that the multi-core heterogeneous SOC is completely dead, the data acquisition device can also be globally reset through the PCIe reset pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a flow chart of a multi-core heterogeneous SOC reset method according to an embodiment of the present application;

[0028] Figure 2 This is a flow chart of a multi-core heterogeneous SOC reset method in an embodiment of the present application in which a security domain sends a reset instruction to a resource management domain through an inter-core communication channel;

[0029] Figure 3 This is a flow chart of the resource management domain releasing the resources of the application domain in response to the resource release signal in the multi-core heterogeneous SOC reset method of the embodiment of the present application;

[0030] Figure 4 This is a flow chart of resetting the application domain according to the configuration information in the multi-core heterogeneous SOC reset method of the embodiment of the present application;

[0031] Figure 5 A schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] Various schemes and features of the present application are described herein with reference to the accompanying drawings. It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0033] The embodiment of the present application provides a multi-core heterogeneous SOC (System on Chip) reset method, which is applied to a data acquisition terminal, and the data acquisition terminal is connected to a host computer through PCIe (Peripheral Component Interconnect Express), wherein the host computer can be a Windows system computer, an industrial control computer or a workstation, etc. In practical applications, a partial reset of a multi-core heterogeneous SOC can be completed on the host computer through the PCIe interface.

[0034] Specifically, the multi-core heterogeneous SOC includes a security domain, an application domain and a resource management domain, wherein an inter-core communication channel is set between the security domain, the application domain and the resource management domain.

[0035] The security domain is mainly used to protect the security and privacy of the system. Specifically, the security domain can be responsible for encrypting important data, verifying the identity of each component or external device in the system, and limiting access to key resources in the system such as security configuration registers and encryption key storage areas. The security domain usually runs some real-time systems with higher security. For example, in an autonomous vehicle, the security domain needs to collect data from various sensors of the vehicle (such as lidar, cameras, etc.) in real time and process this data in a timely manner to make driving decisions.

[0036] The application domain is a functional area in a multi-core heterogeneous SOC for specific application scenarios. The application domain is responsible for processing data information using the GPU / CPU, and then transmitting the processed information to the host computer through the PCIe interface. The application domain can use multiple processor cores to support multiple applications running simultaneously. For example, in an autonomous vehicle, one processor core in the application domain runs an intelligent cruise control application to control the vehicle speed based on sensor data; another processor core runs a lane keeping assist application that relies on camera information to control the vehicle to stay in the lane; and there is also a processor core for the infotainment system, playing music or navigation, etc. Multiple processor cores run different applications at the same time. The application domain can coordinate the use of system resources by various applications to avoid conflicts.

[0037] The resource management domain is used to reasonably allocate resources such as processor cores, memory space, and bandwidth according to the needs of each application domain and security domain.

[0038] The security domain, application domain, and resource management domain exchange information through the inter-core communication channel. The security domain communicates security policies (such as identity authentication and access rights determination) to other domains through the inter-core communication channel, and monitors communication security to prevent illegal access and data leakage. The application domain uses the inter-core communication channel to request the resources required for operation from the resource management domain, and receives resource status information fed back by the resource management domain to ensure the normal operation of the application. The resource management domain receives requests from the application domain with the help of the inter-core communication channel, allocates resources according to the policy, and can also interact with the security domain to ensure that resource allocation meets security requirements. This inter-core communication channel enables the three domains to work together, allowing the system to efficiently realize the rational use of resources by applications under the premise of security.

[0039] The multi-core heterogeneous SOC reset method is described in detail below with reference to the accompanying drawings. Figure 1 Flow chart of the multi-core heterogeneous SOC reset method according to an embodiment of the present application, as shown in FIG. Figure 1 As shown, the method comprises the following steps:

[0040] S100: When the system starts, the reset parameter register of the data acquisition terminal and the register of the interface controller are mapped to the host computer.

[0041] In an embodiment of the present application, the reset parameter register is a storage area in the data acquisition terminal, which is used to store key parameters required for resetting or initializing the data acquisition terminal, such as reset mode, reset trigger conditions, and initial state settings of each module after reset.

[0042] After the data acquisition terminal is powered on or reset, the parameters in the reset parameter register will be read to set the basic working state of the data acquisition terminal. For example, it can determine the starting mode of data acquisition, which can be set to event-triggered acquisition or timed acquisition. When the starting mode is set to timed acquisition, the acquisition cycle also needs to be set, for example, sensor data is collected every 5 seconds. When the system fails, software errors occur, or it needs to restart, the setting of the reset parameter register can restore the data acquisition terminal to the preset initial state.

[0043] Data acquisition terminals usually need to communicate or exchange data with external devices through various interface controllers to achieve functions such as data transmission and command issuance. These interface controllers are equipped with corresponding registers. Among them, the interface controller can be an SPI (Serial Peripheral Interface) interface controller, a UART (Universal Asynchronous Receiver / Transmitter) interface controller, an I 2 C (Inter-Integrated Circuit) interface controller, USB interface controller, CAN (Controller Area Network Bus) interface controller, and Ethernet, Bluetooth, WIFI and other network interface controllers. For different types of interface controllers, the specific functions of their registers have different focuses, but in general they can be used to control the working status of the interface controller and manage the information exchanged with external devices. Taking the USB interface controller as an example, its registers can be registers for storing device connection status information, registers for controlling data transmission rate and transmission direction, and registers for managing interrupt requests.

[0044] The registers of the interface controller can be used to set various parameters for communicating with external devices. For example, the data transmission rate of the communication interface can be set. For the UART (Universal Asynchronous Receiver / Transmitter) interface, the baud rate can be set to 9600bps (bits per second), 19200bps or 38400bps, etc. The data format can also be determined, for example, it can be set to transmit data in a format of 8 data bits and 1 stop bit. The registers of the interface controller can be used to store and set relevant communication protocol parameters. For example, in the I 2 In C communication, the register of the interface controller can set the slave device address so that the data acquisition terminal as the master device can correctly communicate with the specified external device and achieve protocol adaptation. In addition, the register of the interface controller can also record whether the interface has data receiving or sending activities and detect communication errors.

[0045] By mapping the reset parameter register of the data acquisition terminal and the register of the interface controller to the host computer, the host computer can directly access and modify the content in the reset parameter register without having to operate on site at the data acquisition terminal. For example, if the initialization parameters such as the frequency and mode of data acquisition need to be changed, the operator can remotely reset them through the host computer, greatly improving the configuration efficiency. In the case of multiple data acquisition terminals, their register parameters can be uniformly managed on the host computer to ensure the consistency and accuracy of communication and achieve efficient centralized control. In addition, the host computer can read the values ​​in these two types of registers in real time and intuitively present the current status of the data acquisition terminal. For example, by checking the status flag bit in the register of the interface controller, it is possible to quickly determine whether the interface is working properly, whether there is a communication error, etc. When the data acquisition terminal fails, the host computer can also analyze and troubleshoot according to the parameters obtained by the register mapping. For example, after the reset, the data acquisition terminal cannot start working normally. By checking the settings in the reset parameter register with the help of the host computer, it can be determined whether it is caused by an initial parameter error, which helps to quickly locate the root cause of the fault and shorten the maintenance time.

[0046] S200, the host computer monitors the data transmission of the data acquisition terminal. When it is detected that the data transmission of part or all of the application domains is interrupted, the host computer sends a reset preparation signal to the security domain.

[0047] In an embodiment of the present application, the host computer can monitor the data transmission status of the data acquisition terminal through the register of the interface controller, or it can comprehensively judge the status of data transmission by receiving data actively reported by the data acquisition terminal, sending specific query instructions and based on the reply status.

[0048] The security domain plays an important role in the entire system, such as ensuring system security and controlling key operation permissions. When the host computer detects data transmission interruption, it sends a reset preparation signal to the security domain. The main purpose is to trigger a series of subsequent operations that can restore the system to normal operation, and ensure that these operations are carried out in accordance with the security policy.

[0049] S300. In response to the reset preparation signal, the security domain feeds back a reset confirmation signal to the upper computer, and sends a reset instruction to the resource management domain and the application domain through the inter-core communication channel, preparing to perform a partial reset on the multi-core heterogeneous SOC.

[0050] In an embodiment of the present application, after receiving the reset preparation signal, the security domain verifies the legitimacy of the request of the host computer, which involves verifying the identity and authority of the host computer. After passing the verification, the security domain starts the reset-related preparations. For example, the security domain checks the security status of the current system to confirm whether the reset operation is allowed to be performed to prevent new security issues caused by resetting at inappropriate times (for example, the system is undergoing an important security update). Then, the security domain coordinates the resource management domain and the application domain according to the preset security policy and system architecture, and prepares to monitor the reset process throughout the process to ensure that the reset operation is carried out in an orderly manner in accordance with the established security specifications to avoid adverse consequences such as data loss and illegal intrusion of the system. After the preparations are ready, the security domain sends a formal reset instruction to the resource management domain and the application domain to prepare for a partial reset of the multi-core heterogeneous SOC.

[0051] S400: During the process of resetting the application domain, the resource management domain closes the resources of the application domain and clears the interface controller data.

[0052] Generally, an application domain occupies various resources during operation, such as storage resources, computing resources, and network resources. Storage resources are used to store temporary data and configuration files, and computing resources involve the processor time occupied by the running algorithms or tasks. When the application domain communicates with external devices, network resources are involved. In order to ensure that the reset process can proceed smoothly and avoid problems such as resource occupation conflicts or interference from old data that affect the reset effect, the resource management domain needs to first close these resources occupied by the application domain.

[0053] For storage resources, the resource management domain modifies the access permission table of storage resources through the corresponding permission management and storage control mechanism, and sets the corresponding access permission of the application domain to an unavailable state. For example, in a storage architecture based on the file system, the read and write permissions of the application domain-related files and folders are revoked to prevent the application domain from continuing to read and write to them. At the same time, for some temporary data caches in memory, the corresponding memory space is released, and the memory blocks originally allocated to the application domain are marked as free by calling the memory management function at the operating system level or the relevant resource release interface for use by other modules.

[0054] For computing resources, the resource management domain can cooperate with the process scheduling module of the operating system to suspend or terminate the processes related to the application domain. For example, a specific signal is sent to the operating system, such as the SIGTERM signal used to request the normal termination of the process, so that the task processes running in the application domain can stop running in an orderly manner, releasing the CPU time slices and other related system resources they occupy. In addition, the resource management domain updates the relevant records of the application domain in the computing resource allocation table and marks them as closed to avoid the subsequent incorrect allocation of resources to the application domain being reset.

[0055] For network resources, the resource management domain notifies the network module to disconnect the network connection established between the application domain and external devices. By calling the shutdown function of the network programming interface, the network port resources are released, and at the same time, the network router or switch and other devices are notified to update or delete the routing table items related to the application domain, so that the network traffic is no longer directed to the application domain being reset, ensuring the normal order of network communication.

[0056] S500. After the application domain is reset, the application domain sends a clock resource initialization request to the security domain to start the corresponding application; the security domain sends a reset completion signal to the host computer to enable the data acquisition device to transmit data to the host computer again.

[0057] In the embodiment of the present application, when the application domain is reset, it indicates that some key parameters and operating environment of the application domain have been restored to the initial or preset appropriate state. In order to carry out subsequent business application operations normally, the application domain needs to rely on some external resources, such as clock resources.

[0058] By sending a clock resource initialization request to the security domain, the application domain expects to obtain accurate clock signals and corresponding clock configuration information, etc., in preparation for starting the corresponding application. Specifically, in the data acquisition terminal, different applications are responsible for various tasks such as data reading, data preprocessing, data transmission and data caching, and the operation of these applications often requires precise time to accurately control the timing of the data, record operation timestamps, etc., so clock resource initialization is very necessary.

[0059] Specifically, the process of the security domain processing the clock resource initialization request and feeding back the clock resource may be:

[0060] When the security domain receives the clock resource initialization request from the application domain, it first verifies the legitimacy of the request, for example, checking whether the application domain initiating the request has the corresponding authority and whether the request format complies with the specification. Then, after the verification, the security domain obtains the corresponding clock parameters from the internal clock source according to the clock resources it manages and the specific needs of the application domain, and returns these parameters to the application domain in accordance with the established communication method. In the process of returning parameters, the security domain can perform operations such as data encryption and verification to ensure the integrity and confidentiality of the transmitted data, and prevent the clock resources from being tampered with or leaked during transmission, which affects the normal startup and operation of the application.

[0061] In addition, when the security domain completes the relevant reset operation, a reset completion signal is generated. The reset completion signal indicates that the security-related links in the abnormal or initialization stage have been restored to a normal state where subsequent operations can be performed. After the host computer receives the reset completion signal from the security domain, it first verifies and analyzes the signal. The verification is mainly to confirm the legitimacy of the signal source and whether it has been tampered with during the transmission process, and the analysis is to extract useful information, such as the operating status information of each key module after the reset. After confirming that the reset completion signal is valid, the host computer sends corresponding instructions to the data acquisition device according to the internal logic settings and the overall operation requirements of the current system to notify the data acquisition device to resume transmitting data to the host computer.

[0062] In one embodiment of the present application, in the above step S300, when the host computer does not receive the reset confirmation signal fed back after the security domain responds to the reset preparation signal within a preset time period, the global reset process is started, or the data acquisition terminal is powered on again to perform a global reset.

[0063] It should be noted that a specific time period can be pre-set in the host computer. This time period is a reasonable time period set based on multiple factors such as the normal response speed of the system, network transmission delay, and the time required for related operations. For example, after multiple tests and verification of actual application scenarios, it is found that under normal circumstances, the security domain takes an average of about 5 seconds from receiving the reset preparation signal to sending the reset confirmation signal under the conditions of a stable network environment and no equipment failures. Considering a certain margin, the preset time period can be set to 0 to 8 seconds.

[0064] If the host computer does not receive the reset confirmation signal from the safety domain within the preset time, this indicates that some abnormal situation may have occurred. For example, a network communication failure caused the signal transmission to be interrupted, a hardware failure occurred in the safety domain itself, making it unable to complete the preparation work and feedback the signal, or a deadlock or freeze occurred at the software level, thus affecting its normal response.

[0065] In response to the above abnormal situations, the host computer can perform a unified reset operation on the entire related system according to the established global reset logic to ensure that the system can operate normally after the reset as much as possible. The host computer can also re-power on the data acquisition terminal to force the data acquisition terminal to restart at the hardware level, reload the firmware, initialize the hardware module, etc. This can solve the problem of untimely signal feedback caused by the data acquisition terminal's own failure or abnormal state to a certain extent. Moreover, the re-powering on of the data acquisition terminal can drive the host computer connected to it to re-initialize and perform other operations, thereby promoting the entire system to return to a normal resettable state or directly complete the reset.

[0066] In one embodiment of the present application, in the above step S100, the reset parameter register in the data acquisition terminal and the register of the interface controller can be mapped to the address space of the host computer through the bar space.

[0067] Among them, during the BIOS (Basic Input Output System) startup phase, the BIOS needs to identify the various hardware devices connected to the host computer so that the operating system can interact with them correctly later. PCIe devices are one of the hardware types that need to be identified and configured. Each PCIe device has a configuration space, which is used to store various configuration information related to the device, such as the device's identification number, functional feature description, and resource requirements. bar (Base Address Register) is a set of registers in the PCIe device configuration space, which is used to set the memory address space or I / O address space size required by the PCIe device.

[0068] During the BIOS startup phase, the BIOS accesses the configuration space of each PCIe device one by one. After the BIOS reads the address space size set by each bar in the PCIe device configuration space, it allocates a corresponding address space range of appropriate size for this PCIe device in the system's address space resources. This allocated address space is the bar space.

[0069] In an embodiment of the present application, the data acquisition terminal acts as a PCIe device, and the reset parameter registers and the registers of the interface controller in the data acquisition terminal are mapped to the address space of the host computer through the bar space, so that the host computer can manage and use the data acquisition terminal as easily as operating its own memory or I / O port.

[0070] The reset parameter register is mapped to the address space of the host computer through the bar space, and the host computer can directly configure and modify the reset parameters. In the hardware design of the data acquisition terminal, a specific physical address range can be assigned to the reset parameter register, and this physical address range is connected to the bar space through components such as the address decoder. When the system starts or initializes, components such as the address decoder map this physical address range to a specified virtual address in the address space of the host computer according to pre-set rules. In this way, when the host computer accesses this corresponding virtual address, it is equivalent to indirectly accessing the reset parameter register in the data acquisition terminal. For example, the software program in the host computer can change the bit corresponding to the reset mode in the reset parameter register by writing a specific value to this virtual address, thereby switching the reset mode from soft reset to hard reset, and then resetting the data acquisition terminal according to the newly set mode.

[0071] The registers of the interface controller are mapped to the address space of the host computer through the bar space, so that the host computer can monitor and adjust the working status of the interface controller in real time. Similarly, the physical address range of the interface controller registers can be mapped to a specific virtual address area in the host computer address space through the bar space. The host computer can obtain the current status information of the interface controller by reading the data corresponding to these virtual addresses. For example, the host computer can obtain the current network connection speed and data packet loss by checking the registers of the Ethernet interface controller.

[0072] In the embodiment of the present application, further, the bar space is allocated according to the memory address space or I / O address space size required by the data acquisition terminal set by bar in the data acquisition terminal configuration space.

[0073] In one embodiment of the present application, in the above step S300, if Figure 2 As shown, the security domain sends a reset instruction to the resource management domain through the inter-core communication channel, including:

[0074] S310: After the security domain feeds back a reset confirmation signal to the upper computer, it sends a resource release signal to the resource management domain.

[0075] S320. The resource management domain responds to the resource release signal and feeds back a release completion signal to the security domain, and the security domain resets the application domain.

[0076] After receiving the reset preparation signal from the host computer, the security domain starts the internal preparation program, for example, suspending the encryption operation being executed or temporarily saving the security-related data currently being processed, etc., to ensure that each module in the security domain is in a stable and resettable state. When the preparation work is completed, the security domain feeds back a reset confirmation signal to the host computer to inform the host computer that it can continue to advance the reset-related process.

[0077] After the security domain feeds back a reset confirmation signal to the upper computer, it sends a resource release signal to the resource management domain so that the resource management domain releases the memory resources, storage resources, network resources, hardware resources, etc. occupied by the security domain.

[0078] When the resource management domain receives the resource release signal sent by the security domain, it starts a series of resource recovery and management related operations.

[0079] When processing memory resources, the resource management domain first checks the integrity of the memory area to ensure that there are no memory data errors or memory block damage due to the release operation. Then, the resource management domain marks the released memory space as available according to the established memory management algorithm, and performs memory defragmentation to merge the scattered small memory blocks into larger continuous available memory areas, so that they can be more efficiently allocated to other modules or tasks that need memory.

[0080] When processing storage resources, the resource management domain updates the relevant index information in the storage management system, for example, modifies the file allocation table or updates the storage records in the database, accurately marks the corresponding disk space or storage block as free, and cleans up temporary files or invalid data records related to these released resources to facilitate the subsequent storage of new data.

[0081] When processing network resources, the resource management domain notifies the network management module to close the network port previously occupied by the security domain, release the corresponding network bandwidth, and adjust the network traffic control strategy, such as updating the routing table, modifying the bandwidth allocation priority, etc., to ensure a smooth transition after network resources are reallocated, without affecting other modules that are using the network, and maintaining the normal order of network communication.

[0082] When processing hardware resources, the resource management domain marks the occupancy status of certain hardware devices such as processor cores and encryption chips as idle, and then rearranges these hardware resources based on the overall system resource scheduling plan and the current resource requirements of other modules.

[0083] When the resource management domain has released all the resources that should be released, the resource management domain notifies the security domain through a release completion signal that all the resources it requested to release have been successfully released, and the security domain can continue to perform subsequent reset operations.

[0084] In one embodiment of the present application, in the above step S300, if Figure 3 As shown, the resource management domain also responds to the resource release signal to release the resources of the application domain. The process is as follows:

[0085] S330 , controlling the corresponding interface controller of the application domain to stop accessing the external device.

[0086] S340: When it is detected that the external device is in a non-working state, control the external device to stop.

[0087] S350, acquiring memory management configuration information and hardware resource configuration information of the application domain and transmitting them to the security domain, and the security domain resetting the application domain according to the configuration information to release the resources of the application domain.

[0088] In this embodiment, in order to avoid data loss or damage to external devices, the resource management domain can notify the interface controller to stop sending external operation instructions and stop receiving data from external devices through the internal communication mechanism of the system (for example, sending specific control instructions to the driver or hardware module where the corresponding interface controller is located), so that the interface controller enters a silent state and waits for further subsequent resource release operations.

[0089] The resource management domain can determine whether an external device is in a non-working state by:

[0090] The resource management domain can make a judgment by checking the communication status information fed back by the interface controller, for example, whether there is still data transmission activity, whether a response signal from an external device is received, etc.

[0091] For some external devices that support the status self-check function, the resource management domain can also use the status monitoring interface provided by the external device itself to obtain its working status information, and combine this information to determine whether the external device has stopped working.

[0092] The memory management configuration information of the application domain includes the distribution of memory areas occupied by the application during operation, memory allocation strategy, and related identification of important data stored in the memory. The resource management domain interacts with the memory management module of the operating system running the application domain or the built-in memory management mechanism of the application domain itself, and obtains these detailed memory management configuration information according to the query interface and protocol within the system.

[0093] The hardware resource configuration information of the application domain includes the various hardware devices and their related parameters that the application domain depends on for operation, such as the processor cores used by the application programs in the application domain, the occupied hardware interrupt resources, the connected hardware expansion modules such as the graphics card and sound card, and the working mode and configuration parameters of the hardware devices. The resource management domain collects the hardware resource configuration information by communicating and cooperating with the hardware management module of the system. Among them, the hardware management module can be composed of a hardware driver and a hardware abstraction layer. The hardware abstraction layer is a software interface between the operating system kernel and the hardware devices.

[0094] After obtaining the memory management configuration information and hardware resource configuration information, the resource management domain transmits this information accurately to the security domain according to the communication protocol and data format agreed within the system. After receiving this configuration information, the security domain performs a reset operation on the application domain according to the configuration information.

[0095] In the embodiments of the present application, further, Figure 4 As shown, the security domain resets the application domain according to the configuration information, including:

[0096] S360: Initialize relevant resources of the application domain according to the configuration information.

[0097] S370. Restart the application domain.

[0098] S380: Feedback the normal working signal of the application domain to the security domain.

[0099] For memory resources, according to the memory management configuration information, the security domain first backs up the data that needs to be saved to the specified non-volatile storage medium, and then marks the memory area occupied by the application domain as idle according to the memory recycling rules to release memory resources; it performs corresponding sorting work on memory fragments so that memory resources can be reallocated more efficiently.

[0100] For hardware resources, the security domain sends reset instructions to related hardware devices based on the hardware resource configuration information, so that the hardware resources are restored to their initial state when they are not used by the application domain, thereby releasing the application domain hardware resources and creating conditions for the overall reset of the system or subsequent resource allocation.

[0101] In the embodiment of the present application, further, after the security domain receives the normal working signal of the application domain, it feeds back a reset completion signal to the upper computer to notify the upper computer to restart data transmission. After the upper computer receives the reset completion signal, it is clear that the security domain no longer has the potential impact caused by the reset, and the data acquisition device can resume normal data transmission, thereby ensuring that the system's data chain can operate effectively again.

[0102] Based on the same concept, the embodiment of the present application also provides an electronic device, such as Figure 5 As shown, it includes a processor and a memory, wherein an executable program is stored in the memory, and the processor executes the executable program to perform the steps of the method as described above.

[0103] The embodiment of the present application further provides a chip, which adopts a multi-core heterogeneous SOC. The multi-core heterogeneous SOC adopts the method as described above to achieve partial reset of the multi-core heterogeneous SOC by resetting the application domain.

[0104] The storage medium in this embodiment may be included in the electronic device / system; or it may exist independently without being assembled into the electronic device / system. The above storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present application is implemented.

[0105] An embodiment of the present application also provides a vehicle, comprising a processing unit, which is capable of executing the steps of the method described in the above embodiment.

[0106] The vehicle in the embodiments of the present application may be "car", "vehicle" and "entire vehicle" or other similar terms including general motor vehicles, such as sedans, SUVs, MPVs, buses, trucks and other cargo or passenger vehicles, watercraft including various ships and boats, and aircraft, etc., including hybrid vehicles, electric vehicles, fuel vehicles, plug-in hybrid vehicles, fuel cell vehicles and other alternative fuel vehicles. Among them, hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles, extended-range electric vehicles, etc., which are not specifically limited in the present application.

[0107] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0108] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0109] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0110] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0111] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.

[0112] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0113] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0114] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0115] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0116] In the several embodiments provided in the present application, it should be understood that the disclosed multi-core heterogeneous SOC reset method, electronic device and chip can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units (or modules) is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0117] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0118] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0119] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0120] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multi-core heterogeneous SOC reset method, characterized in that: The multi-core heterogeneous SOC is applied to a data acquisition terminal, the data acquisition terminal is connected to a host computer via PCIe, the multi-core heterogeneous SOC includes a security domain, an application domain and a resource management domain, and an inter-core communication channel is provided between the security domain, the application domain and the resource management domain, and the method includes: When the system starts, the reset parameter register of the data acquisition terminal and the register of the interface controller are mapped to the host computer; The host computer monitors the data transmission of the data acquisition terminal, and when it is detected that the data transmission of part or all of the application domains is interrupted, the host computer sends a reset preparation signal to the security domain; In response to the reset preparation signal, the security domain feeds back a reset confirmation signal to the host computer, and sends a reset instruction to the resource management domain and the application domain through the inter-core communication channel, preparing to perform a partial reset on the multi-core heterogeneous SOC; In the process of resetting the application domain, the resource management domain closes the resources of the application domain and clears the interface controller data; After the application domain is reset, the application domain sends a clock resource initialization request to the security domain to start the corresponding application; the security domain sends a reset completion signal to the host computer to enable the data acquisition device to transmit data to the host computer again.

2. The method according to claim 1, characterized in that When the host computer does not receive the reset confirmation signal fed back by the security domain in response to the reset preparation signal within the preset period of time, the global reset process is started, or the data acquisition terminal is powered on again to perform a global reset.

3. The method according to claim 1 or 2, characterized in that: After the security domain feeds back a reset confirmation signal to the host computer, it sends a resource release signal to the resource management domain; the resource management domain responds to the resource release signal and feeds back a release completion signal to the security domain, and the security domain resets the application domain.

4. The method according to claim 3, characterized in that The resource management domain releases the resources of the application domain in response to the resource release signal, which includes: Control the corresponding interface controller of the application domain to stop accessing the external device; When it is detected that the external device is in a non-working state, the external device is controlled to stop; The memory management configuration information and hardware resource configuration information of the application domain are obtained and transmitted to the security domain, and the security domain resets the application domain according to the configuration information to release the resources of the application domain.

5. The method according to claim 4, characterized in that The security domain resetting the application domain according to the configuration information includes: Initialize the relevant resources of the application domain according to the configuration information; Restarting the application domain; Feedback the normal working signal of the application domain to the security domain.

6. The method according to claim 5, characterized in that After receiving the normal working signal of the application domain, the security domain feeds back a reset completion signal to the host computer to notify the host computer to restart data transmission.

7. The method according to claim 1, characterized in that The reset parameter register in the data acquisition terminal and the register of the interface controller are mapped to the address space of the host computer through the bar space.

8. The method according to claim 7, characterized in that The base address register space is allocated according to the memory address space size or I / O address space size required by the data acquisition terminal set by the base address register in the data acquisition terminal configuration space.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein an executable program is stored in the memory, and the processor executes the executable program to perform the steps of the method according to any one of claims 1 to 8.

10. A chip, characterized in that: A multi-core heterogeneous SOC is adopted, and the multi-core heterogeneous SOC adopts the method according to any one of claims 1 to 8 to achieve partial reset of the multi-core heterogeneous SOC by resetting the application domain.

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