Code generation method, device and equipment and readable storage medium

Abstract

The embodiment of the invention provides a code generation method and device, equipment and a readable storage medium, and the method comprises the steps: determining a target module node corresponding to a to-be-verified module in a to-be-verified code based on a target syntax tree corresponding to the to-be-verified code; inserting a delay queue node corresponding to the target delay queue into the target module node, and modifying nodes related to the specified signal group in the target syntax tree; the target delay queue is used for performing random delay output on the specified signal group; converting the modified target syntax tree into a target code containing a target delay queue; the target code is used for verifying the interface time sequence function of the to-be-verified module. Through a syntax tree instrumentation mode, error injection can be conveniently carried out on the to-be-verified module, and the error injection complexity and the requirement threshold for professional skills of verification personnel are reduced. Meanwhile, verification personnel do not need to write tests of test cases corresponding to different transmission delays one by one, verification time is saved, and verification efficiency is improved to a certain extent.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular to a code generation method, apparatus, device and readable storage medium. Background Art

[0002] In hardware verification, verification personnel usually need to fully verify a module to ensure the accuracy and stability of its functions. Taking the timing function verification of the interface as an example, verification needs to be performed based on the timing specification of the interface to ensure that the signal transmission can be carried out within the correct time window.

[0003] In related technologies, verification personnel are often required to write corresponding test cases for different transmission delays one by one, and simulate different transmission delays based on these test cases to verify the timing function of the interface. However, such a hardware verification process uses code that can achieve different transmission delay outputs by writing test cases, which has high code acquisition complexity and low verification efficiency. Summary of the invention

[0004] Embodiments of the present invention provide a code generation method, apparatus, device and readable storage medium.

[0005] In order to solve the above problem, an embodiment of the present invention discloses a code generation method, which includes: Based on the target syntax tree corresponding to the code to be verified, determining the target module node corresponding to the module to be verified in the code to be verified; Inserting a delay queue node corresponding to a target delay queue into the target module node, and modifying nodes related to a designated signal group in the target syntax tree; the target delay queue is used to randomly delay output of each designated signal in the designated signal group; The modified target syntax tree is converted into a target code including the target delay queue; the target code is used to perform interface timing function verification on the module to be verified.

[0006] On the other hand, an embodiment of the present invention discloses a code generation device, the device comprising: A first determination module is used to determine a target module node corresponding to a module to be verified in the code to be verified based on a target syntax tree corresponding to the code to be verified; A first insertion module is used to insert a delay queue node corresponding to a target delay queue into the target module node, and to modify nodes related to a specified signal group in the target syntax tree; the target delay queue is used to randomly delay each specified signal in the specified signal group for output; The first conversion module is used to convert the modified target syntax tree into a target code including the target delay queue; the target code is used to perform interface timing function verification on the module to be verified.

[0007] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned method.

[0008] The embodiment of the present invention further discloses a readable storage medium on which executable instructions are stored. When executed by one or more processors, the processors execute the method as described above.

[0009] The embodiment of the present invention includes the following advantages: in the code generation method provided in the embodiment of the present invention, based on the target syntax tree corresponding to the code to be verified, the target module node corresponding to the module to be verified in the code to be verified is determined; the delay queue node corresponding to the target delay queue is inserted into the target module node, and the node related to the specified signal group in the target syntax tree is modified; the target delay queue is used to randomly delay the output of the specified signal group; the modified target syntax tree is converted into a target code containing the target delay queue; the target code is used to perform timing function verification of the interface of the module to be verified. In this way, since the syntax tree is an abstract representation of the source code syntax structure, it can clearly show the structure and relationship of the code, so by completing the node insertion of the target module node and the node modification in the target syntax tree at the syntax tree level, the node insertion position can be located more quickly based on the structure of the syntax tree, and without changing the original semantic logic of the module to be verified, the logic of random delay output of the signal is introduced. Compared with the verification personnel modifying or rewriting the code to be verified, the complexity of code generation can be reduced by inserting the syntax tree, while reducing the threshold for the professional skills of the verification personnel. At the same time, the target delay queue can randomly delay the output of each specified signal in the specified signal group, eliminating the need for verification personnel to write test cases corresponding to different transmission delays one by one, saving verification time and improving verification efficiency to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0011] Figure 1is a flowchart of a code generation method provided by an embodiment of the present invention; Figure 2 It is a working schematic diagram of a sequential delay queue provided by an embodiment of the present invention; Figure 3 It is a working schematic diagram of a disorderly delay queue provided by an embodiment of the present invention; Figure 4 is a flowchart of specific steps of a code generation method provided by an embodiment of the present invention; Figure 5 It is a delay logic schematic diagram of a target delay queue provided by an embodiment of the present invention; Figure 6 is a block diagram of a code generating device provided by an embodiment of the present invention; Figure 7 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] Reference Figure 1 , shows a flow chart of the steps of a code generation method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps: Step 101: Based on a target syntax tree corresponding to the code to be verified, determine a target module node corresponding to the module to be verified in the code to be verified.

[0014] In an embodiment of the present invention, a code to be verified that needs to be hardware verified is obtained. The code to be verified may be a register transfer level (RTL) code corresponding to a hardware element, and the hardware element may include an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a system on a chip (SoC), etc. In the process of hardware verification of the hardware element, it is necessary to perform interface timing function verification based on the code to be verified corresponding to the hardware element. The interface timing function verification aims to check whether the timing behavior of the interface of the hardware element under different operating conditions meets the design requirements. This is crucial to ensure that the hardware system can communicate with other components or systems correctly and stably. By verifying the timing function of the interface, potential design defects can be discovered and resolved, thereby improving the overall performance and reliability of the hardware system.

[0015] Based on the code to be verified, obtain the target syntax tree corresponding to the code to be verified. The target syntax tree is a data structure generated by the compiler front end when parsing the code to be verified. The target syntax tree can be an abstract syntax tree (AST), which is a tree data structure used to represent the structure of program source code. It is widely used in compilers and interpreters to help analyze and process the syntax structure of programs. The target syntax tree can represent the syntax components in the code to be verified in a tree structure. Each node in the target syntax tree can represent a syntax element (such as a statement, expression, module, signal, etc.) in the syntax structure of the code to be verified. Each instruction in the code to be verified usually corresponds to a node or a group of nodes in the syntax tree.

[0016] Specifically, the compiler front end can perform syntax analysis on the code to be verified, split the code to be verified into multiple word sets (such as token symbols), preprocess or macro expand the word sets (the specific method is similar to the macro expansion of C language), perform syntax analysis on the word sets after preprocessing, identify various syntax structures in them, and then convert them into a target syntax tree. Relevant information in the code to be verified can be extracted from the target syntax tree, such as the port list of a module.

[0017] The module to be verified can be a basic unit in the code to be verified for defining components that need to be verified for timing verification of the data transmission interface. The module to be verified can include input, output, bidirectional (inout) ports and internal logic (such as connections, registers, variables and process blocks). In hardware design, data transmission interfaces can be roughly divided into two types. One is the ready-valid handshake signal for handshake. This type of interface ensures accurate data transmission through the interaction of ready and valid signals. When the valid signal of the sending end is valid, it means that the data is valid, and when the ready signal of the receiving end is valid, it means that the receiving end is ready to receive data. Only when the valid and ready signals are valid at the same time, the data will be transmitted. The other is data transmission based only on the valid signal. This interface is relatively simple. When the valid signal is valid, the data is considered valid and transmitted, but in this case, the receiving end needs to be ready to receive data at all times, otherwise the data may be lost. For these two different types of data transmission interfaces, different strategies and methods need to be adopted in the verification process to ensure the correctness of their functions. In an embodiment of the present invention, the module to be verified can be used as a receiving end, and the module to be verified and another sending module perform data transmission based on a specified signal group.

[0018] The target module node corresponding to the module to be verified is a specific node in the target syntax tree used to represent the module to be verified. The module to be verified usually refers to a larger code block or component, which may contain multiple submodules, functions, variable declarations, etc. Correspondingly, the target module node is usually represented as a subtree or node set in the target syntax tree, and these subtrees or node sets represent the code structure in the module. The target module node can contain multiple child nodes, which represent a specific element inside the module to be verified, such as a statement, expression, parameter, and signal. For example, the target module node can contain multiple port child nodes, signal child nodes, assignment child nodes, and internal logic definitions. The target module node can start with the "module" keyword and end with the "endmodule" keyword. The target module node can start with a root node, and multiple port child nodes and signal child nodes can be connected to it. The port child nodes and signal child nodes are connected by edges, indicating the dependency and connection relationship between them. The assignment child nodes are distributed in different positions of the target module node and are used to describe the signal assignment logic inside the module. The port subnode represents the input and output ports of the module, which can include input ports (input), output ports (output) and bidirectional ports (inout), which are used to describe the interface between the module and the external environment. Each port subnode has attributes such as name, width and direction. The signal subnode represents the signal used inside the module, including wire type (wire) and register type (reg), which are used to describe the signal connection and logical function inside the module. Each signal subnode has attributes such as name, width and type. The assignment subnode represents the assignment operation on a signal, including continuous assignment (assign) and process assignment (such as assignment in the always block), which is used to describe the signal assignment logic inside the module. The continuous assignment subnode usually starts with the assign keyword, followed by an assignment expression. The process assignment subnode is located inside the process block (such as the always block), and can perform assignment operations according to different trigger conditions. The assignment node can contain attributes such as the assigned signal and the assignment expression.

[0019] When the module to be verified and the sending module perform data transmission, data transmission will be performed based on the specified signal group. Among them, the specified signal group is the port signal involved in the interface timing verification requirement of the module to be verified, which can be one signal or multiple signals. It can be specifically determined according to the interface timing verification requirement of the module to be verified. For example, the specified signal group may include multiple port signals for signal handshake. Exemplarily, the specified signal group may include io_task_ready, io_task_valid, io_task_bits_tag, io_task_bits_set, io_task_bits_opcode, io_task_bits_param, and io_task_bits_alias. In the target syntax tree, the specified signal group is usually expressed as a leaf node or a position close to a leaf node under the target module node in the internal logic of the module to be verified.

[0020] Search the target module node corresponding to the module to be verified and the child nodes related to the specified signal group in the target syntax tree. Specifically, based on the module name of the module to be verified in the predefined target configuration file, the node traversal can be performed in the target syntax tree to determine the module node that matches the module name as the target module node. Exemplarily, the traversal can be started from the root node of the target syntax tree. The root node usually represents the entry point of the entire code file or program. Using a depth-first search (DFS) strategy, starting from the root node, traverse down along a path of the target syntax tree until a leaf node is reached. During the traversal process, each node is visited once. For each visited node, first check whether it represents a module, which can be determined by the type or label of the node. If the current node is a module node and its name or identifier matches the name of the target module, it is marked as "target module found". If the current node has been marked as "target module found", continue to search for child nodes related to the specified signal group in its child nodes. Similarly, the node type or label can be used to determine that if the node type or label is a signal node and the name is consistent with the signal name of the specified signal group, the node is determined to be a child node related to the specified signal group.

[0021] If the target signal is not found on the current path, backtrack to the previous node and try to traverse its unvisited child nodes. This process will continue until the target signal is found or all possible paths are traversed. When the target module and target signal are found, the traversal process can end early. If the target module node corresponding to the module to be verified or the child node corresponding to the specified signal group is not found after traversing the entire syntax tree, the traversal fails. It is understandable that during the traversal of the target syntax tree, the position of the module to be verified and the specified signal group in the syntax tree (such as node number, path information, etc.) can be recorded for subsequent processing or analysis.

[0022] Step 102: insert a delay queue node corresponding to a target delay queue into the target module node, and modify the nodes related to the specified signal group in the target syntax tree; the target delay queue is used to randomly delay the output of each specified signal in the specified signal group.

[0023] In an embodiment of the present invention, since it is necessary to verify the interface timing function of the module to be verified when performing hardware verification, the transmission delay logic can be inserted based on the target module node corresponding to the module to be verified to simulate the signal transmission delay and realize the delayed output of the specified signal group in the module to be verified. Based on the pre-built target delay queue, the delay queue node corresponding to the target delay queue is obtained. Among them, the target delay queue can be a pre-built code module for generating random delays to randomly delay the output of each specified signal in the specified signal group, and the target delay queue can include a sequential delay queue or a disordered delay queue. The delay queue node corresponding to the target delay queue can be composed of one or more nodes, and the delay queue node is used to describe the code structure of the target delay queue.

[0024] Insert the delay queue node corresponding to the target delay queue in the target module node. At the same time, since the delay queue node is inserted in the target module node, which is equivalent to introducing a delay mechanism for the specified signal group, it is necessary to modify and adjust the nodes of some nodes related to the specified signal group in the target syntax tree to ensure that the module logic of the module to be verified after the transmission delay logic is inserted is not affected. The nodes related to the specified signal group may include the signal declaration node corresponding to the specified signal group, the expression node related to the specified signal group, the assignment statement node, etc. It is understandable that the positioning method of the sub-nodes related to the specified signal group in the target syntax tree can be determined based on the node type and attribute, which is similar to the positioning method of the target module node, and will not be repeated here. The content of the node modification and adjustment of the sub-nodes related to the specified signal group can be determined according to the code structure change represented by the target syntax tree after the delay queue node is inserted, which can specifically include but is not limited to modifying the signal name, type, connection relationship of the specified signal group and establishing a new connection between the specified signal group and the delay queue. The node modification and adjustment of the sub-nodes related to the specified signal group is to ensure the structural consistency of the target syntax tree after the delay queue node is added.

[0025] In a possible implementation, after inserting a delay queue node corresponding to the target delay queue into the target module node, the original signal names in the signal declaration nodes related to the specified signal group in the target module node are all modified to the target signal names, and the original signal names of the specified signal group in each downstream node corresponding to the code downstream of the module to be verified in the code to be verified in the target syntax tree are all modified to the target signal name. In this way, since the delay queue node is inserted into the target module node, the specified signal group in the delay queue node is represented by the target signal name, and it is necessary to directly update all references to the original signal name in the target module node and the downstream nodes to the target signal name to ensure that the use of the specified signal group inside the module to be verified and in the downstream modules is not affected.

[0026] In another possible implementation, the original port signal of the specified signal group in the port subnode used to describe the port declaration parameters in the target module node can be modified to the target signal name, and the target subnode with the value of the original port signal name can be recreated in the target module node to complete the signal declaration of the specified signal group of the original port signal name, and then a delay queue node is inserted into the target module node, so that the specified signal group named the target signal name will be input into the target delay queue, and the output signal of the target delay queue will be connected to the specified signal group named the original port signal name, that is, the remaining code inside the module to be verified can still access the value of this specified signal group through the original port signal name, and accordingly, the remaining logic inside the module to be verified can continue to use the original port signal name (actually the specified signal group with the internal name of the original port signal name connected to the output of the target delay queue) for subsequent processing or calculation.

[0027] Step 103: convert the modified target syntax tree into a target code including the target delay queue; the target code is used to verify the interface timing function of the module to be verified.

[0028] In an embodiment of the present invention, a delay queue node is inserted into the target module node in the target syntax tree and the nodes related to the specified signal group are modified to complete the logical injection of the transmission delay, and the modified target syntax tree can be converted back into the target code. Among them, the target code contains a target delay queue, and the difference between the converted target code and the original code to be verified is that the target delay queue is inserted and the port signal name of the specified signal group and the signal connection relationship are modified. Based on the target code, the transmission delay test of the module to be verified can be implemented to complete the interface timing function verification of the module to be verified. Exemplarily, simulation operation can be performed based on the target code. Since the target code contains a target delay queue, when the sending module and the module to be verified perform data transmission, each specified signal will be first input into the target delay queue, and the target delay queue will randomly delay the output of each specified signal. It can be judged whether the sending module and the module to be verified can perform normal data transmission under the condition of random delay output of the specified signal, and the sending module and the module to be verified can operate normally to verify the interface timing function of the module to be verified.

[0029] Exemplarily, a compiler can be used to first convert the modified target syntax tree into an intermediate representation, such as GIMPLE, and then convert the intermediate representation into a low-level intermediate representation, such as low-level GIMPLE, and generate a control flow graph (CFG), which is used to represent the control flow within the function and divide the statements into basic blocks. The compiler converts the low-level GIMPLE into a static single assignment (SSA) form. The compiler converts the SSA form of GIMPLE into the initial RTL code, and specifically converts the GIMPLE instructions into RTL instructions, including data conversion and instruction conversion. The generated initial RTL code is optimized to determine the final generated target code containing the target delay queue.

[0030] In summary, based on the target syntax tree corresponding to the code to be verified, the target module node corresponding to the module to be verified in the code to be verified is determined; the delay queue node corresponding to the target delay queue is inserted into the target module node, and the node related to the specified signal group in the target syntax tree is modified; the target delay queue is used to randomly delay the output of the specified signal group; the modified target syntax tree is converted into a target code containing the target delay queue; the target code is used to verify the interface timing function of the module to be verified. In this way, since the syntax tree is an abstract representation of the source code syntax structure, it can clearly show the structure and relationship of the code. Therefore, by completing the node insertion of the target module node and the node modification in the target syntax tree at the syntax tree level, the node insertion position can be located more quickly based on the structure of the syntax tree, and without changing the original semantic logic of the module to be verified, the logic of random delay output of the signal is introduced. Compared with the modification or rewriting of the code to be verified by the verifier, the complexity of code generation can be reduced by inserting the syntax tree, while reducing the threshold for the professional skills of the verifier. At the same time, the target delay queue can randomly delay the output of each specified signal in the specified signal group, eliminating the need for verification personnel to write test cases corresponding to different transmission delays one by one, saving verification time and improving verification efficiency to a certain extent.

[0031] Furthermore, by inserting delay queue nodes in the target syntax tree, random delays are introduced into the code implementation logic (i.e., error injection is performed), and in hardware simulation verification, the delay simulation situation can be adjusted at will by simply adjusting parameters, so that various delay situations can be verified in place, making it easier to discover potential timing problems and boundary conditions, thereby improving test coverage, reducing the risks caused by not covering certain situations, and ensuring the robustness of the module functions of the module to be verified under various transmission conditions.

[0032] Optionally, in step 102, "modifying the nodes related to the specified signal group in the target syntax tree" may include the following steps: Step 201: Based on the signal name of each designated signal in the designated signal group, determine the target port subnode corresponding to the designated signal group in the target module node, and modify the original port signal name corresponding to the designated signal group in the target port subnode to the target signal name.

[0033] In an embodiment of the present invention, a target module node includes a plurality of port subnodes, which describe the port declaration parameters corresponding to the module to be verified. The port declaration parameters define the names of the port signals involved in the module to be verified, including the signal names corresponding to the input port (input), the output port (output) and the bidirectional port (inout). The port subnode corresponding to the specified signal group is determined in the target module node, and the original port signal name corresponding to the specified signal group contained in the target port subnode corresponding to the specified signal group is modified to the target signal name. The target port subnode corresponding to the specified signal group may include the port subnodes in the port subnode of the target syntax tree whose names are the same as the signal names of the specified signals in the specified signal group. Therefore, the target port subnode corresponding to the specified signal group can be determined in the target module node based on the signal names of the specified signals in the specified signal group. The target signal name corresponding to each specified signal group can be determined based on the original port signal name corresponding to each specified signal group. For example, a prefix identifier such as DF_auto_0__ can be added to the front end of the source port signal name to determine the target signal name. Exemplarily, assuming that the original port signal names of the target port sub-nodes corresponding to the specified signal group in the target module node are io_task_ready, io_task_valid, io_task_bits_tag, io_task_bits_set, io_task_bits_opcode, io_task_bits_param, and io_task_bits_alias, respectively, the original port signal names in each port sub-node can be modified to the target signal names DF_auto_0__io_task_ready, DF_auto_0__io_task_valid, DF_auto_0__io_task_bits_tag, DF_auto_0__io_task_bits_set, DF_auto_0__io_task_bits_opcode, DF_auto_0__io_task_bits_param, and DF_auto_0__io_task_bits_alias.

[0034] Since the port sub-node is used to represent the input and output ports of the module, the original port signal name corresponding to the specified signal group contained in the target port sub-node corresponding to the specified signal group is modified to the target signal name, which is equivalent to modifying the signal interface name of each specified signal between the module to be verified and the external environment (such as the sending module), so as to facilitate the target delay queue to delay the output of each specified signal.

[0035] Step 202: Recreate a target child node in the target module node with the name of the original port signal.

[0036] In an embodiment of the present invention, a target subnode whose value is the original port signal name is recreated in the target module node. Specifically, after the signal name in the port subnode corresponding to the specified signal group is modified, a target subnode whose name is the original port signal name can be recreated after the port subnode in the target module node. The type of the target subnode can be a signal subnode, and the target subnode is used to define the connection and logical function of the specified signal group inside the module. Exemplarily, after the port subnode of the target module node, for each specified signal in the specified signal group, a signal subnode whose name is the original port signal name of each specified signal can be recreated. In this way, it is equivalent to adding a declaration about the specified signal group at the very beginning of the module implementation logic of the module to be verified after the port definition of the module to be verified of the code to be verified. For example, the expression in the module to be verified can be based on a statement such as "wire+original port signal name" to declare the specified signal group.

[0037] In an embodiment of the present invention, the original port signal name of the target port subnode corresponding to the specified signal group is modified to the target signal name, and a target subnode with the original port signal name is recreated. This eliminates the need to manually traverse and modify all locations in the target module node where the original port signal name is used, greatly reducing the workload of code reconstruction.

[0038] Optionally, the embodiment of the present invention may further include the following steps: Step 301: Determine a module instance node corresponding to the target module node in the target syntax tree.

[0039] In an embodiment of the present invention, the code to be verified will include a module to be verified and a module instance after the module to be verified is instantiated. Correspondingly, the target syntax tree will also include a target module node corresponding to the module to be verified and a module instance node corresponding to the module instance.

[0040] Exemplarily, the target syntax tree can be traversed based on the node type and node attributes of each node in the target syntax tree to determine whether the node is a node of a module instance type. If so, based on whether the module referenced by the node matches the identifier or name of the target module node, if the module referenced by the node is the same as the identifier or name of the target module node, the node is determined to be a module instance node corresponding to the target module node.

[0041] Step 302: Modify the port signal name corresponding to the designated signal group in the module instance node to the target signal name.

[0042] In an embodiment of the present invention, the port signal name corresponding to the specified signal group in the module instance node is modified to the target signal name, that is, the port signal of the specified signal group of the module instance is modified to the target signal name that is the same as the port signal name of the modified specified signal group of the module to be verified.

[0043] In an embodiment of the present invention, by modifying the port signal name corresponding to the specified signal group in the module instance node corresponding to the target module node to the target signal name that is the same as the port signal name corresponding to the specified signal group of the target module node, it is ensured that the port signal name corresponding to the specified signal group of the module and the module instance is consistent, the consistency of the port signal name is maintained, and errors caused by mismatched port signal names are avoided.

[0044] Optionally, step 102 may include the following steps: Step 401: Generate a target delay queue based on a predefined target configuration file; the target configuration file includes a queue depth, a maximum delay value, a minimum delay value, and a switch state for configuring parameters of the target delay queue.

[0045] In an embodiment of the present invention, a predefined target configuration file is obtained, and the target configuration file may include a queue depth value, a maximum delay value, and a minimum delay value of a delay queue. The target configuration file is parsed to obtain configuration parameters specified by environment variables, including a queue depth value, a maximum delay value, and a minimum delay value of the delay queue. A delay queue is generated according to the parsed configuration parameters. Based on a predefined delay queue class, such as DelayQueue, the configuration parameters are used as initialization parameters of the delay queue class to generate an instance of a delay queue, i.e., a target delay queue.

[0046] The target delay queue can be a code module, in which the connection logic between the specified signal group and the delay queue and the internal delay logic of the target delay queue are defined. The connection logic can specifically include that each specified signal named as the target signal name will be input into the target delay queue, and the output signal of the target delay queue will be connected to each specified signal named as the original port signal name. Exemplarily, inside the target delay queue, based on Verilog statements such as io_in_data[DF_auto_0__bits], io_in_ready[DF_auto_0__io_task_ready], and io_in_valid[DF_auto_0__io_task_valid], the new port signal, that is, the value of the target signal name, is assigned to the input end of the target delay queue. Furthermore, based on Verilog statements such as io_out_data[DF_auto_0__bits_out], io_out_ready[__io_task_ready], and io_out_valid[io_task_valid], the output signal of the target delay queue is connected to the internal designated signal group, that is, each designated signal whose name is the original port signal name.

[0047] Step 402: Obtain a delay queue node corresponding to the target delay queue.

[0048] In an embodiment of the present invention, a grammatical analysis is performed on the target delay queue, the code corresponding to the target delay queue is split into multiple word sets (such as token symbols), the word sets are preprocessed or macro-expanded (the specific method is similar to the macro expansion of the C language), and the word sets after preprocessing are subjected to grammatical analysis to identify various grammatical structures therein, and then converted into a delay queue node corresponding to the target delay queue. The delay queue node may include a root node and child nodes, the root node is used to represent the target delay queue itself, and the child nodes under the root node may represent the signal connection logic and signal assignment logic of the signal output and signal input of the target delay queue.

[0049] Step 403: insert a delay queue node corresponding to the target delay queue after the target child node.

[0050] In the embodiment of the present invention, after the target child node, the delay queue node is inserted into the target syntax tree, and the delay queue node is used as the downstream node of the target child node. The "after" here is based on the traversal order, that is, when traversing the parent node first, then the child node, and the same level nodes from left to right, the delay queue node will appear behind the target child node.

[0051] In an embodiment of the present invention, a specified signal group in the verification code is randomly delayed by syntax tree plugging, and a target delay queue capable of generating random delay is inserted in the middle of the handshake path of the specified signal group. The depth of the queue, the maximum and minimum values ​​of the random delay, and whether to turn on the random delay and set the size of the random delay can be set by setting the depth of the queue, as well as by controlling whether to turn on the random delay and setting the size of the random delay through environment variables during simulation operation. Diversified simulations can be performed, making it easier to trigger edge verification situations that were originally difficult to trigger, thereby improving test coverage. In addition, by converting the target delay queue into a delay queue node and directly inserting it into the target subnode in the target syntax tree to implement the delay plugging logic, the position where the delay queue plugging is required can be more accurately located, thereby ensuring the accuracy of the plugging.

[0052] Optionally, the embodiment of the present invention may further include the following steps: Step 501: Based on the target delay queue in the target code, delay the output of the designated signal group; the target delay queue is a sequential delay queue or a disorderly delay queue.

[0053] In the embodiment of the present invention, based on the target delay queue in the target code, the received designated signal is delayed and output to complete the transmission delay test of the module to be verified. By randomly delaying the output of each designated signal through the target delay queue, it can be further verified whether the sending module and the module to be verified can normally perform data transmission under the condition of the random delay output of the designated signal, and whether the sending module and the module to be verified can operate normally, so as to perform the interface timing verification of the module to be verified.

[0054] The target delay queue is a sequential delay queue or a random delay queue. The sequential delay queue outputs the signal delay of each specified signal in the specified signal group in a predetermined order, and the elements in the sequential delay queue are sorted according to the order of entry and the specified delay time. Only when the delay time of the element is reached, the element will be taken out for processing. The random delay queue allows elements to be processed in any order within the delay time, rather than being output strictly in the order of entry.

[0055] Optionally, when the target delay queue is a sequential delay queue, step 501 may include the following steps: Step 601: Based on the target delay queue, the designated signals sent to the target delay queue by the sending module and the module to be verified are received in sequence.

[0056] In an embodiment of the present invention, when the sending module and the module to be verified perform data transmission, the target delay queue will sequentially receive each designated signal in the designated signal group sent to the target delay queue by the sending module and the module to be verified. After receiving each designated signal, the target delay queue will store each designated signal in a target buffer in order as a table entry in the target buffer. The target buffer may be a first-in, first-out queue (FIFO).

[0057] Step 602: Determine the output order of each of the designated signals according to the order in which each of the designated signals is received.

[0058] In the embodiment of the present invention, the output order of each designated signal is determined according to the order in which each designated signal is received by the target delay queue. The order in which each designated signal is received may be the order in which each designated signal is queued into the target buffer, and the output order of each designated signal is the same as the order in which each designated signal is received, that is, the designated signal received first is output first, and the designated signal received later is output later.

[0059] Step 603: When the output sequence of any designated signal is reached, a first delay time is randomly generated for the designated signal within a target time interval corresponding to the maximum delay value and the minimum delay value.

[0060] In an embodiment of the present invention, after determining the output order for each designated signal, when the output order of any designated signal is reached, a first delay time is randomly generated for the designated signal within a target time interval corresponding to a preset maximum delay value and a preset minimum delay value. The first delay time can be any value within the target time interval. The maximum delay value and the minimum delay value can be determined by the configuration parameters of the delay queue in the target configuration file, and can be set according to the needs, and the embodiment of the present invention does not limit this. Exemplarily, the maximum delay value is 10 time cycles, and the minimum delay value is 1 time cycle. Assuming that there are 3 designated signals, the first delay time generated for each designated signal in turn can be 2 time cycles, 8 time cycles, and 5 time cycles.

[0061] Step 604: When the first delay time randomly generated for the designated signal is reached, output the designated signal through the target delay queue.

[0062] In an embodiment of the present invention, for any designated signal, when the first delay time randomly generated for the designated signal is reached, the target delay queue will output the designated signal, so that the output order of the designated signal output by the target delay queue is the same as the receiving order of the designated signal received by the target delay queue.

[0063] For example, Figure 2 As shown, assuming that the target delay queue receives designated signals 1, 2, and 3 in sequence, the signal output order is also designated signals 1, 2, and 3. First, a first random time delay A is generated for designated signal 1, and when delay A is reached, designated signal 1 is output; then, a first random time delay B is generated for designated signal 2, and when delay B is reached, designated signal 2 is output; finally, a first random time delay C is generated for designated signal 3, and when delay C is reached, designated signal 3 is output.

[0064] In the embodiment of the present invention, when the target delay queue is a sequential delay queue, the sequential delay queue can ensure that each designated signal is processed according to the order of entry and the random delay time. Since the output order of the designated signal is fixed, the simulation verification process is more controllable, which helps the verification personnel to expect and understand the system behavior. In addition, since the output of the designated signal maintains the original order, when a problem occurs, the verification personnel can more easily trace the source of the problem. The sequentiality of the signal output makes the problem location and analysis more intuitive and simple.

[0065] Optionally, when the target delay queue is an out-of-order delay queue, step 501 may include the following steps: Step 701: Based on the target delay queue, the designated signals sent by the receiving and sending module and the module to be verified to the target delay queue are received.

[0066] In the embodiment of the present invention, when the sending module and the module to be verified perform data transmission, the target delay queue will sequentially receive each designated signal in the designated signal group sent to the target delay queue by the sending module and the module to be verified. After receiving the designated signal, the target delay queue will sequentially store the designated signal in the target buffer as a table entry in the target buffer.

[0067] Step 702: Based on a random selector, randomly select a designated signal from the designated signal group as a signal to be output.

[0068] In the embodiment of the present invention, based on the random selector in the target delay queue, a table entry is randomly selected in the target buffer area, that is, a designated signal is selected and the designated signal is used as the signal to be output.

[0069] Step 703: randomly generate a second delay time for the signal to be output within a target time interval corresponding to the maximum delay value and the minimum delay value.

[0070] In an embodiment of the present invention, a second delay time is randomly generated for the signal to be output. The second delay time may be a randomly generated value within a target time interval corresponding to a preset maximum delay value and a preset minimum delay value. The maximum delay value and the minimum delay value may be determined by the configuration parameters of the delay queue in the target configuration file, and may be set according to the needs, and the embodiment of the present invention does not limit this. Exemplarily, the maximum delay value is 10 time periods, and the minimum delay value is 1 time period. Assuming that there are 3 designated signals, the first delay time generated for each designated signal may be 3 time periods, 5 time periods, and 2 time periods.

[0071] Step 704: When the second delay time corresponding to the signal to be output is reached, output the signal to be output through the target delay queue.

[0072] In the embodiment of the present invention, when the second delay time randomly generated for the signal to be output is reached, the target delay queue will output the signal to be output.

[0073] Step 705: reselect a designated signal from the designated signal group based on the random selector and start executing as the signal to be output until all designated signals in the designated signal group are output.

[0074] In an embodiment of the present invention, after the output of a signal to be output is completed, a specified signal is randomly selected from the specified signal group as the signal to be output based on the random selector, and a second delay time is randomly generated for the signal to be output, and when the second delay time is reached, the signal to be output is output until the specified signal group is completely output.

[0075] For example, Figure 3 As shown, assuming that the target delay queue receives designated signals 1, 2, and 3 in sequence, the signal output order is also designated signals 1, 2, and 3. Based on the random selector, the signal to be output is selected as designated signal 2, and the second random time is first generated for designated signal 2, and when the second random time corresponding to designated signal 2 is reached, designated signal 2 is output; then based on the random selector, the signal to be output is selected as designated signal 3, and the second random time is generated for designated signal 3, and when the second random time corresponding to designated signal 3 is reached, designated signal 3 is output; finally, based on the random selector, the signal to be output is selected as designated signal 1, and the second random time is generated for designated signal 1, and when the second random time corresponding to designated signal 1 is reached, designated signal 3 is output.

[0076] In an embodiment of the present invention, when the target delay queue is a disordered delay queue, the disordered delay queue allows each designated signal to arrive at the receiving end in any order after random delay processing. For verification scenarios that are sensitive to data order, a disordered delay queue is used so that the module to be verified can more flexibly deal with the uncertainty of signal arrival. At the same time, the disordered delay queue can more realistically simulate the actual signal transmission situation. Signal transmission in the network is often affected by many factors, including network congestion, transmission delay, etc., which may cause the signal to arrive out of order. The use of a disordered delay queue can better simulate this situation, thereby verifying the performance of the system in an actual environment.

[0077] For example, Figure 4 A flowchart of the specific steps of a code generation method is shown, such as Figure 4 As shown, the user inputs the RTL code (such as Verilog or SystemVerilog) and the target configuration file (the target configuration file contains the specified signal group that needs to be injected with errors), and parses the RTL code. First, the lexical analysis is performed based on the lexer, and then the RTL code is split into multiple word sets (tokens), and then preprocessed. The syntax analysis is performed based on the parser to obtain the abstract syntax tree (AST), that is, the target syntax tree. Based on the specified signal group indicated in the target configuration file, the target syntax tree is modified, including modifying the port signal name of the target port subnode corresponding to the specified signal group in the target module node corresponding to the module to be verified, recreating the target subnode with the original port signal name, inserting the delay queue node corresponding to the target delay queue, and modifying the port signal name corresponding to the specified signal group in the module instance node to the target signal name. The modified target syntax tree is restored to obtain the new RTL code after the target delay queue is inserted.

[0078] For example, Figure 5 A schematic diagram of the delay logic of a target delay queue is shown, such as Figure 5 As shown, when the target delay queue is a sequential delay queue, the designated signal is input into the target buffer area in the sequential delay queue, i.e., Buffers, and random delays are generated for the designated signal in sequence according to the order in which the designated signal is stored in Buffers, and then output. When the target delay queue is a disordered delay queue, the designated signal is input into the target buffer area in the sequential delay queue, i.e., Buffers, and a designated signal is randomly selected from multiple designated signals in the target buffer area through a random selector, and a random delay is generated for it and the designated signal is output.

[0079] Reference Figure 6 , shows a block diagram of a code generation device provided by an embodiment of the present invention, such as Figure 6As shown, the device may specifically include: A first determination module 801 is used to determine a target module node corresponding to the module to be verified based on a target syntax tree corresponding to the code to be verified; A first insertion module 802 is used to insert a delay queue node corresponding to a target delay queue into the target module node and modify the node related to the specified signal group in the target syntax tree; the target delay queue is used to randomly delay each specified signal in the specified signal group; The first conversion module 803 is used to convert the modified target syntax tree into a target code including the target delay queue; the target code is used to perform interface timing function verification on the module to be verified.

[0080] The embodiment of the present invention provides a code generation device, which determines the target module node corresponding to the module to be verified in the code to be verified based on the target syntax tree corresponding to the code to be verified; inserts the delay queue node corresponding to the target delay queue in the target module node, and modifies the node related to the specified signal group in the target syntax tree; the target delay queue is used to randomly delay the output of the specified signal group; the modified target syntax tree is converted into a target code containing the target delay queue; the target code is used to verify the interface timing function of the module to be verified. In this way, since the syntax tree is an abstract representation of the source code syntax structure, it can clearly show the structure and relationship of the code. Therefore, by completing the node insertion of the target module node and the node modification in the target syntax tree at the syntax tree level, the node insertion position can be located more quickly based on the structure of the syntax tree, and without changing the original semantic logic of the module to be verified, the logic of random delay output of the signal is introduced. Compared with the modification or rewriting of the code to be verified by the verification personnel, the complexity of code generation can be reduced by inserting the syntax tree, while reducing the threshold for the professional skills of the verification personnel. At the same time, the target delay queue can randomly delay the output of each specified signal in the specified signal group, eliminating the need for verification personnel to write test cases corresponding to different transmission delays one by one, saving verification time and improving verification efficiency to a certain extent.

[0081] Optionally, the first insertion module 802 includes: A first modification module is used to determine, in the target module node, a target port subnode corresponding to the specified signal group based on the signal name of each specified signal in the specified signal group, and modify the original port signal name corresponding to the specified signal group in the target port subnode to the target signal name; The first creation module is used to recreate a target subnode with the name of the original port signal in the target module node.

[0082] Optionally, the device further comprises: A second determination module, configured to determine, in the target syntax tree, a module instance node corresponding to the target module node; The second modification module is used to modify the port signal name corresponding to the specified signal group in the module instance node to the target signal name.

[0083] Optionally, the first insertion module 802 includes: A first generating module, configured to generate a target delay queue based on a predefined target configuration file; the target configuration file includes a queue depth, a maximum delay value, a minimum delay value, and a switch state for parameter configuration of the target delay queue; A first acquisition module, used to acquire a delay queue node corresponding to the target delay queue; The first insertion sub-node is used to insert a delay queue node corresponding to the target delay queue after the target sub-node.

[0084] Optionally, the device further comprises: The first output module is used to delay the output of the specified signal group based on the target delay queue in the target code; the target delay queue is a sequential delay queue or a disordered delay queue.

[0085] Optionally, when the target delay queue is the sequential delay queue, the first delay module includes: A first receiving module, configured to sequentially receive, based on the target delay queue, the designated signals sent to the target delay queue by the sending module and the module to be verified; A third determining module, used to determine the output order of each of the designated signals according to the order in which each of the designated signals is received; A second generating module is used to randomly generate a first delay time for the designated signal within a target time interval corresponding to a maximum delay value and a minimum delay value when an output sequence of any designated signal is reached; The first output submodule is configured to output the designated signal through the target delay queue when the first delay time randomly generated for the designated signal is reached.

[0086] Optionally, when the target delay queue is the out-of-order delay queue, the first delay module includes: A second receiving module, configured to receive, based on the target delay queue, the designated signals sent by the sending module and the module to be verified to the target delay queue; A first selection module, configured to randomly select a designated signal from the designated signal group based on a random selector as a signal to be output; A third generating module, configured to randomly generate a second delay time for the signal to be output within a target time interval corresponding to the maximum delay value and the minimum delay value; A second output submodule, configured to output the signal to be output through the target delay queue when a second delay time corresponding to the signal to be output is reached; The first execution module is used to randomly select a designated signal from the designated signal group based on the random selector and start execution as the signal to be output until all designated signals in the designated signal group are output.

[0087] Reference Figure 7 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the code generation method of the above embodiment. The executable instructions can form a program.

[0088] An embodiment of the present invention provides a readable storage medium having executable instructions stored thereon. When executed by one or more processors, the processors are enabled to execute the code generation method of the aforementioned embodiment.

[0089] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0090] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. It should be noted that all actions of acquiring signals, information or data in this application are carried out under the premise of complying with the corresponding data protection laws and policies of the country of residence and with the authorization given by the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0091] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0093] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0094] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0095] The above is a detailed introduction to an instruction stream file generation method, an instruction stream file generation device, an electronic device and a readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A code generation method, characterized in that: The method comprises: Based on the target syntax tree corresponding to the code to be verified, determining the target module node corresponding to the module to be verified in the code to be verified; Inserting a delay queue node corresponding to a target delay queue into the target module node, and modifying nodes related to a designated signal group in the target syntax tree; the target delay queue is used to randomly delay output of each designated signal in the designated signal group; The modified target syntax tree is converted into a target code including the target delay queue; the target code is used to perform interface timing function verification on the module to be verified.

2. The method according to claim 1, characterized in that The modifying of the nodes related to the specified signal group in the target syntax tree includes: Based on the signal name of each designated signal in the designated signal group, determining the target port subnode corresponding to the designated signal group in the target module node, and modifying the original port signal name corresponding to the designated signal group in the target port subnode to the target signal name; Recreate a target child node in the target module node with the name of the original port signal.

3. The method according to claim 2, characterized in that The method further comprises: Determining a module instance node corresponding to the target module node in the target syntax tree; The port signal name corresponding to the specified signal group in the module instance node is modified to the target signal name.

4. The method according to claim 2, characterized in that: The inserting a delay queue node corresponding to the target delay queue into the target module node comprises: Generate a target delay queue based on a predefined target configuration file; the target configuration file includes a queue depth, a maximum delay value, a minimum delay value, and a switch state for parameter configuration of the target delay queue; Obtaining a delay queue node corresponding to the target delay queue; A delay queue node corresponding to the target delay queue is inserted after the target child node.

5. The method according to claim 1, characterized in that: The method further comprises: Based on the target delay queue in the target code, the designated signal group is delayed and outputted; the target delay queue is a sequential delay queue or a disorderly delay queue.

6. The method according to claim 5, characterized in that In the case where the target delay queue is the sequential delay queue, the delaying output of the designated signal group based on the target delay queue in the target code includes: Based on the target delay queue, sequentially receiving the designated signals sent to the target delay queue by the sending module and the module to be verified; Determining the output order of each of the designated signals according to the order in which each of the designated signals is received; When the output sequence of any of the designated signals is reached, randomly generating a first delay time for the designated signal within a target time interval corresponding to a maximum delay value and a minimum delay value; When the first delay time randomly generated for the designated signal is reached, the designated signal is output through the target delay queue.

7. The method according to claim 5, characterized in that In the case where the target delay queue is the out-of-order delay queue, the delaying output of the designated signal group based on the target delay queue in the target code includes: Based on the target delay queue, receiving and sending the designated signals sent to the target delay queue by the sending module and the module to be verified; Based on a random selector, randomly selecting a designated signal from the designated signal group as a signal to be output; Randomly generate a second delay time for the signal to be output within a target time interval corresponding to the maximum delay value and the minimum delay value; When a second delay time corresponding to the signal to be output is reached, outputting the signal to be output through the target delay queue; A designated signal is randomly selected from the designated signal group based on the random selector and executed as the signal to be output until all designated signals in the designated signal group are output.

8. A code generating device, characterized in that: The device comprises: A first determination module is used to determine a target module node corresponding to a module to be verified in the code to be verified based on a target syntax tree corresponding to the code to be verified; A first insertion module is used to insert a delay queue node corresponding to a target delay queue into the target module node, and to modify nodes related to a specified signal group in the target syntax tree; the target delay queue is used to randomly delay each specified signal in the specified signal group for output; The first conversion module is used to convert the modified target syntax tree into a target code including the target delay queue; the target code is used to perform interface timing function verification on the module to be verified.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the code generation method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that: Executable instructions are stored thereon, and when executed by one or more processors, the processors are caused to execute the code generation method according to any one of claims 1 to 7.

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