Task deployment method for controlling computer

Abstract

The invention provides a task deployment method for a control computer, and belongs to the technical field of embedded computing systems and equipment in unmanned aerial vehicles, and the method specifically comprises the following steps: deploying a plurality of tasks in the control computer on a multi-core universal processor, enabling a core 0 to carry out an upgrade task through an RS422 interface, an RS422 interface communicating with the core 0 is connected with a PS end through an HP0; the core 1 carries out data receiving and transmitting and completes data resolving through an RS422 interface, and the RS422 interface communicating with the core 1 is connected with a PS end through an HP1; the core 2 carries out data receiving and transmitting and completes data resolving through an RS422 interface, and the RS422 interface in task communication with the core 2 is connected with a PS end through an HP2; and the core 3 performs a parameter binding task. In a synchronous system, quick and efficient data reading and data sending functions are realized when multiple cores access the RS422 bus in parallel.

Description

Technical Field

[0001] The present application relates to the field of embedded computing systems and devices in unmanned aerial vehicles, and more particularly to a method for task deployment of a control computer. Background Art

[0002] The embedded computing system in unmanned aerial vehicles is developing rapidly, with high integration and complex technology. Each subsystem in the aircraft works according to a certain beat or cycle, and the acquisition control of various interfaces has strict timing requirements. This kind of information is strongly related to time, which we call time-sensitive information.

[0003] Missile-borne aircraft have strict timing requirements for the acquisition and control of various interfaces, requiring the control computer to complete the acquisition and calculation in a relatively short time, so it has high requirements for embedded computer systems. At present, facing the data pressure of many interfaces accessing at the same time, the missile-borne aircraft control computer adopts the method of increasing the system semaphore in the system software to queue the multi-core. This method can collect interface data normally, but it wastes system resources and increases the running time of the core. Summary of the invention

[0004] In view of this, the present application provides a task deployment method for controlling a computer, which solves the problems in the prior art and realizes fast and efficient data reading and data sending functions when multiple cores access the RS422 bus in parallel in a synchronous system.

[0005] The present application provides a method for controlling computer task deployment using the following technical solution:

[0006] A method for controlling a task deployment of a computer comprises the following steps:

[0007] Deploy multiple tasks in the control computer on a multi-core general-purpose processor, the multi-core general-purpose processor includes core 0, core 1, core 2, and core 3;

[0008] The RS422 interface of the processor PL end in the control computer is connected to the PS end in the processor through the HP interface controller, the core 0 performs the upgrade task through the RS422 interface, and the RS422 interface communicating with the core 0 is connected to the PS end through HP0;

[0009] Core 1 receives and sends data through the RS422 interface and completes data resolution. The RS422 interface that communicates with Core 1 is connected to the PS end through HP1;

[0010] Core 2 receives and sends data through the RS422 interface and completes data resolution. The RS422 interface that communicates with the core 2 task is connected to the PS end through HP2;

[0011] Core 3 performs parameter binding tasks.

[0012] Optionally, the task external interface control domains of core 0, core 1, core 2 and core 3 are composed of their own AXI HP controllers and UART IPs that are in charge of each core, and each AXI HP controller is bound to a core separately according to user application settings.

[0013] Optionally, the data buffer in the RS422 interface controller is a dual-port RAM. When the RS422 interface receives a complete data packet, it automatically triggers the data sending function of the HP interface, and writes the data packet in the RS422 dual port to the DDR3 memory on the PS side at one time, completing the data reading function; when a core needs to send data, it writes the data to the corresponding storage area of ​​DDR3 at one time, and notifies the corresponding HP interface controller to start the RS422 write operation through a discrete signal, and writes the data in the DDR3 memory to the RS422 write buffer at one time, completing the data sending function.

[0014] Optionally, Core 1 runs guidance and control tasks and communicates with the seeker, servo control unit, autonomous decision-making components and static pressure sensor equipment of the external system through the RS422 interface.

[0015] Optionally, Core 2 runs an integrated navigation mission and communicates with the inertial measurement unit and satellite navigation receiver equipment of an external system through an RS422 interface.

[0016] Optionally, the task cycles on core 0, core 1, core 2 and core 3 are consistent, with a cycle of 2.5-10ms. The control computer synchronizes timing with the external system through synchronization pulses, so that the synchronization pulses of the control computer and the cycle process frequency of the processor core are consistent.

[0017] Optionally, core 1, core 2, and core 3 are synchronized with core 0 via inter-core interrupts, and core 0, core 1, core 2, and core 3 perform inter-core message communication via message queues.

[0018] In summary, this application includes the following beneficial technical effects:

[0019] The method enables fast and efficient data reading and data transmission when multiple cores access the RS422 bus in parallel, solves the access conflict problem of multiple cores accessing external devices through an AXI interface at the same time, solves the jitter problem of task execution time, and solves the problem of low RS422 interface access efficiency. The application method is suitable for task deployment and interface access in a multi-core-based integrated control computer in an unmanned aerial vehicle control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 Schematic diagram of the method for deploying tasks for controlling computers. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0023] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0024] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0026] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0027] An embodiment of the present application provides a method for deploying tasks to control a computer.

[0028] like Figure 1 As shown, a method for deploying tasks to control a computer includes the following steps:

[0029] Multiple tasks in a control computer are deployed on a multi-core general-purpose processor, which includes core 0, core 1, core 2, and core 3; an RS422 interface of a PL end of a processor in the control computer is connected to a PS end in the processor through an HP interface controller.

[0030] Core 0 performs the upgrade task through the RS422 interface. The RS422 interface that communicates with core 0 is connected to the PS end through HP0; core 0 does not perform RS422 communication.

[0031] Core 1 receives and sends data and completes data analysis through the RS422 interface. The RS422 interface that communicates with Core 1 is connected to the PS end through HP1. Core 1 runs the guidance and control tasks. Core 1 communicates with the seeker, servo control unit, autonomous decision-making component and static pressure sensor equipment of the external system through the RS422 interface.

[0032] Core 2 receives and sends data and completes data solution through the RS422 interface. The RS422 interface that communicates with the core 2 task is connected to the PS end through HP2; Core 2 runs the combined navigation task and communicates with the inertial measurement component and satellite navigation receiver equipment of the external system through the RS422 interface.

[0033] Core 3 performs parameter binding tasks and does not perform RS422 communication.

[0034] The task external interface control domains of core 0, core 1, core 2, and core 3 are composed of their own AXI HP controllers and the UART IPs in charge of each core. Each AXI HP controller is bound to a core separately and set according to the user application. The UART IP corresponding to the RS422 interface in charge of core 0 is located in the task external interface control domain of core 0, the UART IP corresponding to the RS422 interface in charge of core 1 is located in the task external interface control domain of core 1, and the UART IP corresponding to the RS422 interface in charge of core 2 is located in the task external interface control domain of core 1.

[0035] The data buffer in the RS422 interface controller is a dual-port RAM. When the RS422 interface receives a complete data packet, it automatically triggers the data sending function of the HP interface, and writes the data packet in the RS422 dual port to the DDR3 memory on the PS side at one time to complete the data reading function; when a core needs to send data, it writes the data to the corresponding storage area of ​​DDR3 at one time, and notifies the corresponding HP interface controller to start the RS422 write operation through a discrete signal, and writes the data in the DDR3 memory to the RS422 write buffer at one time to complete the data sending function.

[0036] The task cycles on core 0, core 1, core 2 and core 3 are consistent, with a cycle of 2.5-10ms. The control computer synchronizes the timing with the external system through synchronization pulses, so that the synchronization pulses of the control computer and the cycle process frequency of the processor core are consistent.

[0037] Core 1, core 2, and core 3 are synchronized with core 0 through inter-core interrupts, and core 0, core 1, core 2, and core 3 communicate with each other through message queues.

[0038] The method of the present application deploys multiple tasks in the control computer on a multi-core general-purpose processor, and the task external interface control domain of each core is composed of respective AXI HP controllers and UART IPs in charge of each core. When the core and the external subsystem perform RS422 data communication, the RS422 interface and the HP interface cooperate to achieve fast and efficient data reading and data sending functions. The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for deploying tasks for controlling a computer, characterized in that: The steps include: Deploy multiple tasks in the control computer on a multi-core general-purpose processor, the multi-core general-purpose processor includes core 0, core 1, core 2, and core 3; The RS422 interface of the processor PL in the control computer is connected to the PS in the processor through the HP interface controller, the core 0 performs the upgrade task through the RS422 interface, and the RS422 interface communicating with the core 0 is connected to the PS through HP0; Core 1 receives and sends data through the RS422 interface and completes data resolution. The RS422 interface that communicates with Core 1 is connected to the PS end through HP1; Core 2 receives and sends data through the RS422 interface and completes data resolution. The RS422 interface that communicates with the core 2 task is connected to the PS end through HP2; Core 3 performs parameter binding tasks.

2. The task deployment method for controlling a computer according to claim 1, characterized in that: The task external interface control domains of core 0, core 1, core 2 and core 3 are composed of their own AXI HP controllers and the UART IPs that each core is responsible for. Each AXI HP controller is bound to a core separately and is set according to the user application.

3. The task deployment method for controlling a computer according to claim 2, characterized in that: The data buffer in the RS422 interface controller is a dual-port RAM. When the RS422 interface receives a complete data packet, it automatically triggers the data sending function of the HP interface, and writes the data packet in the RS422 dual port to the DDR3 memory on the PS side at one time to complete the data reading function; when a core needs to send data, it writes the data to the corresponding storage area of ​​DDR3 at one time, and notifies the corresponding HP interface controller to start the RS422 write operation through a discrete signal, and writes the data in the DDR3 memory to the RS422 write buffer at one time to complete the data sending function.

4. The method for deploying tasks of a control computer according to claim 1, characterized in that: Core 1 runs the guidance and control tasks and communicates with the seeker, servo control unit, autonomous decision-making component and static pressure sensor equipment of the external system through the RS422 interface.

5. The method for deploying tasks of a control computer according to claim 1, characterized in that: Core 2 runs the integrated navigation mission and communicates with the inertial measurement unit and satellite navigation receiver equipment of the external system through the RS422 interface.

6. The method for deploying tasks of a control computer according to claim 1, characterized in that: The task cycles on core 0, core 1, core 2 and core 3 are consistent, with a cycle of 2.5-10ms. The control computer synchronizes the timing with the external system through synchronization pulses, so that the synchronization pulses of the control computer and the cycle process frequency of the processor core are consistent.

7. The method for deploying tasks of a control computer according to claim 1, characterized in that: Core 1, core 2, and core 3 are synchronized with core 0 through inter-core interrupts, and core 0, core 1, core 2, and core 3 communicate with each other through message queues.

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