Interrupt Processing Method, Apparatus, Electronic Device, and Readable Storage Medium

Abstract

An embodiment of the present invention provides an interrupt handling method, apparatus, electronic device, and readable storage medium. The method includes: notifying a virtual processor thread of a pending interrupt triggered by a virtual device thread by setting a value of a first register to a first numerical value; obtaining status parameters of a currently executing code block, and determining whether the currently executing code block meets a first response condition according to the status parameters; the status parameters include: the address of the currently executing instruction in the currently executing code block, whether there is a first response flag bit in the currently executing code block, and the address of the first response flag bit; if the currently executing code block meets the first response condition, exiting the currently executing code block through a first exit and entering an interrupt handling program; if the currently executing code block does not meet the first response condition, exiting the currently executing code block through a second exit and entering an interrupt handling program. The present invention can balance the performance of the translated code during operation and the interrupt response speed.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an interrupt processing method, device, electronic device and readable storage medium. Background Art

[0002] The interrupt mechanism is an important way for peripheral devices (such as hard disk, network card, keyboard, mouse, etc.) to communicate effectively with the processor (Central Processing Unit, CPU).

[0003] System-level Dynamic Binary Translation (DBT) is a technology that translates and converts binary code in real time while a computer system is running. It is typically used to convert binary programs from one instruction set architecture (ISA) to another, or to adapt code between different execution environments, allowing the program to run correctly in the target environment without recompiling the source code.

[0004] Device emulation in system-level DBT is typically implemented in software. The vDEV (Virtual Device) thread simulates the behavior of peripheral devices (such as disks and network cards) and triggers interrupts. The vCPU (Virtual CPU) thread simulates the behavior of the processor (such as instruction translation, execution, and interrupt handling). During the vCPU translation and execution process, long basic blocks may cause interrupts to remain unresponsive for extended periods of time. Summary of the Invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide an interrupt handling method that overcomes the above problems or at least partially solves the above problems, so that interrupts can be responded to in a timely manner at a better time point in different situations, and the performance of the translated code running and the interrupt response speed can be more balanced.

[0006] Correspondingly, an embodiment of the present invention further provides an interrupt processing device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses an interrupt handling method, which is applied to a binary translation system, wherein a virtual device thread and a virtual processor thread are running in the binary translation system. The method includes:

[0008] Notifying the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of the first register to a first value;

[0009] Obtain the status parameters of the currently executing code block, and determine whether the currently executing code block meets the first response condition according to the status parameters; the status parameters include: the address of the currently executing instruction in the currently executing code block, whether there is a first response flag bit in the currently executing code block, and the address of the first response flag bit; wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executing code block exceeds a preset number;

[0010] If the currently executing code block meets the first response condition, the virtual processor thread exits the currently executing code block through the first exit and enters the interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executing code block;

[0011] If the currently executing code block does not meet the first response condition, the virtual processor thread exits the currently executing code block through the second exit and enters the interrupt handler; the second exit is located at the end position of the currently executing code block.

[0012] In a second aspect, an embodiment of the present invention discloses an interrupt processing device, which is applied to a binary translation system, in which a virtual device thread and a virtual processor thread are running, and the device includes:

[0013] An interrupt detection module, configured to notify the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of the first register to a first value;

[0014] A condition judgment module, configured to obtain the status parameters of the currently executing code block, and determine whether the currently executing code block meets the first response condition according to the status parameters; the status parameters include: the address of the currently executing instruction in the currently executing code block, whether there is a first response flag bit in the currently executing code block, and the address of the first response flag bit; wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executing code block exceeds a preset number;

[0015] A first response module, configured to, if the currently executing code block meets the first response condition, exit the currently executing code block through the first exit and enter the interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executing code block;

[0016] A second response module, configured to, if the currently executing code block does not meet the first response condition, exit the currently executing code block through the second exit and enter the interrupt handler; the second exit is located at the end position of the currently executing code block.

[0017] In a third aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the interruption processing method as described in any one of the foregoing.

[0018] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, it can implement the interruption processing method as described in any one of the foregoing.

[0019] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, and when the computer program is executed by a processor, it is the steps of the interruption processing method as described in any one of the foregoing.

[0020] In more other aspects, the present application also provides a binary translation system and a system-level binary translation device.

[0021] The embodiments of the present invention include the following advantages:

[0022] In the translation process of the dynamic binary translator in the embodiments of the present invention, if an interruption to be processed is detected, the state parameter of the currently executing code block is obtained, and it is determined whether the currently executing code block meets the first response condition according to the state parameter; according to whether the currently executing code block meets the first response condition, it is decided to respond to the interruption through the first exit or the second exit. The first response condition is used to determine whether the currently executing code block meets the condition for exiting the currently executing code block in advance. The first exit is used to exit the currently executing code block in advance to respond to the interruption before the currently executing code block ends. The second exit is used to exit the currently executing code block when the currently executing code block ends and respond to the interruption. The embodiments of the present invention select a better interruption response timing (the first exit or the second exit) according to the state parameter of the currently executing code block, so that the interruption can be timely responded at a better time point in different situations; it can avoid overly frequent context switching when there are a large number of and frequent interruptions; it can achieve a better balance between the performance of the translated code running and the interruption response speed.

[0023] In addition, the embodiments of the present invention use a new way to implement the simulation work of interruption detection, which can separate the interruption detection operation from the TB code, and the interruption detection operation no longer depends on the vCPU thread, so that the interruption detection no longer affects the running performance of the translated code, and can further improve the performance of the vCPU thread.

[0024] Furthermore, the embodiments of the present invention do not limit the length of the code block and do not affect the optimization effect of the translator on the code. Description of the Drawings

[0025] Figure 1 It is a schematic diagram of actively detecting interrupts in QEMU;

[0026] Figure 2 It is a flowchart of the steps of an embodiment of an interrupt handling method of the present invention;

[0027] Figure 3 It is a schematic diagram of communication between the qINT thread and the vCPU thread in an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the interrupt handling process in Case 1 in an embodiment of the present invention;

[0029] Figure 5 It is a schematic diagram of the interrupt handling process in Case 2 in an embodiment of the present invention;

[0030] Figure 6 It is a schematic diagram of the interrupt handling process in Case 3 in an embodiment of the present invention;

[0031] Figure 7 It is a block diagram of the structure of an embodiment of an interrupt handling device of the present invention;

[0032] Figure 8 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Embodiments

[0033] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0034] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order different from those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type and do not limit the number of objects. For example, the first object can be one or multiple. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0035] Binary translation technology can solve the problem of applications running across instruction set architectures at the binary level. Specifically, binary translation technology can convert an instruction sequence in one instruction set architecture into an instruction sequence in another instruction set architecture.

[0036] Dynamic Binary Translation (DBT) is widely used in program simulation, instrumentation, debugging, and other applications. The instruction set architecture (ISA) of the guest is emulated, and DBT follows the ISA of the host. By translating the guest binary file into a host binary file, DBT enables cross-ISA translation. For example, it can translate an ARM binary file into an x86 binary file and run it on an x86 platform.

[0037] The translation process is organized in the form of code blocks. A continuous sequence of guest instructions forms a single-entry / single-exit block. This guest block is translated into a host binary block. The guest block can be represented by a "basic block", and the translated host block by a "translation block (TB)". In the following text, depending on the different phases of DBT, the translation block TB may also be referred to as a code block, translated code block, or execution code block. Blocks usually end with a control flow-changing instruction (such as a branch instruction, function call, return instruction, etc.), such as Figure 1 and Figures 3 to 6 the jump exit in

[0038] DBT runs in a loop of a lookup-translation phase (translation state) and an execution phase (execution state). In the lookup-translation phase, DBT searches the code cache for existing translation blocks to find the next block to execute. If the search fails, DBT fetches the guest binary file and generates a translation block. In the execution phase, DBT simply executes the translation block. DBT switches between these two phases using context-switching code.

[0039] There are two modes of dynamic binary translation. The first is user-mode DBT, which executes user-space programs. The second is full-system DBT, which can run a complete operating system. With the help of hardware emulation, the operating system can be any one.

[0040] Full-system DBT can run a complete operating system. To achieve this, the hardware environment must be emulated. Full-system DBT includes software implementations of many hardware devices. Just like real hardware, the emulated hardware also needs to be managed through interrupts. Simulating interrupt delivery is an important part of system DBT.

[0041] The system DBT typically uses multiple threads to help simulate the hardware, separating the simulation of the device from the simulation of the CPU. The vCPU thread is responsible for CPU simulation and manages the translation blocks. It executes the blocks, searches for live lookup blocks (in the code cache), and generates blocks through binary translation. It is also responsible for handling interrupts that may change the control flow. Another thread, called the "I / O thread" in QEMU, is responsible for simulating the hardware devices. In the following text, this thread is also referred to as the vDEV virtual device thread.

[0042] When the simulated hardware needs to send an interrupt to the CPU, the I / O thread will set an interrupt pending flag. Once the interrupt check code of the vCPU thread sees this flag, it will simulate interrupt injection on the vCPU.

[0043] DBT runs in the form of a loop of the lookup-translation phase (translation state) and the execution phase (execution state). Interrupts are detected in the execution state of DBT and, in some embodiments, are processed in the execution state. When there is a pending interrupt, DBT needs to exit the execution phase through the context switch code. The context switch code includes, for example, Figure 1 and Figures 4 to 6 the "exit-context switch" section in

[0044] The interrupt handler in the guest operating system (such as the code pointed to by the IDT table entry of x86) is part of the guest instructions and needs to be dynamically translated into host instructions by DBT like other guest code, and the first execution triggers the translation. When the guest first executes the interrupt handler, DBT searches for existing translation blocks in the lookup-translation phase. If not found, it performs translation to generate the corresponding host code block, as shown in Figure 1 and Figures 4 to 6 "code block lookup" and "code block translation" in

[0045] In a specific implementation, QEMU uses an actively detected interrupt mechanism. Specifically, it actively detects and discovers interrupts at the start position of each TB and immediately exits the TB, as shown in Figure 1As shown in the figure, it is a schematic diagram of actively detecting interrupts in QEMU. When there is an interrupt waiting to be processed, QEMU sets a flag bit for the vCPU thread to indicate the arrival of the interrupt signal. The vCPU thread continuously checks this flag bit during the execution of the TB. When it finds that the flag bit is set, it exits the TB and transfers to the interrupt handling. QEMU generates a section of dynamic detection code for identifying this flag bit at the starting position of each TB, which is an active interrupt detection mechanism. To avoid the interrupt signal not being responded to for a long time, QEMU limits the length of each TB so that the interrupt signal can be detected in time. However, adding detection code at the starting position of each TB introduces additional overhead to the operation of the vCPU thread, affecting the running performance of the translated code. In addition, restricting the length of each code block may result in smaller translated code blocks, further affecting performance and may also affect the optimization effect of the translator on the code.

[0046] Referring to Figure 2 , a flowchart of the steps of an embodiment of an interrupt handling method according to the present invention is shown. The method is applied to a binary translation system in which a virtual device thread (vDEV thread) and a virtual processor thread (vCPU thread) are running. The method includes the following steps:

[0047] Step 101: Notify the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of a first register to a first value;

[0048] Step 102: Obtain the state parameters of the currently executing code block, and determine whether the currently executing code block meets a first response condition according to the state parameters; the state parameters include: the address of the currently executing instruction in the currently executing code block, whether there is a first response flag bit in the currently executing code block, and the address of the first response flag bit; wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executing code block exceeds a preset number;

[0049] Step 103: If the currently executing code block meets the first response condition, the virtual processor thread exits the currently executing code block through a first exit and enters the interrupt handling program; the first exit is located at the end position of a preset number of instructions in the currently executing code block;

[0050] Step 104: If the currently executing code block does not meet the first response condition, the virtual processor thread exits the currently executing code block through a second exit and enters the interrupt handling program; the second exit is located at the end position of the currently executing code block.

[0051] The interrupt handling method provided by the embodiments of the present invention can be applied to a Dynamic Binary Translator (DBT) to optimize the interrupt handling process during binary translation, so as to balance the performance of the translated code during execution and the interrupt response speed.

[0052] In the translation process of the dynamic binary translator in the embodiments of the present invention, the size of the code block is detected; during the execution process, according to the total number of instructions included in the currently executed code block and the position of the currently executed instruction in the currently executed code block, it is determined when to respond to an interrupt. The currently executed code block refers to the code block that is currently in the execution state.

[0053] For different situations, the embodiments of the present invention can set a first exit or a second exit as two interrupt response times. The ways of setting the first exit and the second exit are different, and their positions in the currently executed code block are also different. Therefore, the execution processes of exiting the currently executed code block through the first exit and the second exit to respond to interrupts are also different.

[0054] Exemplarily, if the total number of instructions included in the currently executed code block is large, such as exceeding a preset number, and an interrupt arrives at the beginning of the currently executed code block, if the interrupt is not responded to until all the instructions in the currently executed code block are executed, it will cause the interrupt to not be responded to for a long time. If the interrupt is immediately responded to when it arrives, when there are a large number of frequent interrupts, it will cause too frequent context switching, affecting the system performance.

[0055] To solve this problem, in the execution process of the dynamic binary translator in the embodiments of the present invention, if an interrupt to be processed is detected, the state parameter of the currently executed code block is obtained, and it is determined whether the currently executed code block meets the first response condition according to the state parameter; according to whether the currently executed code block meets the first response condition, it is determined whether to respond to the interrupt through the first exit or the second exit. The first response condition is used to determine whether the currently executed code block meets the condition for exiting the execution state of the currently executed code block in advance, so as to respond to the interrupt in advance. The first exit is used to exit the execution state of the currently executed code block in advance to respond to the interrupt after the Mth instruction in the currently executed code block is executed (corresponding to the interrupt response 2 - exit - context switching in the appendix Figure 5 ). The second exit is used to exit the execution state of the currently executed code block after the currently executed code block is executed, so as to respond to the interrupt after all the instructions in the currently executed code block are executed (corresponding to the jump exit - exit - context switching in the appendix Figure 4 or 6).

[0056] The state parameters may include: the address of the currently executed instruction in the currently executed code block, whether there is a first response flag bit in the currently executed code block, and the address of the first response flag bit. The first response flag bit is inserted into the block by DBT after translating the Mth instruction during the translation phase.

[0057] Wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executed code block exceeds a preset number M, and M is a positive integer. For example, use the variable b to indicate whether there is a first response flag bit in the code block. If b = 1, it means that there is a first response flag bit in the currently executed code block, and the total number of instructions included exceeds the preset number, indicating that the total number of instructions included in the currently executed code block is relatively large. If b = 0, it means that the total number of instructions included in the currently executed code block does not exceed the preset number, indicating that the total number of instructions included in the currently executed code block is not too large. The value of the preset number M can be determined according to the actual scenario, and the embodiments of the present invention do not make any restrictions.

[0058] During the translation phase, when it is detected that the total number of instructions included in the currently translated code block exceeds the preset number M, an interrupt response code is inserted, that is, a response flag bit is set after translating the Mth instruction. Thus, according to the address of the currently executed instruction in the currently executed code block and the address of the first response flag bit, it can be known whether the currently executed instruction is before or after the Mth instruction in the currently executed code block.

[0059] For example, during the execution phase, assume that the total number of instructions included in the currently executed code block exceeds the preset number M. Before executing the Mth instruction, if an interrupt arrives, if the interrupt is not responded until after the remaining instructions are executed, since the number of remaining instructions is still relatively large, it will cause the interrupt to wait for a long time and cannot be responded in time. To solve this problem, in this case, the embodiments of the present invention can exit the currently executed code block through the first exit and enter the interrupt handling program to respond to the interrupt in time; the first exit is located at the end position of the preset number of instructions in the currently executed code block. That is, when the Mth instruction is executed, the first exit is entered. At this time, the currently executed code block can be exited through the first exit and the interrupt handling program can be entered, instead of waiting until all instructions are executed to exit, so that the interrupt can be responded in time.

[0060] Another example, assume that the total number of instructions included in the currently executed code block exceeds the preset number M. After executing the Mth instruction, if there is an interrupt to be processed, since the number of remaining instructions is not much in this case, the currently executed code block can be exited through the second exit and enter the interrupt handling program; the second exit is located at the end position of the currently executed code block.

[0061] Further, when the total number of instructions included in the current execution code block is relatively large (such as b = 1), the embodiments of the present invention can determine whether to exit the current execution code block through the first exit or the second exit according to the status parameters of the current execution code block and enter the interrupt handler, which can not only ensure the boundary integrity of the translated code, but also enable timely response to interrupts in different situations, realizing a balance between the loss of the running performance of the translated code caused by synchronous interrupt detection and the impact of asynchronous interrupt detection on the interrupt response speed.

[0062] In an alternative embodiment of the present invention, the method may further include:

[0063] During the process of translating the binary program of the source platform, if it is recognized that the total number of instructions included in the current translated code block exceeds M (where M is a preset number), then after the Mth instruction and before the (M + 1)th instruction, set the first response flag bit and the code of the first exit (interrupt response code, such as Figure 5 "Interrupt response 2" in). The code of the first exit is used to directly exit the current execution code block and jump to the entry address of the interrupt handler when the value of the first register is detected as the first value in the current execution code block, that is, to go to the context switching code of "exit" at the end, exit the execution stage, switch to the translation stage, and perform interrupt processing.

[0064] To avoid the problem that the vCPU thread cannot exit the execution process of the current execution code block for a long time after receiving an interrupt due to the excessive number of codes in the current execution code block, resulting in untimely response to interrupts, the embodiments of the present invention detect the size of the current translated code block during the process of the dynamic binary translator translating the binary program of the source platform. The current translated code block refers to the code block that is currently in the translation state. For example, after the Mth instruction is translated, if there are still untranslated instructions in the current translated code block, it is recognized that the total number of instructions included in the current translated code block exceeds M, and the first response flag bit can be set (such as setting b = 1) after the Mth instruction and before the (M + 1)th instruction, and the code of the first exit, such as Figure 5 "Interrupt response 2" in, can be added at the position after b = 1.

[0065] The position of the first exit is at the end position of a preset number of instructions in the current translation code block, that is, at the end position of the Mth instruction. After the current translation code block is translated, it is called the translated code block and is stored in the code cache. After the translated code block enters the execution stage or execution state, it is called the current execution code block. The code of the first exit is used to directly exit the execution state of the current execution code block and jump to the entry address of the interrupt handler when the value of the first register in the current execution code block is detected as the first numerical value. Thus, when a pending interrupt is detected, if the current execution code block meets the first response condition, when the dynamic binary translator executes to the code of the first exit and detects that the value of the first register is the first numerical value, such as detecting that the value of register R1 is 1, indicating that there is a pending interrupt currently, at this time, the current execution code block can be directly exited here and jumped to the entry address of the interrupt handler to enter the interrupt handler, without waiting for the current execution code block to finish execution.

[0066] For ease of description, in the embodiments of the present invention, variable a is used to represent the address of the current execution instruction in the current execution code block, variable b is used to represent whether there is a first response flag bit in the current execution code block (b = 0 indicates that there is no first response flag bit, b = 1 indicates that there is a first response flag bit), and variable c is used to represent the address of the first response flag bit. It should be noted that the address of the current execution instruction in the current execution code block and the address of the first response flag bit refer to the value of the program counter (PC) of the client platform (source platform).

[0067] In an optional embodiment of the present invention, the determining whether the current execution code block meets the first response condition according to the state parameter may include:

[0068] If there is a first response flag bit in the current execution code block and the address of the current execution instruction in the current execution code block is less than the address of the first response flag bit, it is determined that the current execution code block meets the first response condition.

[0069] When a pending interrupt is detected, the state parameters of the current execution code block in the vCPU thread can be obtained, including variable a (the address of the current execution instruction in the current execution code block), variable b (whether there is a first response flag bit in the current execution code block), and variable c (the address of the first response flag bit), and it is judged whether the current execution code block has the first response condition through the state parameters of the current execution code block.

[0070] Among them, variable b and variable c belong to the attributes of the currently executing code block and are assigned values during binary translation. They can be stored in a structure that can be obtained by the DBT. Variable a belongs to the attributes of the vCPU thread. The values of variables a, b, and c can be obtained through shared memory.

[0071] If there is a first response flag bit in the currently executing code block and the address of the currently executing instruction is less than the address of the first response flag bit, it is determined that the currently executing code block meets the first response condition. Expressed in variables: If variable b = 1 and variable a < variable c, it is determined that the currently executing code block meets the first response condition.

[0072] When the currently executing code block meets the first response condition, it can exit the currently executing code block through the first exit and enter the interrupt handler. Therefore, there is no need to set the second exit. When the dynamic binary translator executes to the code at the first exit, if it detects that the value of register R1 is 1, it directly exits the currently executing code block and jumps to the entry address of the interrupt handler to enter the interrupt handler, instead of waiting for the currently executing code block to finish execution, that is, it exits the currently executing code block in advance.

[0073] In an alternative embodiment of the present invention, the method may further include:

[0074] If the currently executing code block does not meet the first response condition, the link between the currently executing code block and the next code block is disconnected, and the code of the second exit is set at the end position of the currently executing code block. The code of the second exit indicates that the jump target address is the entry address of the interrupt handler.

[0075] If the currently executing code block does not meet the first response condition, expressed in variables: If variable b = 0 or variable a ≥ variable c, it is determined that the currently executing code block does not meet the first response condition.

[0076] The currently executing code block does not meet the first response condition, including two cases. One case is that the total number of instructions contained in the currently executing code block is small, such as not exceeding the preset number M. In this case, even if the interruption is responded to after the currently executing code block finishes execution, it will not wait for a long time. Another case is that the total number of instructions contained in the currently executing code block is large, such as exceeding the preset number M, but most of the instructions have been executed currently, and the number of remaining unexecuted instructions is small, such as variable a ≥ variable c. In this case, even if the interruption is responded to after all the remaining instructions in the currently executing code block finish execution, it will not wait for a long time. In addition, since variable a ≥ variable c, and the first exit is between the Mth instruction and the (M + 1)th instruction, it indicates that the instruction currently being executed has already been after the first exit, and it is also impossible to exit the currently executing code block through the first exit.

[0077] Therefore, when the currently executing code block does not meet the first response condition, a second exit can be set, and the currently executing code block can be exited through the second exit and enter the interrupt handling program; the second exit is located at the end position of the currently executing code block. That is, after the currently executing code block finishes execution, it exits the currently executing code block through the second exit and enters the interrupt handling program.

[0078] The method of setting the second exit is: disconnect the link between the currently executing code block and the next code block, and set the code of the second exit at the end position of the currently executing code block, and the code of the second exit indicates that the jump target address is the entry address of the interrupt handling program.

[0079] Disconnecting the link between the currently executing code block and the next code block can be achieved by modifying the TB_LINK parameter of the currently executing code block. TB_LINK is a variable or data structure used to describe the link relationship between TBs. During binary translation, the original binary code will be split into multiple TBs, and each TB is a continuous sequence of machine instructions, which can be translated into code that can be executed on the target platform after translation. TB_LINK is responsible for recording the jump, execution order and other association information between these TBs. After a TB finishes execution, through the information recorded in the TB_LINK of this TB, it can be known which TB should be jumped to next to continue execution, so as to ensure the continuity and correctness of the program.

[0080] The TB_LINK parameter can include a jump exit, which is used to indicate the address of the next TB to be jumped to. In the embodiment of the present invention, by modifying the TB_LINK parameter of the currently executing code block, such as setting the jump exit to a null value, the link between the currently executing code block and the next code block can be disconnected.

[0081] In an embodiment of the present invention, when a pending interruption to be processed is detected, the state parameters of the currently executing code block are obtained. If it is determined that the currently executing code block does not meet the first response condition, the link between the currently executing code block and the next code block is disconnected, and a second exit is set at the end position of the currently executing code block, and the jump target address is set to the entry address of the interrupt handler. Thus, when the dynamic binary translator executes to the second exit, it can exit the currently executing code block through the second exit, jump to the entry address of the interrupt handler, and enter the interrupt handler.

[0082] It should be noted that, whether exiting the currently executing code block through the first exit or the second exit, context saving is required before entering the interrupt handler, such as saving the register state and relevant information of the currently executing code block, such as recording the start address and execution progress of the currently executing code block, so as to determine from which position to continue execution when resuming execution. After the interrupt handling is completed, the context needs to be restored to continue executing the guest program.

[0083] Furthermore, for the case of exiting through the first exit, it belongs to the situation where the currently executing code block exits prematurely without being executed to completion. Therefore, after the interrupt handling is completed and the context is restored, the remaining unexecuted instructions in the currently executing code block are continued to be executed, and after all the instructions in the currently executing code block are executed, it jumps to the next code block to continue execution. For the case of exiting through the second exit, it belongs to the situation where the currently executing code block exits after being executed to completion. Therefore, after the interrupt handling is completed and the context is restored, it directly jumps to the next code block to continue execution.

[0084] The embodiment of the present invention does not limit the specific manner of detecting whether there is a pending interruption triggered by the virtual device thread.

[0085] Method 1: An interrupt detection thread also runs in the binary translation system. The steps of detecting whether there is a pending interruption may include:

[0086] The interrupt detection thread queries whether the global interrupt flag bit in the shared memory is set according to a preset frequency. If it is queried that the global interrupt flag bit is set, it is determined that a pending interruption is detected; the global interrupt flag bit is set by the virtual device thread when triggering the interrupt.

[0087] In the related art, an interrupt detection code is set at the head of each translation block (TB), which increases the additional processing overhead and affects the running performance of the translated code. To solve this problem, an embodiment of the present invention proposes a method in which an interrupt detection thread (qINT thread) and a virtual processor thread (vCPU thread) execute in parallel. The work of interrupt detection is separated from the TB code, so that the interrupt detection operation no longer depends on the vCPU thread, avoiding interference with the simulation performance of the vCPU thread. The two threads run independently. While not affecting the normal translation and execution operation of the vCPU thread, the qINT thread completes the interrupt detection work.

[0088] In a system-level dynamic binary translation (DBT) environment, the sending and response of interrupts are simulated by software. Specifically, a vDEV thread (responsible for device simulation) and a vCPU thread (responsible for processor simulation) can cooperate to complete the sending and response of interrupts through a global interrupt flag.

[0089] When the state of a simulated peripheral device (such as a disk, network card, timer, etc.) changes, or when the simulated device requires the intervention of the processor (for example, when the processor needs to read data or handle an exception), the vDEV thread may trigger an interrupt. Specifically, the vDEV thread notifies the vCPU thread that there is an interrupt to be processed by setting the global interrupt flag (such as a boolean variable or a register). The vDEV thread can also write the relevant information of the interrupt (such as the interrupt type, interrupt number, etc.) into the shared memory for the vCPU thread to read.

[0090] In an embodiment of the present invention, the qINT thread that runs in parallel with the vCPU thread periodically queries the global interrupt flag, instead of relying on the vCPU thread, to improve the execution efficiency of the vCPU thread.

[0091] In the first method, when the vDEV thread triggers an interrupt, it only needs to set the global interrupt flag and record the relevant information of the interrupt (such as the interrupt type, interrupt number, etc.). The qINT thread queries whether the global interrupt flag in the shared memory is set according to a preset frequency to detect whether there is an interrupt to be processed; if the qINT thread detects that the global interrupt flag is set, it determines that an interrupt to be processed is detected, and can set the value of the first register R1 to a first value (such as setting the value of R1 to 1) to notify the vCPU thread that there is an interrupt to be processed.

[0092] Further, the preset frequency (denoted as f1 for example) can be comprehensively determined based on the frequency at which the processor in the real machine to be simulated (such as the host machine) queries the interrupt request flag, the running duration of the translated binary program in the target platform, and the running duration of the binary program in the source platform in the source platform, so as to ensure that the vCPU thread will not exit the state parameter due to frequent interrupts, and the interrupt will not be undetected for a long time, resulting in untimely processing.

[0093] Exemplarily, the preset frequency f1 can be calculated by the following formula:

[0094] (1)

[0095] Wherein, f1 represents the preset frequency, and f2 represents the frequency at which the processor in the host machine queries the interrupt request flag. The difference between f1 and f2 is that f2 is the frequency at which the real host hardware performs interrupt detection, while f1 is the frequency of software-simulated interrupt detection. t1 represents the running duration of the translated binary program in the target platform, and t2 represents the running duration of the binary program in the source platform in the source platform.

[0096] It should be noted that in specific implementation, the preset frequency f1 can be a preset fixed frequency, such as once per second or once every 2 seconds, etc. Or, the preset frequency f1 can be adaptively changed according to different scenarios, such as calculated by the above formula (1), so that the interrupt detection frequency in the simulation environment can conform to the actual real situation as much as possible.

[0097] In the embodiment of the present invention, the interrupt detection thread (qINT thread) and the virtual processor thread (vCPU thread) run in parallel in the binary translation system. The qINT thread and the vCPU thread can communicate through shared memory and registers. Refer to Figure 3 , which shows the communication schematic diagram of the qINT thread and the vCPU thread in the embodiment of the present invention. Figure 3 Taking the way of detecting interrupts as Way 1 as an example, when the qINT thread detects an interrupt to be processed, the qINT thread sets the value of the first register to the first numerical value to notify the vCPU thread of the interrupt to be processed.

[0098] Such as Figure 3As shown, the qINT thread queries whether the global interrupt flag bit in the shared memory is set at a preset frequency. The global interrupt flag bit is set by the virtual device thread when an interrupt is triggered. When the qINT thread detects that the global interrupt flag bit is set, it determines that an interrupt signal has arrived, that is, it detects an interrupt to be processed. Once it detects that the global interrupt flag bit is set, the qINT thread can perform the following operation to notify the vCPU thread: set the value of the first register R1 to 1. The vCPU thread can determine whether there is an interrupt to be processed by checking the value of R1 during its execution.

[0099] In addition, the qINT thread can read the status parameters of the current TB in the vCPU thread from the shared memory, including variable a (the number of instructions already executed by the current TB), variable b (whether there is a first response flag bit in the current TB), and variable c (the instruction position for judging the first response flag bit). The qINT thread can determine whether the current TB meets the first response condition based on the values of variables a, b, and c obtained.

[0100] If it is determined that the current TB meets the first response condition, the qINT thread does not modify the code block link related variables (such as the TB_LINK parameter) of the current TB block in the vCPU thread. During the operation of the vCPU thread, when it executes to the code at the first exit, it will check the value of the first register R1. If R1 = 1, while ensuring the integrity of the translated code boundary, the vCPU thread will exit the status parameters of the current TB in advance and perform interrupt response and processing.

[0101] If it is determined that the current TB does not meet the first response condition, the qINT thread actively modifies the code block link related variables (such as the TB_LINK parameter) of the current TB block in the vCPU thread. During the operation of the vCPU thread, it exits the status parameters of the current TB by eliminating the code block link (through the second exit) and performs interrupt response and processing.

[0102] In the embodiment of the present invention, through the communication method between the qINT thread and the vCPU thread, and the processing of interrupt responses under different conditions, the system can effectively and timely process interrupts when they occur, ensuring that after receiving an interrupt signal, the vCPU thread can correctly respond to the interrupt according to different situations, complete the interrupt processing flow, and ensure the balance between the interrupt response speed and the code execution performance.

[0103] Method 2. The steps for detecting whether there is an interrupt to be processed may include:

[0104] When the virtual device thread triggers an interruption, it sends an interruption signal to the virtual processor thread through the signal mechanism of the host operating system; the host operating system intercepts the interruption signal and passes it to the virtual processor thread; when the virtual processor thread receives the interruption signal, it determines that an interruption to be processed is detected.

[0105] In Method 2, the vDEV thread can actively notify the vCPU thread through the signal mechanism, informing it that there is an interruption to be processed. And the relevant information of the interruption (such as interruption type, interruption number, etc.) is passed to the vCPU thread through the signal processing function.

[0106] In the embodiment of the present invention, Method 1 is an active interruption detection mechanism, and Method 2 is a passive interruption detection mechanism.

[0107] Method 2 uses the signal mechanism of the host operating system (such as Linux / Unix) to implement the transmission and processing of interruptions. When the vDEV thread detects a change in the device state or needs to trigger an interruption, it sends an interruption signal to the vCPU thread through the signal mechanism of the operating system. After the vDEV thread sends this interruption signal, the host operating system will intercept this interruption signal and pass it to the vCPU thread. After receiving this interruption signal, the vCPU thread executes the pre-registered signal processing function. In the signal processing function, the vCPU thread reads the global interruption flag bit and the relevant shared data structure, obtains the relevant information of the interruption, and calls the corresponding interruption processing logic.

[0108] In specific implementation, an active interruption detection mechanism (Method 1) in which the qINT thread runs in parallel with the vCPU thread can be adopted, or a passive interruption detection mechanism based on signals (Method 2) can be adopted. The embodiments of the present invention do not make any restrictions in the comparison.

[0109] In Method 2, it is not necessary for the qINT thread to actively query the global interruption flag bit. Instead, the host operating system (host operating system) intercepts the interruption signal sent by the vDEV. The host operating system passes the relevant information of the interruption to the vCPU thread by calling the signal processing function, so that the vCPU thread can perform corresponding processing subsequently.

[0110] In the solution of Method 2, the qINT thread can still communicate with the vCPU thread by modifying the register. However, in the solution of Method 2, the operation of modifying the first register R1 is completed in the signal processing function. According to the state parameter of the currently executed code block and the value of the first register R1, it is determined how to respond to the interruption, and this part is consistent with the solution of Method 1.

[0111] In the solution of Method 2, although the interrupt detection is passive, the frequency of the interrupt interfering with the DBT operation can still be achieved by controlling the frequency of sending inter-core interrupts (causing the translator to actively fall into it), so as to balance the performance of the translated code running and the interrupt response speed.

[0112] In an alternative embodiment of the present invention, the method may further include:

[0113] After the interrupt processing is completed, set the value of the first register to a second value.

[0114] In the embodiment of the present invention, the first register R1 can be used to transfer interrupt signals between the interrupt detection thread (qINT thread) and the virtual processor thread (vCPU thread), coordinate the interrupt response operations of the vCPU thread, and ensure that the system can process interrupts in a timely and correct manner.

[0115] The first register R1 serves as a flag for the interrupt signal. When an interrupt to be processed is detected, it is set to a first value (such as set to 1) to notify the vCPU thread that there is an interrupt to be processed. When the vCPU thread completes the interrupt processing flow, if R1 is not set to the second value (such as set to 0 or other values), the vCPU thread may detect that the value of R1 is 1 again, thus mistakenly thinking that there is a new interrupt coming, resulting in repeated processing of the same interrupt. Therefore, after the interrupt processing is completed, set the value of the first register to the second value to ensure the correct processing of the interrupt. Further, after the interrupt processing is completed, the global interrupt flag bit should also be cleared.

[0116] In a specific implementation, when an interrupt to be processed is detected, obtain the status parameters of the currently executing code block (such as the values of variables a, b, and c), and determine whether the currently executing code block meets the first response condition based on the status parameters. Based on whether the currently executing code block meets the first response condition, when the status parameters are of the currently executing code block, the interrupt response process of the vCPU thread can be divided into the following three situations (taking Method 1 as an example):

[0117] Situation 1: The variable b of the currently executing code block is 0, that is, there is no first response flag bit in the currently executing code block, and the total number of instructions included in the currently executing code block does not exceed M. Situation 1 belongs to the situation where the currently executing code block does not meet the first response condition, and it is necessary to exit the currently executing code block through the second exit and enter the interrupt handler.

[0118] Refer to Figure 4 , which shows a schematic diagram of the interrupt processing flow in Situation 1. As Figure 4As shown, the currently executing code block is TB2, the previous executed code block is TB1, and the next code block to be executed is TB3. In the system-level DBT environment, TB2 starts to execute with its variable b = 0, indicating that there is no first response flag bit in TB2. During the execution, if the qINT thread detects an interrupt to be processed, it sets the value of the first register R1 to 1 and obtains the status parameters of TB2 (such as the values of variables a, b, and c). At this time, the variable b = 0, indicating that there is no first response flag bit in TB2, and the total number of instructions contained in TB2 does not exceed the preset number M. Therefore, the vCPU thread does not need to exit TB2 in advance and can set the second exit by disconnecting the link between TB2 and the next code block (TB3) (corresponding to Figure 4 the interrupt response 1 in). After all the instructions of TB2 are executed in sequence, the vCPU thread exits the status parameters of TB2 through the second exit and prepares for context switching to handle the interrupt. The vCPU thread saves the information related to the current status parameters, such as the values of the registers, the memory mapping relationship, the execution progress of TB2, and the TB_LINK parameter, etc., to complete the context save. Then, the system performs context switching and transfers the execution right to the interrupt handler for corresponding processing. After the interrupt processing is completed, the value of the first register R1 is set to 0, and the system starts to restore the context. According to the saved information, the values of the registers, the memory mapping relationship, the TB_LINK parameter, etc. are restored to the state before the interrupt occurred. After the context restoration is completed, the vCPU thread can determine the next TB to be executed as TB3 by looking up the TB_LINK parameter. Finally, the vCPU thread jumps to TB3 to continue executing the subsequent program code to ensure the continuity and correctness of the program.

[0119] Case 2: The variable b of the currently executing code block is 1 and the variable a < variable c, that is, there is a first response flag bit in the currently executing code block, the total number of instructions contained in the currently executing code block exceeds M, and the address of the currently executing instruction in the currently executing code block is less than the address of the first response flag bit, that is, the first exit position has not been reached yet. Case 2 belongs to the situation where the currently executing code block meets the first response condition, and the currently executing code block can be exited in advance through the first exit and enter the interrupt handler.

[0120] Referring to Figure 5 , a schematic diagram of the interrupt processing flow of Case 2 is shown. As Figure 5As shown, the currently executing code block is TB2, the previous executed code block is TB1, and the next code block to be executed is TB3. In the system-level DBT environment, TB2 starts to execute. During the execution, if the qINT thread detects an interrupt to be processed, it sets the value of the first register R1 to 1 and obtains the status parameters of TB2 (such as the values of variables a, b, and c). At this time, variable b = 1, indicating that there is a first response flag bit in TB2. The total number of instructions included in TB2 exceeds the preset quantity M, and at the same time, variable a (the number of instructions already executed in TB2) is less than variable c (the instruction position for judging the first response flag bit). TB2 meets the first response condition and can exit the execution process of TB2 through the first exit. When executing to the code at the first exit (corresponding to Figure 5 the interrupt response 2 in it), since R1 = 1, it directly exits the execution process of TB2 and enters the interrupt handler. Since the first exit is executed to exit after the execution of the Mth instruction, it can ensure the boundary integrity of the translated code. Before exiting, the context needs to be saved, and after the interrupt handling is completed, the context needs to be restored. This process is similar to that in Case 1 and will not be elaborated here. Finally, the vCPU thread continues to execute the remaining instructions of TB2 and then jumps to TB3 to continue executing the subsequent program code.

[0121] Case 3: The variable b = 1 and variable a ≥ variable c in the currently executing code block, that is, there is a first response flag bit in the currently executing code block, the total number of instructions included in the currently executing code block exceeds M, and the address of the currently executing instruction in the currently executing code block is greater than or equal to the address of the first response flag bit, that is, the position of the currently executing instruction has exceeded the position of the first exit.

[0122] Case 3 belongs to the situation where the currently executing code block does not meet the first response condition, and it is necessary to exit the currently executing code block through the second exit and enter the interrupt handler. Refer to Figure 6 , which shows the schematic diagram of the interrupt handling process in Case 3. As Figure 6As shown, the currently executing code block is TB2, the previous executed code block is TB1, and the next code block to be executed is TB3. In the system-level DBT environment, TB2 starts to execute. During the execution, if the qINT thread detects an interrupt to be processed, it sets the value of the first register R1 to 1 and obtains the status parameters of TB2 (such as the values of variables a, b, and c). At this time, variable b = 1, indicating that there is a first response flag bit in TB2. The total number of instructions contained in TB2 exceeds the preset quantity M, and at the same time, variable a ≥ variable c. TB2 does not meet the first response condition and can exit the execution process of TB2 through the second exit. Specifically, the link between TB2 and the next code block (TB3) is disconnected to set the second exit. After all the instructions of TB2 are executed in sequence, the vCPU thread exits the execution state of TB2 through the second exit and prepares for context switching to handle the interrupt. Subsequently, context saving is performed, and context restoration is required after the interrupt handling is completed. This process is similar to that in Scenario 1 and will not be elaborated here. Finally, the vCPU thread jumps to TB3 to continue executing the subsequent program code to ensure the continuity and correctness of the program.

[0123] In the embodiments of the present invention, when an interrupt to be processed is detected, the status parameters of the currently executing code block (such as the values of variables a, b, and c) are obtained, and the interrupt response mode and execution process of the vCPU thread are determined according to the status parameters of the currently executing code block.

[0124] The role of variable b: Variable b is an identifier indicating whether there is a first response flag bit in the basic block. When b = 1, it indicates that the current TB has the condition to respond to the interrupt in advance; otherwise, the vCPU thread needs to wait until the current TB finishes execution to respond to the interrupt. For example, in Scenario 1, since b = 0, the vCPU thread exits after the current TB finishes execution; while in Scenarios 2 and 3, since b = 1, there is a possibility that the vCPU thread responds to the interrupt in advance and further judgment is required.

[0125] The role of variable a: Variable a is the address of the currently executing instruction in the currently executing code block, which can be used to record the number of instructions that have been executed in the current TB and is used to accurately judge the timing of interrupt response. Variable a cooperates with variables b and c to determine the interrupt response mode of the vCPU thread. For example, in Scenario 2, only when variable b = 1 and variable a < variable c, the vCPU thread adopts the way of exiting in advance; if variable a ≥ variable c, even if variable b = 1, the processing process is the same as that in Scenario 1 and exits after the current TB finishes execution, ensuring the balance between the interrupt response speed and the code execution progress.

[0126] Function of variable c: Variable c represents the instruction position for judging the first response flag bit, providing a specific code position reference for interrupt response. Variable c, in cooperation with variables a and b, determines when to trigger an interrupt response. For example, when variable b = 1 and variable a < variable c, it means that the current TB has executed before the instruction for judging the first response flag bit, that is, before the first exit. If an interrupt is detected (such as the value of the first register R1 being 1), the vCPU thread can exit in advance when reaching the first exit to respond to the interrupt; when variable b = 1 and variable a ≥ variable c, it indicates that the optimal early position for interrupt response has passed. At this time, it is necessary to exit through the second exit to accurately locate the interrupt response during code execution and ensure the balance between the interrupt response speed and the code execution progress.

[0127] In the embodiment of the present invention, by using the state parameters (variables a, b, and c) of the currently executed code block to judge the first response condition and determine the interrupt response method and execution flow of the vCPU thread, it can ensure that the interrupt handling can be carried out accurately and efficiently, maintaining the stable operation of the system.

[0128] In summary, in the translation process of the dynamic binary translator in the embodiment of the present invention, if an interrupt to be processed is detected, the state parameters of the currently executed code block are obtained, and it is judged whether the currently executed code block meets the first response condition according to the state parameters; according to whether the currently executed code block meets the first response condition, it is determined whether to respond to the interrupt through the first exit or the second exit. The first response condition is used to judge whether the currently executed code block meets the condition for exiting the currently executed code block in advance. The first exit is used to exit the currently executed code block in advance to respond to the interrupt. The second exit is used to exit the currently executed code block when the currently executed code block ends to respond to the interrupt. In the embodiment of the present invention, according to the state parameters of the currently executed code block, a better interrupt response timing (the first exit or the second exit) is selected, so that the interrupt can be timely responded at a better time point in different situations; it can avoid overly frequent context switching when there are a large number of frequent interrupts; and it can achieve a better balance between the performance of the translated code operation and the interrupt response speed.

[0129] In addition, the embodiment of the present invention realizes interrupt detection in a new way, which can separate the interrupt detection operation from the TB code. The interrupt detection operation no longer depends on the vCPU thread, so that the interrupt detection no longer affects the running performance of the translated code, and can further improve the performance of the vCPU thread.

[0130] Furthermore, the embodiment of the present invention does not limit the length of the basic block and does not affect the optimization effect of the translator on the code.

[0131] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequences, because according to the embodiments of the present invention, certain steps can be carried out in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0132] The method in the above embodiments can be implemented as a binary translation system, including: a virtual device module, an interrupt detection module, and a virtual processor module, which are respectively used to control a virtual device thread, an interrupt detection thread, and a virtual processor thread; wherein, the interrupt detection thread is used to detect an interrupt triggered by the virtual device thread; the virtual processor thread is used to: in the translation stage, after translating a preset number M of instructions of a code block, insert interrupt response code; in the execution stage, in response to an interrupt to be processed, determine whether the code block has been executed to the position of the interrupt response code; in the case where it has not been executed to the position of the interrupt response code, after executing the Mth instruction, exit the execution stage via the interrupt response code and switch the context to perform interrupt processing; otherwise, exit the execution stage after executing the entire code block.

[0133] The interrupt detection thread can query whether the global interrupt flag bit in the shared memory is set according to a preset frequency. If it is queried that the global interrupt flag bit is set, it is determined that an interrupt to be processed is detected; the global interrupt flag bit is set by the virtual device thread when triggering an interrupt. The interrupt detection thread can notify the virtual processor thread of the interrupt to be processed by setting the value of the first register R1.

[0134] In combination Figure 4 with the embodiment described in 6, in the case where the virtual processor exits the execution stage after executing the entire code block, the interrupt detection thread disconnects the link between the current code block and the next code block in the virtual processor thread.

[0135] In combination Figure 5 with the embodiment described in, after the virtual processor thread processes the interrupt, it switches back to the execution stage and executes the remaining unexecuted code i + 1...m in the code block.

[0136] On the other hand, the above embodiments can also be implemented as a system-level binary translation device, including a context switching unit that enables the device to switch between a translation state for translating client code and an execution state for executing the translated host code; in the translation state, after translating a preset number M of host instructions for a code block, interrupt response code is inserted; in the execution state, if an interrupt to be processed is found before executing the interrupt response code, the binary translation device enters context switching at the interrupt response code, exits the execution state, enters the translation state, and searches for and translates the interrupt handler in the translation state; after executing the interrupt handler, it switches back to the execution state and executes the remaining unexecuted code in the code block.

[0137] Referring to Figure 7 , a structural block diagram of an embodiment of an interrupt handling device according to the present invention is shown, which is applied to a binary translation system. In the binary translation system, a virtual device thread and a virtual processor thread are running. The interrupt handling device may include:

[0138] An interrupt detection module 801, configured to notify a virtual processor thread of a pending interrupt triggered by a virtual device thread by setting a value of a first register to a first numerical value;

[0139] A condition judgment module 802, configured to obtain a status parameter of a currently executed code block and judge whether the currently executed code block meets a first response condition according to the status parameter; the status parameter includes: the address of the currently executed instruction in the currently executed code block, whether a first response flag bit exists in the currently executed code block, and the address of the first response flag bit; wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executed code block exceeds a preset number;

[0140] A first response module 803, configured to, if the currently executed code block meets the first response condition, exit the currently executed code block through a first exit and enter an interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executed code block;

[0141] A second response module 804, configured to, if the currently executed code block does not meet the first response condition, exit the currently executed code block through a second exit and enter an interrupt handler; the second exit is located at the end position of the currently executed code block.

[0142] Optionally, the device further includes:

[0143] The first exit setting module is used to set the first response flag bit and the code of the first exit after the Mth instruction and before the (M + 1)th instruction when it is recognized that the total number of instructions included in the current translation code block exceeds M (M is a preset quantity) during the process of translating the binary program of the source platform; the code of the first exit is used to directly exit the current execution code block and jump to the entry address of the interrupt handler when the value of the first register is detected as the first numerical value in the current execution code block.

[0144] Optionally, the condition judgment module is specifically used for:

[0145] If there is a first response flag bit in the current execution code block and the address of the current execution instruction in the current execution code block is less than the address of the first response flag bit, it is determined that the current execution code block meets the first response condition.

[0146] Optionally, the device further includes:

[0147] The second exit setting module is used to disconnect the link between the current execution code block and the next code block if the current execution code block does not meet the first response condition, and set the code of the second exit at the end position of the current execution code block, and the code of the second exit indicates that the jump target address is the entry address of the interrupt handler.

[0148] Optionally, an interrupt detection thread also runs in the binary translation system, and the interrupt detection module is specifically used for:

[0149] Through the interrupt detection thread, according to a preset frequency, query whether the global interrupt flag bit in the shared memory is set. If it is queried that the global interrupt flag bit is set, it is determined that an interrupt to be processed is detected; the global interrupt flag bit is set by the virtual device thread when triggering an interrupt; set the value of the first register as the first numerical value through the interrupt detection thread.

[0150] Optionally, the preset frequency is calculated based on the frequency at which the processor in the host queries the interrupt request flag, the running duration of the translated binary program on the target platform, and the running duration of the binary program of the source platform on the source platform.

[0151] Optionally, the interrupt detection module is specifically used for:

[0152] When the virtual device thread triggers an interruption, an interruption signal is sent to the virtual processor thread through the signal mechanism of the host operating system; the host operating system intercepts the interruption signal and passes it to the virtual processor thread; when the virtual processor thread receives the interruption signal, it determines that an interruption to be processed is detected; after the virtual processor thread receives the interruption signal, it executes a pre-registered signal processing function, and in the signal processing function, sets the value of a first register to a first numerical value.

[0153] Optionally, the device further includes:

[0154] A register restoration module, configured to, after the interruption processing is completed, set the value of the first register to a second numerical value.

[0155] In the interruption processing device according to an embodiment of the present invention, during the translation process of a dynamic binary translator, if an interruption to be processed is detected, state parameters of a currently executing code block are obtained, and it is determined whether the currently executing code block meets a first response condition according to the state parameters; according to whether the currently executing code block meets the first response condition, it is decided to respond to the interruption through a first exit or a second exit. The first response condition is used to determine whether the currently executing code block meets the condition for exiting the currently executing code block in advance. The first exit is used to exit the currently executing code block in advance and respond to the interruption. The second exit is used to exit the currently executing code block when the currently executing code block ends, and respond to the interruption. According to the state parameters of the currently executing code block, the interruption processing device according to an embodiment of the present invention selects a better interruption response timing (the first exit or the second exit), so that the interruption can be timely responded at a better time point in different situations; it is possible to avoid overly frequent context switching when there are a large number of and frequent interruptions; and it is possible to achieve a better balance between the performance of the translated code during operation and the interruption response speed.

[0156] In addition, the interruption processing device according to an embodiment of the present invention realizes the simulation work of interruption detection in a new way, can separate the interruption detection operation from the TB code, and the interruption detection operation no longer depends on the vCPU thread, so that the interruption detection no longer affects the running performance of the translated code, and can further improve the performance of the vCPU thread.

[0157] Furthermore, the embodiment of the present invention does not limit the length of the basic block and does not affect the optimization effect of the translator on the code.

[0158] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference may be made to the partial description of the method embodiment.

[0159] Referring to Figure 8 , is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. AsFigure 8 As shown in Figure 8 , the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the interruption processing method in the foregoing embodiments.

[0160] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a program or a processor of a terminal, the terminal can execute the steps of the interruption processing method in the foregoing embodiments.

[0161] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0162] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0163] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0164] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0165] These computer program instructions may also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide for implementing the steps of the function specified in one process or multiple processes and / or blocks Figure 1 one process or multiple processes and / or blocks Figure 1 steps of the function specified in one block or multiple blocks.

[0166] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0167] Specific examples are used in this article to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An interrupt handling method, characterized in that, Applied to a binary translation system in which a virtual device thread and a virtual processor thread are running, the method includes: Notifying a virtual processor thread of a pending interrupt triggered by a virtual device thread by setting the value of a first register to a first numerical value; Obtaining status parameters of a currently executing code block, and determining whether the currently executing code block meets a first response condition according to the status parameters; the status parameters include: the address of the currently executing instruction in the currently executing code block, whether there is a first response flag bit in the currently executing code block, and the address of the first response flag bit; wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executing code block exceeds a preset number; If the currently executing code block meets the first response condition, the virtual processor thread exits the currently executing code block through a first exit and enters an interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executing code block; If the currently executing code block does not meet the first response condition, the virtual processor thread exits the currently executing code block through a second exit and enters an interrupt handler; the second exit is located at the end position of the currently executing code block.

2. The method according to claim 1, wherein The method further includes: During the process of translating a binary program of a client platform, if it is recognized that the total number of instructions included in the currently translated code block exceeds M (M is the preset number), the virtual processor thread sets the code of the first response flag bit and the first exit after the Mth instruction and before the (M + 1)th instruction; the code of the first exit is used to directly exit the currently executing code block and jump to the entry address of the interrupt handler when the virtual processor thread reads that the value of the first register is the first numerical value.

3. The method according to claim 1, wherein The determining whether the currently executing code block meets the first response condition according to the status parameters includes: If there is a first response flag bit in the currently executing code block and the address of the currently executing instruction in the currently executing code block is less than the address of the first response flag bit, it is determined that the currently executing code block meets the first response condition.

4. The method according to claim 1, wherein The method further includes: If the currently executing code block does not meet the first response condition, disconnect the link between the currently executing code block and the next code block, and set the code of the second exit at the end position of the currently executing code block, and the code of the second exit indicates that the jump target address is the entry address of the interrupt handler.

5. The method according to claim 1, characterized in that, An interrupt detection thread is also running in the binary translation system. The step of detecting a pending interrupt triggered by a virtual device thread includes: The interrupt detection thread queries whether a global interrupt flag bit in a shared memory is set according to a preset frequency. If it is queried that the global interrupt flag bit is set, it is determined that a pending interrupt is detected; the global interrupt flag bit is set by the virtual device thread when triggering the interrupt; The setting the value of the first register to the first numerical value includes: The interrupt detection thread sets the value of the first register to the first numerical value.

6. The method according to claim 5, wherein The preset frequency is calculated based on the frequency at which the processor in the host queries the interrupt request flag, the running duration of the translated binary program on the target platform, and the running duration of the binary program of the source platform on the source platform.

7. The method according to claim 1, characterized in that, The steps of detecting a pending interrupt triggered by a virtual device thread include: When the virtual device thread triggers an interrupt, it sends an interrupt signal to the virtual processor thread through the signal mechanism of the host operating system; The host operating system intercepts the interrupt signal and passes it to the virtual processor thread; When the virtual processor thread receives the interrupt signal, it determines that a pending interrupt has been detected; setting the value of the first register to a first value includes: After receiving the interrupt signal, the virtual processor thread executes a pre-registered signal processing function, and in the signal processing function, sets the value of the first register to a first value.

8. The method according to claim 1, wherein The method further includes: After the interrupt processing is completed, set the value of the first register to a second value.

9. An interrupt processing method applied to a binary translation system, in which a virtual device thread, an interrupt detection thread, and a virtual processor thread are running. The method includes: The interrupt detection thread detects an interrupt triggered by the virtual device thread; In the translation stage, after the virtual processor thread translates a preset number M of instructions of a code block, interrupt response code is inserted; In the execution stage, in response to a pending interrupt, the virtual processor thread determines whether the code block has been executed to the position of the interrupt response code; In the case where the interrupt response code position has not been executed to, the virtual processor thread will, after executing the Mth instruction, exit the execution stage via the interrupt response code and switch the context to perform interrupt processing; Otherwise, the virtual processor thread exits the execution stage after executing the entire code block.

10. The method according to claim 9, wherein, The interrupt detection thread queries whether the global interrupt flag bit in the shared memory is set according to a preset frequency. If it is queried that the global interrupt flag bit is set, it is determined that a pending interrupt has been detected; the global interrupt flag bit is set by the virtual device thread when triggering an interrupt.

11. The method according to claim 9, wherein, The interrupt detection thread notifies the virtual processor thread of a pending interrupt by setting the value of the first register.

12. The method according to claim 9, wherein In the case where the virtual processor exits the execution stage after executing the entire code block, the interrupt detection thread disconnects the link between the current code block and the next code block in the virtual processor thread.

13. The method according to claim 9, wherein, After the virtual processor thread processes the interrupt, it switches back to the execution stage and executes the remaining unexecuted code in the code block.

14. A binary translation system, comprising: A virtual device module, an interrupt detection module, and a virtual processor module are respectively used to control the virtual device thread, the interrupt detection thread, and the virtual processor thread; The interrupt detection thread is used to detect an interrupt triggered by the virtual device thread; The virtual processor thread is used for: In the translation stage, after translating a preset number M of instructions of a code block, insert interrupt response code; In the execution stage, in response to a pending interrupt, determine whether the code block has been executed to the position of the interrupt response code; In the case where the interrupt response code position is not reached, after executing the Mth instruction, the execution phase will be exited via the interrupt response code, and the context will be switched to perform interrupt handling; Otherwise, after executing the entire code block, the execution phase is exited.

15. A system-level binary translation device includes a context switching unit that enables the device to switch between a translation state for translating client code and an execution state for executing the translated host code; In the translation state, after translating a preset number M of host instructions for a code block, an interrupt response code is inserted; In the execution state, if an interrupt to be processed is found before reaching the interrupt response code, the binary translation device enters context switching at the interrupt response code, exits the execution state, enters the translation state, and searches for and translates the interrupt handler in the translation state; After executing the interrupt handler, it switches back to the execution state and executes the remaining unexecuted code in the code block.

16. An interruption processing device, characterized in that, Applied to a binary translation system in which a virtual device thread and a virtual processor thread are running, the device includes: An interrupt detection module for notifying the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of a first register to a first value; A condition judgment module for obtaining a status parameter of the currently executing code block and judging whether the currently executing code block meets a first response condition according to the status parameter; the status parameter includes: the address of the currently executing instruction in the currently executing code block, whether there is a first response flag bit in the currently executing code block, and the address of the first response flag bit; wherein, the first response flag bit is used to indicate whether the total number of instructions included in the currently executing code block exceeds a preset number; A first response module for, if the currently executing code block meets the first response condition, exiting the currently executing code block through a first exit and entering the interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executing code block; A second response module for, if the currently executing code block does not meet the first response condition, exiting the currently executing code block through a second exit and entering the interrupt handler; the second exit is located at the end position of the currently executing code block.

17. An electronic device, characterized in that, Including: A processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the interrupt handling method according to any one of claims 1 to 13.

18. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the interrupt handling method according to any one of claims 1 to 13 are implemented.

19. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, the steps of the interrupt handling method according to any one of claims 1 to 13 are implemented.

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