Bar code decoding algorithm operation device and method based on PCIE interface

Abstract

The invention discloses a bar code decoding algorithm operation device and method based on a PCIE (Peripheral Component Interface Express) interface, and the device comprises a LINUX system board and an FPGA (Field Programmable Gate Array) system board which are connected through a PCIE bus, and the LINUX system board comprises a core processing CPU (Central Processing Unit), a nonvolatile memory FLASH / MMC, a memory module DDR (Double Data Rate) and a PCIE main controller interface; the FPGA system board comprises an FPGA interface controller, an AXI to AHB bridge, an AXI to APB bridge and a core decoding unit; the core processing CPU of the LINUX system board is connected with the FPGA interface controller of the FPGA system board through a PCIE (Peripheral Component Interface Express) main controller interface; the core processing CPU is respectively connected with the nonvolatile memory FLASH / MMC and the memory module DDR; and the FPGA interface controller of the FPGA system board is connected with the core decoding unit through the AXI-to-AHB bridge and the AXI-to-APB bridge. According to the method, the problem that the efficiency is low when a traditional chip decoding algorithm is used for large-batch image library verification is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of automatic identification, and in particular relates to a barcode decoding algorithm operation device and method based on a PCIE interface. Background Art

[0002] Barcode technology is the abbreviation of barcode auto-identification technology. Barcode technology is a symbol automatic recognition technology that was generated and developed on the basis of contemporary information technology. It integrates the functions of symbol encoding, data collection, automatic identification, input, and information storage, and can effectively solve the problem of collecting and automatically inputting a large amount of data in real work and life. Barcode technology has been widely used in the fields of retail, intelligent traceability, logistics, engineering warehousing management, hospital medicine, etc. At present, the most widely used barcodes are one-dimensional barcodes and two-dimensional barcodes.

[0003] One-dimensional barcode is a graphic symbol composed of a group of regularly arranged black and white stripes. The barcode information is transmitted by the different widths and positions of black and white. This group of graphic symbols is used to represent information such as numbers, characters and symbols. This barcode technology can only store information in one direction through the combination of black and white, so it is called "one-dimensional barcode".

[0004] Two-dimensional barcodes record data symbol information through black and white graphics distributed on a plane (horizontally and vertically) according to a certain pattern; in the compilation of the code, the concept of 0 and 1 bit streams that constitute the internal logic basis of the computer is cleverly used, and several geometric figures corresponding to binary are used to represent textual numerical information. Two-dimensional barcodes use error correction coding in the generation process, making them highly resistant to contamination. Two-dimensional barcodes can express information in both horizontal and vertical directions at the same time, so they can express a large amount of information in a very small area.

[0005] Barcode reading is a technology that converts barcode images into data information. It mainly consists of two parts: barcode image acquisition and decoding processing. Barcode image acquisition scans the barcode image through an optical image sensor and converts the optical signal into an electrical signal. Decoding processing is the process of translating the collected electrical signal into corresponding data information according to certain rules. Barcode reading equipment can be divided into laser reading equipment, linear CCD reading equipment, and area array CMOS / CCD reading equipment according to different reading principles.

[0006] Barcode decoding can be achieved through software on the CPU, or through dedicated logic circuits. Hardware circuits can make full use of their concurrent processing capabilities to increase the decoding speed. In order to improve the correctness, stability and reliability of the decoding algorithm, the algorithm must be fully verified in the early stage, and a large number of image libraries of different types and different code systems must be used to screen out the problems and deficiencies in the decoding algorithm.

[0007] The current verification method for hardware decoding algorithms is mainly through simulation using ModelSim software on a PC. However, the verification time required for software simulation is relatively long and it can usually only be used to locate problems in a single image. Summary of the invention

[0008] The present invention provides a barcode testing device and method based on PCIE interface, aiming to solve the problem of low efficiency when verifying a large number of image libraries of a traditional chip decoding algorithm, and improve the rapidity, convenience, reliability and debuggability of hardware algorithm verification.

[0009] The technical solution of the present invention is as follows:

[0010] On the one hand, the present invention provides a barcode decoding algorithm running device based on a PCIE interface, comprising: a LINUX system board and an FPGA system board connected via a PCIE bus, the LINUX system board comprising a core processing CPU, a non-volatile memory FLASH / MMC, a memory module DDR, and a PCIE main controller interface; the FPGA system board comprises an FPGA interface controller, an AXI to AHB bridge, an AXI to APB bridge, and a core decoding unit.

[0011] The core processing CPU of the LINUX system board is connected to the FPGA interface controller of the FPGA system board through the PCIE main controller interface; the core processing CPU is respectively connected to the non-volatile memory FLASH / MMC and the memory module DDR.

[0012] The FPGA interface controller of the FPGA system board is connected to the core decoding unit through the AXI to AHB bridge and the AXI to APB bridge.

[0013] Preferably, the FPGA interface controller includes an XDMA control unit and an AXI control unit connected via an AXI bus.

[0014] The XDMA control unit is used to exchange data with the LINUX system board through the PCIE host controller interface.

[0015] The AXI control unit is used to transmit and manage data between modules within the FPGA.

[0016] Preferably, the core decoding unit includes an image BMP storage unit, a 1D decoding logic unit, a QR decoding logic unit, a DM decoding logic unit, and a PDF417 decoding logic unit, and each decoding logic unit is correspondingly provided with a status register; the image BMP storage unit is connected to the 1D decoding logic unit, the QR decoding logic unit, the DM decoding logic unit, and the PDF417 decoding logic unit through a bus.

[0017] The AXI control unit reads and writes the status registers of the 1D decoding logic unit, the QR decoding logic unit, the DM decoding logic unit, and the PDF417 decoding logic unit through the AXI to APB bridge.

[0018] The AXI control unit implements the read and write operations of the image BMP storage unit through the AXI to AHB bridge.

[0019] Preferably, the LUNIX system board further comprises a network communication interface module for remotely controlling batch barcode testing and transmission of the barcode library; the network communication interface module is connected to the core processing CPU.

[0020] On the other hand, the present invention provides a method for running a barcode decoding algorithm based on a PCIE interface, comprising the following steps:

[0021] After the LINUX system board and the FPGA system board are powered on, the LINUX system board is connected to the FPGA system board through the PCIE host controller interface. After the connection is successful, the LINUX system board loads the corresponding PCIE driver.

[0022] The test program of the LINUX system board initializes each unit of the FPGA system board through the PCIE main controller interface.

[0023] After the initialization operation is completed, the LINUX system board starts to traverse the barcode library to be tested, and downloads the images in the barcode library to the image BMP storage unit of the core decoding unit in the FPGA system board through the PCIE main controller interface.

[0024] After the image is downloaded, the FPGA system board starts the 1D decoding logic unit, QR decoding logic unit, DM decoding logic unit, and PDF417 decoding logic unit of the core decoding unit to decode the 1D code, QR code, DM code, and PDF417 code in sequence.

[0025] After the barcode decoding is completed, the FPGA system board transmits the barcode decoding result to the test program of the LINUX system board through the PCIE interrupt and status register.

[0026] The test program counts the performance indicators of each decoding algorithm in the core decoding unit to form test data.

[0027] On the other hand, the present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the barcode decoding algorithm operation method based on the PCIE interface as described in any embodiment of the present invention is implemented.

[0028] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for operating a barcode decoding algorithm based on a PCIE interface as described in any embodiment of the present invention is implemented.

[0029] Compared with the prior art, the present invention has the following technical effects:

[0030] The present invention realizes high-speed data transmission and barcode decoding task processing between the LINUX system board and the FPGA system board through the collaborative work of efficient hardware interfaces. By loading the barcode library into the non-volatile memory and using the PCIE interface for image data transmission, the FPGA system board can quickly perform the decoding of various barcode types (such as 1D code, QR code, DM code, PDF417 code), and feed back the decoding results to the test program in real time through the PCIE interrupt and status register. The overall test efficiency of the optimization and evaluation of the barcode decoding algorithm is improved, and it has significant application value and technical advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is an overall architecture diagram of the barcode decoding algorithm running device based on the PCIE interface described in Example 1;

[0032] Figure 2 It is an overall architecture diagram of the barcode decoding algorithm operation device based on the PCIE interface described in Example 2;

[0033] Figure 3 It is an overall flow chart of the barcode decoding algorithm operation method based on PCIE interface described in the present invention. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in combination with specific embodiments of the present application and with reference to the accompanying drawings.

[0035] Embodiment 1

[0036] This embodiment provides a barcode decoding algorithm running device based on a PCIE interface, see Figure 1As shown, it includes: a LINUX system board and an FPGA system board connected through a PCIE bus, the LINUX system board includes a core processing CPU, a non-volatile memory FLASH / MMC, a memory module DDR, and a PCIE main controller interface; the FPGA system board includes an FPGA interface controller, an AXI to AHB bridge, an AXI to APB bridge, and a core decoding unit. The PCIE bus is a high-speed serial point-to-point dual-channel transmission technology with high performance, high bandwidth, low latency, and high reliability, and is suitable for use in occasions where high-speed and large-volume data transmission is required. FPGA (Field-Programmable Gate Array) is a field programmable gate array, and the FPGA can be programmed with algorithms through VHDL (hardware description language) to implement barcode decoding tasks and verify its performance. As a subsystem of the LINUX system board, the FPGA system board is uniformly controlled by the core processing CPU, and the main control LINUX system board can read and write FPGA internal module registers through the PCIE bus.

[0037] The core processing CPU of the LINUX system board is connected to the FPGA interface controller of the FPGA system board through the PCIE main controller interface; the core processing CPU is connected to the non-volatile memory FLASH / MMC and the memory module DDR respectively. The non-volatile memory FLASH / MMC is used to store the operating system, programs and test images, and the memory module DDR is used to cache the running data in the CPU. After the CPU is powered on, the operating system and test program stored in the FLASH / MMC will be loaded into the memory module DDR for operation. According to the instructions of the test program, the image data will be transmitted to the FPGA system board through the PCIE main controller interface for decoding operation.

[0038] The FPGA interface controller of the FPGA system board is connected to the core decoding unit through the AXI to AHB bridge and the AXI to APB bridge.

[0039] As a preferred implementation of this embodiment, the FPGA interface controller includes an XDMA control unit and an AXI control unit connected via an AXI bus.

[0040] The XDMA control unit is used to exchange data with the LINUX system board through the PCIE host controller interface.

[0041] The AXI control unit is used to transmit and manage data between modules within the FPGA to ensure that data can be correctly transferred between modules.

[0042] As a preferred implementation scheme of this embodiment, the core decoding unit includes an image BMP storage unit, a 1D decoding logic unit, a QR decoding logic unit, a DM decoding logic unit, and a PDF417 decoding logic unit, and each decoding logic unit is correspondingly provided with a status register; the image BMP storage unit is connected to the 1D decoding logic unit, the QR decoding logic unit, the DM decoding logic unit, and the PDF417 decoding logic unit through a 32-bit bus with independent addresses and data, and has a very large data exchange throughput.

[0043] The AXI control unit reads and writes the status registers of the 1D decoding logic unit, the QR decoding logic unit, the DM decoding logic unit, and the PDF417 decoding logic unit through the AXI to APB bridge.

[0044] The AXI control unit implements the read and write operations of the image BMP storage unit through the AXI to AHB bridge.

[0045] Embodiment 2

[0046] See also Figure 2 As shown, this embodiment provides a barcode decoding algorithm running device based on the PCIE interface, and the device is basically the same as the embodiment 1, except that: the LUNIX system board in the device of the embodiment 2 also includes a network communication interface module for remotely controlling batch barcode testing and transmission of the barcode library; the network communication interface module is connected to the core processing CPU.

[0047] Through the network communication interface module, you can log in to the LINUX system board through remote desktop or SSH and other tools to perform remote testing operations. At the same time, you can also send the remote barcode library to be tested directly to the decoding core unit of the FPGA system board through the network and PCIE main controller interface for barcode decoding testing to save storage space on the LINUX system board.

[0048] Embodiment 3

[0049] Accordingly, this embodiment provides a method for running a barcode decoding algorithm based on a PCIE interface, and the method is implemented based on the barcode decoding algorithm running device based on a PCIE interface described in any one of Embodiments 1-2, see Figure 3 As shown, the following steps are included:

[0050] The barcode library to be tested, the PCIE driver and the test program of the barcode decoding algorithm are stored in advance in the non-volatile memory FLASH / MMC file system of the LINUX system board.

[0051] After the LINUX system board and the FPGA system board are powered on, the LINUX system board is connected to the FPGA system board through the PCIE host controller interface.

[0052] After the connection is successful (which can be shown as the indicator light is on), the LINUX system board loads the corresponding PCIE driver.

[0053] The test program of the LINUX system board initializes each unit of the FPGA system board through the PCIE main controller interface.

[0054] After the initialization operation is completed, the LINUX system board starts to traverse the barcode library to be tested, and downloads the images in the barcode library to the image BMP storage unit of the core decoding unit in the FPGA system board through the PCIE main controller interface.

[0055] After the image download is completed, the FPGA system board starts the 1D decoding logic unit, QR decoding logic unit, DM decoding logic unit, and PDF417 decoding logic unit of the core decoding unit to decode the 1D code, QR code, DM code, and PDF417 code in turn, and transmits the barcode decoding results to the corresponding status register.

[0056] After the barcode decoding is completed, the FPGA system board transmits the barcode decoding result to the test program of the LINUX system board through the PCIE interrupt and status register.

[0057] The test program collects statistics on the performance indicators of each decoding algorithm in the core decoding unit, including decoding accuracy, decoding time, bit error rate, etc., to form test data, providing reliable data for locating hardware decoding algorithm bugs and improving algorithm performance.

[0058] Embodiment 4

[0059] This embodiment provides an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the barcode decoding algorithm operation method based on the PCIE interface as described in any embodiment of the present invention is implemented.

[0060] Embodiment 5

[0061] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the PCIE interface-based barcode decoding algorithm operation method as described in any embodiment of the present invention is implemented.

[0062] In the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0063] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0064] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0065] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory; hereinafter referred to as: ROM), random access memory (Random Access Memory; hereinafter referred to as: RAM), disk or optical disk, and other media that can store program codes.

[0066] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A barcode decoding algorithm running device based on PCIE interface, characterized in that: include: The LINUX system board and the FPGA system board are connected via the PCIE bus. The LINUX system board includes a core processing CPU, a non-volatile memory FLASH / MMC, a memory module DDR, and a PCIE main controller interface; the FPGA system board includes an FPGA interface controller, an AXI to AHB bridge, an AXI to APB bridge, and a core decoding unit; The core processing CPU of the LINUX system board is connected to the FPGA interface controller of the FPGA system board through the PCIE main controller interface; the core processing CPU is respectively connected to the non-volatile memory FLASH / MMC and the memory module DDR; The FPGA interface controller of the FPGA system board is connected to the core decoding unit through the AXI to AHB bridge and the AXI to APB bridge.

2. The PCIE interface-based barcode decoding algorithm operation device according to claim 1, characterized in that: The FPGA interface controller comprises an XDMA control unit and an AXI control unit connected via an AXI bus; The XDMA control unit is used to exchange data with the LINUX system board through the PCIE host controller interface; The AXI control unit is used to transmit and manage data between modules within the FPGA.

3. The PCIE interface-based barcode decoding algorithm operation device according to claim 2, characterized in that: The core decoding unit comprises an image BMP storage unit, a 1D decoding logic unit, a QR decoding logic unit, a DM decoding logic unit, and a PDF417 decoding logic unit, each decoding logic unit is provided with a corresponding status register; the image BMP storage unit is connected with the 1D decoding logic unit, the QR decoding logic unit, the DM decoding logic unit, and the PDF417 decoding logic unit via a bus; The AXI control unit uses the AXI to APB bridge to read and write the status registers of the 1D decoding logic unit, QR decoding logic unit, DM decoding logic unit, and PDF417 decoding logic unit; The AXI control unit implements the read and write operations of the image BMP storage unit through the AXI to AHB bridge.

4. The PCIE interface-based barcode decoding algorithm operation device according to claim 2, characterized in that: The LUNIX system board also includes a network communication interface module, which is used for remotely controlling batch barcode testing and transmission of the barcode library; the network communication interface module is connected to the core processing CPU.

5. A method for running a barcode decoding algorithm based on a PCIE interface, characterized in that: The method is implemented based on the barcode decoding algorithm running device based on the PCIE interface as described in any one of claims 1 to 4, and comprises the following steps: After the LINUX system board and the FPGA system board are powered on, the LINUX system board is connected to the FPGA system board through the PCIE main controller interface. After the connection is successful, the LINUX system board loads the corresponding PCIE driver; The test program of the LINUX system board initializes each unit of the FPGA system board through the PCIE main controller interface; After the initialization operation is completed, the LINUX system board starts to traverse the barcode library to be tested, and downloads the images in the barcode library to the image BMP storage unit of the core decoding unit in the FPGA system board through the PCIE main controller interface; After the image is downloaded, the FPGA system board starts the 1D decoding logic unit, QR decoding logic unit, DM decoding logic unit, and PDF417 decoding logic unit of the core decoding unit to decode the 1D code, QR code, DM code, and PDF417 code in sequence, and transmits the barcode decoding results to the corresponding status registers; After the barcode decoding is completed, the FPGA system board transmits the barcode decoding result to the test program of the LINUX system board through the PCIE interrupt and status register; The test program counts the performance indicators of each decoding algorithm in the core decoding unit to form test data.

6. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the barcode decoding algorithm operation method based on the PCIE interface as claimed in claim 5 when executing the computer program.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, the PCIE interface-based barcode decoding algorithm operation method according to claim 5 is implemented.

Images