Distributed memory configuration method and device, equipment, medium and product

Abstract

The invention relates to a distributed memory configuration method and device, equipment, a medium and a product, the method is applied to a multi-core micro-control unit MCU system, the multi-core MCU system comprises a global memory, a plurality of local memories and a plurality of kernels, one local memory corresponds to one kernel, and the other local memory corresponds to one kernel. The method comprises the steps of obtaining access information of each target data segment in at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by the first service; the access information is used for representing the frequency of accessing a plurality of kernels when the target data segment runs; the first service is any service to be operated in the MCU system; and based on the access information of each target data segment, configuring a target memory for storing each target data segment in the global memory and the plurality of local memories. The scheme is used for performing memory allocation on the data segments of the at least one intermediate file compiled by the first service, and the access information during operation of each data segment is considered, so that reasonable allocation is realized.

Description

Technical Field

[0001] The present application relates to the field of vehicle technology, and in particular to a configuration method, device, equipment, medium and product of a distributed memory. Background Art

[0002] With the development of multi-core microcontroller technology, the architecture of random access memory (RAM) has also changed greatly, gradually evolving from the previous centralized RAM to a distributed RAM architecture. The distributed RAM architecture consists of the local RAM corresponding to the central processing unit (CPU) core and the global RAM group shared by multiple cores.

[0003] The CPU has the following characteristics when accessing the two types of RAM: When the CPU core accesses local RAM, it does not go through the system bus, and the speed is very fast, but the capacity of local RAM is generally small. When the CPU accesses global RAM, it needs to go through the bus, and the speed is slightly slower, but the space of global RAM is generally larger. Therefore, it is particularly important to effectively manage the allocation of local RAM and global RAM resources.

[0004] Currently, the memory segment allocation method by compiler or human often cannot fully utilize the speed advantage of local RAM, and fails to effectively deal with the access delay of global RAM, thus affecting the performance of the overall system. Summary of the invention

[0005] The present application provides a distributed memory configuration method, apparatus, device, medium and product, which is used to allocate memory to data segments of at least one intermediate file compiled by a first service, and takes into account the access information of each data segment at runtime to achieve reasonable allocation.

[0006] The technical solutions adopted in this application are as follows:

[0007] In a first aspect, the present application provides a distributed memory configuration method, which is applied to a multi-core microcontroller unit MCU system, the multi-core MCU system includes a global memory, multiple local memories, and multiple cores, one local memory corresponds to one core, and the method includes: obtaining access information of each target data segment in at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by a first service; the access information is used to characterize the frequency of accessing multiple cores when the target data segment is running; the first service is any service to be run in the MCU system;

[0008] Based on the access information of the at least one target data segment, a target memory for storing each target data segment is configured in the global memory and the plurality of local memories.

[0009] Based on the above means, a multi-core microcontroller unit MCU system includes a global memory, multiple local memories, and multiple cores. One local memory corresponds to one core. The memory configuration scheme of the related technology is generally used to configure the core for the core. The scheme of the present application is used to allocate memory to the target data segment of at least one intermediate file compiled by the first service, and when configuring memory for the target data segment, the access information of each data segment at runtime is considered to achieve reasonable allocation, thereby improving the operating efficiency of the first service and the operating effect of the multi-core microcontroller unit MCU system.

[0010] In some implementations, based on access information of at least one target data segment, a target memory for storing each target data segment is configured in a global memory and multiple local memories, including: determining a total access frequency of each target data segment in the access information of each target data segment; the total access frequency is used to characterize the sum of the frequencies of the target data segment accessing each kernel in multiple kernels; determining a priority of each target data segment based on the total access frequency of each target data segment; and configuring a target memory for storing each target data segment in a global memory and multiple local memories based on the access information of each target data segment in turn according to the priority of each target data segment.

[0011] Based on the above means, priorities are configured when allocating memory to multiple target data segments, and allocation is performed based on the order of priorities. Since the priorities are determined based on the total access frequency of the target data segments, it can be ensured that target data segments with high access frequencies are allocated memory first, thereby ensuring the rationality of the memory configuration of frequently used target data segments. For example, when memory is insufficient, the priority-based configuration method can ensure the priority use of frequently used target data segments, which has less impact on the first service and improves the operating efficiency of the first service.

[0012] In some implementations, based on access information of at least one target data segment, a target memory for storing each target data segment is configured in a global memory and multiple local memories, including: determining an analysis result of each target data segment based on the access information of each target data segment; based on the analysis result of each target data segment, configuring the target memory of the target data segment in the global memory and multiple local memories; the analysis result includes at least one of the following: a hot or cold type, a nucleophilic type, a shared type, and a size type of the target data segment.

[0013] Based on the above means, when allocating memory, factors such as the hot and cold types, nucleus-friendly types, shared types, and size types of the target data segment are taken into consideration, so that the memory allocation can be more in line with actual needs, making the memory configuration more reasonable, so that the first service can run efficiently, and the multi-core microcontroller unit MCU system can run efficiently.

[0014] In some implementations, based on the access information of each target data segment, determining the analysis result of each target data segment includes: determining the total access frequency of the target data segment in the access information of the target data segment; if the access frequency is greater than or equal to a first threshold, determining the hot / cold type is hot; if the total access frequency is less than the first threshold, determining the hot / cold type is cold;

[0015] and / or, determining, in the access information of the target data segment, a single-core access frequency of the target data segment, and determining a core having the largest single-core access frequency as a core-friendly type;

[0016] and / or, in the access information of the target data segment, determining the single-core access frequency of the target data segment, if there are multiple single-core access frequencies with non-zero values, determining the sharing type as inter-core sharing; if there is only one single-core access frequency with a non-zero value, determining the sharing type as non-inter-core sharing;

[0017] And / or, in the access information of the target data segment, determine the data size of the target data segment; if the data size is greater than or equal to a second threshold, determine the size type as a large block; if the data size is less than the second threshold, determine the size type as a small block.

[0018] Based on the above means, the process of determining the analysis result of each target data segment (hot and cold type, nucleophilic type, shared type and size type of the target data segment) based on the access information of each target data segment is described. It can be seen that the implementation process has the characteristics of convenient implementation, reliability and flexible selection.

[0019] In some implementations, when the analysis results include hot-cold types and nucleophilic types, the target memory of the target data segment is configured in the global memory and multiple local memories based on the analysis results of each target data segment, including: if the hot-cold type of the analysis result is hot, the target memory is determined to be the local memory corresponding to the core pointed to by the nucleophilic type in the multiple local memories; if the hot-cold type of the analysis result is cold, the target memory is determined to be the global memory.

[0020] Based on the above means, for hot target data segments, due to the high access frequency, they are configured in the layout memory. Since the local memory is directly connected to the kernel, the data response rate is improved in the time dimension. Specifically, it can be configured in the local memory corresponding to the kernel with the highest access frequency of the target data segment to ensure the rate of most accesses. For cold target data segments, due to the low access frequency, they are configured in the global memory to reduce the occupancy of local memory and improve the memory utilization efficiency in the spatial dimension.

[0021] In some implementations, when the analysis result includes a sharing type, based on the analysis result of each target data segment, the target memory of the target data segment is configured in the global memory and multiple local memories, including: if the sharing type of the analysis result is inter-core sharing, then the target memory is determined to be the global memory; if the sharing type of the analysis result is non-inter-core sharing, then the target memory is determined to be a local memory of the multiple local memories.

[0022] Based on the above means, for the shared type target data segment, since the shared type target data segment generally accesses multiple cores, it is allocated to the global RAM, which helps the interaction between multiple cores, helps to optimize the memory usage efficiency, and reduces unnecessary data copying and synchronization; for the non-shared type target data segment, it can be allocated to one of the multiple local memories. It can be seen that the allocation is reasonable and efficient.

[0023] In some implementations, when the analysis result includes a size type, based on the analysis result of each target data segment, a target memory of the target data segment is configured in a global memory and a plurality of local memories, including: if the size type of the analysis result is a large block, determining the target memory to be a global memory; if the size type of the analysis result is a small block; determining the target memory to be a local memory among the plurality of local memories.

[0024] Based on the above means, for large target data segments, since they occupy a large memory space and the global memory space has a large capacity, they can be configured in the global memory. For small target data segments, since they occupy a small memory space, they can be configured in one of the local memories among multiple local memories. It can be seen that the allocation is reasonable and efficient.

[0025] In some implementations, obtaining access information of at least one target data segment includes: running a first service in a multi-core MCU system; collecting the frequency of each target data segment in at least one target data segment accessing multiple cores during the running of the first service within a first time period to obtain access information of at least one target data segment.

[0026] Based on the above means, through the operation process of the first service, the access information of each target data segment is actually collected, which has the characteristics of high accuracy and high reliability.

[0027] In some implementations, the target data segment includes: a first data segment, a second data segment, and a third data segment; wherein the first data segment includes initialized global variables and static variables; the second data segment includes: uninitialized global variables and static variables; and the third data segment includes: local variables and function calls.

[0028] Based on the above means, the target data segment is further segmented to achieve reasonable memory allocation for the segmented initialized global variables and static variables, uninitialized global variables and static variables, as well as local variables and function call data, thereby improving the use efficiency of these data.

[0029] In a second aspect, the present application provides a distributed memory configuration device, which is deployed in a multi-core microcontroller unit MCU system. The multi-core MCU system includes a global memory, multiple local memories, and multiple cores. One local memory corresponds to one core. The device includes:

[0030] an acquisition unit, configured to acquire access information of each target data segment in at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by the first service; the access information is used to characterize the frequency of accessing multiple cores when the target data segment is running; the first service is any service to be run in the MCU system;

[0031] The configuration unit is used to configure a target memory for storing each target data segment in the global memory and the plurality of local memories based on access information of the at least one target data segment.

[0032] In a third aspect, the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program or instructions, and when the computer program or instructions are executed by the processor, the method provided in the first aspect is implemented.

[0033] In a fourth aspect, the present application further provides a storage medium having a computer program or instruction stored thereon, and the computer program or instruction, when executed by a processor, implements the method provided in the first aspect above.

[0034] In a fifth aspect, the present application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, the method provided in the first aspect is implemented.

[0035] It should be noted that the technical effects of the second to fifth aspects can refer to the detailed description of the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 An optional structural diagram of a multi-core MCU system provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of a first optional flow chart of a distributed memory configuration method provided in an embodiment of the present application;

[0038] Figure 3A second optional flow chart of the distributed memory configuration method provided in the embodiment of the present application;

[0039] Figure 4 A third optional flow chart of the distributed memory configuration method provided in the embodiment of the present application;

[0040] Figure 5 A fourth optional flow chart of the distributed memory configuration method provided in the embodiment of the present application;

[0041] Figure 6 Another optional structural diagram of the multi-core MCU system provided in the embodiment of the present application;

[0042] Figure 7 An optional structural diagram of a performance analysis processing structure provided in an embodiment of the present application;

[0043] Figure 8 An optional flowchart of a distributed memory configuration process provided in an embodiment of the present application;

[0044] Fig. 9 An optional schematic diagram of the allocation and connection of various target files provided in the embodiment of the present application;

[0045] Fig.10 An optional flowchart of the RAM allocation process provided in the embodiment of the present application;

[0046] Fig.11 An optional structural diagram of a distributed memory configuration device provided in an embodiment of the present application;

[0047] Fig.12 An optional structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0049] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0050] In the following description, the terms "first\second\third" are used only as examples to distinguish different objects, and do not represent a specific order for the objects, nor do they have a limitation on the order of precedence. It is understandable that "first\second\third" can be interchanged with a specific order or order of precedence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0052] The embodiments of the present application provide a distributed memory configuration method, apparatus, device, storage medium and program product, which are applied to a multi-core MCU system.

[0053] To facilitate understanding, the multi-core MCU system provided in the embodiment of the present application is first described.

[0054] refer to Figure 1 As shown, the multi-core MCU system 10 includes a global memory 101 , multiple local memories 102 , and multiple cores 103 , where one local memory 102 corresponds to one core 103 .

[0055] The embodiment of the present application does not limit the number of local memories 102 and cores 103, and can be configured according to actual needs.

[0056] The core 103 refers to a central processing unit (CPU) core.

[0057] The global memory 101 refers to a RAM space accessible to all cores of the multi-core MCU system 10. It needs to be accessed through a data bus, and has a slightly slower access speed, but a larger capacity.

[0058] The local memory 102 refers to a RAM directly connected to a core CPU. The core does not need to cross the bus when accessing, and the access speed is fast, but the capacity is limited.

[0059] Below, various embodiments of the distributed memory configuration method, device, equipment, storage medium and program product provided in the embodiments of the present application are described. The distributed memory configuration method can be implemented by a distributed memory configuration device, and the distributed memory configuration device can be deployed in an electronic device including a memory and a processor.

[0060] In a possible implementation, the electronic device may be deployed in a multi-core MCU system.

[0061] In another possible implementation, the multi-core MCU system may be deployed in an electronic device.

[0062] In a first aspect, the present application embodiment provides a distributed memory configuration method, referring to Figure 2 The content shown takes the electronic device as the execution subject as an example, and the process may include but is not limited to the following S201 and S202.

[0063] S201. The electronic device obtains access information of at least one target data segment.

[0064] The target data segment is a data segment of at least one intermediate file compiled by the first service. The first service is any service to be run in the MCU system.

[0065] Here, one intermediate file corresponds to one data segment, and one or more intermediate files can be obtained after a service is compiled.

[0066] The embodiment of the present application does not limit the type of the intermediate file, and can be configured according to actual needs. For example, the intermediate file here can be a .o file.

[0067] The target data segment stores the data of the compiled intermediate file.

[0068] The access information is used to characterize the frequency of accessing multiple cores when the target data segment is running. The frequency refers to the number of accesses per unit time.

[0069] The access information may include: the frequency of accessing each of the multiple cores when the target data segment is running.

[0070] The access information may also include the total frequency of accesses to the target data segment by all cores at runtime.

[0071] The access information may also include other information (eg, the data size of the target data segment, the timestamp of the acquisition, etc.), which are not listed here one by one.

[0072] In a possible implementation, S201 may be implemented as: the electronic device receives access information of each target data segment in at least one target data segment sent by another device.

[0073] In another possible implementation, S201 may be implemented as follows: the electronic device collects data on the first service running process to obtain access information of each target data segment in a target data segment.

[0074] S202. The electronic device configures a target memory for storing each target data segment in a global memory and a plurality of local memories based on access information of at least one target data segment.

[0075] Here, a target data segment has a target memory of its own.

[0076] The electronic device configures a target memory (global memory or a local memory) for storing each target data segment in the global memory and multiple local memories, and the specific configuration method is determined according to the access information in the target data segment.

[0077] In this embodiment, based on the above means, a multi-core microcontroller unit MCU system includes a global memory, multiple local memories, and multiple cores. One local memory corresponds to one core. The memory configuration scheme of the related technology is generally used to configure the core for the core. The scheme of the present application is used to allocate memory to the target data segment of at least one intermediate file compiled by the first service, and when configuring memory for the target data segment, the access information of each data segment at runtime is taken into account to achieve reasonable allocation, thereby improving the operating efficiency of the first service and the operating effect of the multi-core microcontroller unit MCU system.

[0078] Next, the target data segment is described.

[0079] In a possible implementation, the target data segment includes: a first data segment, a second data segment and a third data segment; wherein the first data segment includes initialized global variables and static variables; the second data segment includes: uninitialized global variables and static variables; the third data segment includes: local variables and function calls.

[0080] Of course, the target data segment may also include more content, or part of the first data segment, the second data segment or the third data segment, which will not be listed here one by one.

[0081] Based on the above means, the target data segment is further segmented to achieve reasonable memory allocation for the segmented initialized global variables and static variables, uninitialized global variables and static variables, as well as local variables and function call data, thereby improving the use efficiency of these data.

[0082] The following describes a process in which the electronic device configures a target memory for storing each target data segment in a global memory and a plurality of local memories based on access information of at least one target data segment in S202.

[0083] refer to Figure 3 As shown in the content, the process may include but is not limited to the following S301 to S303.

[0084] S301. The electronic device determines the total access frequency of each target data segment from the access information of each target data segment.

[0085] The total access frequency is used to represent the sum of the frequencies of the target data segment accessing each of the multiple cores.

[0086] In a possible implementation manner, the access information includes a total access frequency, so that the electronic device can directly obtain the total access frequency of each target data segment from the access information.

[0087] In another possible implementation, the access information does not include the total access frequency, but includes the access frequency of each core, so that the electronic device can sum the access frequencies of all cores to obtain the total access frequency of each target data segment.

[0088] S302: The electronic device determines the priority of each target data segment based on the total access frequency of each target data segment.

[0089] The higher the total access frequency, the higher the corresponding priority, and the higher the priority, the higher the priority.

[0090] In fact, you can configure a corresponding priority for each total access frequency; or you can configure a priority for a total access frequency range.

[0091] S303. The electronic device configures a target memory for storing each target data segment in a global memory and multiple local memories in accordance with the priority of each target data segment and based on the access information of each target data segment.

[0092] Assume that there are 4 target data segments, namely target data segment 1, target data segment 2, target data segment 3 and target data segment 4. The total access frequency of target data segment 1 is 90, the total access frequency of target data segment 2 is 25, the total access frequency of target data segment 3 is 54, and the total access frequency of target data segment 4 is 1. Then the priorities of target data segment 1, target data segment 3, target data segment 2 and target data segment 4 decrease in sequence. The electronic device first allocates target memory to target data segment 1, then allocates target memory to target data segment 3, then allocates target memory to target data segment 2, and finally allocates target memory to target data segment 4.

[0093] In this embodiment, based on the above means, priorities are configured when allocating memory to multiple target data segments, and allocation is performed based on the order of priorities. Since the priorities are determined based on the total access frequency of the target data segments, it can be ensured that target data segments with high access frequency are allocated memory first. This can ensure the rationality of the memory configuration of frequently used target data segments. For example, when memory is insufficient, the priority-based configuration method can ensure the priority use of frequently used target data segments, which has less impact on the first service and improves the operating efficiency of the first service.

[0094] Next, the process of configuring the target memory for storing each target data segment in the global memory and the multiple local memories by the electronic device in S202 or S303 based on the access information of each target data segment is described. The processing process of one target data segment is specifically described as an example, and the processing processes of other target data segments are similar and will not be described one by one.

[0095] refer to Figure 4 As shown in the content, the process may include but is not limited to the following S401 and S402.

[0096] S401. The electronic device determines an analysis result of each target data segment based on access information of each target data segment.

[0097] The analysis result includes at least one of the following: a hot / cold type, a nucleation type, a sharing type, and a size type of the target data segment.

[0098] The content of the analysis results can be configured according to actual needs and the types included are not listed here one by one.

[0099] The hot and cold types of the target data segment include: cold type and hot type. The cold type is used to represent the low access frequency, and the hot type is used to represent the frequent access, that is, the high access frequency.

[0100] The kernel affinity type is used to characterize the kernel with the highest single-core access frequency to the target data segment.

[0101] Sharing type, including inter-core sharing and non-core sharing. Inter-core sharing is used to indicate that the target data segment can access multiple cores. Non-core sharing is used to indicate that the target data segment can only access one core.

[0102] Size type, including large type and small type. The large type is used to indicate that the target data segment has a large amount of data, and the small type is used to indicate that the target data segment has a small amount of data.

[0103] S402: The electronic device configures a target memory of the target data segment in a global memory and a plurality of local memories based on an analysis result of each target data segment.

[0104] The configuration process is related to the values ​​of the hot and cold types, the affinity type, the sharing type, and the size type of the target data segment.

[0105] In this embodiment, based on the above means, factors such as the hot and cold types, nucleophilic types, shared types, and size types of the target data segment are taken into consideration during memory allocation, so that the memory allocation can be more in line with actual needs, making the memory configuration more reasonable, so that the first service can run efficiently, and the multi-core microcontroller unit MCU system can run efficiently.

[0106] Next, the process of determining the analysis result of each target data segment based on the access information of each target data segment by the electronic device in S401 is described.

[0107] The process may include but is not limited to at least one of the following methods 1 to 4.

[0108] Method 1: In the access information of the target data segment, determine the total access frequency of the target data segment; if the access frequency is greater than or equal to the first threshold, determine the hot / cold type to be hot; if the total access frequency is less than the first threshold, determine the hot / cold type to be cold.

[0109] The embodiment of the present application does not limit the value of the first threshold value, and can be configured according to actual needs. For example, the first threshold value can be an empirical value or an average value of the total access frequency of all target data segments.

[0110] Method 2: In the access information of the target data segment, the single-core access frequency of the target data segment is determined, and the core with the largest single-core access frequency is determined as the core-friendly type.

[0111] If there are two largest kernels, the kernel-friendly type of the target data segment is determined to be the two kernels or any one of them.

[0112] Method 3: In the access information of the target data segment, determine the single-core access frequency of the target data segment. If there are multiple single-core access frequencies with non-zero values, the sharing type is determined to be inter-core sharing; if there is only one single-core access frequency with a non-zero value, the sharing type is determined to be non-inter-core sharing.

[0113] In other words, if a target data segment only accesses one core, the sharing type of the target data segment is determined to be non-inter-core sharing; if a target data segment accesses multiple cores, the sharing type of the target data segment is determined to be inter-core sharing.

[0114] Method 4: Determine the data size of the target data segment in the access information of the target data segment; if the data size is greater than or equal to the second threshold, determine the size type as a large block; if the data size is less than the second threshold, determine the size type as a small block.

[0115] The embodiment of the present application does not limit the size of the second threshold value, which can be determined according to actual needs. The second threshold value here can be a fixed empirical value or an adjustable value.

[0116] In this embodiment, based on the above means, the process of determining the analysis result of each target data segment (hot and cold type, nucleophilic type, shared type and size type of the target data segment) based on the access information of each target data segment is described. It can be seen that the implementation process has the characteristics of convenient implementation, reliability and flexible selection.

[0117] Next, the process of configuring the target memory of the target data segment in the global memory and the multiple local memories by the electronic device in S402 based on the analysis result of each target data segment is described.

[0118] The process may include but is not limited to the following implementations 1 to 6.

[0119] Implementation 1. How to determine the target memory of the target data segment when the analysis results include hot and cold types.

[0120] Implementation 2: How to determine the target memory of the target data segment when the analysis result includes the nucleophilic type.

[0121] Implementation 3: How to determine the target memory of the target data segment when the analysis results include the shared type.

[0122] Implementation 4: How to determine the target memory of the target data segment when the analysis result includes the size type.

[0123] Implementation 5. How to determine the target memory of the target data segment when the analysis results include hot-cold type and nucleophilic type.

[0124] Implementation 6. When the analysis results include hot and cold types, nucleophilic types, shared types, and large and small types, how to determine the target memory of the target data segment.

[0125] Next, the process of determining the target memory of the target data segment when the analysis result includes the hot and cold types in implementation 1 is described.

[0126] If the target data segment is of hot type, in order to facilitate efficient calling of the target data segment, the target memory of the target data segment is determined to be a local memory (the specific determination of which local memory can be determined in combination with the nucleophilic type, or one can be directly randomly determined); if the target data segment is of cold type, in order to save storage space, the target type of the target data segment is determined to be global memory.

[0127] Next, the process of how to determine the target memory of the target data segment in implementation 2 when the analysis result includes the nucleophilic type is described.

[0128] The target memory of the target data segment is determined to be the local memory corresponding to the kernel pointed to by the parent kernel type.

[0129] This nucleus-friendly type can generally be used in combination with other types to select a local memory as the target memory from multiple local memories.

[0130] Next, the process of how to determine the target memory of the target data segment in implementation 3 when the analysis result includes the sharing type is described.

[0131] If the sharing type of the analysis result is inter-core sharing, the target memory is determined to be global memory; if the sharing type of the analysis result is non-inter-core sharing, the target memory is determined to be a local memory of multiple local memories.

[0132] The specific implementation of the target memory being a local memory of multiple local memories can be determined in combination with the nucleophilic type, and of course a local memory can also be randomly determined.

[0133] Based on the above means, for the shared type target data segment, since the shared type target data segment generally accesses multiple cores, it is allocated to the global RAM, which helps the interaction between multiple cores, helps to optimize the memory usage efficiency, and reduces unnecessary data copying and synchronization; for the non-shared type target data segment, it can be allocated to one of the multiple local memories. It can be seen that the allocation is reasonable and efficient.

[0134] Next, the process of how to determine the target memory of the target data segment in implementation 4 when the analysis result includes the size type is described.

[0135] If the size type of the analysis result is large block, the target memory is determined to be global memory; if the size type of the analysis result is small block, the target memory is determined to be a local memory among multiple local memories.

[0136] Based on the above means, for large target data segments, since they occupy a large memory space and the global memory space has a large capacity, they can be configured in the global memory. For small target data segments, since they occupy a small memory space, they can be configured in one of the local memories among multiple local memories. It can be seen that the allocation is reasonable and efficient.

[0137] Next, the process of how to determine the target memory of the target data segment in implementation 5 when the analysis results include the cold-hot type and the nucleophilic type is described.

[0138] If the hot-like type of the analysis result is hot, the target memory is determined to be a local memory corresponding to the core pointed to by the nucleophilic type among the multiple local memories; if the cold-hot type of the analysis result is cold, the target memory is determined to be a global memory.

[0139] Based on the above means, for hot target data segments, due to the high access frequency, they are configured in the layout memory. Since the local memory is directly connected to the kernel, the data response rate is improved in the time dimension. Specifically, it can be configured in the local memory corresponding to the kernel with the highest access frequency of the target data segment to ensure the rate of most accesses. For cold target data segments, due to the low access frequency, they are configured in the global memory to reduce the occupancy of local memory and improve the memory utilization efficiency in the spatial dimension.

[0140] Next, the process of how to determine the target memory of the target data segment in implementation 6 when the analysis results include hot and cold types, nucleophilic types, shared types, and large and small types is described.

[0141] If it includes hot and cold types, nucleophilic types, shared types, and size types, multiple target memories corresponding to each type are determined based on each type, and then multiple target memories are merged. If there is no contradiction during fusion, then the respective conditions are met at the same time; if there is a contradiction during fusion, the target memory is determined according to the priority of each type. Among them, the priority from high to low is: hot and cold type, nucleophilic type, shared type, and size type.

[0142] It should be noted that the above 4 types can also be combined in various ways to determine the target memory. The specific implementation method can refer to the description of implementation 6, that is, when the determination results are not contradictory, the target memory is determined based on the results of multiple types. If the results are contradictory, the target memory is determined according to the priority of each type. Among them, the priority from high to low is: hot and cold type, nucleophilic type, shared type and large and small type.

[0143] Next, the process of the electronic device acquiring the access information of each target data segment in at least one target data segment in S201 is described.

[0144] refer to Figure 5 As shown in the content, the process may include but is not limited to the following S501 and S502.

[0145] S501: The electronic device runs a first service in a multi-core MCU system.

[0146] The electronic device compiles and runs the first service in the multi-core MCU system, so that each intermediate file in the first service accesses multiple cores according to the original rules.

[0147] S502: The electronic device collects the frequency of each target data segment in at least one target data segment accessing multiple cores during the operation of the first service within a first time period to obtain access information of the at least one target data segment.

[0148] The duration of the first time period can be configured according to actual needs and is not limited here.

[0149] The electronic device collects the access conditions (access time, access times, etc.) of each data segment to each core, thereby obtaining access information of each target data segment.

[0150] Based on the above means, through the operation process of the first service, the access information of each target data segment is actually collected, which has the characteristics of high accuracy and high reliability.

[0151] Below, taking an embodiment as an example, the configuration process of the distributed memory provided by the embodiment of the present application is explained.

[0152] This embodiment belongs to the embedded system memory management technology, and relates to a resource static allocation method of a random access memory (RAM) (equivalent to the above memory) in a multi-core microcontroller unit (MCU).

[0153] With the development of multi-core microcontroller technology, the architecture of RAM has also changed greatly, from the previous centralized RAM to the distributed RAM architecture. The distributed RAM architecture consists of the local RAM corresponding to the central processing unit (CPU) core and the global RAM shared by multiple cores (hereinafter referred to as local RAM and global RAM).

[0154] refer to Figure 6 As shown, the multi-core MCU system includes: global RAM one 601, global RAM two 602, core zero (COR0) 603, core one (COR1) 604, core two (COR2) 605, core three (COR3) 606, local RAM zero 607, local RAM one 608, local RAM two 609, local RAM three 610 and data bus 611.

[0155] The CPU has the following characteristics when accessing the two types of RAM: When the CPU core accesses local RAM, it does not go through the system bus, and the speed is very fast, but the capacity of local RAM is generally small. When the CPU accesses global RAM, it needs to go through the bus, and the speed is slightly slower, but the space of global RAM is generally larger. Therefore, it is particularly important to effectively manage the allocation of local RAM and global RAM resources.

[0156] Currently, the memory segment allocation method by compiler or human often cannot fully utilize the speed advantage of local RAM, and fails to effectively deal with the access delay of global RAM, thus affecting the performance of the overall system.

[0157] For example, the solution of the related technology includes: obtaining multiple memory segments corresponding to the task to be processed, determining multiple operating cores included in the operating platform that executes the task to be processed; and determining a first capacity memory segment and a second capacity memory segment in the multiple memory segments according to the multiple operating cores. This method does not solve the problem of low access efficiency when accessing memory data across cores.

[0158] In contrast, the method proposed in this embodiment can solve the memory allocation problem of multi-core systems and distributed memory architectures. The link script's link operation on the data segment is optimized through the performance analysis results when actually running on the target platform, and the link addresses of the data segment, stack, and bss segment in the code are changed. The memory access efficiency of the multi-core program at runtime is improved.

[0159] The address space needs to be allocated for the data segment during the code compilation stage. The data segment is divided into data segment, stack segment, and bss segment. Here, the data segment, stack segment, and bss segment are collectively referred to as the data segment.

[0160] RAM segment: divides the physical RAM space into several segments to store data segments, stacks, and bss segments.

[0161] This embodiment provides a RAM segment allocation method based on performance analysis in a multi-core MCU system, which aims to optimize the allocation of memory resources in the code linking stage, and improve the system's operating efficiency and response speed by optimizing the data segment allocation of local bound RAM (equivalent to the local memory corresponding to the kernel mentioned above) and global RAM.

[0162] 1. Performance analysis:

[0163] refer to Figure 7 As shown in the content, the performance analysis processing structure includes: an MCU target board 701, a data recording module 702, a performance analysis module 703, and a development compilation environment 704.

[0164] In a typical application scenario of a multi-core MCU system, connect the MCU target board to the data logging module, enable the data logging module to collect memory access data for a period of time and save it as a log file. The log file contains information such as the frequency of access to a certain data item, the specific core that accesses these data items, and the timestamp information of the access.

[0165] The performance analysis module is used to analyze the collected recorded data. The performance analysis outputs two indicators: the frequency of a certain data being accessed by a single core (A_avg); the total number of times a certain data is accessed by all cores (A_all).

[0166] 2. Data classification.

[0167] refer to Figure 8 As shown in the figure, the distributed memory configuration process may include:

[0168] S801, code compilation;

[0169] S802, generate an intermediate .o file;

[0170] S803, link to hex file;

[0171] S804, running on the target platform;

[0172] S805. Perform performance analysis using performance analysis tools;

[0173] S806, output analysis result file;

[0174] S807, classifying the data segments according to the performance analysis result file;

[0175] S808, classify according to hot data and cold data;

[0176] S809, allocating data segments to RAM segments in order of heat priority;

[0177] S810. Modify the link script.

[0178] According to the performance analysis results, the data segments are classified as follows:

[0179] By data priority: Sort the data in descending order according to the access frequency A_all. The sorting result is used for the allocation order of data segments. The higher the data popularity, the higher the priority of data allocation, and the lower the data popularity, the lower the priority of data allocation. The purpose is to ensure the priority allocation of high-popularity data.

[0180] Hot and cold data types: Based on the frequency of data A_all, select a median access frequency as the threshold point A_thod, and use the threshold A_thod to classify A_all in the performance analysis results. Data above the threshold is classified as hot data, and data below the threshold is classified as cold data.

[0181] According to the data's nucleophilicity: the data's nucleophilicity is classified, and a core-data segment access frequency histogram is drawn. The horizontal axis is the core ID of the core (coreID), and the vertical axis is the frequency of each core's access to the data segment. The data is sorted according to the frequency, and the core with the highest access frequency to the data segment is found to determine the data's nucleophilicity. The purpose is to ensure that the nucleophilic data is allocated to the local RAM bound to the core as much as possible.

[0182] 3. Memory allocation:

[0183] RAM segment planning: According to the physical memory structure of the MCU, the starting address and space size of the local RAM and global RAM bound to each core are planned, which is called a memory segment. In this embodiment, the local RAM bound to each core is divided into 3 segments, and the global RAM is divided into 3 segments. The specific segmentation rules can be modified according to the actual scenario.

[0184] Data segment division: The intermediate result src.o file after code compilation is divided into several data segments according to each file, namely code segment (code, text, string constants), data segment (initialized global variables, static variables), bss segment (uninitialized global variables, static variables), stack segment (local variables, function calls).

[0185] Data allocation: A code project consists of many files. Each file will be compiled into an independent intermediate file with the suffix .o during the compilation phase, which mainly contains the address and size allocation of variables and symbols such as the code segment, data segment, bss segment, stack, heap, etc. The purpose of this method is to record memory access data and perform performance analysis on the basis of a runnable initial version of the program, so as to optimize the link allocation of the code data segment content in the RAM segment.

[0186] When linking compiled data, the following indicators need to be considered: the hot and cold types of the data, the affinity of the data, whether it is shared data, and whether it is a large data block.

[0187] Based on the above indicators, decide which RAM segment the data segment in each target file should be allocated to. The specific allocation details are as follows: According to the overall popularity of the data, the data is allocated to RAM segments according to the priority from high to low. The allocation method is as follows:

[0188] Hot data is allocated to local RAM: Based on the data's affinity, the hot data of each core (such as local variables of core functions and frequently used global variables) is allocated to the local RAM bound to the core. For example:

[0189] Step 1: Assume that there are 5 global data instances (equivalent to the target data segment instances mentioned above) InstanceA, InstanceB, InstanceC, InstanceD, and InstanceE in memory. First, follow the previous performance analysis steps to get the analysis results, find the overall access frequency Facc of the data instances InstanceA, InstanceB, InstanceC, InstanceD, and InstanceE per unit time, and the frequency Fcorex of a data instance being accessed by a single core. According to the calculation method of the data heat threshold, the median of the total data access frequency is used as the threshold, and data above or equal to the threshold is called hot data.

[0190] As shown in the data instance statistics results in Table 1, if the frequency of InstanceA and InstanceB is greater than or equal to the threshold, InstanceA and InstanceB are called hot data, and other instance data (InstanceC, InstanceD, InstanceE) are called cold data.

[0191] Table 1 Statistical results of data examples

[0192]

[0193] Step 2: According to the results of performance analysis, the access frequency of data instances InstanceA, InstanceB, InstanceC, InstanceD, and InstanceE on each core is counted, and the core with the highest access frequency is selected as the parent core of the data instance. The data instance allocation results can be referred to as shown in Table 2.

[0194] Table 2 Data example allocation results

[0195]

[0196] Step 3: Based on the data's hotness and affinity metrics, comprehensively determine whether the data instance needs to be bound to a core.

[0197] For example, if InstanceA and InstanceB are classified as hot data and have core affinity, and the data is not shared data between cores or large data blocks, then the data instances InstanceA and InstanceB are allocated to the RAM segments of their respective cores according to the above four sub-indicators. This can minimize access latency and bus load, and improve memory access efficiency in the time dimension.

[0198] The allocation and connection of each target file can be referred to Fig. 9 The content shown includes target file src1.o901, target file src2.o902, and target file src3.o903. Target file src1.o901 includes code segment 1, data segment 1 (hot data, core1 nucleophilic), bss segment 1 (hot data, core1 nucleophilic), and stack1 (hot data, core1 nucleophilic); target file src2.o902 includes code segment 2, data segment 2 (cold data, non-nucleophilic data), bss segment 2 (cold data, non-nucleophilic data), and stack2 (cold data, non-nucleophilic data); target file src3.o903 includes code segment 3, data segment 3 (large data block), bss segment 3 (shared data block), and stack3 (large data block).

[0199] The target file src1.o901 links to core1 local RAM904, the target file src2.o902 links to global RAM905, and the target file src3.o903 links to global RAM905.

[0200] refer to Fig. 9 As shown in the content, each data segment in the src1.o target file is classified as hot data and is core1-specific data, so it is allocated to the local RAM of Core1.

[0201] Allocate cold data to global RAM: Allocate cold data with low access frequency to global RAM. For example, Instance E is typical cold data and is allocated to the global RAM segment. This reduces the occupancy of local RAM and improves memory usage efficiency in the spatial dimension.

[0202] refer to Fig. 9 As shown in the content, each data segment in the src2.o target file is classified as cold data and non-core data, so it is allocated to the global RAM.

[0203] Shared data is allocated to global RAM: Data that needs to be shared across cores is allocated to global RAM, which helps optimize memory usage efficiency and reduce unnecessary data copying and synchronization. For example, Instance C is a typical inter-core shared data, which is used for cross-core communication and is allocated to the global RAM segment.

[0204] refer to Fig. 9 As shown in the content, the bss segment in the src3.o target file is shared data and is accessed by multiple cores, so it is allocated to the global RAM.

[0205] Allocation of large blocks of data: For large blocks of memory data in the data segment, it is necessary to consider both the popularity and locality of the data, and prioritize ensuring that the data segment can be placed in the local RAM bound to the core. If the local RAM space cannot accommodate it, it is placed in the global RAM. For example, data instance InstanceD is a typical large block of data, which is allocated in the global RAM segment, which can save limited local RAM space.

[0206] refer to Fig. 9 As shown in the content, the data segment and stack segment in the src3.o target file are shared data and are accessed by multiple cores, so they are allocated to the global RAM.

[0207] The RAM allocation process can be referred to Fig.10 The contents shown include but are not limited to the following S1001 to S1010.

[0208] S1001, performance analysis;

[0209] S1002, data classification;

[0210] S1003, data allocation priority sorting;

[0211] S1004, data nucleophilicity sorting;

[0212] S1005, allocating RAM according to data priority;

[0213] S1006, judging whether it is nucleophilic data;

[0214] If yes, execute the following S1008; if no, execute the following S1007;

[0215] S1007, put into global RAM;

[0216] S1008, determine whether the local RAM can accommodate it;

[0217] If yes, execute the following S1009; if no, execute the following S1010;

[0218] S1009, put into local RAM;

[0219] S1010, put it into global RAM.

[0220] 4. Effect evaluation: Repeat the above rules until all data segments in the target file are allocated. Get a new link file, and then recompile and link an executable program based on the new link file. Run the new executable code on the target board, and then perform data recording and performance analysis again to evaluate the effect of this RAM allocation.

[0221] In the second aspect, the embodiment of the present application provides a distributed memory configuration device, which is deployed in a multi-core microcontroller unit MCU system. The multi-core MCU system includes a global memory, multiple local memories, and multiple cores. One local memory corresponds to one core. Fig.11 As shown in the content, the distributed memory configuration device 110 includes an acquisition unit 1101 and a configuration unit 1102.

[0222] The acquisition unit 1101 is used to acquire access information of at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by the first service; the access information is used to characterize the frequency of accessing multiple cores when the target data segment is running; the first service is any service to be run in the MCU system;

[0223] The configuration unit 1102 is used to configure a target memory for storing each target data segment in the global memory and the multiple local memories based on the access information of the at least one target data segment.

[0224] In some embodiments, the configuration unit 1102 is also used to: determine the total access frequency of each target data segment in the access information of each target data segment; the total access frequency is used to characterize the sum of the frequencies of the target data segment accessing each core in multiple cores; determine the priority of each target data segment based on the total access frequency of each target data segment; and configure the target memory for storing each target data segment in the global memory and multiple local memories based on the access information of each target data segment in turn according to the priority of each target data segment.

[0225] In some embodiments, the configuration unit 1102 is also used to: determine the analysis result of each target data segment based on the access information of each target data segment; configure the target memory of the target data segment in the global memory and multiple local memories based on the analysis result of each target data segment; the analysis result includes at least one of the following: the hot and cold type, the nucleophilic type, the shared type and the size type of the target data segment.

[0226] In some embodiments, the configuration unit 1102 is also used to: determine the total access frequency of the target data segment in the access information of the target data segment; if the access frequency is greater than or equal to the first threshold, determine the hot and cold type as hot; if the total access frequency is less than the first threshold, determine the hot and cold type as cold; and / or, in the access information of the target data segment, determine the single-core access frequency of the target data segment, and determine the core with the largest single-core access frequency as the core-friendly type; and / or, in the access information of the target data segment, determine the single-core access frequency of the target data segment, if there are multiple single-core access frequencies that are non-zero values, determine the sharing type as inter-core sharing; if there is only one single-core access frequency that is a non-zero value, determine the sharing type as non-inter-core sharing; and / or, in the access information of the target data segment, determine the data volume of the target data segment; if the data volume is greater than or equal to the second threshold, determine the size type as large block; if the data volume is less than the second threshold, determine the size type as small block.

[0227] In some embodiments, when the analysis results include hot-cold type and nucleophilic type, the configuration unit 1102 is also used to: if the hot-cold type of the analysis result is hot, determine the target memory as the local memory corresponding to the core pointed to by the nucleophilic type in multiple local memories; if the hot-cold type of the analysis result is cold, determine the target memory as the global memory.

[0228] In some embodiments, when the analysis result includes a sharing type, the configuration unit 1102 is also used to: if the sharing type of the analysis result is inter-core sharing, determine that the target memory is global memory; if the sharing type of the analysis result is non-inter-core sharing, determine that the target memory is a local memory of multiple local memories.

[0229] In some embodiments, when the analysis result includes a size type, the configuration unit 1102 is further used to: if the size type of the analysis result is a large block, determine that the target memory is a global memory; if the size type of the analysis result is a small block, determine that the target memory is a local memory among multiple local memories.

[0230] In some embodiments, the acquisition unit 1101 is also used to: run a first service in a multi-core MCU system; collect the frequency of each target data segment in at least one target data segment accessing multiple cores during the operation of the first service within a first time period to obtain access information of at least one target data segment.

[0231] In some embodiments, the target data segment includes: a first data segment, a second data segment and a third data segment; wherein the first data segment includes initialized global variables and static variables; the second data segment includes: uninitialized global variables and static variables; the third data segment includes: local variables and function calls.

[0232] In a third aspect, an embodiment provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program or instructions, and when the computer program or instructions are executed by the processor, the method provided in the first aspect is implemented.

[0233] In one example, reference Fig.12 As shown in the figure, the electronic device 120 includes: a processor 1201, at least one communication bus 1202, a user interface 1203, at least one external communication interface 1204 and a memory 1205. The communication bus 1202 is configured to realize the connection and communication between these components. The user interface 1203 may include a device for receiving user input, and the external communication interface 1204 may include a standard wired interface and a wireless interface.

[0234] The memory 1205 is configured to store instructions and applications executable by the processor 1201, and can also cache data to be processed or processed by the processor 1201 and various modules in the electronic device (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0235] In a fourth aspect, an embodiment provides a storage medium, that is, a computer-readable storage medium, on which a computer program or instructions are stored. When the computer program or instructions are executed by a processor, the method provided in the first aspect is implemented.

[0236] In a fifth aspect, an embodiment provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, the method provided in the first aspect is implemented.

[0237] It should be noted here that the description of the above storage medium, device, apparatus and program product embodiments is similar to the description of the above method embodiment and has similar beneficial effects as the method embodiment. For technical details not disclosed in the storage medium, device, apparatus and program product embodiments, please refer to the description of the method embodiment for understanding.

[0238] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment. The above-mentioned embodiment sequence numbers are for description only and do not represent the advantages and disadvantages of the embodiments.

[0239] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0240] In the several embodiments provided in this embodiment, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0241] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0242] In addition, all functional units in each embodiment may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0243] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0244] Alternatively, if the above-mentioned integrated unit is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods of each embodiment. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0245] The above are only embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the disclosed technical scope, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A distributed memory configuration method, characterized in that: The method is applied to a multi-core microcontroller unit (MCU) system, wherein the multi-core MCU system includes a global memory, a plurality of local memories, and a plurality of cores, wherein one local memory corresponds to one core, and the method includes: Acquire access information of at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by a first service; the access information is used to characterize the frequency of accessing the multiple cores when the target data segment is running; the first service is any service to be run in the MCU system; Based on the access information of the at least one target data segment, a target memory for storing each of the target data segments is configured in the global memory and the plurality of local memories.

2. The method according to claim 1, characterized in that The configuring, based on the access information of the at least one target data segment, a target memory for storing each of the target data segments in the global memory and the plurality of local memories comprises: In the access information of each of the target data segments, a total access frequency of each of the target data segments is determined; the total access frequency is used to represent the sum of the frequencies of the target data segment accessing each of the multiple cores; Determining the priority of each of the target data segments based on the total access frequency of each of the target data segments; According to the priority of each target data segment, a target memory for storing each target data segment is configured in the global memory and the plurality of local memories based on the access information of each target data segment.

3. The method according to claim 1, characterized in that: The configuring, based on the access information of the at least one target data segment, a target memory for storing each of the target data segments in the global memory and the plurality of local memories comprises: Determining an analysis result of each of the target data segments based on the access information of each of the target data segments; Based on the analysis result of each of the target data segments, configuring a target memory of the target data segment in the global memory and the plurality of local memories; The analysis result includes at least one of the following: a hot / cold type, a nucleation type, a sharing type, and a size type of the target data segment.

4. The method according to claim 3, characterized in that The step of determining the analysis result of each target data segment based on the access information of each target data segment comprises: Determining the total access frequency of the target data segment in the access information of the target data segment; If the access frequency is greater than or equal to the first threshold, the hot / cold type is determined to be hot; if the total access frequency is less than the first threshold, the hot / cold type is determined to be cold; and / or, Determining the single-core access frequency of the target data segment in the access information of the target data segment, and determining the core with the largest single-core access frequency as the core-friendly type; and / or, In the access information of the target data segment, determine the single-core access frequency of the target data segment, if there are multiple single-core access frequencies with non-zero values, determine the sharing type as inter-core sharing; if there is only one single-core access frequency with a non-zero value, determine the sharing type as non-inter-core sharing; and / or, In the access information of the target data segment, the data size of the target data segment is determined; if the data size is greater than or equal to a second threshold, the size type is determined to be a large block; if the data size is less than the second threshold, the size type is determined to be a small block.

5. The method according to claim 3, characterized in that: In a case where the analysis result includes a cold-hot type and a nucleophilic type, configuring a target memory of the target data segment in the global memory and the plurality of local memories based on the analysis result of each of the target data segments includes: If the heat-like type of the analysis result is heat, determining the target memory to be a local memory among the multiple local memories corresponding to the kernel pointed to by the nucleophilic type; If the cold / hot type of the analysis result is cold, the target memory is determined to be the global memory.

6. The method according to claim 3, characterized in that In a case where the analysis result includes a sharing type, configuring a target memory of the target data segment in the global memory and the plurality of local memories based on the analysis result of each of the target data segments includes: If the sharing type of the analysis result is inter-core sharing, determining that the target memory is the global memory; If the sharing type of the analysis result is non-inter-core sharing, it is determined that the target memory is a local memory of the multiple local memories.

7. The method according to claim 3, characterized in that In a case where the analysis result includes a size type, configuring a target memory of the target data segment in the global memory and the plurality of local memories based on the analysis result of each of the target data segments comprises: If the size type of the analysis result is large block, determining that the target memory is the global memory; If the size type of the analysis result is small block, the target memory is determined to be a local memory among the multiple local memories.

8. The method according to any one of claims 1 to 7, characterized in that: The obtaining access information of at least one target data segment includes: Running the first service in the multi-core MCU system; The frequency of each of the at least one target data segment accessing the multiple cores during the operation of the first service is collected within a first time period to obtain access information of the at least one target data segment.

9. The method according to any one of claims 1 to 7, characterized in that: The target data segment includes: a first data segment, a second data segment and a third data segment; Wherein, the first data segment includes initialized global variables and static variables; The second data segment includes: uninitialized global variables and static variables; The third data segment includes: local variables and function calls.

10. A distributed memory configuration device, characterized in that: The device is deployed in a multi-core microcontroller unit MCU system, the multi-core MCU system includes a global memory, multiple local memories, and multiple cores, one local memory corresponds to one core, and the device includes: an acquisition unit, configured to acquire access information of at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by a first service; the access information is used to characterize the frequency of accessing the multiple cores when the target data segment is running; the first service is any service to be run in the MCU system; A configuration unit is used to configure a target memory for storing each of the target data segments in the global memory and the multiple local memories based on the access information of the at least one target data segment.

11. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program or instructions, and when the processor executes the computer program or instructions, the method according to any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or an instruction, and when the processor executes the computer program or the instruction, the method according to any one of claims 1 to 9 is implemented.

13. A computer program product, characterized in that The computer program product includes a computer program or instructions, and when a processor executes the computer program or instructions, the method according to any one of claims 1 to 9 is implemented.

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