Display device

Abstract

The embodiment of the invention provides a display device which comprises a backlight assembly, a plurality of gate lines, a plurality of data lines, a power line and a plurality of sub-pixel circuits are arranged on the backlight assembly, each sub-pixel circuit comprises a pixel driving circuit and a light-emitting element, and in the pixel driving circuit, the light-emitting element is arranged on the pixel driving circuit. Comprising a first capacitor, and outputs a first light-emitting control signal from a second end of the first capacitor by using a control power supply signal obtained by a first end of the first capacitor and target light-emitting duration driving data stored in the first capacitor, in the process, the power line transmitting high level continuously transmits electric energy to the power line transmitting low level, the energy consumption generated in the light emitting duration regulation and control process is reduced, and the light intensity of the light emitting element is controlled. Therefore, the loss generated in the driving process of the light-emitting element is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technology, and in particular, to a display device. Background Art

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LEDs has developed rapidly and has become a research hotspot for display devices.

[0003] The pixel driving circuit of the micro LED can drive the micro LED to emit light through pulse width modulation (PWM) + pulse amplitude modulation (PAM), that is, the pixel driving circuit controls the conduction state of the PWM driving transistor according to the PWM signal and the changing ramp signal it obtains, so as to regulate the time when the pixel driving circuit generates the driving signal, that is, the light-emitting time of the micro transistor in each frame display cycle; and then determine the current value in the driving signal according to the PAM signal to determine the light intensity of the micro transistor during the light-emitting process, thereby determining the brightness of the micro LED in each frame display cycle.

[0004] However, in the circuit for pulse width modulation within the pixel driving circuit, two transistors are connected to both ends of the PWM driving transistor. When the luminous time is adjusted, the PWM driving transistor and the two transistors will be turned on at the same time, and the power line transmitting a high level will transmit an electrical signal to the power line transmitting a low level through the two turned-on transistors and the PWM driving transistor, resulting in high energy consumption when the luminous duration is adjusted by using the on-state of the PWM driving transistor. Summary of the invention

[0005] The present application provides a display device for solving the technical problem of high energy consumption when adjusting the light emission duration by using the on-state of a PWM driving transistor.

[0006] An embodiment of the present application provides a display device, including:

[0007] A backlight assembly, on which a plurality of gate lines, a plurality of data lines, a power supply line and a plurality of sub-pixel circuits are arranged;

[0008] Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element;

[0009] The pixel driving circuit comprises:

[0010] a light-emission duration control circuit, electrically connected to the power line and the data line, the light-emission duration control circuit comprising a first capacitor, and configured to output a first light-emission control signal from a second end of the first capacitor using a control power signal obtained at a first end of the first capacitor and target light-emission duration driving data stored in the first capacitor;

[0011] a light-emitting driving circuit electrically connected to the light-emitting duration control circuit, wherein the light-emitting driving circuit comprises a driving transistor configured to adjust the duration of the driving transistor generating the driving signal in each display cycle according to the first light-emitting control signal;

[0012] The light emitting element is electrically connected to the light emitting driving circuit and is configured to emit light according to the driving signal.

[0013] In the above technical solution, a pixel driving circuit is provided, including a light-emitting duration control circuit and a light-emitting driving circuit. After obtaining the target light-emitting duration driving data, the light-emitting duration control circuit adjusts the level of the first end of the first capacitor storing the target light-emitting duration driving data to correspond to the level state of the first light-emitting control signal generated by the second end, thereby in the process of driving the driving transistor electrically connected to the second end of the first capacitor in the light-emitting driving circuit, regulating the duration of the driving transistor generating the driving signal to regulate the light intensity of the light-emitting element. In the above process, there is no process in which a power line transmitting a high level continuously transmits electrical energy to a power line transmitting a low level, thereby reducing the energy consumption generated in the process of adjusting the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element.

[0014] In a feasible implementation manner, the light emission duration control circuit further includes a drive data writing unit:

[0015] The driving data writing unit is electrically connected to the data line and the second end of the first capacitor, and is configured to obtain original light-emitting duration driving data from the data line in each display cycle before the first end of the first capacitor obtains the control power signal, and store the target light-emitting duration driving data in the first capacitor according to the capacitance of the first capacitor;

[0016] The first end of the first capacitor is electrically connected to the power line and is configured to obtain the control power signal from the first end thereof and generate the first light-emitting control signal according to the control power signal and the target light-emitting duration driving data.

[0017] In a feasible implementation manner, the driving data writing unit includes a second capacitor and a fifth transistor;

[0018] The first end of the fifth transistor is electrically connected to the data line, the control end thereof is electrically connected to the gate line, and the second end thereof is electrically connected to the first end of the second capacitor, and is configured to obtain driving data from the first end thereof, obtain a third scanning signal from the control end thereof, control its conduction state by the third scanning signal, and output the driving data from the second end thereof when it is turned on; the driving data includes the original light emission duration driving data or the initialization driving data;

[0019] The second end of the second capacitor is electrically connected to the second end of the first capacitor, and is configured to obtain the original light-emitting duration driving data from its first end, and couple with the first capacitor to store the target light-emitting duration driving data.

[0020] In the above technical scheme, the light-emitting duration control circuit obtains the original light-emitting duration driving data through the fifth transistor, and stores the corresponding target light-emitting duration driving data according to the coupling effect of the first capacitor and the second capacitor. When generating the first light-emitting control signal, the level of the first end of the first capacitor is regulated. The first capacitor adjusts the level state of the target light-emitting duration driving data generated by its second end according to its coupling effect with other capacitors. In the above process, the conduction state of the driving transistor is controlled by adjusting the energy stored in the capacitor. Compared with controlling the conduction state of the driving transistor by regulating the on and off state of the PWM driving transistor electrically connected to the power line that transmits high and low levels, the energy loss generated during the conduction of the PWM driving transistor is saved, thereby reducing the loss generated during the driving process of the light-emitting element.

[0021] The display device provided in the embodiment of the present application includes a backlight assembly, on which a plurality of gate lines, a plurality of data lines, a power line and a plurality of sub-pixel circuits are arranged, each sub-pixel circuit includes a pixel driving circuit and a light-emitting element, in which a light-emitting duration control circuit including a first capacitor utilizes a control power signal obtained at the first end of the first capacitor and target light-emitting duration driving data stored in the first capacitor to output a first light-emitting control signal from the second end of the first capacitor to adjust the duration of the driving transistor in the light-emitting driving circuit to generate a driving signal in each display cycle, thereby controlling the light intensity of the light-emitting element, and in the above process, there is no process in which a power line transmitting a high level continuously transmits electrical energy to a power line transmitting a low level, thereby reducing the energy consumption generated in the process of regulating the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1This is an application scenario diagram of a display device provided by the present application according to an exemplary embodiment;

[0024] Figure 2 This is a schematic diagram of the structure of a display device provided according to an exemplary embodiment of the present application;

[0025] Figure 3 A schematic diagram of the structure of a display provided by the present application according to an exemplary embodiment;

[0026] Figure 4 A schematic diagram of the structure of a display provided according to another exemplary embodiment of the present application;

[0027] Figure 5 A circuit structure diagram of a conventional pixel driving circuit provided by the present application according to an exemplary embodiment;

[0028] Figure 6 This is a schematic structural diagram of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0029] Figure 7 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0030] Figure 8 This is a schematic structural diagram of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0031] Fig. 9 This is a driving signal timing diagram of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment.

[0032] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0033] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] It should be noted that, in this article, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, the parts, features, and elements with the same names in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment. It should be further understood that the terms "include", "comprise" indicate the existence of features, steps, operations, elements, components, projects, types, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, types, and / or groups.

[0035] In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0036] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] The display device provided in the embodiments of the present application may have various implementation forms, for example, it may be a smart TV, a laser projection device, a monitor, an electronic bulletin board, an electronic table, etc. Figure 1 This is a specific implementation of the display device of the present application.

[0038] Figure 1 is a schematic diagram of an operation scenario between a display device and a control device according to an embodiment, such as Figure 1As shown, the user can operate the display device 200 through the smart device 1003 or the control device 1005.

[0039] In some embodiments, the control device 1005 may be a remote controller, and the communication between the remote controller and the display device 200 includes infrared protocol communication or Bluetooth protocol communication, and other short-range communication methods, and the display device 200 is controlled wirelessly or wired. The user can input user commands through buttons on the remote controller, voice input, control panel input, etc. to control the display device 200.

[0040] In some embodiments, a smart device 1003 (such as a mobile terminal, a tablet computer, a computer, a laptop computer, etc.) may also be used to control the display device 200. For example, the display device 200 is controlled using an application running on the smart device.

[0041] In some embodiments, the display device 200 may not use the above-mentioned smart device or control device to receive instructions, but may receive user control through gestures or the like.

[0042] In some embodiments, the display device 200 can also be controlled in a manner other than the control device 1005 and the smart device 1003. For example, the user's voice command control can be directly received through a module for obtaining voice commands configured inside the display device 200, or the user's voice command control can be received through a voice control device set outside the display device 200.

[0043] In some embodiments, the display device 200 also communicates data with the server 1004. The display device 200 may be allowed to communicate via a local area network (LAN), a wireless local area network (WLAN), and other networks. The server 1004 may provide various content and interactions to the display device 200. The server 1004 may be a cluster or multiple clusters, and may include one or more types of servers.

[0044] Figure 2 A schematic diagram showing the structure of a display device in an example is shown in FIG. Figure 2 The display device 200 includes at least one of a tuner and demodulator 210 , a communicator 220 , a detector 230 , an external device interface 240 , a controller 250 , a display 260 , an audio output interface 270 , a memory 290 , a power supply 280 , and a user interface 291 .

[0045] In some embodiments, the controller includes a processor, a video processor, an audio processor, a graphics processor, a RAM, a ROM, and a first interface to an nth interface for input / output.

[0046] The display 260 includes a display screen component for presenting images, and a driving component for driving image display, which is used to receive image signals output from the controller, and display video content, image content, and menu control interface components and user control UI interface.

[0047] The display 260 may be a liquid crystal display, an OLED display, or a projection display, and may also be a projection device and a projection screen.

[0048] The communicator 220 is a component for communicating with an external device or server according to various communication protocol types. For example, the communicator may include at least one of a Wifi module, a Bluetooth module, a wired Ethernet module, and other network communication protocol chips or near field communication protocol chips, and an infrared receiver. The display device 200 can establish transmission and reception of control signals and data signals with the external control device 100 or the server 400 through the communicator 220.

[0049] The power supply 290 may be used to provide the controller 250 and its related components with the required power supply electrical signals.

[0050] The user interface 291 may be used to receive a control signal from the control device 100 (eg, an infrared remote controller, etc.).

[0051] The detector 230 is used to collect signals from the external environment or the external interaction. For example, the detector 230 includes a light receiver, a sensor for collecting the intensity of ambient light; or, the detector 230 includes an image collector, such as a camera, which can be used to collect external environment scenes, user attributes or user interaction gestures; or, the detector 230 includes a sound collector, such as a microphone, etc., for receiving external sounds.

[0052] The external device interface 240 may include, but is not limited to, any one or more of the following: a high-definition multimedia interface (HDMI), an analog or digital high-definition component input interface (component), a composite video input interface (CVBS), a USB input interface (USB), an RGB port, etc. It may also be a composite input / output interface formed by the above multiple interfaces.

[0053] The tuner-demodulator 210 receives broadcast television signals via wired or wireless reception, and demodulates audio and video signals, such as EPG data signals, from a plurality of wireless or wired broadcast television signals.

[0054] In some embodiments, the controller 250 and the tuner-demodulator 210 may be located in different separate devices, that is, the tuner-demodulator 210 may also be located in an external device of the main device where the controller 250 is located, such as an external set-top box.

[0055] The controller 250 controls the operation of the display device and responds to user operations through various software control programs stored in the memory 290. The controller 250 controls the overall operation of the display device 200. For example, in response to receiving a user command for selecting a UI object to be displayed on the display 260, the controller 250 can perform operations related to the object selected by the user command.

[0056] In some embodiments, the controller includes a central processing unit (CPU), a video processor, an audio processor, a graphics processing unit (GPU), RAM Random Access Memory (RAM), ROM (Read-Only Memory, ROM), a first interface to an nth interface for input / output, a communication bus (Bus), etc.

[0057] The user may input a user command through a graphical user interface (GUI) displayed on the display 260, and the user input interface receives the user input command through the graphical user interface (GUI). Alternatively, the user may input a user command through a specific sound or gesture, and the user input interface recognizes the sound or gesture through a sensor to receive the user input command.

[0058] "User interface" is the medium interface for interaction and information exchange between applications or operating systems and users. It realizes the conversion between the internal form of information and the form acceptable to users. The commonly used form of user interface is the Graphical User Interface (GUI), which refers to the user interface related to computer operation displayed in a graphical way. It can be an interface element such as an icon, window, control, etc. displayed on the display screen of an electronic device, where the control can include icons, buttons, menus, tabs, text boxes, dialog boxes, status bars, navigation bars, widgets, etc.

[0059] The display 260 includes a display panel and a backlight assembly configured to provide backlight.

[0060] The display panel is placed in front of the backlight assembly and includes a plurality of liquid crystal display units. The display panel drives and adjusts the state of its internal imaging structure according to the display data obtained, and displays the picture when the backlight is obtained. The display data is the data obtained from the main control system of the display.

[0061] The backlight assembly includes a diaphragm, a diffusion plate, a reflection plate, a lamp board and a back board from top to bottom, and micro diodes distributed in an array are arranged in the lamp board.

[0062] The circuit structure diagram of the backlight assembly and its control device is shown in Figure 3 As shown, the backlight assembly 40 includes a control circuit 250, a data driving circuit 20, a gate driving circuit 30, a backlight assembly 40, and a power supply circuit 280. The control circuit 250 and the data driving circuit 20 are electrically connected, the control circuit 250 and the gate driving circuit 30 are electrically connected, and the backlight assembly 40 and the data driving circuit 20, the gate driving circuit 30, and the power supply circuit 280 are electrically connected.

[0063] The backlight assembly 40 includes a display area AA where a plurality of pixel units 80 are arranged and a non-display area NA outside the display area. In the display area AA, a power line 90, a plurality of gate lines 60 and a plurality of data lines 50 are arranged. The plurality of pixel units 80 are arranged in an array in the display area AA, and each pixel unit 80 is located in an area where the gate line 60 and the data line 50 intersect.

[0064] The gate drive circuit 30 is electrically connected to the gate line 60. The gate drive circuit 30 is configured to obtain a clock signal and a trigger signal from the control circuit 250, and generate a gate drive signal based on the clock signal and the trigger signal, and transmit the gate drive signal to the corresponding pixel unit 80 through the gate line 60 to control the transistor in the pixel unit 80 to be turned on or off.

[0065] More specifically, the gate driver circuit 30 can be made into a separate gate driver integrated circuit (GDIC), and the gate driver circuit 30 can also be integrated in the backlight assembly. The way of integrating the gate driver circuit 30 in the backlight assembly is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the backlight assembly 40 through the COG process (Chip on Glass), and the GDIC can be electrically connected to the backlight assembly 40 through the COF process (Chipon Film). In the COF process, the component is electrically connected to the backlight assembly 40 through a flexible printed circuit (FPC).

[0066] The data driving circuit 20 is a circuit for driving the data line 50, and is configured to obtain display data from the control circuit 250, convert it into an analog data voltage (Vdata), and transmit the data analog voltage to the corresponding pixel unit 80 through the data line 50, so that the light-emitting element 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the light-emitting brightness of the light-emitting element 813.

[0067] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0068] The power circuit 280 is a circuit for providing stable electrical signals, and is configured to provide corresponding required power signals to the backlight assembly 40 , the control circuit 250 , the data driving circuit 20 , and the gate driving circuit 30 .

[0069] In one case, each pixel unit 80 includes three sub-pixel circuits 810, which are respectively used to display red light, blue light, and green light. In another case, each pixel unit 80 includes four sub-pixel circuits 810, which are respectively used to display red light, blue light, green light, and white light. This is not specifically limited here.

[0070] The luminous color of each pixel unit 80 is determined by the properties of the luminous element 813. The luminous element 813 can be any luminous device, including but not limited to OLED and micro LED.

[0071] Micro LED refers to a micro light emitting body made of inorganic semiconductor layers. Micro LEDs can generally include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, such as vertical, horizontal, flip-chip, etc., and is not particularly limited to a specific structure.

[0072] More specifically, if Figure 4 As shown, a sub-pixel circuit 810 includes a pixel driving circuit 814 and a light-emitting element 813. The pixel driving circuit 814 is electrically connected to the light-emitting element 813, and the pixel driving circuit 814 is configured to drive the light-emitting element 813 to emit light. The signals required by the pixel driving circuit 814 include a driving signal, a scanning signal (Scan), and an emission control signal (Emission, referred to as: EM control signal).

[0073] The driving signal may be generated by the control circuit 250 or obtained from the outside. It includes but is not limited to a start pulse signal, a clock signal, and an enable signal. The light-emitting control signal may be a global signal provided by the control circuit 250 or a signal generated by the gate drive circuit 30, which is not specifically limited here. The scanning signal is a successive displacement signal generated by the gate drive circuit 30.

[0074] If the EM control signal is a global signal generated by the control circuit 250 , the gate driving circuit 30 obtains the EM control signal from the control circuit 250 , and transmits the EM control signal to the corresponding pixel driving circuit 814 through the gate line 60 .

[0075] If both the EM control signal and the scan signal are generated by the gate driving circuit 30, the gate driving circuit 30 includes a scan signal generating circuit 301 and an EM control signal generating circuit 302. The scan signal generating circuit 301 outputs the scan signal, and the EM control signal generating circuit 302 outputs the EM control signal.

[0076] Figure 5 It is a circuit structure diagram of a traditional pixel driving circuit provided in the present application according to an exemplary embodiment, including a PWM driving circuit 803 and a PAM driving circuit 804 .

[0077] The PWM driving circuit 803 is configured to obtain the lighting duration driving data PWMD and the control power signal SWEEP, and adjust the level of the first lighting control signal generated by it according to the lighting duration driving data PWMD and the control power signal SWEEP, and the level of the lighting control signal is the first level or the second level.

[0078] The PAM driving circuit 804 is electrically connected to the PWM driving circuit 803 and the light emitting element LED, and is configured to obtain the first light emitting control signal and the current brightness driving data PAMD, and generate a driving signal according to the first light emitting control signal and the current brightness driving data PAMD to drive the light emitting element LED to emit light. The first light emitting control signal is used to adjust the light emitting time of the light emitting element LED, and the current brightness driving data PAMD is used to adjust the magnitude of the current passing through the light emitting element LED.

[0079] The PWM driving circuit 803 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a first capacitor C1 .

[0080] The circuit structure and principle of the PWM driving circuit 803 are explained below based on the case where all transistors in the conventional pixel driving circuit are N-type transistors.

[0081] The first transistor T1 has a first terminal electrically connected to the power line 90, a control terminal electrically connected to the gate line 60, and is configured to obtain an initialization signal RESET from its control terminal, obtain a reference power signal REF from its first terminal, and be turned on when the initialization signal RESET is at a high level, and output the reference power signal REF from its second terminal. The reference power signal REF is a high level signal.

[0082] The first end of the third transistor T3 is electrically connected to the data line 50, and the control end is electrically connected to the gate line 60. The third transistor T3 is configured to obtain a scan signal SN from its control end, obtain a light-emitting duration driving data PWMD from its first end, turn on when the scan signal SN is at a high level, and output the light-emitting duration driving data PWMD from its second end.

[0083] The control end of the sixth transistor T6 is electrically connected to the second end of the first transistor T1, and the first end is electrically connected to the second end of the third transistor T3, and is configured to be turned on when its control end obtains a high level, and when its control end and the second end are short-circuited, and when its first end obtains the light-emitting duration driving data PWMD, the light-emitting duration driving data after threshold voltage compensation is determined from its control end.

[0084] The control end of the second transistor T2 is electrically connected to the gate line 60, the first end is electrically connected to the control end of the sixth transistor T6, and the second end is electrically connected to the second end of the sixth transistor T6. The second transistor T2 is configured to obtain a scan signal SN from its control end, and is turned on when the scan signal SN is at a high level, so as to short-circuit the control end and the second end of the sixth transistor T6.

[0085] The first end of the first capacitor C1 is electrically connected to the power line 90, and the second end is electrically connected to the control end of the sixth transistor T6. The first capacitor C1 is configured such that its first end obtains the control power signal SWEEP from the power line 90, and the second end is used to store the threshold voltage compensated light-emitting duration driving data generated by the control end of the sixth transistor T6, and is also used to follow the voltage change of its first end to adjust the voltage value of its second end.

[0086] The fourth transistor T4 has a first end electrically connected to the power line 90, a second end electrically connected to the first end of the sixth transistor T6, and a control end electrically connected to the gate line 60. The fourth transistor T4 is configured to obtain a low-level power signal VGL from its first end, obtain a second light-emitting control signal EM1 from its control end, turn on when the second light-emitting control signal EM1 is at a high level, and transmit the power signal VGL obtained at its first end to the first end of the sixth transistor T6.

[0087] The first end of the fifth transistor T5 is electrically connected to the second end of the sixth transistor T6, the second end is electrically connected to the power line 90, and the control end is electrically connected to the gate line 60. It is configured to obtain a high-level reference power signal REF from its second end, obtain a second light-emitting control signal EM1 from its control end, turn on when the second light-emitting control signal EM1 is at a high level, and transmit the reference power signal REF obtained at its first end to the second end.

[0088] The sixth transistor T6 is also configured to be turned on when the electrical signal generated at the second end of the first capacitor C1 obtained at its control end is greater than a preset threshold when its control end and its second end are disconnected, and to be turned off when the electrical signal generated at the second end of the first capacitor C1 obtained at its control end is less than the preset threshold.

[0089] When the sixth transistor T6 is turned on, since the size of the sixth transistor T6 is larger than the fifth transistor T5, the potential value of its second end is determined by the electrical signal obtained at its first end, which is a low level; when the sixth transistor T6 is turned off, the potential value of the second end of the sixth transistor T6 is determined by the fifth transistor T5 electrically connected to this point, which is a high level.

[0090] The PAM driving circuit 804 adjusts the time period for generating the driving signal according to the level state provided by the second end of the sixth transistor T6, that is, when the second end of the sixth transistor T6 is at a high level, it stops generating the driving signal, and the light-emitting element LED does not emit light; when the first end of the sixth transistor T6 is at a low level, it generates the driving signal, and the light-emitting element LED emits light.

[0091] Since when the sixth transistor T6 is turned on, the fifth transistor T5 and the fourth transistor T4 are also turned on, the power line providing the reference power signal REF transmits the electrical signal to the power line providing the power signal VGL through the turned-on fifth transistor T5, the sixth transistor T6 and the fourth transistor T4, and a cross-charging phenomenon occurs in the sixth transistor T6, consuming a large amount of power.

[0092] In order to solve the above problems, the present application provides a display device to solve the technical problem of high energy consumption when adjusting the light-emitting duration by using the conduction state of a PWM driving transistor. The technical concept of the present application is to provide a pixel driving circuit, including a light-emitting duration control circuit and a light-emitting driving circuit. After obtaining the target light-emitting duration driving data, the light-emitting duration control circuit adjusts the level of the first end of the first capacitor storing the target light-emitting duration driving data to correspond to the level state of the first light-emitting control signal generated by the second end, thereby in the process of driving the driving transistor electrically connected to the second end of the first capacitor in the light-emitting driving circuit, adjusting the duration of the driving transistor to generate the driving signal to adjust the light intensity of the light-emitting element. In the above process, there is no process in which the power line transmitting a high level continuously transmits electrical energy to the power line transmitting a low level, thereby reducing the energy consumption generated in the process of adjusting the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element.

[0093] The pixel driving circuit proposed in this application is explained in detail below. Figure 6 The schematic diagram of the structure of a pixel driving circuit provided by the present application according to an exemplary embodiment is shown in FIG.

[0094] like Figure 6 As shown, the pixel driving circuit provided in the present application includes a light emitting duration control circuit 901 and a light emitting driving circuit 902 .

[0095] The luminous duration control circuit 901 is electrically connected to the power line 90 and the data line 50. The luminous duration control circuit includes a first capacitor C1, and is configured to utilize the control power signal SWEEP obtained at the first end of the first capacitor C1 and the target luminous duration driving data stored in the first capacitor to output a first luminous control signal from the second end (point A) of the first capacitor C1.

[0096] The light-emitting driving circuit 902 is electrically connected to the light-emitting control circuit 901 . The light-emitting driving circuit 902 includes a driving transistor T2 , and is configured to adjust the duration of the driving transistor T2 generating the driving signal in each display period according to the first light-emitting control signal.

[0097] The light emitting element LED is electrically connected to the light emitting driving circuit 902 and is configured to emit light according to a driving signal.

[0098] In the above technical scheme, after obtaining the target light-emitting duration driving data, the light-emitting duration control circuit adjusts the level of the first end of the first capacitor storing the target light-emitting duration driving data to correspond to the level state of the first light-emitting control signal generated by the second end, thereby in the process of driving the driving transistor electrically connected to the second end of the first capacitor in the light-emitting driving circuit, regulating the duration of the driving transistor generating the driving signal to regulate the light intensity of the light-emitting element. In the above process, there is no process in which the power line transmitting a high level continuously transmits electrical energy to the power line transmitting a low level, thereby reducing the energy consumption generated in the process of controlling the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element.

[0099] The light-emitting duration control circuit 901 includes a driving data writing unit 903 and a first capacitor C1.

[0100] The first end of the first capacitor C1 is electrically connected to the power line 90, and the second end is electrically connected to the drive data writing unit 903 through point A. It is configured to obtain a control power signal SWEEP from its first end, and generate a first light-emitting control signal according to the control power signal SWEEP and the target light-emitting duration drive data stored therein.

[0101] The potential value of the first light emitting control signal generated by the second end of the first capacitor C1 increases with the increase of the potential value of the control power signal SWEEP obtained by the first end thereof, and decreases with the decrease of the potential value of the control power signal SWEEP obtained by the first end thereof.

[0102] When the second end of the first capacitor C1 is electrically connected to other capacitors, when the potential value of the control power signal SWEEP obtained at the first end thereof changes, the first capacitor C1 will couple with other capacitors to adjust the potential value of point A.

[0103] The first end of the driving data writing unit 903 is electrically connected to the data line 50, and the second end thereof is electrically connected to the second end of the first capacitor C1 at point A. It is configured to obtain the original light-emitting duration driving data PWMD from the data line 50 in each display cycle before the first end of the first capacitor C1 obtains the control power signal SWEEP, and store the target light-emitting duration driving data in the first capacitor C1 through point A according to the capacitance of the first capacitor C1.

[0104] The driving data writing unit 903 includes a second capacitor C2 and a fifth transistor T5.

[0105] The first end of the fifth transistor T5 is electrically connected to the data line 50, the control end thereof is electrically connected to the gate line 60, and the second end thereof is electrically connected to the first end of the second capacitor C2. The fifth transistor T5 is configured to obtain the driving data PWMD from its first end and the third scanning signal S3 from its control end, and its conduction state is controlled by the third scanning signal S3.

[0106] The fifth transistor T5 is turned on when the third scanning signal S3 is at a low level, and outputs the driving data PWMD from its second end; it is turned off when the third scanning signal S3 is at a high level, and keeps the potential value of the first end of the second capacitor C2 unchanged. The driving data includes the original light-emitting duration driving data or the initialization driving data.

[0107] The second end of the second capacitor C2 is electrically connected to the second end of the first capacitor C1, and is configured to initialize its first end when obtaining initialization driving data from its first end; when obtaining original light-emitting duration driving data PWMD from its first end, it is coupled with the first capacitor C1 to store target light-emitting duration driving data.

[0108] Among them, the second capacitor C2 allocates the electric energy change generated when the original light-emitting duration driving data PWMD is transmitted compared with the initialization driving data according to its capacitance value and the capacitance value of the first capacitor C1 and the capacitance value of other capacitors electrically connected to point A, so that the first capacitor C1 stores the target light-emitting duration driving data.

[0109] In the above technical scheme, the light-emitting duration control circuit obtains the original light-emitting duration driving data through the fifth transistor, and stores the corresponding target light-emitting duration driving data according to the coupling effect of the first capacitor and the second capacitor. When generating the first light-emitting control signal, the level of the first end of the first capacitor is regulated. The first capacitor adjusts the level state of the target light-emitting duration driving data generated by its second end according to its coupling effect with other capacitors. In the above process, the conduction state of the driving transistor is controlled by adjusting the energy stored in the capacitor. Compared with controlling the conduction state of the driving transistor by regulating the on and off state of the PWM driving transistor electrically connected to the power line that transmits high and low levels, the energy loss generated during the conduction of the PWM driving transistor is saved, thereby reducing the loss generated during the driving process of the light-emitting element.

[0110] The light-emitting driving circuit 902 includes a light-emitting control circuit 906 , a light-emitting threshold compensation circuit 905 and a reset circuit 904 .

[0111] The first end of the reset circuit 904 is electrically connected to the power line 90, and the second end thereof is electrically connected to the luminescence threshold compensation circuit 905 and the second end of the first capacitor C1 through point D. The reset circuit 904 is configured to obtain a reference power signal REF from the power line 90 at its first end before the compensation stage, and transmit the reference power signal REF to the luminescence threshold compensation circuit 905 and the second end of the first capacitor C1 when it is turned on, to perform a reset operation, so that the potential value of the second end of the first capacitor C1 and the potential value of the device terminal electrically connected to point D in the luminescence threshold compensation circuit 905 are adjusted to the same low level as the reference power signal REF.

[0112] The control end of the luminous threshold compensation circuit 905 is electrically connected to the second end of the first capacitor C1 through point D, its first end is electrically connected to the third end of the luminous control circuit 906 through point C, its second end is electrically connected to the fourth end of the luminous control circuit 906 through point E, and its power supply end is electrically connected to the power line 90 through point B.

[0113] The luminous threshold compensation circuit 905 is configured to obtain a first power supply signal VDD from its power supply end and its first end respectively during the compensation stage, store the threshold voltage of the driving transistor T2 according to the first power supply signal VDD, and generate and transmit a driving signal to the luminous control circuit 906 according to the stored threshold voltage and the first luminous control signal during the display stage.

[0114] The first end of the light-emitting control circuit 906 is electrically connected to the power line 90 through point B, the second end thereof is electrically connected to the light-emitting element LED through point F, the third end thereof is electrically connected to the light-emitting threshold compensation circuit 905 through point C, and the fourth end thereof is electrically connected to the light-emitting threshold compensation circuit 905 through point E.

[0115] The light-emitting control circuit 906 is configured to obtain a first power signal VDD from the power line 90 at its first end, output the first power signal from its third end to the light-emitting threshold compensation circuit 905 during the compensation phase and the display phase of the display cycle, and transmit the drive signal generated by the light-emitting threshold compensation circuit 905 obtained at its fourth end during the display phase to the light-emitting element LED from its second end to drive the light-emitting element LED to emit light.

[0116] The reset circuit 904 includes a first transistor T1 .

[0117] The first end of the first transistor T1 is electrically connected to the power line 90, the control end thereof is electrically connected to the gate line 60, the second end thereof is electrically connected to the second end of the first capacitor C1, the second end of the second capacitor C2, the second end of the third capacitor C3, and the control end of the driving transistor T2, and is configured to obtain the first scanning signal S1 from its control end and obtain the reference power signal REF from its first end, and its conduction state is controlled by the first scanning signal S1.

[0118] The first transistor T1 is turned on when the first scan signal S1 is at a low level, and outputs a reference power signal REF from its second end for resetting the device electrically connected to the second end; it is turned off when the first scan signal S1 is at a high level, and stops outputting the reference power signal REF.

[0119] The light emitting control circuit 906 includes a fourth transistor T4 and a sixth transistor T6.

[0120] The first end of the fourth transistor T4 serves as the first end of the light emitting control circuit 906, and the second end thereof serves as the third end of the light emitting control circuit 906. The control end thereof is electrically connected to the gate line 60, and is configured to obtain the first power supply signal VDD from the first end thereof and the second light emitting control signal EM1 from the control end thereof, and the conduction state thereof is controlled by the second light emitting control signal EM1.

[0121] The fourth transistor T4 is turned on when the second light emitting control signal EM1 is at a low level, and outputs the first power signal VDD from its second end; and is turned off when the second light emitting control signal EM1 is at a high level, and stops the transmission of the first power signal VDD.

[0122] The first end of the sixth transistor T6 serves as the fourth end of the light-emitting control circuit 906, and the second end thereof serves as the second end of the light-emitting control circuit 906. The control end thereof is electrically connected to the gate line 60, and is configured to obtain the third light-emitting control signal EM2 from the control end thereof, and the conduction state thereof is controlled by the third light-emitting control signal EM2.

[0123] The sixth transistor T6 is turned on when the third light emitting control signal EM2 is at a low level. When a driving signal is obtained at its first end, the driving signal is transmitted from its second end to the positive electrode of the light emitting element LED, so that the light emitting element LED emits light according to the driving signal.

[0124] The light emission threshold compensation circuit 905 includes: a third capacitor C3, a driving transistor T2 and a third transistor T3.

[0125] The first end of the third transistor T3 serves as the control end of the light-emitting threshold compensation circuit 905 and is electrically connected to the control end of the driving transistor T2. The control end is electrically connected to the gate line 60. The second end of the third transistor T3 serves as the second end of the light-emitting threshold compensation circuit 905 and is electrically connected to the second end of the driving transistor T2. The third transistor T3 is configured to obtain the second scanning signal S2 from its control end, and its conduction state is controlled by the second scanning signal.

[0126] The third transistor T3 is turned on when the second scanning signal S2 is at a low level, short-circuiting the control terminal and the second terminal of the driving transistor T2; and is turned off when the second scanning signal S2 is at a high level, disconnecting the control terminal and the second terminal of the driving transistor T2.

[0127] The first end of the driving transistor T2 is used as the first end of the light emitting threshold compensation circuit 905, and is configured to be short-circuited between its control end and its second end, and when its first end obtains the first power supply signal VDD transmitted by the fourth transistor T4, the first power supply signal compensated by its threshold voltage is output from its control end, and the voltage value is V A =V VDD +V th , where V A represents the potential value of point A, that is, the potential value of the control terminal of the driving transistor T2, V VDD represents the potential value of the first power signal VDD, V th represents the threshold voltage of the driving transistor T2.

[0128] The driving transistor T2 is further configured to control its conduction state by an electrical signal obtained from its control terminal when the control terminal and the second terminal are disconnected.

[0129] The driving transistor T2 is turned on to generate a driving signal when the voltage value of the electrical signal obtained at its control end is within a preset voltage range; it is turned off to stop generating the driving signal when the voltage value of the electrical signal obtained at its control end is not within the preset voltage range.

[0130] The third capacitor C3 has a first end electrically connected to the power line 90 and a second end electrically connected to the control end of the driving transistor T2. The third capacitor C3 is configured to obtain a first power signal VDD from its first end and adjust the stored data according to the electrical signal obtained at its second end.

[0131] The third capacitor C3 is configured to maintain a reference power signal REF for resetting at its second terminal when the first transistor T1 is turned on, so that the control terminal of the driving transistor T2 can continuously obtain the low-level reference power signal REF and maintain the turned-on state.

[0132] The third capacitor C3 is further configured to obtain the threshold voltage compensated first power signal generated by the control terminal of the driving transistor T2 at its second terminal, and determine the voltage difference between its two terminals as the threshold voltage VDD of the driving transistor T2 according to the first power signal VDD obtained at its first terminal. th , and stores the threshold voltage.

[0133] Since the second end of the third capacitor C3 is also electrically connected to the second end of the first capacitor C1 and the second end of the second capacitor C2, after the driving transistor T2 generates the first power supply signal for threshold voltage compensation, when the first end of the second capacitor C2 obtains the original light-emitting duration driving data PWMD, the first capacitor C1, the second capacitor C2 and the third capacitor C3 are coupled to adjust the stored electric energy, and the potential value of point A is changed: Among them, ▲V PWMD represents the potential difference between the initialization driving data and the original light-emitting duration driving data, c1 represents the capacitance of the first capacitor, c2 represents the capacitance of the second capacitor C2, and c3 represents the capacitance of the third capacitor C3.

[0134] In the above technical solution, the pixel driving circuit not only utilizes the change of the potential value at both ends of the first capacitor to regulate the conduction time of the driving transistor in the process of controlling the conduction of the driving transistor, but also replaces the function of the transistor for regulating the change of the potential value, thereby saving the power consumption of the transistor used for regulation. At the same time, compared with the traditional pixel driving circuit, the above pixel driving circuit simplifies the circuit structure, reduces the use of transistors, saves the area occupied by the pixel circuit in the backlight assembly, and can effectively improve the pixel density and panel resolution.

[0135] Figure 6 The circuit structure shown is composed of Figure 7 Drive according to the driving signal timing diagram shown.

[0136] Below Figure 6 The circuit structure shown is explained by the circuit operation in a display cycle. A display cycle T includes a reset phase T1, a compensation phase T2, a data writing phase T3 and a display phase T4 in sequence.

[0137] In the period corresponding to the reset phase T1 in the driving signal timing diagram, the first scanning signal S1 and the third scanning signal S3 are at a low level, the second scanning signal S2, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a high level, and the reference power signal REF is at a low level. The control power signal SWEEP is adjusted from a low level to a high level, and the driving data is the initialization driving data.

[0138] Since the first scanning signal S1 is at a low level, the first transistor T1 is turned on, and the reference power signal REF obtained at the first end thereof is transmitted to the D point.

[0139] Since the second light emitting control signal EM1 is at a high level, the fourth transistor T4 is turned off and cannot transmit the first power signal VDD to the driving transistor T2.

[0140] Since the reference power signal REF is at a low level, the signal obtained by the control terminal of the driving transistor T2 is at a low level, and the driving transistor T2 is turned on; since the first terminal of the driving transistor T2 does not obtain the first power signal VDD, the driving transistor T2 does not generate a driving signal.

[0141] In addition, the second end of the third capacitor C3, the second end of the first capacitor C1 and the second end of the second capacitor C2 follow the signal obtained at point D and adjust the potential to initialize their second ends, wherein the adjusted potential value is the same as the potential value of the reference power supply signal REF.

[0142] During the process of adjusting the potential value of the second end of the first capacitor C1, the control power signal SWEEP obtained by the first end thereof is adjusted from a low level to a high level, so as to prepare for the level change according to the ramp signal during the display stage T4, thereby avoiding affecting the accuracy of the data stored at the second end when adjusting the level of the first end in the compensation stage T2 and the data writing stage T3.

[0143] Since the third scanning signal S3 is at a low level, the fifth transistor T5 is turned on and transmits the initialization driving data obtained at its first end to the first end of the second capacitor C2, so that the second capacitor C2 adjusts the potential of its first end to the same potential as the initialization driving data according to the initialization driving data, thereby achieving initialization.

[0144] The level of the initialization driving data is data of a preset level transmitted by the data line 50 , for example, 0V.

[0145] During the period corresponding to the compensation phase T2 in the driving signal timing diagram, the second scanning signal S2 and the second light-emitting control signal EM1 are at low levels, and the first scanning signal S1, the third scanning signal S3, the third light-emitting control signal EM2 and the control power signal SWEEP are at high levels.

[0146] Since the first scanning signal S1 is at a high level, the first transistor T1 is turned off and stops transmitting the reference power signal REF to each capacitor.

[0147] Since the second light emitting control signal EM1 is at a low level, the fourth transistor T4 is turned on, and the first power signal VDD obtained at the first end thereof is transmitted to the first end of the driving transistor T2.

[0148] Since the second scanning signal S2 is at a low level, the third transistor T3 is turned on, and the control terminal and the second terminal of the driving transistor T2 are short-circuited.

[0149] Since the control terminal and the second terminal of the driving transistor T2 are short-circuited, and the first terminal thereof obtains the first power supply signal VDD, the potential value obtained from the control terminal thereof is V DD +V th , then the potential value of the second end of each capacitor is adjusted to V DD +V th .

[0150] In the period corresponding to the data writing phase T3 in the driving signal timing diagram, the third scanning signal S3 is at a low level, and the first scanning signal S1, the second scanning signal S2, the second light-emitting control signal EM1, the third light-emitting control signal EM2 and the control power supply signal SWEEP are at a high level.

[0151] Since the second light emitting control signal EM1 is at a high level, the fourth transistor T4 is turned off, and stops transmitting the first power signal VDD obtained at its first end to the first end of the driving transistor T2.

[0152] Since the second scanning signal S2 is at a high level, the third transistor T3 is turned off, and the control terminal and the second terminal of the driving transistor T2 are disconnected.

[0153] Since the electric signal obtained by the control terminal of the driving transistor T2 is the electric signal stored in the capacitor (V DD +V th ), the signal is at a high level, and the driving transistor T2 is turned off.

[0154] Since the third scan signal S3 is at a low level, the fifth transistor T5 is turned on, and transmits the driving data obtained at its first end to the first end of the third capacitor C3.

[0155] The data writing phase T3 can be further divided into: a first data writing sub-phase and a second data writing sub-phase.

[0156] In the first data writing sub-phase, the driving data obtained by the first end of the third capacitor C3 is still the initialization driving data. In the second data writing sub-phase, the first end of the third capacitor C3 obtains the original light emission duration driving data.

[0157] In the second data writing sub-phase, according to the coupling effect of each capacitor, the potential value of the second end of the third capacitor C3 is adjusted to Among them, ▲V PWMD Represents the difference between the initialization driving data and the original luminous duration driving data, V A Indicates the target light emitting duration driving data stored at the second end of the first capacitor C1.

[0158] The potential value obtained by the control terminal of the driving transistor T2 changes with the potential value of the second terminal of the third capacitor C3. If the voltage level is still high, the driving transistor T2 remains in the off state.

[0159] It is worth noting that at the end of the second data writing sub-stage, before the fifth transistor T5 is turned off, the first end of the third capacitor C3 still maintains the state of receiving the original light-emitting duration driving data. After the fifth transistor T5 is turned off, the transmission of the original light-emitting duration driving data is stopped to ensure the accuracy of the target light-emitting duration driving data obtained by coupling the second ends of each capacitor.

[0160] After entering the display phase, the data line 50 continues to transmit the original light-emitting duration driving data for a period of time and then jumps back to the state of transmitting the initialization driving data. The duration of the data line 50 transmitting the original light-emitting duration driving data in the display phase is the same as the duration of the data line 50 transmitting the initialization driving data in the data writing phase, so that the clock signal used by the data line 50 when transmitting the driving data is the same as the clock signal used by the gate line 50 when transmitting the scanning signal, thereby ensuring a simple structure of the driving circuit.

[0161] In the driving signal timing diagram, during the time period corresponding to stage T4, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a low level, the first scanning signal S1, the second scanning signal S2 and the third scanning signal S3 are at a high level, and the control power signal SWEEP is a ramp signal adjusted from a high level to a low level.

[0162] Since the second light emitting control signal EM1 is at a low level, the fourth transistor T4 is turned on, and the first power signal VDD obtained at the first end thereof is transmitted to the first end of the driving transistor T2.

[0163] Since the second scanning signal S2 is at a high level, the third transistor T3 is turned off, the control terminal and the second terminal of the driving transistor T2 are disconnected, and the driving transistor T2 adjusts its conduction state according to the level state of the electrical signal obtained at its control terminal.

[0164] Since the control power signal SWEEP is a ramp signal adjusted from a high level to a low level, the potential value of the first light emitting control signal generated at the second end of the first capacitor C1 decreases as the potential value of the first end decreases.

[0165] The potential value of the second end of the first capacitor C1 is determined according to the coupling effect of each capacitor and the potential change value of the first end thereof: Where, ΔV A represents the potential change at the second end of the first capacitor C1, ΔV SWEEP represents the potential change of the control power signal SWEEP obtained by the first end of the first capacitor C1, c1 represents the capacitance of the first capacitor C1, c2 represents the capacitance of the first capacitor C2, and c3 represents the capacitance of the first capacitor C3.

[0166] According to the change of the potential value of the second end of the first capacitor C1 and the turn-on voltage range of the driving transistor T2, the display stage T4 is divided into a non-light-emitting stage and a light-emitting stage.

[0167] In the non-light-emitting stage, when the potential value of the second end of the first capacitor C1 continues to decrease but is still not within the preset voltage range corresponding to the driving transistor T2 being turned on, the driving transistor T2 remains in the off state. In this embodiment, the potential value of the second end of the first capacitor C1 is not within the preset voltage range corresponding to the driving transistor T2 being turned on, indicating that the potential value of the second end of the first capacitor C1 is greater than the first turn-on preset voltage threshold.

[0168] In the light-emitting stage, when the potential value of the second end of the first capacitor C1 continues to decrease and is within the driving voltage range corresponding to the driving transistor T2 being turned on, the driving transistor T2 is turned on, and a driving signal is generated according to the first power signal VDD obtained at its first end, the potential value obtained at its control end and its threshold voltage, which is Right now In this embodiment, the potential value of the second end of the first capacitor C1 is within the preset voltage range corresponding to the conduction of the driving transistor T2, which means that the potential value of the second end of the first capacitor C1 is less than or equal to the first conduction preset voltage threshold.

[0169] Since the third light-emitting control signal EM2 is at a low level, the sixth transistor T6 is turned on. In the non-light-emitting stage, its first end does not obtain the driving signal transmitted by the driving transistor T2, and the driving signal cannot be transmitted to the light-emitting element LED, and the light-emitting element LED does not emit light; in the light-emitting stage, the sixth transistor T6 transmits the driving signal obtained at its first end to the positive electrode of the light-emitting element LED, and the light-emitting element LED emits light.

[0170] Figure 8 Schematic diagram of the structure of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment, in which each transistor in the pixel driving circuit is an N-type transistor. Figure 6The circuit structure shown is Figure 8 The circuit structure shown is briefly explained.

[0171] Compared to Figure 6 The circuit structure shown is different in that:

[0172] Each transistor is turned on when a high level is obtained and turned off when a low level is obtained;

[0173] The reference power signal REF obtained by the first end of the first transistor T1 from the power line 90 is a high level signal, the first end of the fourth transistor T4 and the first end of the third capacitor C3 obtain the first power signal VSS from the power line 90 as a low level signal, the second end of the sixth transistor T6 is electrically connected to the cathode of the light-emitting element LED, and the light-emitting element LED obtains the second power signal VDD at its anode and emits light when its cathode obtains the driving signal transmitted by the sixth transistor T6.

[0174] Other circuit connections and Figure 6 The circuit structure shown is the same and will not be repeated here.

[0175] Figure 8 The circuit structure shown is composed of Fig. 9 Drive according to the driving signal timing diagram shown.

[0176] In the period corresponding to the reset phase T1 in the driving signal timing diagram, the first scanning signal S1 and the third scanning signal S3 are at a high level, the second scanning signal S2, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a low level, and the reference power signal REF is at a high level. The control power signal SWEEP is adjusted from a high level to a low level.

[0177] The first transistor T1 is turned on according to the first scanning signal S1, and transmits the reference power signal REF obtained at its first end to the second end of each capacitor and the control end of the driving transistor T2, so as to reset the second end of each capacitor and control the driving transistor T2 to turn on.

[0178] The fifth transistor T5 is turned on according to the third scanning signal S3, and transmits the initialization driving data obtained at the first end thereof to the first end of the second capacitor C2, so as to reset the first end of the second capacitor C2.

[0179] During the period corresponding to the compensation phase T2 in the driving signal timing diagram, the second scanning signal S2 and the second light-emitting control signal EM1 are at high levels, and the first scanning signal S1, the third scanning signal S3, the third light-emitting control signal EM2 and the control power signal SWEEP are at low levels.

[0180] The fourth transistor T4 is turned on according to the second light emitting control signal EM1 , and transmits the first power signal VSS obtained at the first end thereof to the first end of the driving transistor T2 .

[0181] The third transistor T3 is turned on according to the second scanning signal S2, and the second end and the control end of the driving transistor T2 are short-circuited, so that the driving transistor T2 determines the first power signal VSS+Vth after threshold voltage compensation from its control end according to the first power signal VSS obtained at its first end, and stores the compensated first power signal at the second end of each capacitor, wherein Vth is the threshold voltage of the driving transistor T2.

[0182] In the period corresponding to the data writing phase T3 in the driving signal timing diagram, the third scanning signal S3 is at a high level, and the first scanning signal S1, the second scanning signal S2, the second light-emitting control signal EM1, the third light-emitting control signal EM2 and the control power supply signal SWEEP are at a low level.

[0183] The fifth transistor T5 is turned on according to the third scanning signal S3, and the original light-emitting duration driving data obtained at its first end is transmitted to the first end of the third capacitor C3. The third capacitor C3 combines with other capacitors to couple the driving data obtained at its first end, and stores the target light-emitting duration driving data at the second end of each capacitor.

[0184] Since the control end of the driving transistor T2 is electrically connected to the second end of each capacitor, the driving data is turned off according to the above determined target light emitting duration.

[0185] In the driving signal timing diagram, during the time period corresponding to stage T4, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a high level, the first scanning signal S1, the second scanning signal S2 and the third scanning signal S3 are at a low level, and the control power signal SWEEP is a ramp signal adjusted from a low level to a high level.

[0186] The fourth transistor T4 is turned on according to the second light emitting control signal EM2, and transmits the first power signal VSS obtained at the first end thereof to the first end of the driving transistor T2.

[0187] The second end of the first capacitor C1 follows the change of the control power signal SWEEP obtained at the first end thereof to adjust the potential value of the first light emitting control signal outputted by it, which is:

[0188] When the potential value of the first light emitting control signal is smaller than the second on-preset voltage threshold for turning on the driving transistor T2 , the driving transistor T2 is not turned on and does not generate a driving signal.

[0189] As the control power signal SWEEP increases, the potential value of the first light-emitting control signal increases. When its potential value is greater than or equal to the second turn-on preset voltage threshold that turns on the driving transistor T2, the driving transistor T2 is turned on, and a driving signal is generated according to the first power signal VSS obtained at its first end and its threshold voltage. Right now Wherein, k is the current conversion coefficient associated with the driving transistor T2.

[0190] The sixth transistor T6 is turned on according to the third light emitting control signal EM2 , and transmits the driving signal obtained at the first end thereof to the cathode of the light emitting element LED when the driving transistor T2 generates the driving signal.

[0191] The light emitting element LED emits light according to the driving signal.

[0192] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0193] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display device, comprising: A backlight assembly, on which a plurality of gate lines, a plurality of data lines, a power supply line and a plurality of sub-pixel circuits are arranged; Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element; Characterized in that the pixel driving circuit comprises: a light-emission duration control circuit, electrically connected to the power line and the data line, the light-emission duration control circuit comprising a first capacitor, and configured to output a first light-emission control signal from a second end of the first capacitor using a control power signal obtained at a first end of the first capacitor and target light-emission duration driving data stored in the first capacitor; a light-emitting driving circuit electrically connected to the light-emitting duration control circuit, wherein the light-emitting driving circuit comprises a driving transistor configured to adjust the duration of the driving transistor generating the driving signal in each display cycle according to the first light-emitting control signal; The light emitting element is electrically connected to the light emitting driving circuit and is configured to emit light according to the driving signal.

2. The display device according to claim 1, characterized in that The light emitting duration control circuit further includes a drive data writing unit: The driving data writing unit is electrically connected to the data line and the second end of the first capacitor, and is configured to obtain original light-emitting duration driving data from the data line in each display cycle before the first end of the first capacitor obtains the control power signal, and store the target light-emitting duration driving data in the first capacitor according to the capacitance of the first capacitor; The first end of the first capacitor is electrically connected to the power line and is configured to obtain the control power signal from the first end thereof and generate the first light-emitting control signal according to the control power signal and the target light-emitting duration driving data.

3. The display device according to claim 2, characterized in that: The driving data writing unit includes a second capacitor and a fifth transistor; The first end of the fifth transistor is electrically connected to the data line, the control end thereof is electrically connected to the gate line, and the second end thereof is electrically connected to the first end of the second capacitor, and is configured to obtain driving data from the first end thereof, obtain a third scanning signal from the control end thereof, control its conduction state by the third scanning signal, and output the driving data from the second end thereof when it is turned on; the driving data includes the original light emission duration driving data or the initialization driving data; The second end of the second capacitor is electrically connected to the second end of the first capacitor, and is configured to obtain the original light-emitting duration driving data from its first end, and couple with the first capacitor to store the target light-emitting duration driving data.

4. The display device according to claim 2, characterized in that: The light-emitting driving circuit includes a light-emitting control circuit, a light-emitting threshold compensation circuit and a reset circuit; The light emitting control circuit has a first end electrically connected to the power line, a second end electrically connected to the light emitting element, a third end and a fourth end electrically connected to the light emitting threshold compensation circuit, and is configured such that the first end thereof obtains a first power signal from the power line, outputs the first power signal from the third end thereof to the light emitting threshold compensation circuit during the compensation phase and the display phase of the display cycle, and transmits a driving signal obtained at the fourth end thereof to the light emitting element during the display phase to drive the light emitting element to emit light; The control end of the light-emitting threshold compensation circuit is electrically connected to the second end of the first capacitor, the first end of the light-emitting threshold compensation circuit is electrically connected to the third end of the light-emitting control circuit, and the second end of the light-emitting threshold compensation circuit is electrically connected to the fourth end of the light-emitting control circuit, and is configured to store the threshold voltage of the driving transistor according to the first power supply signal during the compensation phase, and generate and transmit a driving signal to the light-emitting control circuit according to the stored threshold voltage and the first light-emitting control signal during the display phase; The first end of the reset circuit is electrically connected to the power line, and the second end of the reset circuit is electrically connected to the luminous threshold compensation circuit and the second end of the first capacitor. The reset circuit is configured to obtain a reference power signal at its first end and transmit it to the luminous threshold compensation circuit and the second end of the first capacitor before the compensation stage to perform a reset operation.

5. The display device according to claim 4, characterized in that: The light emission threshold compensation circuit comprises: a driving transistor, wherein the first end of the driving transistor serves as the first end of the light-emitting threshold compensation circuit, the second end of the driving transistor serves as the second end of the light-emitting threshold compensation circuit, and the control end of the driving transistor serves as the control end of the light-emitting threshold compensation circuit, and is configured to output a first power supply signal compensated by the threshold voltage thereof from the control end when the control end and the second end are short-circuited; and to be turned on according to a first light-emitting control signal obtained at the control end and having a voltage value within a preset voltage range, and to be turned off according to a first light-emitting control signal obtained at the control end and having a voltage value not within the preset voltage range, when the control end and the second end are disconnected; a third transistor, a first end of which is electrically connected to the control end of the driving transistor, a control end of which is electrically connected to the gate line, a second end of which is electrically connected to the second end of the driving transistor, and is configured to obtain a second scanning signal from its control end, and to control its conduction state by the second scanning signal; The third capacitor has a first end electrically connected to the power line and a second end electrically connected to the control end of the driving transistor, and is configured to store an electrical signal obtained by the control end of the driving transistor.

6. The display device according to claim 4, characterized in that: The light emitting control circuit comprises: a fourth transistor, a first end of which serves as the first end of the light emitting control circuit, a second end of which serves as the third end of the light emitting control circuit, a control end of which is electrically connected to the gate line, and is configured to obtain a second light emitting control signal from the control end of the fourth transistor, and to control its conduction state by the second light emitting control signal; A sixth transistor, whose first end serves as the fourth end of the light emitting control circuit, whose second end serves as the second end of the light emitting control circuit, whose control end is electrically connected to the gate line, is configured to obtain a third light emitting control signal from its control end, and whose conduction state is controlled by the third light emitting control signal.

7. The display device according to claim 4, characterized in that: The reset circuit comprises: A first transistor, whose first end is electrically connected to the power line, whose control end is electrically connected to the gate line, and whose second end is electrically connected to the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor, and the control end of the driving transistor. The first transistor is configured to obtain a first scanning signal from its control end and a reference power signal from its first end, and its conduction state is controlled by the first scanning signal. When the first transistor is turned on, the reference power signal is output from its second end to reset the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor, and the control end of the driving transistor.

8. The display device according to claim 4, characterized in that: A display cycle includes a reset phase, a compensation phase, a data writing phase and a display phase in sequence; In the reset stage, the first scanning signal and the third scanning signal are at a first level, the second scanning signal, the second light-emitting control signal and the third light-emitting control signal are at a second level, and the control power supply signal is adjusted from the first level to the second level; The first transistor is turned on according to the first scanning signal, and transmits the reference power signal obtained at the first end thereof to the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor, and the control end of the driving transistor; The first capacitor, the second capacitor and the third capacitor reset their second ends according to the reference power signal; The fifth transistor is turned on according to the third scanning signal, and transmits the initialization driving data obtained at the first end thereof to the second end, so as to reset the first end of the second capacitor; The first capacitor adjusts the potential value of the first end thereof according to the control power signal; The driving transistor is turned on according to the reference power signal.

9. The display device according to claim 8, characterized in that: In the compensation stage, the second scanning signal and the second light emitting control signal are at a first level, and the first scanning signal, the third scanning signal, the third light emitting control signal and the control power supply signal are at a second level; The fourth transistor is turned on according to the second light emitting control signal, and transmits the first power signal obtained at the first end thereof to the first end of the driving transistor; The third transistor is turned on according to the second scanning signal to short-circuit the control terminal and the second terminal of the driving transistor; The driving transistor determines the threshold voltage compensated first power signal from its control terminal according to the first power signal obtained at its first terminal and its threshold voltage; The third capacitor determines that the voltage difference stored therein is the threshold voltage of the driving transistor according to the first power signal obtained by the second terminal of the third capacitor after the threshold voltage compensation and the first power signal obtained by the first terminal of the third capacitor.

10. The display device according to claim 8, characterized in that: In the data writing stage, the third scanning signal is at a first level, and the first scanning signal, the second scanning signal, the second light emitting control signal, the third light emitting control signal and the control power supply signal are at a second level; The fifth transistor is turned on according to the third scanning signal, and transmits the original light emitting duration driving data acquired by the first end thereof to the first end of the second capacitor; The second capacitor outputs the target light emission duration driving data from its second end according to the original light emission duration driving data, the capacitance value of the second capacitor, the capacitance value of the third capacitor, the capacitance value of the first capacitor and the threshold voltage of the driving transistor stored in the third capacitor; The first capacitor stores the target light emitting duration driving data at its second end.

11. The display device according to claim 8, characterized in that In the display stage, the second light-emitting control signal and the third light-emitting control signal are at a first level, the first scanning signal, the second scanning signal and the third scanning signal are at a second level, and the control power supply signal is a ramp signal adjusted from the second level to the first level; The fourth transistor is turned on according to the second light emitting control signal, and transmits the first power signal obtained at the first end thereof to the first end of the driving transistor; The first capacitor adjusts the potential value of the second end thereof according to the potential change of the first end thereof; The driving transistor is turned on when the potential value of the first light emitting control signal obtained at the control terminal thereof is within a preset voltage range to generate a driving signal; When the voltage value obtained at the control terminal is not within the first light emitting control signal of the preset voltage range, the control terminal is turned off and no driving signal is generated; The sixth transistor is turned on according to the third light emitting control signal, and when the first terminal thereof obtains the driving signal, the sixth transistor transmits the driving signal to the light emitting element; The light emitting element emits light according to the driving signal.

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