Signal transmission circuit, chip and electronic device

Abstract

The invention discloses a signal transmitting circuit, a chip and electronic equipment, and belongs to the technical field of display. The signal transmitting circuit comprises a first signal driving circuit and a second signal driving circuit; under the condition that the first signal driving circuit and the second signal driving circuit are disconnected, the first signal driving circuit is used for sending an output differential signal in a CML driving mode according to a first input differential signal, and the second signal driving circuit does not work; and under the condition that the first signal driving circuit is connected with the second signal driving circuit, the first signal driving circuit and the second signal driving circuit are used for sending an output differential signal in the LVDS driving mode according to the first input differential signal. The signal transmitting circuit can support switching of the LVDS driving mode and the CML driving mode, so that the signal transmitting circuit can be compatible with electrical interface standards in different driving modes, and the flexibility of the signal transmitting circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a signal sending circuit, a chip and an electronic device. Background Art

[0002] In a SerDes (Serializer-Deserializer), a signal transmission circuit of a SerDes transmitter (TX) generally supports only a single driving mode, so if other driving modes are required, the signal transmission circuit needs to be redesigned. Summary of the invention

[0003] The present application provides a signal transmission circuit, a chip and an electronic device that can support two driving modes.

[0004] In a first aspect, a signal transmission circuit is provided, the signal transmission circuit comprising a first signal driving circuit and a second signal driving circuit;

[0005] When the first signal driving circuit is disconnected from the second signal driving circuit, the first signal driving circuit is used to send an output differential signal in a CML (Current Mode Logic) driving mode according to the first input differential signal, and the second signal driving circuit does not work;

[0006] When the first signal driving circuit is connected to the second signal driving circuit, the first signal driving circuit and the second signal driving circuit are used to send an output differential signal in an LVDS (Low Voltage Differential Signaling) driving mode according to the first input differential signal.

[0007] In a possible implementation, the signal sending circuit also includes a first control circuit and a second control circuit; the first control circuit is used to control the input signal of the second signal driving circuit; the second control circuit is used to control the connection mode of the first signal driving circuit; when the input signal of the second signal driving circuit is a first level and the connection mode of the first signal driving circuit is a first connection mode, the first signal driving circuit is disconnected from the second signal driving circuit; when the input signal of the second signal driving circuit is the first input differential signal and the connection mode of the first signal driving circuit is a second connection mode, the first signal driving circuit is connected to the second signal driving circuit.

[0008] In a possible implementation, the first control circuit includes a signal generating circuit, a first switch, and a second switch; the signal generating circuit is used to generate a signal of the first level; the first switch is used to control the conduction and disconnection of the second signal driving circuit and the signal end of the first input differential signal; the second switch is used to control the conduction and disconnection of the second signal driving circuit and the signal generating circuit.

[0009] In a possible implementation, the first input differential signal includes a first input positive signal and a first input negative signal, the first signal driving circuit includes a first negative signal driving circuit and a first positive signal driving circuit, the first negative signal driving circuit is connected to the signal end of the first input negative signal, and the first positive signal driving circuit is connected to the signal end of the first input positive signal; the first connection method is that the first negative signal driving circuit and the first positive signal driving circuit are both connected to the ground, and the second connection method is that the first negative signal driving circuit and the first positive signal driving circuit are connected.

[0010] In a possible implementation, the first input differential signal includes a first input positive signal and a first input negative signal, the second signal driving circuit includes a second negative signal driving circuit and a second positive signal driving circuit, and the first switch includes a first sub-switch and a second sub-switch; the first sub-switch is used to control the conduction and disconnection of the second negative signal driving circuit and the signal end of the first input negative signal; the second sub-switch is used to control the conduction and disconnection of the second positive signal driving circuit and the signal end of the first input positive signal.

[0011] In a possible implementation, the signal transmission circuit further includes a pre-emphasis circuit; the pre-emphasis circuit is used to increase the high-frequency component of the output differential signal according to the second input differential signal to compensate for the attenuation of the high-frequency component during transmission, and the second input differential signal is a differential signal of the first input differential signal delayed by one clock cycle. In a possible implementation, the second input differential signal includes a second input positive signal and a second input negative signal, and the pre-emphasis circuit includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit, and the negative signal pre-emphasis circuit is connected to the signal end of the second input negative signal, and the positive signal pre-emphasis circuit is connected to the signal end of the second input positive signal.

[0012] In a possible implementation, the signal sending circuit also includes a voltage conversion circuit; the voltage conversion circuit is used to receive an initial differential signal, the voltage amplitude of the initial differential signal is less than a voltage threshold; the initial differential signal is voltage converted to obtain the first input differential signal, and the voltage amplitude of the first input differential signal is greater than or equal to the voltage threshold.

[0013] In one possible implementation, the initial differential signal includes an initial positive signal and an initial negative signal, the first input differential signal includes a first input positive signal and a first input negative signal, and the voltage conversion circuit includes a first conversion circuit and a second conversion circuit; the first conversion circuit is used to convert the initial positive signal into the first input positive signal; the second conversion circuit is used to convert the initial negative signal into the first input negative signal.

[0014] On the other hand, a chip is provided, wherein the chip includes the signal sending circuit as described in the above aspect.

[0015] On the other hand, an electronic device is provided, comprising the signal sending circuit as described in the above aspect.

[0016] In summary, the beneficial effects brought about by the technical solution provided by this application may at least include:

[0017] The signal sending circuit provided in the present application can flexibly switch between the LVDS driving mode and the CML driving mode by controlling the connection relationship between the first signal driving circuit and the second signal driving circuit, so that the signal sending circuit can be compatible with the electrical interface standards under different driving modes, and further make it compatible with application scenarios of different signal transmission protocols, thereby improving the flexibility of the signal sending circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a structural schematic diagram of a signal sending circuit provided in an embodiment of the present application;

[0020] Figure 2 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0021] Figure 3 is a structural schematic diagram of a first voltage conversion circuit provided in an embodiment of the present application;

[0022] Figure 4 is a structural schematic diagram of a second voltage conversion circuit provided in an embodiment of the present application;

[0023] Figure 5 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0024] Figure 6 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0025] Figure 7 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0026] Figure 8 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0027] Fig. 9 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0028] Fig.10 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0029] Fig.11 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0030] Fig.12 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0031] Fig.13 is a schematic diagram of the structure of a third voltage conversion circuit and a fourth voltage conversion circuit provided in an embodiment of the present application;

[0032] Fig.14 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0033] Fig.15 is a structural schematic diagram of another signal sending circuit provided in an embodiment of the present application;

[0034] Fig.16 is a driving schematic diagram under a CML driving mode provided in an embodiment of the present application;

[0035] Fig.17 is a driving schematic diagram of another CML driving mode provided in an embodiment of the present application;

[0036] Fig.18 is a driving schematic diagram of another CML driving mode provided in an embodiment of the present application;

[0037] Fig.19 is a waveform diagram of a CML driving mode provided in an embodiment of the present application;

[0038] Fig. 20 This is a driving schematic diagram under an LVDS driving mode provided in an embodiment of the present application;

[0039] Fig.21 This is another driving schematic diagram under LVDS driving mode provided in an embodiment of the present application;

[0040] Fig. 22 This is another driving schematic diagram under LVDS driving mode provided in an embodiment of the present application;

[0041] Fig.23 This is a waveform diagram of an LVDS driving mode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0043] In high-speed serial communication systems, especially in application scenarios such as big data centers, high-performance computing, high-definition video transmission and remote communication, SerDes (Serializer-Deserializer) plays a vital role. Serializer is used to convert parallel data into serial data, and Deserializer is used to convert serial data into parallel data. However, with the continuous increase in data transmission rate and the increase in transmission distance, the signal transmission circuit of the SerDes transmitter (Transmitter, TX) faces many challenges in signal integrity, power consumption, compatibility and flexibility.

[0044] The signal transmission circuit of SerDes TX can be referred to as SerDes TX circuit for short, which is mainly used to convert parallel data into high-speed serial signals and send them out in the form of differential signals for transmission in high-speed serial communication links. For example, in high-speed communication systems, such as high-speed Ethernet, optical fiber communication, high-speed backplane, etc., SerDes TX circuit can serialize multiple low-speed parallel data (usually from the parallel bus inside the chip) to achieve high-speed data transmission, overcoming the wiring difficulties, large crosstalk between signals, complex synchronization and other problems existing in parallel transmission.

[0045] The workflow of the SerDes TX circuit includes: first, parallel data enters the data encoding module of the SerDes TX circuit through the parallel data input port from various functional modules inside the system (such as processors, memory controllers, etc.); the parallel data is encoded by the data encoding module to ensure data reliability and clock synchronization performance; the encoded parallel data is combined into serial data in bit order by the multiplexer; the serial data passes through the pre-emphasis and equalization modules to optimize the signal and reduce distortion during transmission; finally, the optimized signal is amplified to the required power level by the driving circuit and sent out through the electrical interface.

[0046] Pre-emphasis is a signal processing method that compensates for the high-frequency components of the signal at the transmitting end. As the signal is transmitted through the transmission medium (such as printed circuit board traces, cables, etc.), the high-frequency component will decay faster than the low-frequency component, resulting in signal distortion. Pre-emphasis technology enhances the high-frequency part of the signal at the transmitting end to compensate for the excessive attenuation of the high-frequency component during the transmission process, ensuring that the receiving end can receive a waveform closer to the original signal, thereby improving the integrity and transmission distance of the signal.

[0047] In related technologies, SerDes TX circuits usually support a single electrical interface standard, such as the LVDS interface standard. The electrical interface standard defines the physical connection method between devices and the electrical characteristics of the physical layer, including the voltage range, current range, impedance matching, transmission rate, and distance limit of the signal, to ensure interoperability and security between devices.

[0048] Among them, the LVDS interface standard transmits data in the form of low-voltage differential signals, and represents data through the voltage difference between two signal lines (positive signal and negative signal), which has the advantages of low power consumption, low noise and good anti-interference ability. Differential signal refers to two signals with equal amplitude and opposite polarity transmitted through two lines. The receiving end restores the data by comparing the difference between the two signals. For example, when the voltage on the positive signal line is higher than the voltage on the negative signal line, it represents a logical "1"; conversely, when the voltage on the positive signal line is lower than the voltage on the negative signal line, it represents a logical "0".

[0049] However, with the development of communication technology and the changes in application requirements, supporting only a single LVDS interface standard can no longer meet the diverse needs of scenarios. For example, in TCON (Timing Controller) applications that support P2P (point to point) transmission protocols, it is also necessary to support the P2P interface standard; or in long-distance transmission scenarios that support VBO (Video by One) transmission protocols, it is also necessary to support the VBO interface standard.

[0050] Different electrical interface standards have differences in signal level, driving mode, transmission rate, etc. For example, under the LVDS interface standard, the LVDS driving mode is adopted, the driving current is relatively small, the power consumption is low, and it works in the rate range of 155Mbps (megabits per second) to 1.25Gbps (gigabits per second), which is suitable for medium and high-speed transmission. Under the P2P interface standard or VBO interface standard, the CML driving mode is adopted, the driving current is relatively large, the power consumption is high, and it can work stably in the rate range of 600Mbps to 10Gbps and above, with high noise resistance, which is suitable for higher-speed transmission.

[0051] Therefore, if the SerDes TX circuit is to be compatible with multiple electrical interface standards such as P2P / LVDS / BVO, the SerDes TX circuit needs to support LVDS drive mode and CML drive mode.

[0052] The embodiment of the present application provides a signal transmission circuit, which can support LVDS driving mode and CML driving mode. Figure 1 , Figure 1 This is a schematic diagram of the structure of a signal sending circuit provided in an embodiment of the present application. The signal sending circuit 00 includes a first signal driving circuit 11 and a second signal driving circuit 12.

[0053] When the first signal driving circuit 11 and the second signal driving circuit 12 are disconnected, the first signal driving circuit 11 is used to send the output differential signal in the CML driving mode according to the first input differential signal, and the second signal driving circuit 12 does not work; when the first signal driving circuit 11 and the second signal driving circuit 12 are connected, the first signal driving circuit 11 and the second signal driving circuit 12 are used to send the output differential signal in the LVDS driving mode according to the first input differential signal. The transmission frequency of the output differential signal in the CML driving mode is greater than the transmission frequency of the output differential signal in the LVDS driving mode.

[0054] In the embodiment of the present application, the first signal driving circuit 11 corresponds to the driving circuit in the CML driving mode, and the combination of the first signal driving circuit 11 and the second signal driving circuit 12 corresponds to the driving circuit in the LVDS driving mode. Therefore, the embodiment of the present application combines two driving circuits corresponding to the two driving modes in the same signal transmission circuit 00, and by controlling the connection relationship between the first signal driving circuit 11 and the second signal driving circuit 12, the signal transmission circuit 00 can flexibly switch between the two driving modes, and thus can be flexibly applicable to electrical interface standards under different driving modes.

[0055] In a possible implementation, the signal transmission circuit further includes a voltage conversion circuit 16; the voltage conversion circuit 16 is used to receive an initial differential signal, the voltage amplitude of the initial differential signal is less than a voltage threshold; the initial differential signal is voltage converted to obtain a first input differential signal, the voltage amplitude of the first input differential signal is greater than or equal to the voltage threshold. The voltage threshold is the minimum voltage for driving the first signal driving circuit 11 or the second signal driving circuit 12.

[0056] Optionally, the initial differential signal is a differential signal after the parallel data is converted into serial data in the SerDes circuit, and belongs to the digital domain. The voltage amplitude of the signal in the digital domain is small, and it is difficult to drive the devices in the subsequent signal driving circuit. The embodiment of the present application converts the initial differential signal in the digital domain into the first input differential signal in the analog domain through the voltage conversion circuit 16, and the voltage amplitude of the signal in the digital domain is large. For example, the voltage range of the initial differential signal is 0-0.9V (volts), and the voltage range of the first input differential signal is 0.45-1.35V. The differential signal in the digital domain may refer to a specific analog voltage output after the digital signal is input into the digital-to-Analog Conversion (DAC) in binary form.

[0057] Thus, the differential signal input to the first signal driving circuit 11 and the second signal driving circuit 12 can match the requirements of the first signal driving circuit 11 and the second signal driving circuit 12 through the voltage conversion circuit 16. In the embodiment of the present application, the differential signal includes two parts of the signal, namely, a positive signal and a negative signal. Then, the first input differential signal includes a first input positive signal and a first input negative signal, the output differential signal includes an output positive signal and an output negative signal, and the initial differential signal includes an initial positive signal and an initial negative signal.

[0058] Alternatively, see Figure 2 In the signal transmission circuit 00 shown in the figure, the voltage conversion circuit 16 includes a first conversion circuit 161 and a second conversion circuit 162. The first conversion circuit 161 is used to convert the initial positive signal into a first input positive signal; the second conversion circuit 162 is used to convert the initial negative signal into a first input negative signal. Thus, the voltage conversion of the two signals in the differential signal is respectively realized by two independent conversion circuits.

[0059] In a possible implementation, the first conversion circuit 161 includes a first capacitor and a first bias circuit, one end of the first capacitor is connected to the first signal end, the other end of the first capacitor is connected to the second signal end through the first node, and the first bias circuit is connected to the first node. The first bias circuit is used to control the voltage of the first node to be the first common mode voltage; the first capacitor is used to control the second signal end to output the first input positive signal according to the initial positive signal input to the first signal end, and the voltage range of the first input positive signal floats above and below the first common mode voltage.

[0060] In the embodiment of the present application, the floating distance of the first input positive signal is the same as the floating distance of the initial positive signal. For example, the voltage range of the initial differential signal is 0-0.9V, the initial differential signal floats around 0.45V, and the floating distance is 0.45V; the voltage range of the first input differential signal is 0.45-1.35V, the first input differential signal floats around 0.9V, and the floating distance is also 0.45V, then the first common mode voltage is 0.9V. The circuit structure of the second conversion circuit 162 can refer to the circuit of the first conversion circuit 161, and will not be repeated here.

[0061] Optionally, the first bias circuit may include a first bias impedance and a second bias impedance, one end of the first bias impedance is connected to the power supply terminal, and the other end of the first bias impedance is connected to the first node; one end of the second bias impedance is connected to the ground terminal, and the other end of the second bias impedance is connected to the first node. The voltage of the power supply terminal is set to twice the first common mode voltage, for example, 1.8V, and the impedance of the first bias impedance and the second bias impedance are set to be equal, so that the first bias impedance and the second bias impedance can produce the same voltage drop, then the voltage of the first node between the first bias impedance and the second bias impedance is half of the voltage of the power supply terminal, that is, the first common mode voltage, for example, 0.9V.

[0062] Among them, the first bias impedance and the second bias impedance can be realized by devices such as PMOS tube and NMOS tube. PMOS tube refers to P (Positive) type MOS tube, and the working principle is: when the signal received by the gate is a high level signal, the source and drain of the PMOS tube are not conducting; when the signal received by the gate is a low level signal, the source and drain of the PMOS tube are conducting. NMOS tube refers to N (Negative) type MOS transistor, and the working principle is: when the signal received by the gate is a high level signal, the source and drain of the NMOS tube are conducting; when the signal received by the gate is a low level signal, the source and drain of the NMOS tube are not conducting. MOS transistor is the abbreviation of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is abbreviated as metal-oxide semiconductor field effect transistor or field effect tube.

[0063] Exemplarily, the circuit structure of the first conversion circuit 161 can be as follows: Figure 3 As shown, INP is the first signal terminal for inputting the initial positive signal, and OUTP is the second signal terminal for outputting the first input positive signal. VDD is the power supply terminal, VSS is the ground terminal, C1 is the first capacitor, and X1 is the first node. MN3 and MN4 are two NMOS transistors, and MP5 and MP6 are two PMOS transistors. Among them, MP5 and MN3, MP6 and MN4 are respectively set with corresponding bias voltages, for example Figure 3 V2, V3, V4 and V5 in the circuit. Bias Voltage, also known as bias or bias, refers to an additional DC voltage applied in a circuit to make transistors or other active devices work in a specific area.

[0064] Thus, MP5 and MN3 form a first bias impedance, MP6 and MN4 form a second bias impedance, the first bias impedance is equal to the second bias impedance, and X1 is the static operating point of the first common mode voltage. Similarly, the circuit structure of the second conversion circuit 162 can be as follows: Figure 4 As shown, INN is a third signal terminal for inputting an initial negative signal; OUTN is a fourth signal terminal for outputting a first input negative signal.

[0065] In one possible implementation, see Figure 5 The signal sending circuit 00 also includes a first control circuit 13 and a second control circuit 14; the first control circuit 13 is used to control the input signal of the second signal driving circuit 12; the second control circuit 14 is used to control the connection mode of the first signal driving circuit 11; when the input signal of the second signal driving circuit 12 is a first level and the connection mode of the first signal driving circuit 11 is a first connection mode, the first signal driving circuit 11 is disconnected from the second signal driving circuit 12; when the input signal of the second signal driving circuit 12 is a first input differential signal and the connection mode of the first signal driving circuit 11 is a second connection mode, the first signal driving circuit 11 is connected to the second signal driving circuit 12.

[0066] The embodiment of the present application does not limit the manner in which the first control circuit 13 controls the input signal of the second signal driving circuit 12. Figure 6The first control circuit 13 includes a signal generating circuit 131, a first switch 132 and a second switch 133; the signal generating circuit 131 is used to generate a signal of a first level; the first switch 132 is used to control the conduction and disconnection of the second signal driving circuit 12 and the signal end of the first input differential signal; the second switch 133 is used to control the conduction and disconnection of the second signal driving circuit 12 and the signal generating circuit.

[0067] Since the first input differential signal includes a first input positive signal and a first input negative signal, and the output differential signal includes an output positive signal and an output negative signal, the first signal driving circuit 11 and the second signal driving circuit 12 also correspond to driving circuits including positive and negative parts. Figure 7 As shown, the first signal driving circuit 11 includes a first negative signal driving circuit 111 and a first positive signal driving circuit 112. The first negative signal driving circuit 111 is connected to the signal end of the first input negative signal, and the first positive signal driving circuit 112 is connected to the signal end of the first input positive signal. In this mode, the first connection mode is that the first negative signal driving circuit 111 and the first positive signal driving circuit 112 are both connected to the ground end, and the second connection mode is that the first negative signal driving circuit 111 and the first positive signal driving circuit 112 are connected. Among them, the second control circuit 14 is located between the first negative signal driving circuit 111 and the first positive signal driving circuit 112, and is connected to the first negative signal driving circuit 111 and the first positive signal driving circuit 112 respectively.

[0068] For example, see Figure 8 , the first negative signal driving circuit 111 includes a first transistor and a first impedance, and the first positive signal driving circuit 112 includes a second transistor and a second impedance. The gate of the first transistor inputs the first input negative signal, the source of the first transistor is connected to the first positive current source, the drain of the first transistor is connected to one end of the first impedance through the first output terminal, and the first output terminal is used to send an output positive signal; the gate of the second transistor inputs the first input positive signal, the source of the second transistor is connected to the first positive current source, the drain of the second transistor is connected to one end of the second impedance through the second output terminal, and the second output terminal is used to send an output negative signal; the second control circuit 14 is respectively connected to the other end of the first impedance and the other end of the second impedance, and is used to control the connection mode between the first impedance and the second impedance. In this mode, the first connection mode is that the first impedance and the second impedance are both connected to the ground terminal, and the second connection mode is that the first impedance and the second impedance are connected.

[0069] like Fig. 9As shown, the second signal driving circuit 12 includes a second negative signal driving circuit 121 and a second positive signal driving circuit 122, and the first switch 132 includes a first sub-switch 1321 and a second sub-switch 1322; the first sub-switch 1321 is used to control the conduction and disconnection of the second negative signal driving circuit and the signal end of the first input negative signal; the second sub-switch 1322 is used to control the conduction and disconnection of the second positive signal driving circuit and the signal end of the first input positive signal.

[0070] For example, see Fig.10 , the first negative signal driving circuit 111 includes a third transistor, and the first positive signal driving circuit 112 includes a fourth transistor. The gate of the third transistor is connected to the first sub-switch 1321, the source of the third transistor is connected to the negative current source, and the drain of the third transistor is connected to the first output terminal; the gate of the fourth transistor is connected to the second sub-switch 1322, the source of the fourth transistor is connected to the negative current source, and the drain of the fourth transistor is connected to the second output terminal. Optionally, the second switch 133 may also include two sub-switches, one sub-switch is used to control the switch between the signal generating circuit 131 and the third transistor, and the other sub-switch is used to control the switch between the signal generating circuit 131 and the fourth transistor.

[0071] In the embodiment of the present application, the first transistor and the second transistor are turned on when the gate input signal is at the first level and turned off when the gate input signal is at the second level, and the third transistor and the fourth transistor are turned off when the gate input signal is at the first level. That is, the type of the first transistor and the second transistor is different from the type of the third transistor and the fourth transistor. Exemplarily, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

[0072] Exemplarily, the schematic diagram of the signal transmission circuit can be as follows: Fig.11 As shown. The first transistor corresponds to MP1, the second transistor corresponds to MP2, MP is the abbreviation of PMOS tube; the third transistor corresponds to MN1, the fourth transistor corresponds to MN2, MN is the abbreviation of NMOS tube; the first impedance corresponds to RON1, the second impedance corresponds to RON2; the first output terminal corresponds to OUT_P, and the second output terminal corresponds to OUT_N. AVDD represents analog voltage, for example, AVDD is 1.8V, and AVSS represents analog ground.

[0073] like Fig.11As shown, the second control circuit 14 includes four switches, namely SW5, SW6, SW7 and SW8. When SW5 and SW7 are closed and SW6 and SW8 are disconnected, RON1 is connected to RON2. When SW5 and SW7 are disconnected and SW6 and SW8 are closed, RON1 and RON2 are both connected to AVSS. The first switch 132 includes two switches, namely SW3 and SW4. The second switch 133 includes two switches, namely SW1 and SW2. The signal generating circuit 131 includes two resistors, which are also connected to AVSS respectively. The resistance values ​​of the two resistors can be equal, and both are used to generate a signal of the first level (i.e., a low level). When SW1 and SW2 are closed and SW3 and SW4 are disconnected, the gate voltages of MN1 and MN2 remain at a low level, and MN1 and MN2 remain disconnected; when SW1 and SW2 are disconnected and SW3 and SW4 are closed, the gate input of MN1 is OUTN, and the gate input of MN2 is OUTP, and MN1 and MN2 are turned on or off according to the changes of OUTN and OUTP.

[0074] Among them, taking the NMOS tube as an example, the gate-source voltage (VGS) of the NMOS tube needs to be greater than the threshold voltage (Vth) to form a conductive channel to turn on the transistor. The typical value of the threshold voltage of the NMOS tube varies due to different processes and device parameters. For example, when the first input negative signal is input to the gate of MN1, the gate drive voltage, that is, the voltage of OUTN, must be at least greater than the threshold voltage to turn on the MN1 tube. Therefore, the minimum voltage for driving the first signal driving circuit 11 is the threshold voltage of the NMOS tube in the first signal driving circuit 11, and the minimum voltage for driving the second signal driving circuit 12 is the threshold voltage of the NMOS tube in the second signal driving circuit 12.

[0075] In one possible implementation, see Fig.12 The signal transmission circuit also includes a pre-emphasis circuit 15; the pre-emphasis circuit 15 is used to increase the high-frequency component of the output differential signal according to the second input differential signal to compensate for the attenuation of the high-frequency component during transmission. The second input differential signal is a differential signal of the first input differential signal delayed by one clock cycle.

[0076] Optionally, the signal sending circuit further includes Fig.12 The pre-emphasis circuit 15 and Figure 2 In the case of the voltage conversion circuit 16 shown, the voltage conversion circuit 16 is also used to receive the initial differential signal after a delay of one clock cycle; the initial differential signal after a delay of one clock cycle is voltage converted to obtain a second input differential signal, and the voltage amplitude of the second input differential signal is greater than or equal to the voltage threshold, and the voltage threshold at this time is the minimum voltage for driving the pre-emphasis circuit 15.

[0077] Consistent with the above differential signal, the second input differential signal includes a second input positive signal and a second input negative signal. Optionally, the voltage conversion circuit 16 includes a third conversion circuit and a fourth conversion circuit in addition to the first conversion circuit 161 and the second conversion circuit 162. The third conversion circuit is used to convert the initial positive signal after a delay of one clock cycle into the second input positive signal; the fourth conversion circuit is used to convert the initial negative signal after a delay of one clock cycle into the second input negative signal.

[0078] The structures of the third conversion circuit and the fourth conversion circuit can refer to the structures of the first conversion circuit 161 and the second conversion circuit 162, which will not be described in detail here. Fig.13 As shown in (a), INP_EM is used to input the initial positive signal after a delay of one clock cycle, and OUTP_EM is used to output the second input positive signal. The fourth conversion circuit can be as follows Fig.13 As shown in (b), INN_EM is used to input the initial negative signal after a delay of one clock cycle; OUTN_EM is used to output the second input negative signal.

[0079] In a possible implementation, the pre-emphasis circuit 15 includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit, wherein the negative signal pre-emphasis circuit is connected to the signal end of the second input negative signal, and the positive signal pre-emphasis circuit is connected to the signal end of the second input positive signal. Exemplarily, the negative signal pre-emphasis circuit includes a fifth transistor, and the positive signal pre-emphasis circuit includes a sixth transistor; the gate of the fifth transistor inputs the second input positive signal, the source of the fifth transistor is connected to the second positive current source, the drain of the fifth transistor is connected to the first output end, and the first output end is used to send the output positive signal after the high-frequency component is increased; the gate of the sixth transistor inputs the second input negative signal, the source of the sixth transistor is connected to the second positive current source, the drain of the sixth transistor is connected to the second output end, and the second output end is used to send the output negative signal after the high-frequency component is increased.

[0080] For example, in Fig.11 Based on the first signal driving circuit 11 and the second signal driving circuit 12 shown in FIG. 1 , a circuit structure after adding a pre-emphasis circuit 15 is shown in FIG. Fig.14 As shown, the fifth transistor corresponds to MP3, and the sixth transistor corresponds to MP4.

[0081] In the embodiments of the present application, Fig.14 The function of the switch SW in can be realized by a transistor. In this case, Fig.15As shown, SW3 and SW4 can be implemented by two parallel transistors, wherein the gate and source of the transistors are both connected to bias voltages, so that the two parallel transistors can realize the function of switches. SW1 and SW2 can be implemented by one transistor, and the corresponding bias voltages are connected to the gate and source of the transistor to realize the function of switches.

[0082] Optionally, the gates of MP3 and MP4 are also connected to SW9 and SW10, and SW9 and SW10 are used to control whether the pre-emphasis circuit 15 works. Fig.15 As shown, SW9 and SW10 can be implemented by a transistor connected to a bias voltage. The bias voltage applied in the embodiment of the present application is not limited in the embodiment of the present application, as long as it can realize the corresponding switch function. The bias voltage applied when realizing different switch functions may be the same or different.

[0083] by Fig.15 The structural schematic diagram of the signal driving circuit shown in FIG. 1 is taken as an example to illustrate the working mode of the signal driving circuit provided in the embodiment of the present application. In the CML driving mode, the first stage is as follows Fig.16 As shown, MP2, MP3, SW1, SW2, SW6, and SW8 are turned on, and MP1, MP4, MN1, MN2, SW3, SW4, SW5, and SW7 are turned off. The current flow path is as follows Fig.16 As shown by the dotted line in the middle, therefore, the output voltage of the first stage V(OUT_P-OUT_N)=I_EME*RON1-I_MAIN*RON2, where I_MAIN is the current value of the first positive current source, I_EME is the current value of the second positive current source, and RON1 and RON2 are impedance matching resistances.

[0084] When a signal is transmitted from one circuit part to another, impedance matching is required to achieve maximum power transmission or reduce signal reflection. Take the transmission of high-speed digital signals in PCB (printed circuit board) traces as an example. If the characteristic impedance of the PCB trace is designed to be 100Ω (ohms), and the input impedance of the connected chip is also 100Ω, then impedance matching is achieved, and the signal can be effectively transmitted from the trace to the chip, reducing signal distortion and interference caused by reflection.

[0085] The second stage Fig.17 As shown, MP1, MP3, SW1, SW2, SW6, and SW8 are turned on, and MP2, MP4, MN1, MN2, SW3, SW4, SW5, and SW7 are turned off. The current flow path is as follows Fig.17 As shown by the dashed line in the middle, therefore, the output voltage V(OUT_P-OUT_N) of the second stage is I_MAIN*RON1+I_EME*RON1. Fig.18As shown, MP1, MP4, SW1, SW2, SW6, and SW8 are turned on, and MP2, MP3, MN1, MN2, SW3, SW4, SW5, and SW7 are turned off. The current flow path is as follows Fig.18 As shown by the dotted line in the middle, therefore, the output voltage of the third stage V(OUT_P-OUT_N)=I_MAIN*RON1-I_EME*RON2.

[0086] For example, Fig.19 Schematic diagram of the waveform of the output differential signal sent in CML driving mode. Fig.19 The upper part of shows the output differential signal in the CML driving mode, the thin curve represents the output positive signal in the output differential signal, and the thick curve represents the output negative signal in the output differential signal; Fig.19 The lower part of the figure shows the output signal obtained based on the output differential signal conversion. The output signal is the difference between the output positive signal and the output negative signal. Fig.19 Taking the first stage in the example, the voltage value of the output positive signal is about 0.8 volts, the voltage value of the output negative signal is about 0.5 volts, and the voltage value of the output signal is about 0.3 volts.

[0087] In the embodiment of the present application, the pre-emphasis circuit achieves signal enhancement by adjusting the drive current. Specifically, for the high-speed digital signal to be sent, additional drive current is added at the rising and falling edges of the signal (i.e., the part where the high-frequency components are concentrated) to enhance the signal amplitude. For example, when sending a high-speed pulse sequence, the amplitude of the pulse is fixed under normal circumstances, but in the pre-emphasis mode, the amplitude of the rising and falling edges of each pulse will be higher than the middle part.

[0088] In LVDS drive mode, the first stage is as follows Fig. 20 As shown, MP2, MP3, MN1, SW3, SW4, SW5, SW7 are turned on, and MP1, MP4, MN2, SW1, SW2, SW6, SW8 are turned off. The output voltage V(OUT_P-OUT_N) of the first stage is -I_MAIN*(RON1+RON2). Fig.21 As shown, MP1, MP3, MN2, SW3, SW4, SW5, SW7 are turned on, and MP2, MP4, MN1, MN1, SW1, SW2, SW6, SW8 are turned off. Then the output voltage of the second stage V(OUT_P-OUT_N)=(I_MAIN+I_EME)*(RON1+RON2). Fig. 22As shown, MP1, MP4, MN2, SW3, SW4, SW5, SW7 are turned on, and MP2, MP3, MN1, SW1, SW2, SW6, SW8 are turned off, then V(OUT_P-OUT_N)=(I_MAIN)*(RON1+RON2).

[0089] Fig.23 FIG. 4 is a waveform diagram of the output differential signal sent in the LVDS driving mode. Fig.23 The upper part of shows the output differential signal in the LVDS driving mode, the thin curve represents the output positive signal in the output differential signal, and the thick curve represents the output negative signal in the output differential signal; Fig.23 The lower part of the figure shows the output signal obtained based on the output differential signal conversion. The output signal is the difference between the output positive signal and the output negative signal. Fig.23 Taking the first stage in the example, the voltage value of the output positive signal is about 1 volt, the voltage value of the output negative signal is about 1.4 volts, and the voltage value of the output signal is about -0.4 volts.

[0090] Exemplarily, the above-mentioned signal transmission circuit provided in the embodiment of the present application may be a SerDes TX circuit. In summary, the SerDes TX circuit in the related art relies on a single electrical interface, and fails to fully utilize the convenience of the P2P interface, the low power consumption advantage of the LVDS interface, and the electrical characteristics of the VBO interface. In response to the above technical bottlenecks, the embodiment of the present application provides a SerDes TX circuit, which is not only compatible with the P2P / LVDS interface to ensure low power consumption and stable data transmission, but also integrates the adaptability to the VBO electrical characteristics, and realizes the ability to switch seamlessly between different scenarios. In addition, the optimal solution for area is achieved through the adjustment of the architecture and the unique voltage conversion design, so it can be compatible with most application scenarios of the transmission protocols on the market.

[0091] An embodiment of the present application provides a chip, which includes any of the signal transmission circuits shown above, so that the chip can support the switching of two driving modes, LVDS driving mode and CML driving mode, and can be compatible with electrical interface standards under different driving modes.

[0092] Optionally, the chip may be an interface chip, for example, a High Definition Multimedia Interface (HDMI) chip, a DisplayPort (DP) chip, or a Mobile Industry Processor Interface (MIPI) chip.

[0093] An electronic device provided in an embodiment of the present application includes any of the signal transmission circuits shown above. Optionally, the electronic device includes the chip, and the chip includes any of the signal transmission circuits shown above.

[0094] It should be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0095] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components.

[0096] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0097] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0098] "Up", "down", "left" or "right" etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly. "Connected" or "coupled" refers to electrical connection.

[0099] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0100] Technicians in the relevant field can clearly understand that for the convenience and simplicity of description, the specific working processes of the gate drive circuit, shift register unit, each circuit and each sub-circuit described above can refer to the corresponding processes in the method embodiment and will not be repeated here.

[0101] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A signal transmission circuit, characterized in that: The signal sending circuit includes a first signal driving circuit and a second signal driving circuit; When the first signal driving circuit is disconnected from the second signal driving circuit, the first signal driving circuit is used to send an output differential signal in a current mode logic CML driving mode according to the first input differential signal, and the second signal driving circuit is not working; When the first signal driving circuit is connected to the second signal driving circuit, the first signal driving circuit and the second signal driving circuit are used to send an output differential signal in a low voltage differential signal LVDS driving mode according to the first input differential signal.

2. The signal transmission circuit according to claim 1, characterized in that: The signal sending circuit further includes a first control circuit and a second control circuit; the first control circuit is used to control the input signal of the second signal driving circuit; the second control circuit is used to control the connection mode of the first signal driving circuit; When the input signal of the second signal driving circuit is at the first level and the connection mode of the first signal driving circuit is the first connection mode, the first signal driving circuit is disconnected from the second signal driving circuit; When the input signal of the second signal driving circuit is the first input differential signal and the connection mode of the first signal driving circuit is the second connection mode, the first signal driving circuit is connected to the second signal driving circuit.

3. The signal transmission circuit according to claim 2, characterized in that: The first control circuit includes a signal generating circuit, a first switch and a second switch; The signal generating circuit is used to generate the signal of the first level; The first switch is used to control the conduction and disconnection between the second signal driving circuit and the signal end of the first input differential signal; The second switch is used to control the conduction and disconnection of the second signal driving circuit and the signal generating circuit.

4. The signal transmission circuit according to claim 2, characterized in that: The first input differential signal includes a first input positive signal and a first input negative signal, the first signal driving circuit includes a first negative signal driving circuit and a first positive signal driving circuit, the first negative signal driving circuit is connected to the signal end of the first input negative signal, and the first positive signal driving circuit is connected to the signal end of the first input positive signal; The first connection mode is that the first negative signal driving circuit and the first positive signal driving circuit are both connected to the ground, and the second connection mode is that the first negative signal driving circuit and the first positive signal driving circuit are connected to each other.

5. The signal transmission circuit according to claim 3, characterized in that: The first input differential signal includes a first input positive signal and a first input negative signal, the second signal driving circuit includes a second negative signal driving circuit and a second positive signal driving circuit, and the first switch includes a first sub-switch and a second sub-switch; The first sub-switch is used to control the conduction and disconnection between the second negative signal driving circuit and the signal terminal of the first input negative signal; The second sub-switch is used to control the conduction and disconnection of the second positive signal driving circuit and the signal terminal of the first positive signal input.

6. The signal transmission circuit according to any one of claims 1 to 5, characterized in that: The signal transmission circuit also includes a pre-emphasis circuit; The pre-emphasis circuit is used to increase the high-frequency component of the output differential signal according to the second input differential signal to compensate for the attenuation of the high-frequency component during transmission. The second input differential signal is a differential signal of the first input differential signal delayed by one clock cycle.

7. The signal transmission circuit according to claim 6, characterized in that: The second input differential signal includes a second input positive signal and a second input negative signal, the pre-emphasis circuit includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit, the negative signal pre-emphasis circuit is connected to the signal end of the second input negative signal, and the positive signal pre-emphasis circuit is connected to the signal end of the second input positive signal.

8. The signal transmission circuit according to any one of claims 1 to 5, characterized in that: The signal transmission circuit also includes a voltage conversion circuit; The voltage conversion circuit is used to receive an initial differential signal, the voltage amplitude of the initial differential signal is less than a voltage threshold; and perform voltage conversion on the initial differential signal to obtain the first input differential signal, the voltage amplitude of the first input differential signal is greater than or equal to the voltage threshold.

9. The signal transmission circuit according to claim 8, characterized in that: The initial differential signal includes an initial positive signal and an initial negative signal, the first input differential signal includes a first input positive signal and a first input negative signal, and the voltage conversion circuit includes a first conversion circuit and a second conversion circuit; The first conversion circuit is used to convert the initial positive signal into the first input positive signal; The second conversion circuit is used to convert the initial negative signal into the first input negative signal.

10. A chip, characterized in that: The chip includes the signal sending circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises the signal sending circuit as claimed in any one of claims 1 to 9.

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