Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a pixel circuit; the driving circuit is used for receiving the first power supply signal and the second power supply signal, generating a gate driving signal according to the first power supply signal and the second power supply signal, and providing the gate driving signal to the corresponding pixel circuit; the plurality of demultiplexer units are used for receiving the data signals and controlling the data signals to be transmitted to the corresponding data signal lines under the action of the branch control signals; wherein the shunt control signal comprises a first low level signal and a first high level signal, and the absolute value of the difference between the first power supply signal and the second power supply signal is different from the absolute value of the difference between the first low level signal and the first high level signal. The display panel provided by the invention has relatively low power consumption.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As an important part of the information industry, display technology has played an important role in the development of information technology. With the development of display technology, organic light emitting diode display panels and other types of display panels have been widely used.

[0003] However, the display panel in the related art has the problem of high power consumption. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to reduce the power consumption of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including:

[0006] Pixel circuit;

[0007] A driving circuit, the driving circuit is used to provide a gate driving signal to the corresponding pixel circuit, wherein the driving circuit is also used to receive a first power signal and a second power signal, and to generate a gate driving signal according to the first power signal and the second power signal;

[0008] A plurality of demultiplexer units, each of which comprises a signal input terminal, a plurality of signal output terminals and a plurality of branch control terminals, wherein the signal input terminal is used to receive a data signal, each of the signal output terminals is respectively connected to a corresponding data signal line, and each of the branch control terminals is respectively used to receive a branch control signal, so as to control the data signal to be transmitted to the corresponding data signal line under the action of the branch control signal;

[0009] The branch control signal includes a first low-level signal and a first high-level signal, and the absolute value of the difference between the first power signal and the second power signal is different from the absolute value of the difference between the first low-level signal and the first high-level signal.

[0010] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.

[0011] The display panel provided in the embodiment of the present application includes a pixel circuit, a driving circuit and a plurality of demultiplexer units. The driving circuit is used to receive a first power supply signal and a second power supply signal, generate a gate driving signal according to the first power supply signal and the second power supply signal, and then provide the generated gate driving signal to the corresponding pixel circuit. The demultiplexer unit is used to control the data signal to be transmitted to the corresponding data signal line under the action of a branch control signal, thereby providing the data signal to the pixel circuit. In the present application, by setting the absolute value of the difference between the first power supply signal and the second power supply signal to be different from the absolute value of the difference between the first low-level signal and the first high-level signal in the branch control signal, the energy efficiency waste caused by using the same amplitude driving voltage for the demultiplexer and the driving circuit in the related art can be avoided, and refined control can be achieved to reduce the power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0013] Figure 2 A waveform diagram of a branch control signal provided in an embodiment of the present application;

[0014] Figure 3 A schematic diagram of another display panel provided in an embodiment of the present application;

[0015] Figure 4 A circuit structure diagram of a pixel circuit provided in an embodiment of the present application;

[0016] Figure 5 A schematic diagram of another display panel provided in an embodiment of the present application;

[0017] Figure 6 A circuit structure diagram of a light emitting control driving circuit provided in an embodiment of the present application;

[0018] Figure 7 A circuit structure diagram of a first driving unit provided in an embodiment of the present application;

[0019] Figure 8 A circuit structure diagram of a second driving unit provided in an embodiment of the present application;

[0020] Fig. 9 A circuit structure diagram of another pixel circuit provided in an embodiment of the present application;

[0021] Fig.10 A schematic diagram of another display panel provided in an embodiment of the present application;

[0022] Fig.11 A circuit structure diagram of another light emitting control driving circuit provided in an embodiment of the present application;

[0023] Fig.12 A circuit structure diagram of a fourth driving unit provided in an embodiment of the present application;

[0024] Fig.13 A circuit structure diagram of a fifth driving unit provided in an embodiment of the present application;

[0025] Fig.14 A circuit structure diagram of a third driving unit provided in an embodiment of the present application;

[0026] Fig.15 A circuit structure diagram of a sixth driving unit provided in an embodiment of the present application;

[0027] Fig.16 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0028] Explanation of the accompanying drawings: 10-pixel circuit, 20-driving circuit, 21-light-emitting control driving circuit, 22-scanning driving circuit, 221-first driving unit, 222-second driving unit, 223-third driving unit, 224-fourth driving unit, 225-fifth driving unit, 226-sixth driving unit, 30-multiplexer unit, 40-data signal line, 50-driving module, 51-branch signal output terminal group, 52-power signal output terminal group, 521-first power signal output terminal group, 53-clock signal output terminal group. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0031] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0032] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0033] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0034] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0035] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0036] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0037] As described in the background technology section, the display panel in the related art has the problem of high power consumption. The inventor found that the reason for the above phenomenon is that the driver chip of the display panel in the related art uses a relatively compatible large-amplitude voltage to drive the pixel circuit and multiplexing circuit of the display panel, and the voltage flowing through the transistor in different areas of the display panel is different. If the same amplitude voltage is used for driving, there will be a certain energy efficiency waste.

[0038] Based on the above technical problems, the inventors have found that the pixel circuit and the multiplexing circuit of the display panel are driven by voltages of different amplitudes, which can improve the energy efficiency waste phenomenon. Based on this, the inventors further studied the technical solution of the embodiment of the present application. Specifically, the display panel provided by the embodiment of the present application includes a pixel circuit, a driving circuit and a plurality of multiplexer units, the driving circuit is used to provide a gate drive signal to the corresponding pixel circuit, wherein the driving circuit is also used to receive a first power supply signal and a second power supply signal, and is used to generate a gate drive signal according to the first power supply signal and the second power supply signal; the multiplexer unit includes a signal input terminal, a plurality of signal output terminals and a plurality of branch control terminals, the signal input terminal is used to receive a data signal, each signal output terminal is respectively connected to each data signal line, and each branch control terminal is respectively used to receive each branch control signal, so as to control the data signal to be transmitted to the corresponding data signal line under the action of the branch control signal; wherein the branch control signal includes a first low level signal and a first high level signal, and the absolute value of the difference between the first power supply signal and the second power supply signal is different from the absolute value of the difference between the first low level signal and the first high level signal. By adopting the above technical solution, by providing the multiplexer with a branch control signal with an amplitude different from the first power supply signal and the second power supply signal used to generate the gate drive signal, the multiplexer and the drive circuit can be driven with independent amplitudes respectively. This can avoid the energy waste caused by using a compatible large-amplitude voltage for driving and reduce the power consumption of the display panel.

[0039] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] In an exemplary embodiment, see Figure 1 and Figure 2 The present application provides a display panel 100 , which includes: a pixel circuit 10 , a driving circuit 20 and a multiplexer unit 30 .

[0041] The driving circuit 20 is used to provide a gate driving signal to the corresponding pixel circuit 10, wherein the driving circuit is also used to receive a first power signal VGH1 and a second power signal VGL1, and to generate a gate driving signal according to the first power signal VGH1 and the second power signal VGL1; the multiplexer unit 30 includes a signal input terminal, multiple signal output terminals and multiple branch control terminals, the signal input terminal is used to receive a data signal Data, each signal output terminal is respectively connected to each data signal line 40, and each branch control terminal is respectively used to receive each branch control signal Mux, so as to control the data signal Data to be transmitted to the corresponding data signal line 40 under the action of the branch control signal Mux; wherein the branch control signal Mux includes a first low-level signal VGL2 and a first high-level signal VGH2, and the absolute value of the difference between the first power signal VGH1 and the second power signal VGL1 is different from the absolute value of the difference between the first low-level signal VGL2 and the first high-level signal VGH2.

[0042] It can be understood that the display panel 100 includes a display area AA and a non-display area FA, each pixel circuit 10 is arranged in rows and columns in the display area AA, and each driving circuit 20 and each multiplexer 30 are respectively located in the non-display area FA. Each driving circuit 20 is used to receive a first power signal VGH1 and a second power signal VGL1, and provide each gate driving signal to the corresponding pixel circuit 10 according to the first power signal VGH1 and the second power signal VGL1 to control the on and off of each transistor in the pixel circuit. It can be understood that the gate driving signal is a pulse signal composed of the first power signal VGH1 and the second power signal VGL1. When the gate driving signal is at an effective level, the corresponding transistor in the pixel circuit is turned on, and when the gate driving signal is at an invalid level, the corresponding transistor in the pixel circuit is turned off. The effective level of the gate driving signal is one of the first power signal VGH1 and the second power signal VGL1, and the invalid level of the gate driving signal is one of the first power signal VGH1 and the second power signal VGL1. The level state of the effective level of the gate driving signal is opposite to that of the invalid level. Each branch control terminal of the multiplexer 30 is used to receive each branch control signal Mux. For example, the multiplexer 30 includes four branch control terminals, each of which is used to receive each branch control signal Mux (branch control signal Mux1, branch control signal Mux2, branch control signal Mux3, branch control signal Mux4). The branch control signal Mux is a pulse signal. Figure 2 , Figure 2 is a waveform diagram of a branch control signal Mux in an example. It can be seen that the branch control signal Mux includes a first low level signal VGL2 and a first high level signal VGH2.

[0043] In the application, for TFT devices, whether N-type transistors or P-type transistors, the key factor that determines the on-off is not only the characteristics of the device itself, but also the gate-source voltage. When the source input voltage is different, the gate on-off voltage needs to be adjusted accordingly. Since the multiplexer 30 is only used to transmit the data signal Data, and the data signal Data is usually a positive voltage, the absolute value of the difference between the first low-level signal VGL2 and the first high-level signal VGH2 of the shunt control signal Mux used to control the on-off of each transistor in the multiplexer 30 can be different from the absolute value of the difference between the first power signal VGH1 and the second power signal VGL1 that form the gate drive signal. Specifically, the absolute value of the difference between the first power signal VGH1 and the second power signal VGL1 can be higher than the absolute value of the difference between the first low-level signal VGL2 and the first high-level signal VGH2. By providing a shunt control signal with a smaller voltage difference to the multiplexer, refined control can be achieved to avoid energy efficiency waste.

[0044] The display panel provided in the embodiment of the present application includes a pixel circuit, a driving circuit and a plurality of demultiplexer units. The driving circuit is used to receive a first power supply signal and a second power supply signal, generate a gate driving signal according to the first power supply signal and the second power supply signal, and then provide the generated gate driving signal to the corresponding pixel circuit. The demultiplexer unit is used to control the data signal to be transmitted to the corresponding data signal line under the action of a branch control signal, thereby providing the data signal to the pixel circuit. In the present application, by setting the absolute value of the difference between the first power supply signal and the second power supply signal to be different from the absolute value of the difference between the first low-level signal and the first high-level signal in the branch control signal, the energy efficiency waste caused by using the same amplitude driving voltage for the demultiplexer and the driving circuit in the related art can be avoided, and refined control can be achieved to reduce the power consumption of the display panel.

[0045] In an exemplary embodiment, the display panel 100 further includes a driving module 50, the driving module 50 includes a branch signal output terminal group 51 and at least one power signal output terminal group 52, each power signal output terminal group 52 includes a first power terminal and a second power terminal. The first power terminal and the second power terminal are respectively connected to the driving circuit 20, the first power terminal is used to output the first power signal VGH1, and the second power terminal is used to output the second power signal VGL1; the branch signal output terminal group 51 is respectively connected to each branch control terminal of the multiplexer unit 30, and is used to output the branch control signal Mux.

[0046] It can be understood that the driving module 50 may include a driving chip and a plurality of conductive pads, the driving chip is used to generate signals such as the first power signal VGH1, the second power signal VGL1 and the shunt control signal Mux, and is connected to the driving circuit 20 and the multiplexer unit 30 through the conductive pads to transmit the first power signal VGH1 and the second power signal VGL1 to each driving circuit, and transmit the shunt control signal Mux to the multiplexer unit 30. In another example, the driving chip may also be directly connected to the multiplexer unit 30 without the conductive pads, and directly transmit the shunt control signal Mux to the multiplexer unit 30.

[0047] In the present application, by writing a control program for the driver chip, the absolute value of the difference between the first power signal VGH1 and the second power signal VGL1 output by the driver chip can be made higher than the absolute value of the difference between the first low-level signal VGL2 and the first high-level signal VGH2 of the branch control signal Mux output by the driver chip, thereby achieving fine control of the pixel circuit 10 and the multiplexer 30 using voltages of independent amplitudes, thereby reducing the power consumption of the display panel.

[0048] In an exemplary embodiment, see Figure 4 and Figure 5 (For ease of review, Figure 5 Only the connection relationship between the driving module 50 and the primary driving circuit 20 is shown, and the multiplexer 30 and the remaining driving circuits 20 at each level are not shown). The conductivity type of each transistor of the pixel circuit 10 is the same, and the conductivity type of each transistor of the pixel circuit is P type; the driving circuit 20 includes a scanning driving circuit 22 and a light-emitting control driving circuit 21, wherein the power signal output terminal group 52 includes a first power signal output terminal group 521, the first power signal output terminal group includes 521 a first A power terminal and a second A power terminal, the first power signal includes a first A power signal VGH11, and the second power signal includes a second A power signal VGL11, wherein the first A power terminal is respectively connected to the scanning driving circuit and the light-emitting control driving circuit, and is used to provide the first A power signal VGH11 to the scanning driving circuit 22 and the light-emitting control driving circuit 21; the second A power terminal is respectively connected to the scanning driving circuit and the light-emitting control driving circuit, and is used to provide the second A power signal VGL11 to the scanning driving circuit 22 and the light-emitting control driving circuit 21.

[0049] In this embodiment, the pixel circuit 10 is an LTPS pixel circuit, and in this example, the LTPS pixel circuit of 8T1C is used as an example for description. The pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first reset transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, and a third reset transistor T8. The light emission control driving circuit 21 is used to provide a light emission control signal EM for the first light emission control transistor T5 and the second light emission control transistor T6, and the scanning driving circuit 22 is used to provide a scanning signal for the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T4, the second reset transistor T7, and the third reset transistor T8.

[0050] In an exemplary embodiment, the driving module 50 further includes:

[0051] At least one clock signal output terminal group 53, each clock signal output terminal group 53 includes a first clock signal terminal and a second clock signal terminal, each first clock signal terminal and each second clock signal terminal are respectively connected to the scanning driving circuit 22 and the light-emitting control driving circuit 21, each first clock signal terminal is used to provide a first clock signal XCK for the scanning driving circuit 22 and the light-emitting control driving circuit 21, the second clock signal terminal is respectively connected to the scanning driving circuit 22 and the light-emitting control driving circuit 21, and is used to provide a second clock signal CK for the scanning driving circuit 22 and the light-emitting control driving circuit 21, the first clock signal XCK and the second clock signal CK both include a second low-level signal VGL11 and a second high-level signal VGH11, the second high-level signal VGH11 is the same as the first A power supply signal VGH11, and the second low-level signal VGL11 is the same as the second A power supply signal VGL11.

[0052] In a detailed embodiment, please refer to Figures 4 to 8 The light-emitting control driving circuit 21 is respectively connected to a first power signal output terminal group 521 and a clock signal output terminal group 533, and is used to respond to the first clock signal XCK3 and the second clock signal CK3, and provide a light-emitting control signal EM for the corresponding pixel circuit 10 according to the first power signal A VGH11 and the second power signal A VGL11. The light-emitting control signal EM is used to control the pixel circuit 10 to provide a driving current for the light-emitting element D.

[0053] The scanning driving circuit 22 includes a first driving unit 221 and a second driving unit 222. The first driving unit 221 is connected to a first power signal output terminal group 521 and a clock signal output terminal group 532, respectively, and is used to respond to the first clock signal XCK2 and the second clock signal CK2, and provide a first scanning signal SP1 for the corresponding pixel circuit 10 according to the first A power signal VGH11 and the second A power signal VGL11, and the first scanning signal SP1 is used to control the reset process of the pixel circuit 10. The second driving unit 222 is connected to the first power signal output terminal group 521 and the clock signal output terminal group 53, respectively, and the second driving unit 222 is used to respond to the first clock signal XCK1 and the second clock signal CK1, and provide a second scanning signal SP2 for the corresponding pixel circuit 10 according to the first A power signal VGH11 and the first clock signal XCK1, and the second scanning signal SP2 is used to control the data writing process of the pixel circuit 10.

[0054] Figure 6 FIG. 2 is a circuit structure diagram of a light emitting control driving circuit 21 in an example. Figure 7 is a circuit structure diagram of the first driving unit 221 in an example, Figure 8 FIG. 2 is a circuit structure diagram of the second driving unit 222 in an example.

[0055] The light-emitting control driving circuit 21 is used to receive the input signal STV3, the first clock signal XCK3, the second clock signal CK3, the first A power signal VGH11 and the second A power signal VGL11, and respond to the first clock signal XCK3 and the second clock signal CK3, and provide the light-emitting control signal EM for the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the pixel circuit according to the first A power signal VGH11 and the second A power signal VGL11. Since the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both P-type transistors, the effective level of the light-emitting control signal EM is a low level, and the invalid level is a high level. When the light-emitting control driving circuit 21 outputs the light-emitting control signal EM of the high level VGH11, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off; when the light-emitting control driving circuit 21 outputs the light-emitting control signal EM of the low level VGL11, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving transistor T1 provides the driving current for the light-emitting element D.

[0056] The first driving unit 221 is used to receive the input signal STV2, the first clock signal XCK2, the second clock signal CK2, the first A power signal VGH11 and the second A power signal VGL11, and respond to the first clock signal XCK2 and the second clock signal CK2, and provide the first scanning signal SP1 for the first reset transistor T4, the second reset transistor T7 and the third reset transistor T8 in the pixel circuit according to the first A power signal VGH11 and the second A power signal VGL11. Since the first reset transistor T4, the second reset transistor T7 and the third reset transistor T8 are all P-type transistors, the effective level of the first scanning signal SP1 is a low level, and the invalid level is a high level. When the first driving unit 221 outputs the first scanning signal SP1 of the high level VGH11, the first reset transistor T4, the second reset transistor T7 and the third reset transistor T8 are turned off; when the first driving unit 221 outputs the first scanning signal SP1 of the low level VGL11, the first reset transistor T4, the second reset transistor T7 and the third reset transistor T8 are turned on, the first reset signal Vref1 is used to reset the gate of the driving transistor T1 through the first reset transistor T4, the second reset signal Vref2 is used to reset the anode of the light-emitting element through the second reset transistor T7, and the bias adjustment signal DVH is used to reset the source of the driving transistor T1 through the third reset transistor T8.

[0057] The second driving unit 222 is used to receive the input signal STV1, the first clock signal XCK1, the second clock signal CK1, the first A power signal VGH11 and the second A power signal VGL11, and respond to the first clock signal XCK1 and the second clock signal CK1, and provide the second scanning signal SP2 for the data writing transistor T2 and the threshold compensation transistor T3 in the pixel circuit according to the first clock signal XCK1 and the first A power signal VGH11. The first clock signal XCK1 includes a second low level signal VGL11 and a second high level signal VGH11. The second high level signal VGH11 has the same size as the first A power signal VGH11, and the second low level signal VGL11 has the same size as the second A power signal VGL11. Since the data writing transistor T2 and the threshold compensation transistor T3 are both P-type transistors, the effective level of the second scanning signal SP2 is a low level, and the invalid level is a high level. When the second driving unit 222 outputs a high-level signal of VGH11, the data writing transistor T2 and the threshold compensation transistor T3 are turned off; when the second driving unit 222 outputs a low-level signal of VGL11, the data writing transistor T2 and the threshold compensation transistor T3 are turned on, and the data signal Data is written into the gate of the driving transistor T1 through the data writing transistor T2 and the threshold compensation transistor T3.

[0058] It can be understood that in this example, the transistors in the light-emitting control driving circuit 21, the first driving unit 221 and the second driving unit 222 are all P-type transistors, so the input signal STV, the first clock signal XCK, and the second clock signal CK used to control the on and off of each transistor in the light-emitting control driving circuit 21, the first driving unit 221 and the second driving unit 222 all include a second low-level signal VGL11 and a second high-level signal VGH11, the second high-level signal VGH11 is the same as the first A power supply signal VGH11, and the second low-level signal VGL11 is the same as the second A power supply signal VGL11.

[0059] In this embodiment, by controlling the pixel circuit 10 and the scanning circuit 20 with a set of voltages with independent amplitudes and controlling the multiplexer 30 with another set of voltages with independent amplitudes, refined control can be achieved and the power consumption of the display panel can be reduced.

[0060] In an exemplary embodiment, see Fig. 9 and Fig.10 (For ease of review, Fig.10 Only the connection relationship between the driving module 50 and the first-stage driving circuit 20 is shown, and the multiplexer 30 and the remaining driving circuits 20 at each stage are not shown). In the pixel circuit 10 of this embodiment, at least two transistors have different conductivity types, and the driving circuit 20 includes a scanning driving circuit 22 and a light-emitting control driving circuit 21. The driving module 50 includes a second power signal output terminal group 522 and a third power signal output terminal group 523, the second power signal output terminal group includes a first B power terminal and a second B power terminal, and the third power signal output terminal group includes a first C power terminal and a second C power terminal; the first power signal VGH1 includes a first B power signal VGH12 and a first C power signal VGH13, and the second power signal VGL1 includes a second B power signal VGL12 and a second C power signal VGL13.

[0061] The first B power supply terminal and the second B power supply terminal are connected to the scan driving circuit 22 and the light emitting control driving circuit 21, respectively, and are used to provide the corresponding first B power supply signal VGH12 and the second B power supply signal VGL12 to the scan driving circuit 22 and the light emitting control driving circuit 21. The first C power supply terminal and the second C power supply terminal are connected to the scan driving circuit 22, respectively, and are used to provide the corresponding first C power supply signal VGH13 and the second C power supply signal VGL13 to the scan driving circuit 22; wherein the absolute value of the difference between the first B power supply signal VGH12 and the second B power supply signal VGL12 is different from the absolute value of the difference between the first C power supply signal VGH13 and the second C power supply signal VGL13.

[0062] In this embodiment, the pixel circuit 10 is an LTPO pixel circuit, and in this example, the LTPS pixel circuit of 8T1C is used as an example for description. The pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first reset transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, and a third reset transistor T8. The driving transistor T1, the data writing transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7, and the third reset transistor T8 are P-type transistors, and the threshold compensation transistor T3 and the first reset transistor T4 are N-type transistors.

[0063] The light emitting control driving circuit 21 is used to provide the light emitting control signal EM to the first light emitting control transistor T5 and the second light emitting control transistor T6 according to the first B power supply signal VGH12 and the second B power supply signal VGL12. Some driving units in the scanning driving circuit 22 are used to provide scanning signals to some P-type transistors in the pixel circuit according to the first B power supply signal VGH12 and the second B power supply signal VGL12, and some driving units are used to provide scanning signals to N-type transistors in the pixel circuit according to the first C power supply signal VGH13 and the second C power supply signal VGL13.

[0064] In the present application, the magnitude of the first B power signal VGH12 is the same as the magnitude of the first A power signal VGH11 in the above embodiment, and the magnitude of the second B power signal VGL12 is the same as the magnitude of the second A power signal VGL11 in the above embodiment. In addition, since the first B power signal VGH12 and the second B power signal VGL12 provide scanning signals for some P-type transistors in the pixel circuit, and the first C power signal VGH13 and the second C power signal VGL13 provide scanning signals for N-type transistors in the pixel circuit, the absolute value of the difference between the first B power signal VGH12 and the second B power signal VGL12 can be higher than the difference between the first C power signal VGH13 and the second C power signal VGL13.

[0065] Similar to the above-mentioned embodiment of the LTPS pixel circuit, the driving module 50 in this embodiment also includes at least one clock signal output terminal group 53 ( Fig.10), each clock signal output terminal group 53 includes a first clock signal terminal and a second clock signal terminal, each first clock signal terminal and each second clock signal terminal are respectively connected to the scanning driving circuit 22 and the light-emitting control driving circuit 21, each first clock signal terminal is used to provide the first clock signal XCK for the scanning driving circuit 22 and the light-emitting control driving circuit 21, the second clock signal terminal is respectively connected to the scanning driving circuit 22 and the light-emitting control driving circuit 21, and is used to provide the second clock signal CK for the scanning driving circuit 22 and the light-emitting control driving circuit 21, the first clock signal XCK and the second clock signal CK both include a second low-level signal VGL11 and a second high-level signal VGH11, the second high-level signal VGH11 is the same as the first B power supply signal VGH12, and the second low-level signal VGL11 is the same as the second B power supply signal VGL12.

[0066] For a detailed example, see Figures 9 to 15 The scan driving circuit 22 includes a third driving unit 223 , a fourth driving unit 224 , a fifth driving unit 225 and a sixth driving unit 226 . Fig.11 FIG. 2 is a circuit structure diagram of a light emitting control driving circuit 21 in an example. Fig.12 is a circuit structure diagram of the fourth driving unit 224 in an example, Fig.13 is a circuit structure diagram of the fifth driving unit 225 in an example, Fig.14 is a circuit structure diagram of the third driving unit 223 in an example, Fig.14 FIG. 2 is a circuit structure diagram of the sixth driving unit 226 in an example.

[0067] The light-emitting control driving circuit 21 is used to receive the input signal STV4, the first clock signal XCK4, the second clock signal CK4, the first B power supply signal VGH12 and the second B power supply signal VGL12, and respond to the first clock signal XCK4 and the second clock signal CK4, and provide the light-emitting control signal EM for the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the pixel circuit 10 according to the first B power supply signal VGH12 and the second B power supply signal VGL12. Since the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both P-type transistors, the effective level of the light-emitting control signal EM is a low level, and the invalid level is a high level. When the light-emitting control driving circuit 21 outputs the light-emitting control signal EM of the high level VGH11, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off; when the light-emitting control driving circuit 21 outputs the light-emitting control signal EM of the low level VGL11, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving transistor T1 provides the driving current for the light-emitting element D.

[0068] The third driving unit 223 is connected to the second power signal output terminal group 522 and a clock signal output terminal group, and is used to receive the input signal STV7, the first clock signal XCK7, the second clock signal CK7, the first B power signal VGH12 and the second B power signal VGL12, and respond to the first clock signal XCK7 and the second clock signal CK7, and provide the third scanning signal SP3 for the corresponding pixel circuit according to the first B power signal VGH12 and the second B power signal VGL12. Since the second reset transistor T7 and the eighth reset transistor T8 are both P-type transistors, the effective level of the third scanning signal SP3 is a low level, and the ineffective level is a high level. When the third driving unit 223 outputs the third scanning signal SP3 of the high level VGH12, the second reset transistor T7 and the third reset transistor T8 are turned off; when the third driving unit 223 outputs the third scanning signal SP3 of the low level VGL12, the second reset transistor T7 and the third reset transistor T8 are turned on, the second reset signal Vref2 is reset as the anode of the light-emitting element through the second reset transistor T7, and the bias adjustment signal DVH is reset as the source of the driving transistor T1 through the third reset transistor T8.

[0069] The fourth driving unit 224 is connected to the second power signal output terminal group 522, the third power signal output terminal group 523 and the clock signal output terminal group, respectively, and is used to receive the input signal STV5, the first clock signal XCK5, the second clock signal CK5, the first B power signal VGH12, the second B power signal VGL12, the first C power signal VGH13 and the second C power signal VGL13, and respond to the first clock signal XCK5 and the second clock signal CK5, and provide the fourth scanning signal SN1 for the corresponding pixel circuit according to the first C power signal VGH13 and the second C power signal VGL13. Since the threshold compensation transistor T3 is an N-type transistor, the effective level of the fourth scanning signal SN1 is a high level, and the invalid level is a low level. When the fourth driving unit 224 outputs the fourth scanning signal SN1 of the low level VGL13, the threshold compensation transistor T3 is turned off; when the fourth driving unit 224 outputs the fourth scanning signal SN1 of the high level VGH13, the threshold compensation transistor T3 is turned on.

[0070] The fifth driving unit 225 is connected to the second power signal output terminal group 522, the third power signal output terminal group 523 and the clock signal output terminal group respectively, and is used to receive the input signal STV6, the first clock signal XCK6, the second clock signal CK6, the first B power signal VGH12, the second B power signal VGL12, the first C power signal VGH13 and the second C power signal VGL13, and respond to the first clock signal XCK6 and the second clock signal CK6, and provide the fifth scanning signal SN2 for the corresponding pixel circuit according to the first C power signal VGH13 and the second C power signal VGL13. Since the first reset transistor T4 is an N-type transistor, the effective level of the fifth scanning signal SN2 is a high level, and the ineffective level is a low level. When the fifth driving unit 225 outputs the fifth scanning signal SN2 of the low level VGL13, the first reset transistor T4 is turned off; when the fifth driving unit 225 outputs the fifth scanning signal SN2 of the high level VGH13, the first reset signal Vref1 resets the gate of the driving transistor T1 through the first reset transistor T4.

[0071] It should be understood that in this example, the transistors in the fourth driving unit 224 and the fifth driving unit 225 are all P-type transistors. In this application, the magnitude of the high-level signal in the control signal for controlling the on-off of the P-type transistors in the pixel circuit and the driving circuit is VGH12 or VGH11, and the magnitude of the low-level signal in the control signal for controlling the on-off of the P-type transistors in the pixel circuit and the driving circuit is VGL12 or VGL11. Therefore, the fourth driving unit 224 and the fifth driving unit 225 also need to be connected to the second power supply signal output terminal group 522 to receive the first B power supply signal VGH12 and the second B power supply signal VGL12, so that the corresponding transistors in the fourth driving unit 224 and the fifth driving unit 225 respond to the first B power supply signal VGH12 and the second B power supply signal VGL12 to turn off or turn on. In one example, when the driving circuit 20 includes an N-type transistor, the first C power supply signal VGH13 and the second C power supply signal VGL13 can be used to control the N-type transistor in the driving circuit 20.

[0072] The sixth driving unit 226 is used to receive the input signal STV8, the first clock signal XCK8, the second clock signal CK8, the first B power supply signal VGH12 and the second B power supply signal VGL12, and respond to the first clock signal XCK8 and the second clock signal CK8, and provide the sixth scanning signal SP4 for the data writing transistor T2 in the pixel circuit according to the first clock signal XCK8 and the first B power supply signal VGH12. The first clock signal XCK8 includes a second low level signal VGL11 and a second high level signal VGH11. The second high level signal VGH11 is the same as the first B power supply signal VGH12, and the second low level signal VGL11 is the same as the second B power supply signal VGL12. Since the data writing transistor T2 is a P-type transistor, the effective level of the sixth scanning signal SP4 is a low level, and the invalid level is a high level. When the sixth driving unit 226 outputs a high level signal of VGH12, the data writing transistor T2 is turned off; when the sixth driving unit 226 outputs a low level signal of VGL12, the data writing transistor T2 is turned on.

[0073] In this embodiment, by controlling the multiplexer 30 with a set of voltages with independent amplitudes and controlling the P-type transistors and N-type transistors in the pixel circuit 10 and the scanning circuit 20 with a set of voltages with independent amplitudes respectively, refined control can be further achieved and the power consumption of the display panel can be reduced.

[0074] It can be understood that, in this example, the transistors in the light-emitting control driving circuit 21, the third driving unit 223, the fourth driving unit 224, the fifth driving unit 225 and the sixth driving unit 226 are all P-type transistors, so the input signal STV, the first clock signal XCK and the second clock signal CK used to control the on and off of each transistor in the light-emitting control driving circuit 21, the third driving unit 223, the fourth driving unit 224, the fifth driving unit 225 and the sixth driving unit 226 all include a second low-level signal VGL11 and a second high-level signal VGH11, the second high-level signal VGH11 is the same as the first B power supply signal VGH12, and the second low-level signal VGL11 is the same as the second B power supply signal VGL12.

[0075] Based on the same application concept, an embodiment of the present application also provides a display device. Fig.16 A schematic diagram of the structure of a display device 200 provided in an embodiment of the present application is shown in FIG. Fig.16 As shown, the display device 200 includes the display panel 100 in any of the above embodiments. Fig.16As shown, the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0076] The display device 200 provided in the embodiment of the present application can be Fig.16 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0077] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: Pixel circuit; A driving circuit, the driving circuit is used to provide a gate driving signal to the corresponding pixel circuit, wherein the driving circuit is also used to receive a first power signal and a second power signal, and to generate a gate driving signal according to the first power signal and the second power signal; A plurality of demultiplexer units, each of which comprises a signal input terminal, a plurality of signal output terminals and a plurality of branch control terminals, wherein the signal input terminal is used to receive a data signal, each of the signal output terminals is respectively connected to a corresponding data signal line, and each of the branch control terminals is respectively used to receive a branch control signal, so as to control the data signal to be transmitted to the corresponding data signal line under the action of the branch control signal; The branch control signal includes a first low-level signal and a first high-level signal, and the absolute value of the difference between the first power signal and the second power signal is different from the absolute value of the difference between the first low-level signal and the first high-level signal.

2. The display panel according to claim 1, characterized in that: An absolute value of a difference between the first power signal and the second power signal is higher than an absolute value of a difference between the first low level signal and the first high level signal.

3. The display panel according to claim 1, characterized in that: The display panel further comprises: a driving module, the driving module comprising a branch signal output terminal group and at least one power signal output terminal group, each of the power signal output terminal groups comprising a first power terminal and a second power terminal; Wherein, the first power supply end and the second power supply end are respectively connected to the driving circuit, the first power supply end is used to output the first power supply signal, and the second power supply end is used to output the second power supply signal; The branch signal output terminal group is respectively connected to each of the branch control terminals of the multiplexer unit to output the branch control signal.

4. The display panel according to claim 3, characterized in that: The conductive types of the transistors in the pixel circuit are the same; the driving circuit includes a scanning driving circuit and a light emitting control driving circuit, wherein: The power signal output terminal group includes a first power signal output terminal group, the first power signal output terminal group includes a first A power terminal and a second A power terminal, the first power signal includes a first A power signal, and the second power signal includes a second A power signal, wherein the first A power terminal is respectively connected to the scanning drive circuit and the light-emitting control drive circuit to provide the first A power signal to the scanning drive circuit and the light-emitting control drive circuit; the second A power terminal is respectively connected to the scanning drive circuit and the light-emitting control drive circuit to provide the second A power signal to the scanning drive circuit and the light-emitting control drive circuit.

5. The display panel according to claim 4, characterized in that: The conductivity type of each transistor of the pixel circuit is P type.

6. The display panel according to claim 4, characterized in that: The driving module further includes: At least one clock signal output terminal group, each of the clock signal output terminal groups includes a first clock signal terminal and a second clock signal terminal, each of the first clock signal terminals and each of the second clock signal terminals are respectively connected to the scanning drive circuit and the light-emitting control drive circuit, each of the first clock signal terminals is used to provide a first clock signal for the scanning drive circuit and the light-emitting control drive circuit, the second clock signal terminal is respectively connected to the scanning drive circuit and the light-emitting control drive circuit, and is used to provide a second clock signal for the scanning drive circuit and the light-emitting control drive circuit, the first clock signal and the second clock signal each include a second low-level signal and a second high-level signal, the second high-level signal is the same as the first A power supply signal, and the second low-level signal is the same as the second A power supply signal.

7. The display panel according to claim 6, characterized in that: The scanning driving circuit comprises: a first driving unit, the first driving unit being connected to the first power signal output terminal group and the clock signal output terminal group respectively, and being used for responding to the first clock signal and the second clock signal, and providing a first scanning signal for a corresponding pixel circuit according to the first A power signal and the second A power signal, wherein the first scanning signal is used for controlling a reset process of the pixel circuit; A second driving unit, the second driving unit is respectively connected to the first power signal output terminal group and the clock signal output terminal group, the second driving unit is used to respond to the first clock signal and the second clock signal, and provide a second scanning signal for the corresponding pixel circuit according to the first power signal A and the first clock signal, and the second scanning signal is used to control the data writing process of the pixel circuit.

8. The display panel according to claim 3, characterized in that: In the pixel circuit, at least two transistors have different conductivity types, and the driving circuit includes a scanning driving circuit and a light emitting control driving circuit, wherein: The driving module includes a second power signal output terminal group and a third power signal output terminal group, the second power signal output terminal group includes a first B power terminal and a second B power terminal, the third power signal output terminal group includes a first C power terminal and a second C power terminal; the first power signal includes a first B power signal and a first C power signal, the second power signal includes a second B power signal and a second C power signal, wherein, The first B power supply terminal and the second B power supply terminal are connected to the scan driving circuit and the light emitting control driving circuit respectively, and are used to provide the scan driving circuit and the light emitting control driving circuit with corresponding first B power supply signals and second B power supply signals; The first C power supply terminal and the second C power supply terminal are respectively connected to the scan driving circuit, and are used to provide the scan driving circuit with corresponding first C power supply signals and second C power supply signals; wherein, An absolute value of a difference between the first B power signal and the second B power signal is different from an absolute value of a difference between the first C power signal and the second C power signal.

9. The display panel according to claim 8, characterized in that: An absolute value of a difference between the first B power signal and the second B power signal is higher than a difference between the first C power signal and the second C power signal.

10. The display panel according to claim 8, characterized in that: The scanning driving circuit comprises: a third driving unit, connected to the second power signal output terminal group, for providing a third scanning signal to the corresponding pixel circuit according to the first B power signal and the second B power signal, wherein the third scanning signal is used to control a reset process of a source electrode of a driving transistor and a reset process of an anode electrode of a light-emitting element in the pixel circuit; a fourth driving unit connected to the third power signal output terminal group, and configured to provide a fourth scanning signal to the corresponding pixel circuit according to the first C power signal and the second C power signal, wherein the fourth scanning signal is used to control a threshold compensation process of the pixel circuit; A fifth driving unit is connected to the third power signal output terminal group, and is used to provide a fifth scanning signal for the corresponding pixel circuit according to the first C power signal and the second C power signal, and the fifth scanning signal is used to control the reset process of the gate of the driving transistor in the pixel circuit.

11. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 10.

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