Display substrate and display device

Abstract

The invention provides a display substrate and a display device, relates to the technical field of display, and aims to solve the problem that when a shifting register unit is applied to a display product, internal nodes of the shifting register unit are easily affected by coupling, and consequently output of the shifting register unit is unstable. The display substrate comprises a substrate body, a second level signal line and a gate drive circuit, wherein the second level signal line and the gate drive circuit are arranged on the substrate body. The gate drive circuit comprises a plurality of cascaded shift register units, each shift register unit comprises an output transistor, and the output transistor is coupled with a gate drive signal output end of the shift register unit; the second level signal line extends in the first direction, and the orthographic projection of the output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate. The orthographic projections of other transistor structures except the output transistor in the shift register unit on the substrate are located on the second side of the orthographic projection of the second level signal line on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the development of display products shows a trend of high integration and low cost. A very important technology used in display products is the mass production of GOA (English: Gate Driver on Array; Chinese: integrated gate drive circuit) technology. The gate drive circuit is integrated on the array substrate of the display panel using GOA technology, so that the gate drive integrated circuit part can be omitted to reduce product costs in terms of material cost and manufacturing process. This gate drive circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit, where each shift register circuit in the gate drive circuit is also called a shift register unit.

[0003] However, currently when the shift register unit is applied to display products, there is a problem that the internal nodes of the shift register unit are easily affected by coupling, resulting in unstable output of the shift register unit. Summary of the invention

[0004] The object of the present invention is to provide a display substrate and a display device for solving the problem that when a shift register unit is applied to a display product, internal nodes of the shift register unit are easily affected by coupling, resulting in unstable output of the shift register unit.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display substrate, comprising a base substrate, a second level signal line and a gate driving circuit arranged on the base substrate; the gate driving circuit comprises a plurality of cascaded shift register units, the shift register unit comprises an output transistor, and the output transistor is coupled to a gate driving signal output terminal of the shift register unit;

[0007] The second-level signal line extends along a first direction, the orthographic projection of the output transistor on the substrate is located on a first side of the orthographic projection of the second-level signal line on the substrate, the orthographic projections of other transistor structures in the shift register unit except the output transistor on the substrate are located on a second side of the orthographic projection of the second-level signal line on the substrate, the first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

[0008] Optionally, the display substrate also includes a first level signal line; the shift register unit also includes: a first output node and a first output transistor; the gate of the first output transistor is coupled to the first output node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate drive signal output end of the shift register unit; the orthographic projection of the first output transistor on the base substrate is located on the first side of the orthographic projection of the second level signal line on the base substrate.

[0009] Optionally, the shift register unit further includes: a first coupling node and a second capacitor; a first plate of the second capacitor is coupled to the first output node, and a second plate of the second capacitor is coupled to the first coupling node;

[0010] The orthographic projection of the second electrode plate of the second capacitor on the base substrate is located at a second side of the orthographic projection of the second level signal line on the base substrate, and is adjacent to the orthographic projection of the second level signal line on the base substrate.

[0011] Optionally, the orthographic projection of the second level signal line on the base substrate of the display substrate is located between the orthographic projection of the second electrode plate of the second capacitor on the base substrate and the orthographic projection of the active layer of the first output transistor on the base substrate;

[0012] The shift register unit also includes an eighth control transistor; the gate of the eighth control transistor is coupled to the first output node, the first electrode of the eighth control transistor is coupled to the first clock signal input terminal, and the second electrode of the eighth control transistor is coupled to the first coupling node; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the eighth control transistor on the substrate are arranged along the first direction.

[0013] Optionally, the shift register unit also includes: a second output node and a second output transistor; the gate of the second output transistor is coupled to the second output node, the first electrode of the second output transistor is coupled to the second level signal line, and the second electrode of the second output transistor is coupled to the gate drive signal output end of the shift register unit; the orthographic projection of the second output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate.

[0014] Optionally, the shift register unit also includes a third capacitor, a first plate of the third capacitor is coupled to the gate of the second output transistor, and a second plate of the third capacitor is coupled to the second level signal line; the orthographic projection of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the second level signal line on the substrate.

[0015] Optionally, the shift register unit further includes a seventh control transistor, a gate of the seventh control transistor is coupled to the first output node in the shift register unit, a first electrode of the seventh control transistor is coupled to the second level signal line, and a second electrode of the seventh control transistor is coupled to the second output node in the shift register unit;

[0016] At least a portion of an orthographic projection of the active layer of the seventh control transistor on the base substrate is located on a second side of an orthographic projection of the second-level signal line on the base substrate.

[0017] Optionally, the display substrate further includes a plurality of sub-pixel rows; the shift register unit is used to drive two sub-pixel rows;

[0018] The orthographic projection of the second plate of the second capacitor in the shift register unit on the base substrate and the orthographic projection of the active layer of the seventh control transistor on the base substrate are arranged along the first direction.

[0019] Optionally, the gate of the seventh control transistor and the gate of the first output transistor in the shift register unit form an integrated structure.

[0020] Optionally, the shift register unit further includes a fifth control transistor and a sixth control transistor; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first electrode of the fifth control transistor is coupled to the second level signal line, and the second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second electrode of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor form an active layer of an integrated structure, and the active layer of the integrated structure extends along the second direction; the orthographic projection of the active layer of the eighth control transistor on the substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate; and / or,

[0021] The shift register unit also includes a second coupling node, a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to the first level signal line, and the second electrode of the first control transistor is coupled to the second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to the second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node. point coupling; the gate of the fourth control transistor is coupled to the first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to the second output node; the orthographic projection of the second plate of the second capacitor on the substrate, the orthographic projection of the active layer of the fourth control transistor on the substrate, the orthographic projection of the active layer of the second control transistor on the substrate, and the orthographic projection of the active layer of the third control transistor on the substrate are arranged in sequence along the first direction; the orthographic projection of the active layer of the second control transistor on the substrate is located between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the second level signal line on the substrate.

[0022] Optionally, the display substrate further includes a plurality of sub-pixel rows; the shift register unit is used to drive a sub-pixel row;

[0023] At least part of the orthographic projection of the active layer of the eighth control transistor in the shift register unit on the base substrate is located between the orthographic projection of the active layer of the seventh control transistor on the base substrate and the orthographic projection of the second-level signal line on the base substrate.

[0024] Optionally, the gate of the seventh control transistor and the gate of the eighth control transistor form an integrated structure.

[0025] Optionally, the shift register unit further includes a fourth control transistor, a fifth control transistor and a sixth control transistor; the gate of the fourth control transistor is coupled to the first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to the second output node; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first electrode of the fifth control transistor is coupled to the second level signal line, and the second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second electrode of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor form an active layer of an integrated structure, and the active layer of the integrated structure extends along the first direction; at least part of the positive projection of the active layer of the fourth control transistor on the substrate substrate is located between the positive projection of the second plate of the second capacitor on the substrate substrate and the positive projection of the active layer of the integrated structure on the substrate substrate; at least part of the active layer of the seventh control transistor is located between the active layer of the integrated structure and the active layer of the fourth control transistor; and / or,

[0026] The shift register unit further includes a second coupling node, a first control transistor, a second control transistor and a third control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to the first level signal line, and the second electrode of the first control transistor is coupled to the second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to the second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the active layer of the seventh control transistor is located between the active layer of the first control transistor and the active layer of the eighth control transistor; the active layer of the first control transistor and the active layer of the third control transistor are arranged along the first direction, and at least part of the active layer of the second control transistor is located between the active layer of the first control transistor and the active layer of the third control transistor; the active layer of the first control transistor, the active layer of the second control transistor and the active layer of the third control transistor are coupled in sequence to form an integrated structure.

[0027] Optionally, the first-level signal line and the second-level signal line in the display substrate are arranged along the second direction; the orthographic projection of other transistor structures in the shift register unit except the output transistor on the base substrate is located between the orthographic projection of the first-level signal line on the base substrate and the orthographic projection of the second-level signal line on the base substrate.

[0028] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present invention provides a display device, comprising the above-mentioned display substrate.

[0029] In the technical solution provided by the present invention, the orthographic projection of the output transistor on the substrate is arranged to be located on the first side of the orthographic projection of the second-level signal line on the substrate, and the orthographic projections of other transistor structures in the shift register unit except the output transistor on the substrate are located on the second side of the orthographic projection of the second-level signal line on the substrate; so that the second-level signal line can separate the output transistor from the other transistor structures, thereby effectively reducing the coupling between the output node of the control output transistor and the other transistor structures, and the nodes coupled to the other transistor structures, avoiding the output node from being affected by the coupling, and further avoiding the output transistor from being affected by the coupling, thereby ensuring that the gate drive signal output end can output stably, effectively reducing the disturbance effect on the output waveform, and effectively improving the reliability of the shift register unit.

[0030] Therefore, in the display substrate provided by the embodiment of the present invention, the voltage stability of the internal nodes of the shift register unit is effectively improved, and the stability of the output signal of the shift register unit is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0032] Figure 1 A schematic cross-sectional view of a film layer of a display substrate provided by an embodiment of the present invention;

[0033] Figure 2 A circuit schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0034] Figure 3 A working timing diagram of a shift register unit provided by an embodiment of the present invention;

[0035] Figure 4 A signal waveform diagram of the N3 node provided in an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of the layout of an active layer in a shift register unit provided by an embodiment of the present invention;

[0037] Figure 6 A schematic diagram of the layout of a first gate metal layer in a shift register unit provided by an embodiment of the present invention;

[0038] Figure 7 A schematic diagram of the layout of a second gate metal layer in a shift register unit provided by an embodiment of the present invention;

[0039] Figure 8 A schematic diagram of the layout of an active layer and a first gate metal layer and a second gate metal layer in a shift register unit provided by an embodiment of the present invention;

[0040] Fig. 9 A schematic diagram of the layout of a first source-drain metal layer in a shift register unit provided by an embodiment of the present invention;

[0041] Fig.10 For Figure 8 A schematic diagram of a layout of adding a first source-drain metal layer on the basis of FIG.

[0042] Fig.11 For Figure 8 A schematic diagram of a layout of adding a first source-drain metal layer on the basis of FIG.

[0043] Fig.12 A schematic diagram of the layout of an active layer in another shift register unit provided by an embodiment of the present invention;

[0044] Fig.13 A schematic diagram of the layout of a first gate metal layer in another shift register unit provided by an embodiment of the present invention;

[0045] Fig.14 A schematic diagram of the layout of a second gate metal layer in another shift register unit provided by an embodiment of the present invention;

[0046] Fig.15 A schematic diagram of the layout of an active layer and a first gate metal layer and a second gate metal layer in another shift register unit provided by an embodiment of the present invention;

[0047] Fig.16 A schematic diagram of the layout of a first source-drain metal layer in another shift register unit provided by an embodiment of the present invention;

[0048] Fig.17 For Fig.15 A schematic diagram of a layout of adding a first source-drain metal layer on the basis of FIG.

[0049] Fig.18 For Fig.15A schematic diagram of a layout of adding a first source-drain metal layer on the basis of FIG.

[0050] Fig.19 Schematic diagram of the layout of two shift register units provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0052] See also Figure 2 , Figures 5 to 18 , an embodiment of the present invention provides a display substrate, comprising a base substrate, a second level signal line VGH' and a gate driving circuit arranged on the base substrate; the gate driving circuit comprises a plurality of cascaded shift register units 10, the shift register unit 10 comprises an output transistor (such as a first output transistor T10 and a second output transistor T9), and the output transistor is coupled to a gate driving signal output terminal OUT of the shift register unit 10;

[0053] The second-level signal line VGH' extends along a first direction, the orthographic projection of the output transistor on the substrate is located on a first side of the orthographic projection of the second-level signal line VGH' on the substrate, the orthographic projections of other transistor structures in the shift register unit 10 except the output transistor on the substrate are located on a second side of the orthographic projection of the second-level signal line VGH' on the substrate, the first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

[0054] Exemplarily, the display substrate also includes a first level signal line VGL'; the shift register unit 10 also includes: a first output node N3 and a first output transistor T10; a gate 310 of the first output transistor T10 is coupled to the first output node N3, a first electrode of the first output transistor T10 is coupled to the first level signal line VGL', and a second electrode of the first output transistor T10 is coupled to the gate drive signal output terminal OUT of the shift register unit 10; an orthographic projection of the first output transistor T10 on the substrate is located on a first side of an orthographic projection of the second level signal line VGH' on the substrate.

[0055] Exemplarily, the shift register unit 10 also includes: a second output node N5 and a second output transistor T9; a gate 39 of the second output transistor T9 is coupled to the second output node N5, a first electrode of the second output transistor T9 is coupled to the second level signal line VGH', and a second electrode of the second output transistor T9 is coupled to the gate drive signal output terminal OUT of the shift register unit 10; the orthographic projection of the second output transistor T9 on the substrate is located on the first side of the orthographic projection of the second level signal line VGH' on the substrate.

[0056] Exemplarily, the active layer 210 of the first output transistor T10 and the active layer 29 of the second output transistor T9 are arranged along the first direction.

[0057] Exemplarily, the first level signal line VGL' is used to transmit a first level signal, and the second level signal line VGH' is used to transmit a second level signal; for example: the first level signal includes a low level signal, and the second level signal includes a high level signal, but is not limited thereto.

[0058] It should be noted that Figure 1 Schematic diagram of a first level signal input terminal VGL and a second level signal input terminal VGH. The first level signal input terminal VGL is coupled to the first level signal line VGL′, and the second level signal input terminal VGH is coupled to the second level signal line VGH′.

[0059] like Figures 5 to 11 , Figures 13 to 18 As shown, illustratively, the orthographic projection of the second level signal line VGH' on the substrate substrate is located between the orthographic projection of the first level signal line VGL' on the substrate substrate and the orthographic projection of the output transistor on the substrate substrate. The shift register unit further includes an eleventh conductive connection portion 42, which is respectively coupled to the first electrode of the first output transistor T10 and the first level signal line VGL', and the orthographic projection of the eleventh conductive connection portion 42 on the substrate substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate substrate.

[0060] like Figures 5 to 11As shown, illustratively, the shift register unit further includes a first conductive connection portion 51, the first conductive connection portion 51 is respectively coupled to the first electrode of the input transistor T1, and the tenth conductive connection portion 41, the tenth conductive connection portion 41 is coupled to the gate drive signal output terminal of the previous stage shift register unit. The orthographic projection of the first conductive connection portion 51 on the substrate is located between the orthographic projections of the first level signal line VGL' and the second level signal line VGH' on the substrate.

[0061] like Figures 13 to 18 Exemplarily, the shift register unit further includes a twelfth conductive connection portion 61, the twelfth conductive connection portion 61, the twelfth conductive connection portion 61 is respectively coupled to the first electrode of the input transistor T1 and the tenth conductive connection portion 41, and the tenth conductive connection portion 41 is coupled to the gate drive signal output terminal of the previous stage shift register unit. The orthographic projection of the twelfth conductive connection portion 61 on the substrate is located between the orthographic projections of the first level signal line VGL' and the second level signal line VGH' on the substrate.

[0062] like Figures 5 to 11 As shown, exemplarily, the distance between the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate and the orthographic projection of the tenth conductive connection part 41 on the substrate is greater than the distance between the orthographic projection of the active layer 29 of the second output transistor T9 on the substrate and the orthographic projection of the tenth conductive connection part 41 on the substrate; this arrangement enables the plate of the third capacitor C3 to be away from the tenth conductive connection part 41, thereby effectively reducing the coupling effect of the signal transmitted by the tenth conductive connection part 41 on the third capacitor C3.

[0063] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present invention, by setting the orthographic projection of the output transistor on the base substrate to be located on the first side of the orthographic projection of the second-level signal line VGH' on the base substrate, the orthographic projections of other transistor structures in the shift register unit 10 except the output transistor on the base substrate are located on the second side of the orthographic projection of the second-level signal line VGH' on the base substrate; so that the second-level signal line VGH' can separate the output transistor from the other transistor structures, thereby effectively reducing the coupling between the output node (such as the first output node N3 and the second output node N5) of the control output transistor and the other transistor structures, as well as the nodes coupled with the other transistor structures, avoiding the output node from being affected by the coupling, and further avoiding the output transistor from being affected by the coupling, thereby ensuring that the gate drive signal output terminal OUT can output stably, effectively reducing the disturbance effect on the output waveform, and effectively improving the reliability of the shift register unit.

[0064] Therefore, in the display substrate provided by the embodiment of the present invention, the voltage stability of the internal nodes of the shift register unit 10 is effectively improved, and the stability of the output signal of the shift register unit 10 is also improved.

[0065] like Figure 2 , Figures 5 to 18 As shown, in some embodiments, the shift register unit 10 further includes: a first coupling node N0 and a second capacitor C2; a first plate C21 of the second capacitor C2 is coupled to the first output node N3, and a second plate C22 of the second capacitor C2 is coupled to the first coupling node N0;

[0066] The orthographic projection of the second electrode plate C22 of the second capacitor C2 on the base substrate is located at a second side of the orthographic projection of the second level signal line VGH' on the base substrate and is adjacent to the orthographic projection of the second level signal line VGH' on the base substrate.

[0067] Exemplarily, the orthographic projection of the second level signal line VGH' on the base substrate of the display substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the base substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the base substrate.

[0068] Exemplarily, the gate 310 of the first output transistor T10 and the first plate C21 of the second capacitor C2 form an integrated structure, and the orthographic projection of the integrated structure on the substrate overlaps with the orthographic projection of the second level signal line VGH′ on the substrate.

[0069] The above arrangement enables the second capacitor C2 to be arranged near the second level signal line VGH', effectively reducing the coupling effect of other AC signals on the second capacitor C2; further, the above arrangement enables the second level signal line VGH' to separate the second capacitor C2 and the first output transistor T10, reducing the coupling effect of other AC signals on the gate 310 potential of the first output transistor T10 through the second capacitor C2, reducing the gate 310 coupling capacitance of the first output transistor T10, thereby effectively reducing the step formed in the process of lowering the potential of the first output node N3, so that the gate drive signal output terminal OUT can output stably, effectively reducing the disturbance effect of the output waveform. Therefore, in the display substrate provided by the above embodiment, the voltage stability of the internal node (such as the first output node N3) of the shift register unit 10 is effectively improved, and the stability of the output signal of the shift register unit 10 is improved.

[0070] In more detail, Figure 4 As shown, in the layout of the existing shift register unit 10, there is a large step (such as L1) in the waveform when the first output node N3 is pulled down; in the layout of the shift register unit 10 of the display substrate provided by an embodiment of the present invention, the step height of the waveform is greatly reduced (such as L2) when the first output node N3 is pulled down.

[0071] like Figure 2 , Figures 5 to 18 As shown, in some embodiments, the orthographic projection of the second level signal line VGH' on the base substrate of the display substrate is located between the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the base substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the base substrate;

[0072] The shift register unit 10 also includes an eighth control transistor T11; a gate 311 of the eighth control transistor T11 is coupled to the first output node N3, a first electrode of the eighth control transistor T11 is coupled to the first clock signal input terminal CKB, and a second electrode of the eighth control transistor T11 is coupled to the first coupling node N0; an orthographic projection of a second electrode plate C22 of the second capacitor C2 on the substrate and an orthographic projection of an active layer 211 of the eighth control transistor T11 on the substrate are arranged along the first direction.

[0073] Exemplarily, the eighth control transistor T11 includes a dual-gate transistor structure, but is not limited thereto.

[0074] Exemplarily, the active layer 211 of the eighth control transistor T11 extends along the first direction, which helps to reduce the layout space occupied by the eighth control transistor T11 as a whole along the second direction.

[0075] Illustratively, along the first direction, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the base substrate is adjacent to the orthographic projection of the second plate C22 of the second capacitor C2 on the base substrate; along the second direction, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the base substrate is adjacent to the orthographic projection of the second level signal line VGH' on the base substrate.

[0076] Exemplarily, the gate 311 of the eighth control transistor T11, the gate 310 of the first output transistor T10 and the first electrode plate C21 of the second capacitor C2 form an integrated structure.

[0077] The above-mentioned configuration enables the eighth control transistor T11, the second capacitor C2 and the first output transistor T10 to be centrally arranged, which not only reduces the difficulty of connection among the three and ensures the reliability of the connection, but also helps to reduce the overall layout space occupied by the shift register unit 10, which is conducive to achieving a narrow frame for the display substrate.

[0078] like Figure 2 , Figures 5 to 18 As shown, in some embodiments, the shift register unit 10 also includes a third capacitor C3, a first plate C31 of the third capacitor C3 is coupled to the gate 39 of the second output transistor T9, and a second plate C32 of the third capacitor C3 is coupled to the second level signal line VGH'; the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0079] Exemplarily, the first plate C31 of the third capacitor C3 and the gate 39 of the second output transistor T9 form an integral structure. The orthographic projection of the first plate C31 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0080] Exemplarily, the display substrate also includes multiple rows of sub-pixel rows; when the shift register unit 10 is used to drive two rows of sub-pixel rows, the second plate C32 of the third capacitor C3 extends along the first direction; when the shift register unit 10 is used to drive one row of sub-pixel rows, the second plate C32 of the third capacitor C3 extends along the second direction.

[0081] Exemplarily, the orthographic projection of the second electrode plate C32 of the third capacitor C3 on the substrate is located inside the orthographic projection of the first electrode plate C31 of the third capacitor C3 on the substrate.

[0082] The orthographic projection of the second electrode plate C32 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate, which better saves the layout space occupied by the entire shift register unit 10 and is conducive to realizing a narrow frame of the display substrate.

[0083] like Figure 2 , Figures 5 to 18 As shown, in some embodiments, the second level signal line VGH' extends along a first direction; the active layer 210 of the first output transistor T10 and the active layer 29 of the second output transistor T9 are arranged along the first direction, and the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate and the orthographic projection of the active layer 29 of the second output transistor T9 on the substrate are arranged along a second direction, and the second direction intersects with the first direction.

[0084] Exemplarily, the orthographic projection of the second output transistor T9 on the substrate is located on the first side of the orthographic projection of the second level signal line VGH' on the substrate along the second direction. This arrangement enables the second level signal line VGH' to separate the first output transistor T10 and the second output transistor T9 from other functional structures (such as other transistors, capacitors, etc.), thereby reducing the interference of the first output transistor T10 and the second output transistor T9 with other functional structures, and better ensuring the output stability of the first output transistor T10 and the second output transistor T9.

[0085] The above configuration makes the third capacitor C3 adjacent to the second output transistor T9, effectively reduces the difficulty of connecting the third capacitor C3 and the second output transistor T9, and ensures the reliability of the connection between the third capacitor C3 and the second output transistor T9.

[0086] like Figure 2 , Figures 5 to 18 As shown, in some embodiments, the shift register unit 10 further includes a seventh control transistor T8, a gate 38 of the seventh control transistor T8 is coupled to the first output node N3 in the shift register unit 10, a first electrode of the seventh control transistor T8 is coupled to the second level signal line VGH', and a second electrode of the seventh control transistor T8 is coupled to the second output node N5 in the shift register unit 10;

[0087] At least a portion of the orthographic projection of the active layer 28 of the seventh control transistor T8 on the base substrate is located at a second side of the orthographic projection of the second level signal line VGH′ on the base substrate.

[0088] Exemplarily, the active layer 28 of the seventh control transistor T8 extends along the second direction.

[0089] like Figure 2 , Figures 5 to 11 As shown, in some embodiments, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit 10 is used to drive two rows of sub-pixel rows; the orthographic projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 on the substrate and the orthographic projection of the active layer 28 of the seventh control transistor T8 on the substrate are arranged along the first direction.

[0090] Exemplarily, the gate 38 of the seventh control transistor T8 and the gate 310 of the first output transistor T10 in the shift register unit 10 form an integrated structure.

[0091] Exemplarily, the display area of ​​the display substrate includes multiple rows of sub-pixel rows, each row of sub-pixel rows includes multiple sub-pixels arranged along the second direction. When the shift register unit 10 is used to drive two rows of sub-pixel rows, the shift register unit 10 can provide driving signals to the two rows of sub-pixel rows.

[0092] The above configuration is conducive to narrowing the width of the layout space occupied by the shift register unit 10 along the second direction, and is conducive to achieving a narrow frame of the display substrate.

[0093] like Figure 2 , Figures 5 to 11 As shown, in some embodiments, the shift register unit 10 further includes an input transistor T1, a gate 31 of the input transistor T1 is coupled to the second clock signal input terminal CK, a first electrode of the input transistor T1 is coupled to the input signal terminal STV, and a second electrode of the input transistor T1 is coupled to the first input node N1 of the shift register unit 10; at least a portion of the positive projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 on the substrate is located between the positive projection of the active layer 21 of the input transistor T1 on the substrate and the positive projection of the second level signal line VGH' on the substrate; and / or,

[0094] The shift register unit 10 further includes a transfer transistor T12, a gate 312 of the transfer transistor T12 is coupled to a first level signal line VGL', a first electrode of the transfer transistor T12 is coupled to a first input node N1, and a second electrode of the transfer transistor T12 is coupled to a first output node N3; an orthographic projection of a second plate C22 of a second capacitor C2 in the shift register unit 10 on the substrate and an orthographic projection of an active layer 212 of the transfer transistor T12 on the substrate are arranged along the first direction; and / or,

[0095] The shift register unit 10 further includes a fifth control transistor T6 and a sixth control transistor T7; a gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to a first electrode of the sixth control transistor T7; a gate 37 of the sixth control transistor T7 is coupled to the second input node N2, a second electrode of the sixth control transistor T7 is coupled to the first input node N1; an active layer 26 of the fifth control transistor T6 is coupled to the sixth control transistor T7. The active layer 27 of the transistor T7 is formed as an active layer of an integrated structure, and the active layer of the integrated structure extends along the second direction; the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is located between the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate; the orthographic projection of the active layer 212 of the transmission transistor T12 on the substrate is located between the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate; and / or,

[0096] The shift register unit 10 also includes a second coupling node N4, a first control transistor T2, a second control transistor T3, a third control transistor T4 and a fourth control transistor T5; a gate 32 of the first control transistor T2 is coupled to the second coupling node N4, a first electrode of the first control transistor T2 is coupled to the first level signal line VGL', and a second electrode of the first control transistor T2 is coupled to the second input node N2; a gate 33 of the second control transistor T3 is coupled to the first input node N1, a first electrode of the second control transistor T3 is coupled to the second level signal line VGH', and a second electrode of the second control transistor T3 is coupled to the second input node N2; a gate 34 of the third control transistor T4 is coupled to the first input node N1, a first electrode of the third control transistor T4 is coupled to the second level signal line VGH', and a second electrode of the third control transistor T4 is coupled to the first input node N2. The gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB, the first electrode of the fourth control transistor T5 is coupled to the second input node N2, and the second electrode of the fourth control transistor T5 is coupled to the second output node N5; the positive projection of the second plate C22 of the second capacitor C2 on the substrate, the positive projection of the active layer 25 of the fourth control transistor T5 on the substrate, the positive projection of the active layer 23 of the second control transistor T3 on the substrate, and the positive projection of the active layer 24 of the third control transistor T4 on the substrate are arranged in sequence along the first direction; the positive projection of the active layer 23 of the second control transistor T3 on the substrate is located between the positive projection of the active layer 22 of the first control transistor T2 on the substrate and the positive projection of the second level signal line VGH' on the substrate; and / or,

[0097] The shift register unit 10 also includes a first capacitor C1, a first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and a second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate are arranged along the second direction.

[0098] Exemplarily, the active layer 21 of the input transistor T1 extends along the first direction, the active layer 212 of the transmission transistor T12 extends along the first direction, and the active layer 212 of the transmission transistor T12 is at least partially offset from the active layer 21 of the input transistor T1 along the second direction.

[0099] Exemplarily, the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate, the active layer of the integrated structure formed by the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7, the orthographic projection of the active layer 25 of the fourth control transistor T5 on the substrate, the orthographic projection of the active layer 23 of the second control transistor T3 on the substrate, and the orthographic projection of the active layer 24 of the third control transistor T4 on the substrate are arranged in sequence along the first direction.

[0100] Exemplarily, the active layer 23 of the second control transistor T3 and the active layer 22 of the first control transistor T2 form an integrated structure extending along the second direction.

[0101] The above configuration is conducive to narrowing the width of the layout space occupied by the shift register unit 10 along the second direction, and is conducive to achieving a narrow frame of the display substrate.

[0102] like Figures 5 to 11 As shown, the shift register unit further includes a first conductive connection portion 51, which is respectively coupled to the first electrode of the input transistor T1, and a tenth conductive connection portion 41, which is coupled to the gate drive signal output terminal of the previous stage shift register unit.

[0103] The shift register unit further includes a second conductive connection portion 52 , which is coupled to the first electrode C21 of the second capacitor C2 and the second electrode of the transmission transistor T12 , respectively.

[0104] The shift register unit further includes a third conductive connection portion 53 , and the third conductive connection portion 53 is coupled to the second electrode C22 of the second capacitor C2 and the second electrode of the eighth control transistor T11 , respectively.

[0105] The shift register unit further includes a fourth conductive connection portion 54 , which is respectively coupled to the second electrode of the input transistor T1 , the first electrode of the transmission transistor T12 , the second electrode of the sixth control transistor T7 , and the gate of the second control transistor T3 .

[0106] The shift register unit further includes a fifth conductive connection portion 55 , which is respectively coupled to the first electrode of the eighth control transistor T11 and the gate of the fifth control transistor T6 .

[0107] The shift register unit further includes a sixth conductive connection portion 56 , which is respectively coupled to the gate of the sixth control transistor T7 , the first electrode of the fourth control transistor T5 , the second electrode of the first control transistor T2 , and the second electrode of the second control transistor T3 .

[0108] The shift register unit further includes a seventh conductive connection portion 57 , which is respectively coupled to the second electrode of the fourth control transistor T5 , the gate of the second output transistor T9 , and the second electrode of the fourth control transistor T8 .

[0109] The shift register unit further includes an eighth conductive connection portion 58 , which is coupled to the second electrode C21 of the first capacitor C1 , the gate 32 of the first control transistor T2 , and the second electrode of the third control transistor T4 , respectively.

[0110] The shift register unit further includes an eleventh conductive connection portion 42 , which is respectively coupled to the first electrode of the first output transistor T10 and the first level signal line VGL′.

[0111] like Figure 1 , Figures 12 to 18 As shown, in some embodiments, the display substrate further includes a plurality of rows of sub-pixel rows; the shift register unit 10 is used to drive a row of sub-pixel rows; at least a portion of the positive projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 on the base substrate is located between the positive projection of the active layer 28 of the seventh control transistor T8 on the base substrate and the positive projection of the second level signal line VGH' on the base substrate.

[0112] Exemplarily, the gate 38 of the seventh control transistor T8 and the gate 311 of the eighth control transistor T11 form an integrated structure.

[0113] Exemplarily, the display area of ​​the display substrate includes multiple rows of sub-pixel rows, each row of sub-pixel rows includes multiple sub-pixels arranged along the second direction. When the shift register unit 10 is used to drive a row of sub-pixel rows, the shift register unit 10 can provide a driving signal to the row of sub-pixel rows.

[0114] The above configuration is conducive to narrowing the width of the layout space occupied by the shift register unit 10 along the first direction, and reducing the layout difficulty of the multi-stage shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixels.

[0115] like Figure 1 , Figures 12 to 18As shown, in some embodiments, the shift register unit 10 further includes an input transistor T1, a gate 31 of the input transistor T1 is coupled to the second clock signal input terminal CK, a first electrode of the input transistor T1 is coupled to the input signal terminal STV, and a second electrode of the input transistor T1 is coupled to the first input node N1 of the shift register unit 10; at least a portion of the positive projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 on the substrate is located between the positive projection of the active layer 21 of the input transistor T1 on the substrate and the positive projection of the second level signal line VGH' on the substrate; and / or,

[0116] The shift register unit 10 further includes a transfer transistor T12, a gate 312 of the transfer transistor T12 is coupled to a first level signal line VGL', a first electrode of the transfer transistor T12 is coupled to a first input node N1, and a second electrode of the transfer transistor T12 is coupled to a first output node N3; at least a portion of an orthographic projection of an active layer 212 of the transfer transistor T12 on the substrate is located between an orthographic projection of an active layer 21 of the input transistor T1 on the substrate and an orthographic projection of a second plate C22 of the second capacitor C2 on the substrate; and / or,

[0117] The shift register unit 10 further includes a fourth control transistor T5, a fifth control transistor T6 and a sixth control transistor T7; a gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB, a first electrode of the fourth control transistor T5 is coupled to the second input node N2, and a second electrode of the fourth control transistor T5 is coupled to the second output node N5; a gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to the first electrode of the sixth control transistor T7; a gate 37 of the sixth control transistor T7 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to the first electrode of the sixth control transistor T7; a gate 38 of the sixth control transistor T7 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to the first electrode of the sixth control transistor T7; a gate 39 of the sixth control transistor T7 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to the first electrode of the sixth control transistor T7; a gate 31 of the sixth control transistor T7 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to the first electrode of the sixth control transistor T7; a gate 32 of the sixth control transistor T7 is coupled to the first clock signal input terminal CKB, a first electrode of the fifth control transistor T6 is coupled to the second level signal line VGH', a second electrode of the fifth control transistor T6 is coupled to the first electrode of the sixth control The first input node N2 is coupled to the second input node N2, and the second electrode of the sixth control transistor T7 is coupled to the first input node N1; the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 form an active layer of an integrated structure, and the active layer of the integrated structure extends along the first direction; at least a part of the positive projection of the active layer 25 of the fourth control transistor T5 on the substrate is located between the positive projection of the second electrode plate C22 of the second capacitor C2 on the substrate and the positive projection of the active layer of the integrated structure on the substrate; at least a part of the active layer 28 of the seventh control transistor T8 is located between the active layer of the integrated structure and the active layer 25 of the fourth control transistor T5; and / or,

[0118] The shift register unit 10 further includes a second coupling node N4, a first control transistor T2, a second control transistor T3 and a third control transistor T4; a gate 32 of the first control transistor T2 is coupled to the second coupling node N4, a first electrode of the first control transistor T2 is coupled to the first level signal line VGL', and a second electrode of the first control transistor T2 is coupled to the second input node N2; a gate 33 of the second control transistor T3 is coupled to the first input node N1, a first electrode of the second control transistor T3 is coupled to the second level signal line VGH', and a second electrode of the second control transistor T3 is coupled to the second input node N2; a gate 34 of the third control transistor T4 is coupled to the first input node N1, a first electrode of the third control transistor T4 is coupled to the first level signal line VGH', and a second electrode of the second control transistor T3 is coupled to the second input node N2; The second electrode of the third control transistor T4 is coupled to the second coupling node N4; the active layer 28 of the seventh control transistor T8 is located between the active layer 22 of the first control transistor T2 and the active layer 211 of the eighth control transistor T11; the active layer 22 of the first control transistor T2 and the active layer 24 of the third control transistor T4 are arranged along the first direction, and at least part of the active layer 23 of the second control transistor T3 is located between the active layer 22 of the first control transistor T2 and the active layer 24 of the third control transistor T4; the active layer 22 of the first control transistor T2, the active layer 23 of the second control transistor T3 and the active layer 24 of the third control transistor T4 are coupled in sequence to form an integrated structure; and / or,

[0119] The shift register unit 10 also includes a first capacitor C1, a first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and a second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate are arranged along the second direction.

[0120] Exemplarily, the active layer 21 of the input transistor T1 extends along the second direction, and the active layer 212 of the transmission transistor T12 extends along the second direction. The active layer 212 of the transmission transistor T12 is partially offset from the active layer 21 of the input transistor T1 along the second direction.

[0121] Exemplarily, the second plate C22 of the second capacitor C2 includes a plate main body and a plate protrusion, the plate main body extends along the first direction, the plate protrusion protrudes beyond the plate main body along the second direction, and the orthographic projection of the plate main body on the substrate is located between the orthographic projection of the plate protrusion on the substrate and the orthographic projection of the second level signal line VGH' on the substrate.

[0122] Exemplarily, an orthographic projection of the active layer 212 of the transmission transistor T12 on the substrate is offset from an orthographic projection of the electrode protrusion on the substrate along the second direction.

[0123] Exemplarily, the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 form an integrated structure, the active layer 28 of the seventh control transistor T8, and the active layer 25 of the fourth control transistor T5 are coupled in sequence to form an integrated structure.

[0124] Exemplarily, the active layer 22 of the first control transistor T2 extends along the second direction, the active layer 24 of the third control transistor T4 extends along the second direction, and the active layer 23 of the second control transistor T3 extends along the first direction.

[0125] The above configuration is conducive to narrowing the width of the layout space occupied by the shift register unit 10 along the first direction, and reducing the layout difficulty of the multi-stage shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixels.

[0126] like Figures 12 to 18 As shown, the shift register unit also includes a twelfth conductive connection part 61, which is respectively coupled to the first electrode of the input transistor T1, and a tenth conductive connection part 41, and the tenth conductive connection part 41 is coupled to the gate drive signal output end of the previous stage shift register unit.

[0127] The shift register unit further includes a thirteenth conductive connection portion 62 , which is respectively coupled to the second electrode of the transmission transistor T12 and the first electrode plate C21 of the second capacitor C2 .

[0128] The shift register unit further includes a fourteenth conductive connection portion 63 , which is respectively coupled to the gate of the sixth control transistor T7 and the first electrode of the fourth control transistor T5 .

[0129] The shift register unit further includes a fifteenth conductive connection portion 64 , which is respectively coupled to the second electrode plate C22 of the second capacitor C2 and the second electrode of the eighth control transistor T11 .

[0130] The shift register unit further includes a sixteenth conductive connection portion 65 , which is respectively coupled to the second electrode of the input transistor T1 , the first electrode of the transmission transistor T12 , the gate of the second control transistor T3 , and the gate of the third control transistor T4 .

[0131] The shift register unit further includes a seventeenth conductive connection portion 66 , which is respectively coupled to the second electrode of the second control transistor T3 and the gate of the sixth control transistor T7 .

[0132] The shift register unit further includes a nineteenth conductive connection portion 68 , which is respectively coupled to the second electrode C12 of the first capacitor C1 , the second electrode of the third control transistor T4 , and the gate of the first control transistor T2 .

[0133] The shift register unit further includes a twentieth conductive connection portion 69, which is respectively coupled to the second level signal line VGH', the first electrode of the third control transistor T4, the first electrode of the seventh control transistor T8, and the first electrode of the second control transistor T3.

[0134] The shift register unit further includes a twenty-first conductive connection portion 610 , which is respectively coupled to the first electrode of the eighth control transistor T11 and the gate of the fourth control transistor T5 .

[0135] The shift register unit further includes a twenty-second conductive connection portion 611 , which is respectively coupled to the first electrode C31 of the third capacitor C3 and the second electrode of the seventh control transistor T8 .

[0136] like Figures 5 to 18 As shown, in some embodiments, the first level signal line VGL' and the second level signal line VGH' in the display substrate are arranged along the second direction; the orthographic projection of other transistor structures in the shift register unit 10 except the output transistor on the base substrate is located between the orthographic projection of the first level signal line VGL' on the base substrate and the orthographic projection of the second level signal line VGH' on the base substrate.

[0137] The above method realizes that the other transistor structures included in the shift register unit 10 are all concentratedly arranged between the first level signal line VGL' and the second level signal line VGH', so that the CNT via distribution density around each other transistor structure is uniform, avoiding the increase of regional characteristic differences due to the layout area being affected by dehydrogenation caused by uneven via distribution.

[0138] Exemplarily, the display substrate also includes a frame start signal line (e.g., ESTV, RSTV), a first clock signal line (e.g., ECB, RCB) and a second clock signal line (e.g., ECK, RCK); the frame start signal line, the first clock signal line, the second clock signal line, the first level signal line VGL' and the second level signal line VGH' are arranged in sequence along the second direction.

[0139] Exemplarily, in the cascaded multiple shift register units 10, the first electrode of the first input transistor T1 in the first-stage shift register unit 10 is coupled to the frame start signal line, and the first electrode of the first input transistor T1 in the n+1-stage shift register unit 10 is coupled to the gate drive signal output terminal OUT of the n-stage shift register unit 10; n is an integer greater than or equal to 1.

[0140] Exemplarily, in one shift register unit 10 among the odd-numbered shift register units 10 and the even-numbered shift register units 10, the first clock signal input terminal CKB is coupled to the first clock signal line, and the second clock signal input terminal CK is coupled to the second clock signal line; in another shift register unit 10 among the odd-numbered shift register units 10 and the even-numbered shift register units 10, the first clock signal input terminal CKB is coupled to the second clock signal line, and the second clock signal input terminal CK is coupled to the first clock signal line.

[0141] For example, Fig.19 As shown, the display substrate includes two types of shift register units 10. The first type of shift register unit 10 is used to drive two rows of pixel units at the same time, which can be specifically used as EM GOA. The second type of shift register unit 10 is used to drive one row of pixel units at the same time, which can be specifically used as Reset GOA. In actual layout, ResetGOA can be arranged between EM GOA and the display area. It should be noted that Fig.19 The middle display area is located on the far right.

[0142] For example, Figures 5 to 11 , Figures 13 to 19As shown, the width of the first shift register unit along the first direction is greater than the width of the second shift register unit along the first direction, and the width of the first shift register unit along the second direction is less than the width of the second shift register unit along the second direction.

[0143] The width of the second plate C32 of the third capacitor C3 in the first shift register unit along the first direction is greater than the width of the second plate C32 of the third capacitor C3 in the second shift register unit along the first direction; the width of the second plate C32 of the third capacitor C3 in the first shift register unit along the second direction is less than the width of the second plate C32 of the third capacitor C3 in the second shift register unit along the second direction.

[0144] The width of the second plate C22 of the second capacitor C2 in the first shift register unit along the first direction is greater than the width of the second plate C22 of the second capacitor C2 in the second shift register unit along the first direction; the width of the second plate C22 of the second capacitor C2 in the first shift register unit along the second direction is less than the width of the second plate C22 of the second capacitor C2 in the second shift register unit along the second direction.

[0145] It is worth noting that the shift register unit 10 provided in the above embodiment is suitable for LTPS or LTPO or full oxide display products. The shift register unit 10 can be used for EM GOA (luminescence control shift register unit), ResetGOA (reset control shift register unit), Scan GOA (gate scan drive shift register unit).

[0146] It should be noted that the types of transistors included in the shift register unit 10 are various and are not limited to P-type transistors. For example, N-type transistors may also be used, but are not limited thereto.

[0147] like Figure 2 and Figure 3 As shown, taking EM GOA as an example, the working process of the shift register unit 10 is as follows:

[0148] In the P1 phase, the signal inputted by the input signal terminal STV is at a low level, the second clock signal inputted by the second clock signal input terminal CK is at a high level, the first clock signal inputted by the first clock signal input terminal CKB is at a low level, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs a first level signal.

[0149] In the P2 stage, the signal input by the input signal terminal STV is at a high level, the second clock signal input by the second clock signal input terminal CK is at a low level, the first clock signal input by the first clock signal input terminal CKB is at a high level, the input transistor T1 and the sixth control transistor T7 are turned on, and the gate drive signal output terminal OUT maintains the potential of the first level signal.

[0150] In the P3 and P4 stages, the signal input by the input signal terminal STV is high level, the second clock signal input by the second clock signal input terminal CK is high level, the first clock signal input by the first clock signal input terminal CKB is low level, the second output transistor T9 is turned on, and the gate drive signal output terminal OUT outputs a second level signal.

[0151] In the stage between P3 and P4, the signal input by the input signal terminal STV is at a high level, the second clock signal input by the second clock signal input terminal CK alternates between a high level and a low level, the first clock signal input by the first clock signal input terminal CKB alternates between a high level and a low level, and the gate drive signal output terminal OUT continuously outputs a second level signal.

[0152] In the P5 stage, the signal input by the input signal terminal STV is at a low level, the second clock signal input by the second clock signal input terminal CK is at a low level, the first clock signal input by the first clock signal input terminal CKB is at a high level, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs a first level signal.

[0153] In the P6 stage, the signal input by the input signal terminal STV is at a low level, the second clock signal input by the second clock signal input terminal CK is at a high level, the first clock signal input by the first clock signal input terminal CKB is at a low level, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs a first level signal.

[0154] In the above-mentioned shift register unit 10, the eighth control transistor T11 can control the conduction or disconnection of the electrical connection between the first coupling node N0 and the first clock signal input terminal CKB, so that the potential of the first coupling node N0 can be the same as the potential of the clock signal input by the first clock signal input terminal CKB; at the same time, the second capacitor C2 can control the potential of the first output node N3 according to the potential of the first coupling node N0; in this way, when the gate drive signal output terminal OUT is reset, the first coupling node can be controlled to have a suitable potential by controlling the first clock signal input terminal CKB to input a signal with a suitable potential, thereby being able to control the potential of the first output node N3 to be quickly lowered, eliminating the step formed in the process of lowering the potential of the first output node N3, so that the gate drive signal output terminal OUT can output stably, effectively reducing the disturbance influence of the output waveform.

[0155] like Figure 1 As shown, exemplarily, the display substrate includes a conductive layer BSM, a barrier layer Bar, a buffer layer BUF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source-drain metal layer SD1, a first flat layer PLN1, a second source-drain metal layer SD2, a second flat layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may also include a passivation layer PVX, but is not limited to it.

[0156] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0157] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0158] In the display substrate provided by the above embodiment, the positive projection of the output transistor on the substrate substrate is located on the first side of the positive projection of the second level signal line VGH' on the substrate substrate, and the positive projection of other transistor structures in the shift register unit 10 except the output transistor on the substrate substrate is located on the second side of the positive projection of the second level signal line VGH' on the substrate substrate; so that the second level signal line VGH' can separate the output transistor from other transistor structures, thereby effectively reducing the coupling between the output node (such as the first output node N3 and the second output node N5) of the control output transistor and other transistor structures, as well as the nodes coupled with other transistor structures, avoiding the output node from being affected by the coupling, and then avoiding the output transistor from being affected by the coupling, thereby ensuring that the gate drive signal output terminal OUT can output stably, effectively reducing the disturbance effect on the output waveform, and effectively improving the reliability of the shift register unit. Therefore, in the display substrate provided by the above embodiment, the voltage stability of the internal nodes of the shift register unit 10 is effectively improved, and the stability of the output signal of the shift register unit 10 is improved.

[0159] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0160] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extending along the certain direction is greater than the length of the secondary part extending along other directions.

[0161] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0162] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0163] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0164] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0165] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0166] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0167] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: The invention comprises a substrate substrate and a second level signal line and a gate driving circuit arranged on the substrate substrate; the gate driving circuit comprises a plurality of cascaded shift register units, the shift register unit comprises an output transistor, and the output transistor is coupled to a gate driving signal output terminal of the shift register unit; The second-level signal line extends along a first direction, the orthographic projection of the output transistor on the substrate is located on a first side of the orthographic projection of the second-level signal line on the substrate, the orthographic projections of other transistor structures in the shift register unit except the output transistor on the substrate are located on a second side of the orthographic projection of the second-level signal line on the substrate, the first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

2. The display substrate according to claim 1, characterized in that: The display substrate also includes a first level signal line; the shift register unit also includes: a first output node and a first output transistor; the gate of the first output transistor is coupled to the first output node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate drive signal output end of the shift register unit; the orthographic projection of the first output transistor on the base substrate is located on the first side of the orthographic projection of the second level signal line on the base substrate.

3. The display substrate according to claim 2, characterized in that: The shift register unit further includes: a first coupling node and a second capacitor; a first plate of the second capacitor is coupled to the first output node, and a second plate of the second capacitor is coupled to the first coupling node; The orthographic projection of the second electrode plate of the second capacitor on the base substrate is located at a second side of the orthographic projection of the second level signal line on the base substrate, and is adjacent to the orthographic projection of the second level signal line on the base substrate.

4. The display substrate according to claim 3, characterized in that: The orthographic projection of the second level signal line on the base substrate of the display substrate is located between the orthographic projection of the second electrode plate of the second capacitor on the base substrate and the orthographic projection of the active layer of the first output transistor on the base substrate; The shift register unit also includes an eighth control transistor; the gate of the eighth control transistor is coupled to the first output node, the first electrode of the eighth control transistor is coupled to the first clock signal input terminal, and the second electrode of the eighth control transistor is coupled to the first coupling node; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the eighth control transistor on the substrate are arranged along the first direction.

5. The display substrate according to claim 1, characterized in that: The shift register unit also includes: a second output node and a second output transistor; the gate of the second output transistor is coupled to the second output node, the first electrode of the second output transistor is coupled to the second level signal line, and the second electrode of the second output transistor is coupled to the gate drive signal output end of the shift register unit; the orthographic projection of the second output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate.

6. The display substrate according to claim 5, characterized in that: The shift register unit also includes a third capacitor, a first plate of the third capacitor is coupled to the gate of the second output transistor, and a second plate of the third capacitor is coupled to the second level signal line; the orthographic projection of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the second level signal line on the substrate.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The shift register unit further includes a seventh control transistor, a gate of the seventh control transistor is coupled to the first output node in the shift register unit, a first electrode of the seventh control transistor is coupled to the second level signal line, and a second electrode of the seventh control transistor is coupled to the second output node in the shift register unit; At least a portion of an orthographic projection of the active layer of the seventh control transistor on the base substrate is located on a second side of an orthographic projection of the second-level signal line on the base substrate.

8. The display substrate according to claim 7, characterized in that: The display substrate further comprises a plurality of sub-pixel rows; the shift register unit is used to drive two sub-pixel rows; The orthographic projection of the second plate of the second capacitor in the shift register unit on the base substrate and the orthographic projection of the active layer of the seventh control transistor on the base substrate are arranged along the first direction.

9. The display substrate according to claim 8, characterized in that: The gate of the seventh control transistor and the gate of the first output transistor in the shift register unit form an integrated structure.

10. The display substrate according to claim 8, characterized in that: The shift register unit further includes a fifth control transistor and a sixth control transistor; a gate of the fifth control transistor is coupled to the first clock signal input terminal, a first electrode of the fifth control transistor is coupled to the second level signal line, and a second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; a gate of the sixth control transistor is coupled to the second input node, and a second electrode of the sixth control transistor is coupled to the first input node; an active layer of the fifth control transistor and an active layer of the sixth control transistor form an active layer of an integrated structure, and the active layer of the integrated structure extends along the second direction; The orthographic projection of the active layer of the eighth control transistor on the substrate is located between the orthographic projection of the second electrode plate of the second capacitor on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate; and / or, The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to the first level signal line, and the second electrode of the first control transistor is coupled to the second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to the second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the gate of the fourth control transistor is coupled to the first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to the second output node; the positive projection of the second plate of the second capacitor on the substrate, the positive projection of the active layer of the fourth control transistor on the substrate, the positive projection of the active layer of the second control transistor on the substrate, and the positive projection of the active layer of the third control transistor on the substrate are arranged in sequence along the first direction; The orthographic projection of the active layer of the second control transistor on the base substrate is located between the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the second level signal line on the base substrate.

11. The display substrate according to claim 7, characterized in that: The display substrate further comprises a plurality of sub-pixel rows; the shift register unit is used to drive a sub-pixel row; At least part of the orthographic projection of the active layer of the eighth control transistor in the shift register unit on the base substrate is located between the orthographic projection of the active layer of the seventh control transistor on the base substrate and the orthographic projection of the second-level signal line on the base substrate.

12. The display substrate according to claim 11, characterized in that: The gate of the seventh control transistor and the gate of the eighth control transistor form an integrated structure.

13. The display substrate according to claim 11, characterized in that: The shift register unit further includes a fourth control transistor, a fifth control transistor and a sixth control transistor; the gate of the fourth control transistor is coupled to the first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to the second output node; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first electrode of the fifth control transistor is coupled to the second level signal line, and the second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second electrode of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor form an active layer of an integrated structure, and the active layer of the integrated structure extends along the first direction; At least a portion of the orthographic projection of the active layer of the fourth control transistor on the substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate; At least a portion of the active layer of the seventh control transistor is located between the active layer of the integrated structure and the active layer of the fourth control transistor; and / or, The shift register unit further includes a second coupling node, a first control transistor, a second control transistor and a third control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to the first level signal line, and the second electrode of the first control transistor is coupled to the second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to the second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the active layer of the seventh control transistor is located between the active layer of the first control transistor and the active layer of the eighth control transistor; The active layer of the first control transistor and the active layer of the third control transistor are arranged along the first direction, and at least a portion of the active layer of the second control transistor is located between the active layer of the first control transistor and the active layer of the third control transistor; The active layer of the first control transistor, the active layer of the second control transistor and the active layer of the third control transistor are coupled in sequence to form an integrated structure.

14. The display substrate according to any one of claims 1 to 6, characterized in that: The first-level signal line and the second-level signal line in the display substrate are arranged along the second direction; the orthographic projection of other transistor structures in the shift register unit except the output transistor on the base substrate is located between the orthographic projection of the first-level signal line on the base substrate and the orthographic projection of the second-level signal line on the base substrate.

15. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 14.

Images