Drive controller and display device

Abstract

The invention provides a display device and a drive controller. The display device includes: a display panel; a driving controller receiving an input image signal and outputting an image data signal; a voltage generator that generates a plurality of gamma voltages in response to the voltage control signal; and a data driving circuit receiving the plurality of gamma voltages and providing a data signal corresponding to the image data signal to the display panel. The drive controller operates between a normal mode and a power saving mode. In the power saving mode, the drive controller generates a voltage control signal for changing a plurality of voltage levels of the plurality of gamma voltages in response to an input image signal and a peak signal. In the normal mode, at least one of the plurality of gamma voltages has a first voltage level and in the power saving mode, at least one of the plurality of gamma voltages has a second voltage level lower than the first voltage level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0144109 filed in the Korean Intellectual Property Office on October 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a driving controller and a display device, and more particularly, to a display device capable of reducing power consumption of a display panel and an operating method of the display device. Background Art

[0004] A display device is a component of an electronic device that displays images to a user. Examples of these electronic devices include smartphones, digital cameras, notebook computers, navigation systems, monitors, and smart televisions. Images are created by a display device and displayed to a user through a display screen.

[0005] The display device includes a display panel and a drive controller for controlling the display panel. When the drive controller sends a data signal to the display panel and the pixels in the display panel receive a current corresponding to the data signal, an image is displayed. Generally, it is desirable to prevent the power consumption of the display device from increasing. To this end, the drive controller can play an important role because the drive controller can adjust the brightness of the display panel based on the load of the input image signal. Summary of the invention

[0006] Embodiments of the present disclosure provide a driving controller capable of reducing power consumption of a display panel, a display device including the driving controller, and an operating method of the display device.

[0007] According to an embodiment, a display device includes: a display panel; a driving controller configured to receive an input image signal and output an image data signal based on the input image signal; a voltage generator configured to generate a plurality of gamma voltages in response to a voltage control signal; and a data driving circuit configured to receive a plurality of gamma voltages and provide a data signal corresponding to the image data signal to the display panel. The driving controller operates between a normal mode and a power saving mode. In the power saving mode, the driving controller generates a voltage control signal for changing a plurality of voltage levels of a plurality of gamma voltages in response to an input image signal and a peak signal. In the normal mode, at least one of the plurality of gamma voltages has a first voltage level, and in the power saving mode, at least one of the plurality of gamma voltages has a second voltage level lower than the first voltage level.

[0008] In an embodiment, the driving controller is configured to: generate a peak grayscale signal corresponding to an input image signal and a peak signal, generate a maximum voltage code based on a peak voltage code corresponding to the peak grayscale signal and a degradation compensation value corresponding to an operation time, and output a voltage control signal corresponding to the maximum voltage code.

[0009] In an embodiment, the driving controller is configured to operate in a power saving mode when the maximum voltage code is less than a reference value, and to operate in a normal mode when the maximum voltage code is equal to the reference value.

[0010] In an embodiment, the voltage generator is configured to further generate a power supply voltage to be provided to the data driving circuit.

[0011] In an embodiment, the driving controller is configured to output a voltage control signal for changing a voltage level of the power supply voltage in the power saving mode.

[0012] In an embodiment, in the power saving mode, the voltage level of the power supply voltage may be lower than the voltage level of the power supply voltage in the normal mode.

[0013] In an embodiment, the driving controller may include: a power control module configured to output a peak grayscale signal in response to a peak signal; a peak voltage memory configured to store a peak voltage code corresponding to the peak grayscale signal from the power control module; a degradation compensator configured to provide a degradation compensation value corresponding to an operation time; a maximum voltage calculator configured to output a maximum voltage code based on the peak voltage code from the peak voltage memory and the degradation compensation value from the degradation compensator; and a voltage controller configured to output a voltage control signal based on the maximum voltage code from the maximum voltage calculator.

[0014] In an embodiment, the maximum voltage calculator is configured to add the peak voltage code and the degradation compensation value, and to output a maximum voltage code corresponding to a result of the addition of the peak voltage code and the degradation compensation value.

[0015] In an embodiment, in the power saving mode, voltage levels of some gamma voltages lower than a voltage level corresponding to a maximum voltage code among a plurality of gamma voltages may be maintained at the same voltage level as that of the normal mode.

[0016] In an embodiment, in the power saving mode, a voltage level of one gamma voltage higher than and closest to a voltage level corresponding to the maximum voltage code among the plurality of gamma voltages may be maintained at the same voltage level as that of the normal mode.

[0017] In an embodiment, in the power saving mode, a voltage level of at least one gamma voltage higher than a voltage level corresponding to a maximum voltage code among a plurality of gamma voltages may be changed to be lower than a voltage level in the normal mode.

[0018] In an embodiment, the degradation compensator may receive a feedback current from the display panel, and may provide a degradation compensation value based on the feedback current and an operation time.

[0019] According to an embodiment, a driving controller includes: a power control module configured to output a peak grayscale signal in response to a peak signal; a peak voltage memory configured to store a peak voltage code corresponding to the peak grayscale signal provided from the power control module; a degradation compensator configured to provide a degradation compensation value corresponding to an operation time; a maximum voltage calculator configured to output a maximum voltage code based on the peak voltage code provided from the peak voltage memory and the degradation compensation value provided from the degradation compensator; and a voltage controller configured to output a voltage control signal for adjusting a voltage level of a plurality of gamma voltages based on the maximum voltage code provided from the maximum voltage calculator.

[0020] In an embodiment, the voltage controller is configured to operate in a power saving mode when the maximum voltage code is less than a reference value, and to operate in a normal mode when the maximum voltage code is equal to the reference value.

[0021] In an embodiment, the maximum voltage calculator may add the peak voltage code and the degradation compensation value, and may output a maximum voltage code corresponding to a result of adding the peak voltage code and the degradation compensation value.

[0022] In an embodiment, in the power saving mode, the voltage controller may maintain voltage levels of some gamma voltages lower than a voltage level corresponding to a maximum voltage code among the plurality of gamma voltages at the same voltage level as that of the normal mode.

[0023] In an embodiment, during the power saving mode, the voltage controller may maintain a voltage level of one gamma voltage higher than and closest to a voltage level corresponding to the maximum voltage code among the plurality of gamma voltages at the same voltage level as that of the normal mode.

[0024] In an embodiment, during the power saving mode, the voltage controller may change a voltage level of at least one gamma voltage higher than a voltage level corresponding to a maximum voltage code among the plurality of gamma voltages to be lower than a voltage level in the normal mode.

[0025] According to an embodiment, an operating method of a display device includes: generating a plurality of gamma voltages in response to a voltage control signal; providing a data signal corresponding to an input image signal to a display panel based on the plurality of gamma voltages; and generating a voltage control signal in response to the input image signal and a peak signal, so that a voltage level of each of the plurality of gamma voltages corresponds to one of a normal mode and a power saving mode, and at least one of the plurality of gamma voltages has a first voltage level in the normal mode and has a second voltage level lower than the first voltage level in the power saving mode.

[0026] In an embodiment, the generation of a voltage control signal can be achieved by generating a peak voltage code in response to an input image signal and a peak signal, generating a degradation compensation value corresponding to an operation time, generating a maximum voltage code based on the peak voltage code and the degradation compensation value, and generating a voltage control signal based on the maximum voltage code. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is an exploded view of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0032] Figure 5 is a block diagram showing the configuration of a drive controller.

[0033] Fig. 6A and Figure 6B is a diagram showing the operation of the power control module according to the peak signal.

[0034] Fig. 7A and Figure 7B is a diagram showing the operation of the power control module according to the gain signal.

[0035] Fig. 8A is a diagram showing a power voltage and a gamma voltage generated by a second voltage generator in a normal mode.

[0036] Figure 8B is a diagram showing a voltage code corresponding to each of a plurality of gamma voltages in a normal mode.

[0037] Fig.9A is a diagram showing a peak voltage code and a maximum voltage code when the peak luminance is 500 nits.

[0038] Fig. 9B is shown in the power saving mode according to Fig.9A The maximum voltage code is shown in the diagram of the power supply voltage and the gamma voltage.

[0039] Fig. 10A is a diagram showing a peak voltage code and a maximum voltage code when the peak luminance is 500 nits.

[0040] Fig. 10B is shown in the power saving mode according to Fig. 10A The maximum voltage code is shown in the diagram of the power supply voltage and the gamma voltage.

[0041] Fig.11A is a diagram showing a peak voltage code and a maximum voltage code when the peak luminance is 200 nits.

[0042] Fig. 11B is shown in the power saving mode according to Fig.11A The maximum voltage code is shown in the diagram of the power supply voltage and the gamma voltage.

[0043] Fig. 12A is a diagram showing a peak voltage code and a maximum voltage code when the peak luminance is 200 nits.

[0044] Fig. 12B is shown in the power saving mode according to Fig. 12A The maximum voltage code is shown in the diagram of the power supply voltage and the gamma voltage.

[0045] Fig.13A is a diagram showing a peak voltage code and a maximum voltage code when the peak luminance is 100 nits.

[0046] Fig. 13B is shown in the power saving mode according to Fig.13A The maximum voltage code is shown in the diagram of the power supply voltage and the gamma voltage.

[0047] Fig.14A is a diagram showing a peak voltage code and a maximum voltage code when the peak luminance is 100 nits.

[0048] Fig. 14B is shown in the power saving mode according to Fig.14A The maximum voltage code is shown in the diagram of the power supply voltage and the gamma voltage. DETAILED DESCRIPTION

[0049] In this specification, the statement that a first component (or region, layer, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is between the first component and the second component.

[0050] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated to effectively describe the technical features. The term "and / or" includes one or more combinations of the related listed items.

[0051] The terms "first", "second", etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a "second component", and similarly, a second component may be referred to as a "first component". Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0052] In addition, the terms "below", "below", "above", "on", etc. are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions shown in the drawings.

[0053] It will be understood that the terms "include", "comprising", "having", etc. specify the presence of the features, numbers, steps, operations, elements or components, or a combination thereof, described in the specification, but do not exclude the presence or additional possibility of one or more other features, numbers, steps, operations, elements or components, or a combination thereof.

[0054] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning.

[0055] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure, and Figure 2 is an exploded view of a display device DD according to an embodiment of the present disclosure.

[0057] Reference Figure 1 and Figure 2, the display device DD can be a device activated based on an electrical signal. The display device DD according to the present disclosure can be a small or medium-sized display device for a mobile phone, a tablet computer, a car navigation system or a game console, and a large display device for a television or a monitor. The display device is provided only as an example, and any other type of display device may be included without departing from the concept of the present disclosure. The display device DD is a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto. For example, the display device DD can be implemented in various shapes. The display device DD can display an image IM in a display surface IS parallel to each of the first direction DR1 and the second direction DR2, so that each of the first direction DR1 and the second direction DR2 is perpendicular to the third direction DR3. The display surface IS on which the image IM is displayed corresponds to the front surface of the display device DD.

[0058] In an embodiment, the front surface (or upper / top surface) and the rear surface (or lower / bottom surface) of each member are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface are opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface is parallel to the third direction DR3.

[0059] The spacing distance between the front and rear surfaces in the third direction DR3 corresponds to the thickness of the display device DD in the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative in concept and may be changed to different directions.

[0060] The display device DD can sense an external input applied from the outside. The external input may include various types of inputs provided from the outside of the display device DD. The display device DD according to an embodiment of the present disclosure can sense an external input of a user applied from the outside. The external input of the user may be one of various types of external inputs (such as a part of his / her body, light, heat, his / her sight, or pressure), or may be a combination thereof. In addition, the display device DD may sense the external input of the user applied to the side surface or rear surface of the display device DD based on the structure of the display device DD, and the present disclosure is not limited thereto. As an example of the present disclosure, the external input may include an input applied by an input device (e.g., a stylus, an active pen, a touch pen, an electronic pen, or an electronic-like pen).

[0061] The display surface IS of the display device DD is divided into a display area DA and a non-display area NDA. The display area DA refers to an area in which an image IM is displayed. The user visually perceives the image IM through the display area DA. In an embodiment, the display area DA is shown in the shape of a quadrilateral whose vertices are rounded. However, the shape is not limited thereto. In another example, the display area DA may have various shapes, such as a triangle, a circle, or any type of polygon other than a triangle and a quadrilateral.

[0062] The non-display area NDA is adjacent to the display area DA. In one example, the non-display area NDA surrounds the display area DA. In this way, the shape of the display area DA is substantially defined by the non-display area NDA. However, in another example, the non-display area NDA may be disposed adjacent to one side of the display area DA, or may be omitted. The display device DD according to an embodiment of the present disclosure includes various embodiments and is not limited to any one embodiment.

[0063] like Figure 2 As shown in FIG. 1 , the display device DD includes a display module DM and a window WM disposed on or above the display module DM. The display module DM includes a display panel DP and an input sensing layer ISP.

[0064] In this case, the display panel DP may be a light-emitting display panel. More specifically, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. In the following embodiments, a description will be given under the condition that the display panel DP is an organic light-emitting display panel.

[0065] The display panel DP outputs an image IM, and the output image IM is displayed through the display surface IS.

[0066] The input sensing layer ISP is disposed on the display panel DP to sense external input. The input sensing layer ISP is directly disposed on the display panel DP so that no layer is interposed between the input sensing layer ISP and the display panel DP. According to an embodiment of the present disclosure, the input sensing layer ISP is formed on the display panel DP in the same process as that of the display panel DP. For example, in the case where the input sensing layer ISP is directly disposed on the display panel DP, an internal adhesive film (not shown) is not disposed between the input sensing layer ISP and the display panel DP. However, the internal adhesive film is disposed between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP is not manufactured in the same process as that of the display panel DP. For example, the input sensing layer ISP may be manufactured by a process independent of the manufacturing process of the display panel DP, and may then be fixed on the upper surface of the display panel DP by the internal adhesive film.

[0067] The window WM is formed of a transparent material capable of outputting the image IM. For example, the window WM is formed of glass, sapphire, plastic, etc. It is shown that the window WM is implemented with a single layer. However, in another example, the window WM may include two or more layers.

[0068] Meanwhile, although not shown, the non-display area NDA of the above-mentioned display device DD corresponds to an area defined by printing a material including a given color on an area of ​​the window WM. In this example, the window WM includes a light-blocking (or light-shielding) pattern to define the non-display area NDA. The light-blocking pattern as a colored organic film is formed, for example, in a coating manner.

[0069] The window WM is coupled to the display module DM via an adhesive film. In this example, the adhesive film includes an optically clear adhesive (OCA) film. However, in another example, the adhesive film includes a typical adhesive or adhesive. For example, the adhesive film includes an optically clear resin (OCR) film or a pressure sensitive adhesive (PSA) film.

[0070] The anti-reflection layer may be between the window WM and the display module DM. The anti-reflection layer reduces the reflectivity of external light incident from above the window WM. In an embodiment, the anti-reflection layer may include a phase retarder and a polarizer. Each of the phase retarder and the polarizer may be a film type or a liquid crystal coating type. For example, a film type polarizer may include a stretched synthetic resin film, and a liquid crystal coating type polarizer may include liquid crystals arranged in a given direction. The phase retarder and the polarizer may be implemented with one polarizing film.

[0071] In an embodiment, the anti-reflection layer includes a color filter. Considering a plurality of pixels PX (refer to Figure 3 The arrangement of the color filters is determined according to the color of the light generated by the anti-reflection layer. The anti-reflection layer also includes a light-blocking pattern.

[0072] The display module DM displays an image IM according to an electrical signal, and transmits or receives information about an external input. The display module DM is defined by an active area AA and a non-active area NAA. The active area AA is defined as an area through which an image IM provided from the display module DM is output. In addition, the active area AA is defined as an area in which the input sensing layer ISP senses an external input applied from the outside.

[0073] The non-active area NAA is disposed adjacent to the active area AA. For example, the non-active area NAA surrounds the active area AA. However, in another example, the non-active area NAA is defined as various shapes without being limited to any one embodiment. According to an embodiment, the active area AA of the display module DM corresponds to at least a portion of the display area DA.

[0074] The display device DD also includes a main circuit board MCB, a flexible circuit film D-FCB, a driver chip DIC, a driving controller 100, a first voltage generator 400 and a second voltage generator 500. The main circuit board MCB is connected to the flexible circuit film D-FCB so that the main circuit board MCB is electrically connected to the display panel DP. The flexible circuit film D-FCB is connected to the display panel DP so that the flexible circuit film D-FCB electrically connects the display panel DP to the main circuit board MCB. The main circuit board MCB includes a plurality of driving elements. The plurality of driving elements constitute a circuit module for driving the display panel DP. The driver chip DIC is mounted on the flexible circuit film D-FCB.

[0075] In one embodiment, the flexible circuit film D-FCB includes a first flexible circuit film D-FCB1, a second flexible circuit film D-FCB2, and a third flexible circuit film D-FCB3. The driver chip DIC includes a first driver chip DIC1, a second driver chip DIC2, and a third driver chip DIC3. The first flexible circuit film D-FCB1, the second flexible circuit film D-FCB2, and the third flexible circuit film D-FCB3 are spaced apart from each other in the first direction DR1, and are connected to the display panel DP to electrically connect the display panel DP and the main circuit board MCB together. The first driver chip DIC1 is mounted on the first flexible circuit film D-FCB1, the second driver chip DIC2 is mounted on the second flexible circuit film D-FCB2, and the third driver chip DIC3 is mounted on the third flexible circuit film D-FCB3. However, in another example, the display panel DP is electrically connected to the main circuit board MCB through one flexible circuit film, and at least one driver chip is mounted on one flexible circuit film. In addition, the display panel DP is electrically connected to the main circuit board MCB through four or more flexible circuit films, and the driver chips are mounted on the flexible circuit films, respectively.

[0076] Figure 2, a structure in which the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are mounted on the first flexible circuit film D-FCB1, the second flexible circuit film D-FCB2, and the third flexible circuit film D-FCB3, respectively, is shown. However, the present disclosure is not limited thereto. For example, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are directly mounted on the display panel DP. In this case, the portion of the display panel DP on which the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are mounted is bendable, so that when the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are bent, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are disposed on the rear surface of the display module DM. In addition, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are directly mounted on the main circuit board MCB.

[0077] The input sensing layer ISP is electrically connected to the main circuit board MCB through the flexible circuit film D-FCB. However, the present disclosure is not limited thereto. For example, the display module DM further includes a separate flexible circuit film for electrically connecting the input sensing layer ISP and the main circuit board MCB together.

[0078] In an embodiment, the driving controller 100, the first voltage generator 400 and the second voltage generator 500 are mounted on the main circuit board MCB. The driving controller 100, the first voltage generator 400 and the second voltage generator 500 are electrically connected to the display panel DP through the main circuit board MCB and the flexible circuit film D-FCB.

[0079] The display device DD also includes a housing EDC that snugly accommodates the display module DM. The housing EDC is coupled to the window WM to further define the appearance of the display device DD. The housing EDC can absorb external shocks and prevent foreign matter / moisture, etc. from penetrating into the display module DM, thereby protecting the components accommodated in the housing EDC. Meanwhile, in this example, the housing EDC can be provided in the form of a combination of multiple accommodating members.

[0080] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0081] like Figure 3As shown in , the display device DD includes a drive controller 100, a data drive circuit 200, a scan drive circuit 300, a first voltage generator 400, a second voltage generator 500 and a display panel DP. The drive controller 100, the data drive circuit 200 and the scan drive circuit 300 are referred to as drive circuits for providing data signals to the pixels PX of the display panel DP. The display panel DP includes first scan lines SCL1 to SCLn, second scan lines SSL1 to SSLn, data lines DL1 to DLm, and pixels PX. Wherein, n and m are each a natural number greater than 0. The first scan line and the second scan line are arranged along the second direction DR2, and the data line is arranged along the first direction DR1.

[0082] The driving controller 100 receives an input image signal RGB and a control signal CTRL from an external source. The driving controller 100 converts the input image signal RGB into an image data signal DS and outputs the image data signal DS to the data driving circuit 200. The driving controller 100 also outputs a scan control signal SCS to the scan driving circuit 300 and a data control signal DCS to the data driving circuit 200. In an embodiment, the driving controller 100 outputs a voltage control signal VCTRL to the second voltage generator 500 for controlling the second voltage generator 500. In an embodiment, the driving controller 100 may also output a signal to the first voltage generator 400 for controlling the first voltage generator 400.

[0083] The data driving circuit 200 receives a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 converts the image data signal DS into a data signal and then outputs the data signal to a plurality of data lines DL1 to DLm. The data signal is an analog voltage corresponding to a grayscale value of the image data signal DS. The data driving circuit 200 is set Figure 2 The driver chip DIC is shown in FIG.

[0084] The display panel DP is divided into an active area AA and a non-active area NAA. The pixels PX are arranged in the active area AA, and the scan driving circuit 300 is arranged in the non-active area NAA. The driving controller 100, the data driving circuit 200, the first voltage generator 400 and the second voltage generator 500 are arranged outside the display panel DP.

[0085] The first scan lines SCL1 to SCLn and the second scan lines SSL1 to SSLn extend from the scan driving circuit 300 in the first direction DR1 and are spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driving circuit 200 in a direction away from the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0086] The pixels PX are electrically connected to the first scan lines SCL1 to SCLn, the second scan lines SSL1 to SSLn, and the data lines DL1 to DLm, respectively. For example, some pixels belonging to the first row are connected to the first scan line SCL1 and the second scan line SSL1. In addition, other pixels belonging to the second row are connected to the first scan line SCL2 and the second scan line SSL2.

[0087] Each of the plurality of pixels PX includes a light emitting element ED (see Figure 4 ) and a pixel circuit PXC for controlling emission of the light emitting element ED (refer to Figure 4 ). The pixel circuit PXC includes a plurality of transistors and at least one capacitor. The scan drive circuit 300 includes transistors formed by the same process as that of the pixel circuit PXC. In an embodiment, the light emitting element ED is an organic light emitting diode. However, in another example, the light emitting element ED is any type of light emitting device.

[0088] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0089] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit 300 outputs a first scan signal to the first scan lines SCL1 to SCLn and outputs a second scan signal to the second scan lines SSL1 to SSLn.

[0090] In an embodiment, the scan driving circuit 300 is disposed in a non-active area NA disposed outside of a first side of the active area AA.

[0091] In another embodiment, the scan driving circuit 300 includes at least two scan driving circuits that may be respectively disposed on the first side and the second side of the active area AA. For example, the first scan driving circuit disposed on the first side of the active area AA provides a first scan signal to the first scan lines SCL1 to SCLn, and the second scan driving circuit disposed on the second side of the active area AA provides a second scan signal to the second scan lines SSL1 to SSLn.

[0092] The first voltage generator 400 generates a voltage for operating the display panel DP. In an embodiment, the first voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT required for the operation of the display panel DP. The first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT may be provided to the display panel DP through a first voltage line VL1, a second voltage line VL2, and a third voltage line VL3.

[0093] The second voltage generator 500 may generate various voltages for operating the data driving circuit 200 and the scan driving circuit 300. For example, the second voltage generator 500 may generate a power voltage AVDD and a gamma voltage VGMA necessary for the operation of the data driving circuit 200. In an embodiment, the gamma voltage VGMA may include different gamma voltages VGMA1 to VGMA9.

[0094] The data driving circuit 200 converts the image data signal DS into a data signal based on the power voltage AVDD and the gamma voltage VGMA, and outputs the data signal to the plurality of data lines DL1 to DLm.

[0095] In an embodiment, the driving controller 100 generates a voltage control signal VCTRL for controlling the second voltage generator 500. The voltage control signal VCTRL is generated based on a feedback current signal FI received from the display panel DP through the feedback line FL. A detailed configuration and operation of the driving controller 100 will be described later.

[0096] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0097] like Figure 4 As shown in FIG. 1 , the equivalent circuit diagram of the pixel PX is connected to the data lines DL1 to DLm (refer to FIG. 1 ). Figure 3 ) in the i-th data line DLi (hereinafter also referred to as the data line DLi), the first scan lines SCL1 to SCLn (refer to Figure 3 ) in the j-th first scan line SCLj (hereinafter also referred to as the first scan line SCLj), and the second scan lines SSL1 to SSLn (refer to Figure 3 ) in the j-th second scan line SSLj (hereinafter also referred to as the second scan line SSLj). Wherein, i may be a natural number greater than or equal to 1 and less than or equal to m, and j may be a natural number greater than or equal to 1 and less than or equal to n.

[0098] Figure 3 Each of the plurality of pixels PX shown in FIG. Figure 4 The equivalent circuit diagram of the pixel PX shown in FIG. 1 has the same circuit configuration. In the embodiment, the pixel PX includes at least one light emitting element ED and a pixel circuit PXC.

[0099] The pixel circuit PXC includes at least one transistor, which is electrically connected to the light emitting element ED and provides a current corresponding to the data signal Di transmitted from the data line DLi to the light emitting element ED. In an embodiment, the pixel circuit PXC of the pixel PX includes a first transistor T1, a second transistor T2, a third transistor T3 and a capacitor Cst. By using an oxide semiconductor as a semiconductor layer, each of the first transistor T1 to the third transistor T3 is an N-type transistor. However, in another example, each of the first transistor T1 to the third transistor T3 may be a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. In an embodiment, at least one of the first transistor T1 to the third transistor T3 may be an N-type transistor, and the other transistors may be P-type transistors. In addition, the circuit configuration of each pixel is not limited to Figure 4 , and therefore, the configuration of the pixel circuit PXC can be modified and implemented.

[0100] Reference Figure 4 The first scan line SCLj transmits a first scan signal SCj, and the second scan line SSLj transmits a second scan signal SSj. The data line DLi transmits a data signal Di. The data signal Di has a similar signal to that input to the display device DD (refer to Figure 3 )’s input image signal RGB corresponding to the voltage level.

[0101] The first and third voltage lines VL1 and VL3 transmit the first driving voltage ELVDD and the initialization voltage VINT to the pixel circuit PXC, and the second voltage line VL2 transmits the second driving voltage ELVSS to the cathode (or second terminal) of the light emitting element ED.

[0102] The first transistor T1 includes a first electrode connected to the first voltage line VL1 to receive the first driving voltage ELVDD, a second electrode electrically connected to the anode (or first terminal) of the light emitting element ED, and a first end of the capacitor Cst and a gate electrode of the second transistor T2. The first transistor T1 can supply a driving current to the light emitting element ED in response to a data signal Di transmitted through the data line DLi based on a switching operation of the second transistor T2.

[0103] The second transistor T2 includes a first electrode connected to the data line DLi to receive the data signal Di, a second electrode connected to the gate electrode of the first transistor T1 and the first end of the capacitor Cst, and a gate electrode connected to the first scan line SCLj to receive the first scan signal SCj. The second transistor T2 can be turned on based on the first scan signal SCj transmitted through the first scan line SCLj, and can transmit the data signal Di from the data line DLi to the gate electrode of the first transistor T1.

[0104] The third transistor T3 includes a first electrode connected to the third voltage line VL3, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the second scan line SSLj to receive the second scan signal SSj. The third transistor T3 can be turned on based on the second scan signal SSj transmitted through the second scan line SSLj, and can transmit the initialization voltage VINT to the anode of the light emitting element ED.

[0105] A first end of the capacitor Cst is connected to the gate electrode of the first transistor T1 , and a second end of the capacitor Cst is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3 .

[0106] In an embodiment, the pixel PX may operate in an emission mode and a current sensing mode. In the emission mode, when the third transistor T3 is turned on, the initialization voltage VINT from the third voltage line VL3 may be transmitted to the anode of the light emitting element ED.

[0107] In the current sensing mode, when the third transistor T3 is turned on, the voltage of the anode of the light emitting element ED corresponding to the data signal Di may be transmitted to the third voltage line VL3. In an embodiment, the third voltage line VL3 may be a feedback line FL. Figure 4 An example in which the third voltage line VL3 and the feedback line FL are implemented with the same line is shown in FIG. In an embodiment, the third voltage line VL3 and the feedback line FL may be implemented with different wirings.

[0108] Figure 5 is a block diagram showing the configuration of the drive controller 100 .

[0109] In this example, components associated with the voltage control function among the functions of the drive controller 100 are shown in FIG. Figure 5 In addition to Figure 5 In addition to the components shown in FIG. 1 , the driving controller 100 may further include various components, such as a component for outputting an image data signal DS and a component for outputting a data control signal DCS (see FIG. 1 ). Figure 3 ) components.

[0110] The driving controller 100 operates in a normal mode and a power saving mode. During the power saving mode, the driving controller 100 generates a signal for changing the gamma voltages VGMA1 to VGMA9 (refer to Figure 3 ) voltage level.

[0111] like Figure 5As shown in , the driving controller 100 includes a power control module 110 , a peak voltage memory 120 , a maximum voltage calculator 130 , a degradation compensator 140 , and a voltage controller 150 .

[0112] The power control module 110 may be referred to as a net power control (NPC) block. The power control module 110 may adjust the display panel DP (refer to Figure 3 ). For example, when the load of the input image signal RGB is greater than a reference value (i.e., a threshold value), the power control module 110 reduces the brightness of the display panel DP, and when the load of the input image signal RGB is less than the reference value (i.e., the threshold value), the power control module 110 increases the brightness of the display panel DP.

[0113] In an embodiment, the power control module 110 generates a peak grayscale signal P_G in response to a peak signal IN_PEAK and a gain signal IN_GAIN. In an embodiment, the peak signal IN_PEAK and the gain signal IN_GAIN are provided from an external source (e.g., an external device such as a main processor, a graphics processor, or a host processor). In an embodiment, the peak signal IN_PEAK and the gain signal IN_GAIN are values ​​stored in a memory, a register, etc. in the drive controller 100.

[0114] The peak voltage memory 120 stores a peak voltage code P_VCODE corresponding to the peak grayscale signal P_G.

[0115] The degradation compensator 140 generates a signal based on the image data signal DS, the feedback current signal FI and the display device DD (see Figure 3 )’s operation time generates a degradation compensation value C_AGE.

[0116] The maximum voltage calculator 130 generates a maximum voltage code M_VCODE based on the peak voltage code P_VCODE from the peak voltage memory 120 and the degradation compensation value C_AGE from the degradation compensator 140 .

[0117] The voltage controller 150 generates a voltage control signal VCTRL corresponding to the maximum voltage code M_VCODE from the maximum voltage calculator 130. The voltage control signal VCTRL is used to set the power supply voltage AVDD (refer to Figure 3 ) and gamma voltages VGMA1 to VGMA9 (reference Figure 3 ) voltage level signal.

[0118] Figure 3The second voltage generator 500 shown in generates a power voltage AVDD and gamma voltages VGMA1 to VGMA9 , whose voltage levels correspond to the voltage control signal VCTRL.

[0119] Fig. 6A and Figure 6B is a graph showing the peak signal IN_PEAK (refer to Figure 5 ) of the power control module 110 (refer to Figure 5 ) operation.

[0120] Fig. 6A is a graph showing the relationship between the load of the power control module 110 and the scaling factor SF.

[0121] Reference Fig. 6A , also refer to Figure 5 , in order to maintain or reduce the image data signal DS corresponding to the input image signal RGB (refer to Figure 3 ) gray level, the power control module 110 can calculate the proportional factor SF according to the load.

[0122] In an embodiment, the scale factor SF may be set differently based on the load. In an embodiment, the load may be calculated based on the grayscale of the input image signal RGB. For example, the load may be calculated based on the characteristics (i.e., grayscale) of the input image signal RGB. The power control module 110 calculates the load based on the input image signal RGB provided from an external source.

[0123] For example, when the load is less than a reference value (ie, a threshold), the maximum value of the scale factor SF may be 1. Also, when the load is greater than or equal to a reference value (ie, a threshold), the scale factor SF becomes smaller.

[0124] For example, when the scale factor SF is "1", the gray level of the image data signal DS may be the same as the gray level of the input image signal RGB. When the scale factor SF is 0.5, the gray level of the image data signal DS may be reduced to half of the gray level of the input image signal RGB.

[0125] When the peak signal IN_PEAK has a first peak value P1, the power control module 110 may set the maximum value of the proportional factor SF to "1". When the peak signal IN_PEAK has a second peak value P2, the power control module 110 may set the maximum value of the proportional factor SF to 0.5. When the peak signal IN_PEAK has a third peak value P3, the power control module 110 may set the maximum value of the proportional factor SF to 0.25. In an embodiment, the first peak value P1 is greater than the second peak value P2, the second peak value P2 is greater than the third peak value P3, and the first peak value P1 is greater than the third peak value P3.

[0126] For example, as the peak value of the peak signal IN_PEAK decreases, the peak grayscale of the image data signal DS may decrease accordingly.

[0127] Figure 6B is a diagram showing the relationship between the load of the power control module 110 and the brightness.

[0128] Reference Fig. 6A and Figure 6B , also refer to Figure 3 and Figure 5 Since the peak grayscale of the image data signal DS is determined based on the peak value of the peak signal IN_PEAK, the peak brightness of the image displayed in the display panel DP may be determined based on the peak value of the peak signal IN_PEAK.

[0129] When the peak signal IN_PEAK has a first peak value P1, the peak brightness of the image displayed in the display panel DP is about 2000 nits. When the peak signal IN_PEAK has a second peak value P2, the peak brightness of the image displayed in the display panel DP may be about 1000 nits. When the peak signal IN_PEAK has a third peak value P3, the peak brightness of the image displayed in the display panel DP may be about 500 nits. For example, the second peak value P2 is about half of the first peak value P1, and the third peak value P3 is half of the second peak value P2.

[0130] As the peak value of the peak signal IN_PEAK decreases, the peak brightness of the image displayed in the display panel DP may decrease.

[0131] Fig. 7A and Figure 7B is a graph showing the gain signal IN_GAIN (refer to Figure 5 ) of the power control module 110 (refer to Figure 5 ) operation.

[0132] More specifically, Fig. 7A is a diagram showing the relationship between the load of the power control module 110 and the scale factor SF.

[0133] Reference Fig. 7A , also refer to Figure 5 In order to maintain or reduce the gray level of the image data signal DS corresponding to the input image signal RGB, the power control module 110 may calculate the scale factor SF based on the load.

[0134] In an embodiment, the value of the scale factor SF may be set differently based on the load. In an embodiment, the load may be calculated based on the grayscale of the input image signal RGB. For example, the load may be calculated based on one of the characteristics (i.e., grayscale) of the input image signal RGB. Therefore, the power control module 110 may calculate the load based on the input image signal RGB. In this case, the power control module 110 may calculate the scale factor SF based on the load, which is based on the input image signal RGB.

[0135] For example, when the load is less than a reference value (ie, a threshold value), the maximum value of the scale factor SF may be “1.” In addition, when the load is greater than or equal to the reference value, the scale factor SF becomes smaller.

[0136] For example, when the scale factor SF is 1, the gray level of the image data signal DS may be the same as the gray level of the input image signal RGB. When the scale factor SF is 0.5, the gray level of the image data signal DS may be reduced to half of the gray level of the input image signal RGB.

[0137] When the gain signal IN_GAIN has a first gain value G1, the power control module 110 may set the maximum value of the proportional factor SF to "1". When the gain signal IN_GAIN has a second gain value G2, the power control module 110 may set the maximum value of the proportional factor SF to 0.5. When the gain signal IN_GAIN has a third gain value G3, the power control module 110 may set the maximum value of the proportional factor SF to 0.25. In an embodiment, the first gain value G1 is greater than the second gain value G2, and the second gain value G2 is greater than the third gain value G3. For example, the maximum value of the proportional factor SF of the second gain value G2 is approximately half of the proportional factor SF of the first gain value G1, and the maximum value of the proportional factor SF of the third gain value G3 is approximately half of the proportional factor SF of the second gain value G2.

[0138] In this case, as the gain value of the gain signal IN_GAIN decreases, the peak gray scale of the image data signal DS may decrease.

[0139] exist Fig. 6A In the example shown in FIG. 1 , the power control module 110 adjusts the maximum value of the proportional factor SF based on the peak value of the peak signal IN_PEAK. Fig. 7A In the example shown in FIG. 1 , when the load is less than a reference value (i.e., a threshold value), the power control module 110 adjusts the maximum value of the proportional factor SF based on the gain value of the gain signal IN_GAIN. In addition, when the load is greater than a reference value (i.e., a threshold value), the power control module 110 gradually reduces the proportional factor SF based on the gain value of the gain signal IN_GAIN.

[0140] In this way, the minimum value of the scale factor SF may also vary based on the gain value of the gain signal IN_GAIN. In this case, when the gain signal IN_GAIN has the first gain value G1, the minimum value of the scale factor SF is 0.2; when the gain signal IN_GAIN has the second gain value G2, the minimum value of the scale factor SF is 0.15; when the gain signal IN_GAIN has the third gain value G3, the minimum value of the scale factor SF is 0.1. Similar to the maximum value of the scale factor SF, the minimum value of the scale factor SF of the second gain value G2 is less than the minimum value of the scale factor SF of the first gain value G1, and the minimum value of the scale factor SF of the third gain value G3 is less than the minimum value of the scale factor SF of the second gain value G2.

[0141] Figure 7B is a diagram showing the relationship between the load of the power control module 110 and the brightness.

[0142] like Fig. 7A and Figure 7B As shown in Figure 3 and Figure 5 Since the gray scale of the image data signal DS is determined based on the gain value of the gain signal IN_GAIN, the brightness of the image displayed in the display panel DP may be correspondingly determined based on the gain value of the gain signal IN_GAIN.

[0143] In this case, when the gain signal IN_GAIN has the first gain value G1, the peak brightness of the image displayed in the display panel DP may be about 2000 nits. When the gain signal IN_GAIN has the second gain value G2, the peak brightness of the image displayed in the display panel DP may be about 1000 nits. When the gain signal IN_GAIN has the third gain value G3, the peak brightness of the image displayed in the display panel DP may be about 500 nits. Both the peak and overall brightness of the image displayed in the display panel DP may be reduced based on the gain value of the gain signal IN_GAIN.

[0144] In this case, when the gain value of the gain signal IN_GAIN becomes smaller in a state where the input image signal RGB indicates full white (ie, the load is large), the brightness of the image displayed in the display panel DP may become lower.

[0145] As reference Fig. 6A , Figure 6B , Fig. 7A and Figure 7B Described, also refer to Figure 3 and Figure 5, the power control module 110 may output a peak grayscale signal P_G in response to the peak signal IN_PEAK and the gain signal IN_GAIN. The peak grayscale signal P_G may correspond to the maximum grayscale of the image data signal DS corresponding to the input image signal RGB. In this case, the maximum grayscale of the image data signal DS may be determined by both the peak signal IN_PEAK and the gain signal IN_GAIN.

[0146] Furthermore, the power control module 110 may reduce the brightness of an image displayed in the display panel DP in response to both the peak signal IN_PEAK and the gain signal IN_GAIN.

[0147] Flow through the pixel PX (refer to Figure 4 ) in the light emitting element ED (refer to Figure 4 ) can be adjusted by the operation of the above-mentioned power control module 110. Therefore, the power consumption of the display panel DP can be reduced.

[0148] Return to reference Figure 5 , the driving controller 100 according to the embodiment of the present disclosure may perform a control operation to reduce the power consumption of the driving circuit. In detail, the driving controller 100 may perform a control operation to reduce the power consumption of the data driving circuit 200 (refer to Figure 3 ) and the second voltage generator 500 (refer to Figure 3 ) power consumption.

[0149] Fig. 8A is a diagram showing the operation of the second voltage generator 500 (see Figure 3 ) is a graph of a power supply voltage AVDD and gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9 generated by the power supply voltage AVDD. In this case, the graph compares the voltage levels between the power supply voltage AVDD and each of the plurality of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0150] Figure 8B is a diagram showing a voltage code VCODE corresponding to each of a plurality of gamma voltages VGMA1 , VGMA3 , VGMA5 , VGMA7 , and VGMA9 in a normal mode.

[0151] Reference Fig. 8A and Figure 8B The voltage levels of the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9 may be lower than the power supply voltage AVDD and may be different from each other. For example, the last gamma voltage VGMA9 has a voltage level lower than the first gamma voltage VGMA1, and the power supply voltage AVDD has a voltage level higher than the first gamma voltage VGMA1.

[0152] The voltage levels of the power supply voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9 and the voltage codes corresponding to the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9 are shown in FIG. Fig. 8A and Figure 8B , but the present disclosure is not limited thereto.

[0153] In addition, by Figure 3 The number of gamma voltages (e.g., gamma voltages VGMA1 to VGMA9) generated by the second voltage generator 500 shown in FIG. 5 may be changed or modified differently. In this case, the number of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9 is 5. In another case, the number of gamma voltages may be less than or greater than 5.

[0154] Fig.9A is a diagram showing a peak voltage code P_VCODE and a maximum voltage code M_VCODE when the peak luminance is 500 nits.

[0155] Fig. 9B is shown in the power saving mode according to Fig.9A 4. A diagram of the power supply voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9 of the maximum voltage code M_VCODE shown in FIG.

[0156] Reference Figure 5 , Fig.9A and Fig. 9B , assuming that when the gray scale of the image data signal DS is 255G, the display panel DP (refer to Figure 3 ) is about 1000 nits, and when the gray scale of the image data signal DS is 186G, the brightness of the image displayed in the display panel DP is about 500 nits.

[0157] In this case, the peak voltage code P_VCODE corresponds to the peak grayscale signal P_G. As described above, the peak grayscale signal P_G may correspond to a maximum grayscale of the image data signal DS determined by both the peak signal IN_PEAK and the gain signal IN_GAIN.

[0158] For example, the peak voltage code P_VCODE is a voltage code corresponding to the maximum brightness (eg, 500 nits) of the image data signal DS to be displayed in the display panel DP.

[0159] Also refer to Figure 3 and Figure 4, the light emitting element ED in the pixel PX may be degraded based on the operation time and gray scale of the data signal Di. The degradation compensator 140 generates a degradation compensation value C_AGE based on the operation time of the display device DD, the image data signal DS, and the feedback current signal FI.

[0160] In an embodiment, the degradation compensator 140 may calculate the degradation compensation value C_AGE by considering various factors (e.g., operating temperature) in addition to the operating time of the display device DD, the image data signal DS, and the feedback current signal FI. In an embodiment, in the absence of the image data signal DS and the feedback current signal FI, the degradation compensator 140 may count the operating time of the display device DD to output the degradation compensation value C_AGE.

[0161] In an embodiment, the maximum voltage calculator 130 may generate a result of adding the peak voltage code P_VCODE and the degradation compensation value C_AGE as the maximum voltage code M_VCODE.

[0162] exist Fig.9A In the example shown in , in a case where the degradation compensation value C_AGE is 48, when the peak voltage code P_VCODE is “5470”, the maximum voltage calculator 130 outputs “5518” as the maximum voltage code M_VCODE.

[0163] Accordingly, in this example, when the maximum voltage code M_VCODE is "5518", the voltage controller 150 may output the power supply voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9, as shown in FIG. Fig. 9B as shown in .

[0164] like Fig.9A As shown in , the peak voltage code P_VCODE of “5470” may correspond to 11.0V, and the maximum voltage code M_VCODE of “5518” may correspond to 11.1V.

[0165] In an embodiment, when the maximum voltage code M_VCODE is equal to or less than a reference value (ie, a threshold value), the voltage controller 150 may operate in a power saving mode. In this example, when the reference value has a voltage code of "7168" corresponding to 255 grayscale (255G) and the maximum voltage code M_VCODE is "5519", the voltage controller 150 may operate in a power saving mode.

[0166] In the power saving mode, the voltage controller 150 maintains the voltage levels of the gamma voltages VGMA9, VGMA7, and VGMA5 to be the same as in the normal mode, and the voltage levels of all the gamma voltages VGMA9, VGMA7, and VGMA5 are lower than the voltage level of 11.1V corresponding to the maximum voltage code M_VCODE. In addition, the voltage controller 150 maintains the gamma voltage VGMA3 whose voltage level is higher than the voltage level of 11.1V corresponding to the maximum voltage code M_VCODE and closest to the voltage level of 11.1V to be the same as in the normal mode. In an embodiment, the gamma voltage VGMA3 whose voltage level is higher than the voltage level (voltage level of 11.1V) corresponding to the maximum voltage code M_VCODE and closest to the voltage level corresponding to the maximum voltage code M_VCODE may be referred to as the maximum gamma voltage.

[0167] In the power saving mode, the voltage controller 150 may change the voltage levels of the gamma voltage VGMA1 and the power voltage AVDD to 11.9 V and 13.0 V, respectively, where the gamma voltage VGMA1 and the power voltage AVDD are greater than the gamma voltage VGMA3, which is the maximum gamma voltage. The voltage controller 150 outputs a voltage control signal VCTRL corresponding to the voltage levels of the power voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0168] In the power saving mode, when the peak brightness is 500 nits, the gamma voltage VGMA1 required to generate the grayscale voltage to obtain a brightness higher than the peak brightness is not used in the data driving circuit 200. Therefore, the driving controller 100 can reduce the voltage level of the unnecessary gamma voltage VGMA1, and can also reduce the voltage level of the power supply voltage AVDD to be suitable for the gamma voltage VGMA1 with the reduced voltage level. In this case, the second voltage generator 500 (refer to Figure 3 ) and the data driving circuit 200 (refer to Figure 3 ) power consumption.

[0169] Fig. 10A is a diagram showing a peak voltage code P_VCODE and a maximum voltage code M_VCODE when the peak luminance is 500 nits.

[0170] Fig. 10B is shown in the power saving mode according to Fig. 10A 1 and 2. In this case, the graph compares the voltage level between the power supply voltage AVDD and each of the plurality of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0171] Fig. 10A The peak voltage code P_VCODE shown in Fig.9A The peak voltage code P_VCODE shown in the figure is the same as "5470". However, in Fig. 10A , the degradation compensation value C_AGE increases from "48" to "935".

[0172] Reference Figure 5 , Fig. 10A and Fig. 10B , for the degradation compensation value C_AGE of "935", when the peak voltage code P_VCODE is set to "5470", the maximum voltage calculator 130 outputs "6405" as the maximum voltage code M_VCODE. In an embodiment, the output value of "6405" as the maximum voltage code M_VCODE may correspond to 12.0V.

[0173] In the power saving mode, the voltage controller 150 maintains the gamma voltages VGMA9, VGMA7, VGMA5, and VGMA3 the same as in the normal mode, and all of the gamma voltages VGMA9, VGMA7, VGMA5, and VGMA3 have voltage levels lower than the voltage level of 12.0 V corresponding to the maximum voltage code M_VCODE. In addition, the voltage controller 150 maintains the gamma voltage VGMA1 whose voltage level is higher than the voltage level of 12.0 V corresponding to the maximum voltage code M_VCODE and closest to the voltage level of 12.0 V the same as in the normal mode.

[0174] exist Fig. 10B In the example shown in , since the gamma voltage VGMA1 is maintained the same as that in the normal mode, the power supply voltage AVDD must be maintained the same as that in the normal mode.

[0175] As described above, the pixel PX (refer to Figure 4 ) may degrade based on the operation time. For example, when the operation time becomes longer, the grayscale of the image data signal DS for displaying an image of a given brightness must become higher than the grayscale when the operation time becomes shorter. Therefore, in this case, the grayscale of the image data signal DS for displaying an image of a given brightness may depend on the operation time.

[0176] As from Fig.9A and Fig. 10A As understood, when the degradation degree of the light emitting element ED increases, the degradation compensation value C_AGE may increase. In this case, even if the peak voltage code P_VCODE in both cases is equally maintained, the maximum voltage code M_VCODE may become larger.

[0177] Fig.11A is a diagram showing a peak voltage code P_VCODE and a maximum voltage code M_VCODE when the peak luminance is 200 nits.

[0178] Fig. 11B is shown in the power saving mode according to Fig.11A 1 and 2. In this case, the graph compares the voltage level between the power supply voltage AVDD and each of the plurality of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0179] Reference Figure 5 , Fig.11A and Fig. 11B When the gray scale of the image data signal DS is 255G, the display panel DP (refer to Figure 3 ) is 1000 nits, and when the grayscale of the image data signal DS is 123G, the brightness of the image displayed in the display panel DP is 200 nits. In this case, "G" has the meaning of grayscale.

[0180] exist Fig.11A In the example shown in , for the degradation compensation value C_AGE of “49”, when the peak voltage code P_VCODE is set to “3918”, the maximum voltage calculator 130 outputs “3967” as the maximum voltage code M_VCODE.

[0181] When the maximum voltage code M_VCODE is "3967", the voltage controller 150 may output the power supply voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9, as shown in FIG. Fig. 11B as shown in .

[0182] The peak voltage code P_VCODE of '3918' may correspond to a voltage level of 9.3V, and the maximum voltage code M_VCODE of '3967' may correspond to a voltage level of 9.4V.

[0183] In the power saving mode, the voltage controller 150 maintains the voltage levels of the gamma voltages VGMA9 and VGMA7, which are lower than the 9.4V voltage level corresponding to the maximum voltage code M_VCODE, to be the same as in the normal mode. In addition, the voltage controller 150 maintains the gamma voltage VGMA5, whose voltage level is higher than the 9.4V voltage level corresponding to the maximum voltage code M_VCODE and closest to the 9.4V voltage level, to be the same as in the normal mode. In an embodiment, the gamma voltage VGMA5, whose voltage level is higher than the voltage level corresponding to the maximum voltage code M_VCODE and closest to the voltage level corresponding to the maximum voltage code M_VCODE, may be referred to as the maximum gamma voltage.

[0184] In the power saving mode, the voltage controller 150 may change the voltage levels of the gamma voltages VGMA3 and VGMA1 and the power voltage AVDD to 9.6 V, 9.7 V, and 10.7 V, respectively, and the voltage levels of the gamma voltages VGMA3 and VGMA1 and the power voltage AVDD are greater than the gamma voltage VGMA5, which is a maximum gamma voltage of 9.5 V. The voltage controller 150 outputs a voltage control signal VCTRL corresponding to the voltage levels of the power voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0185] In the power saving mode, when the peak brightness is 200 nits, the gamma voltages VGMA3 and VGMA1 required for generating grayscale voltages for obtaining a brightness higher than the peak brightness are not used in the data driving circuit 200. Therefore, the driving controller 100 can reduce the voltage levels of the unnecessary gamma voltages VGMA3 and VGMA1, and can also reduce the voltage level of the power supply voltage AVDD to be suitable for the gamma voltages VGMA3 and VGMA1 having the reduced voltage levels. In this case, the second voltage generator 500 (refer to Figure 3 ) and the data driving circuit 200 (refer to Figure 3 ) power consumption.

[0186] Fig. 12A is a diagram showing a peak voltage code P_VCODE and a maximum voltage code M_VCODE when the peak luminance is 200 nits.

[0187] Fig. 12B is shown in the power saving mode according to Fig. 12A1 and 2. In this case, the graph compares the voltage level between the power supply voltage AVDD and each of the plurality of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0188] Fig. 12A The peak voltage code P_VCODE shown in Fig.11A The peak voltage code P_VCODE shown in the figure is the same as "3918". However, in Fig. 12A , the degradation compensation value C_AGE increases from "49" to "912".

[0189] Reference Figure 5 , Fig. 12A and Fig. 12B , for the degradation compensation value C_AGE of "912", when the peak voltage code P_VCODE is set to "3918", the maximum voltage calculator 130 outputs "4830" as the maximum voltage code M_VCODE. In an embodiment, the value of "4830" is the maximum voltage code M_VCODE and may correspond to 10.3V.

[0190] In the power saving mode, the voltage controller 150 maintains the voltage levels of the gamma voltages VGMA9, VGMA7, and VGMA5, which are lower than the voltage level of 10.3V corresponding to the maximum voltage code M_VCODE, to be the same as in the normal mode. In addition, the voltage controller 150 maintains the gamma voltage VGMA3, whose voltage level is higher than the voltage level of 10.3V corresponding to the maximum voltage code M_VCODE and closest to the voltage level of 10.3V, to be the same as in the normal mode. In an embodiment, the gamma voltage VGMA3, whose voltage level of 11.8V is higher than the voltage level of 10.3V corresponding to the maximum voltage code M_VCODE and closest to the voltage level corresponding to the maximum voltage code M_VCODE, may be referred to as the maximum gamma voltage.

[0191] In the power saving mode, the voltage controller 150 may change the voltage levels of the gamma voltage VGMA1 and the power voltage AVDD to 11.9 V and 12.9 V, respectively, the voltage levels of the gamma voltage VGMA1 and the power voltage AVDD being greater than the gamma voltage VGMA3, which is a maximum gamma voltage of 11.8 V. The voltage controller 150 outputs a voltage control signal VCTRL corresponding to the voltage levels of the power voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0192] As described above, the pixel PX (refer to Figure 4 ) may degrade based on the operation time. When the operation time becomes longer, the grayscale of the image data signal DS for displaying an image of a given brightness must become higher than the grayscale when the operation time becomes shorter. Therefore, in this case, the grayscale of the image data signal DS for displaying an image of a given brightness may depend on the operation time.

[0193] As from Fig.11A and Fig. 12A As understood, when the degradation degree of the light emitting element ED increases, the degradation compensation value C_AGE may increase. In this case, even if the peak voltage code P_VCODE is maintained the same, the maximum voltage code M_VCODE may become larger.

[0194] Fig.13A is a diagram showing a peak voltage code P_VCODE and a maximum voltage code M_VCODE when the peak luminance is 100 nits.

[0195] Fig. 13B is shown in the power saving mode according to Fig.13A 1 and 2. In this case, the graph compares the voltage level between the power supply voltage AVDD and each of the plurality of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0196] Reference Figure 5 , Fig.13A and Fig. 13B When the gray scale of the image data signal DS is 255G, on the display panel DP (refer to Figure 3 ) is 1000 nits, and when the grayscale of the image data signal DS is 90G, the brightness of the image displayed in the display panel is 100 nits.

[0197] exist Fig.13A In the example shown in , for the degradation compensation value C_AGE of "246", when the peak voltage code P_VCODE is set to "3105", the maximum voltage calculator 130 outputs "3351" as the maximum voltage code M_VCODE.

[0198] When the maximum voltage code M_VCODE is "3351", the voltage controller 150 may output the power supply voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9, as shown in FIG. Fig. 13B as shown in .

[0199] The peak voltage code P_VCODE of '3105' may correspond to a voltage level of 8.4V, and the maximum voltage code M_VCODE of '3351' may correspond to a voltage level of 8.7V.

[0200] In the power saving mode, the voltage controller 150 maintains the voltage levels of the gamma voltages VGMA9 and VGMA7, which are lower than the voltage level of 8.7V corresponding to the maximum voltage code M_VCODE, to be the same as in the normal mode. In addition, the voltage controller 150 maintains the gamma voltage VGMA5, whose voltage level is higher than the voltage level of 8.7V corresponding to the maximum voltage code M_VCODE and closest to the voltage level of 8.7V, to be the same as in the normal mode. In an embodiment, the gamma voltage VGMA5, whose voltage level is higher than the voltage level of 8.7V corresponding to the maximum voltage code M_VCODE and closest to the voltage level of 9.5V corresponding to the maximum voltage code M_VCODE, may be referred to as the maximum gamma voltage.

[0201] In the power saving mode, the voltage controller 150 may change the voltage levels of the gamma voltages VGMA3 and VGMA1 and the power voltage AVDD to 9.6 V, 9.7 V, and 10.7 V, respectively, and the voltage levels of the gamma voltages VGMA3 and VGMA1 and the power voltage AVDD are greater than the gamma voltage VGMA5, which is a maximum gamma voltage of 9.5 V. The voltage controller 150 outputs a voltage control signal VCTRL corresponding to the voltage levels of the power voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0202] In the power saving mode, when the peak brightness is 100 nits, the gamma voltages VGMA3 and VGMA1 required for generating grayscale voltages for obtaining brightness higher than the peak brightness are not used in the data driving circuit 200. Therefore, the driving controller 100 can reduce the voltage levels of the unnecessary gamma voltages VGMA3 and VGMA1, and also reduce the voltage level of the power supply voltage AVDD to the gamma voltages VGMA3 and VGMA1 suitable for the reduced voltage levels. In this case, the second voltage generator 500 (refer to Figure 3 ) and the data driving circuit 200 (refer to Figure 3 ) power consumption.

[0203] Fig.14A is a diagram showing a peak voltage code P_VCODE and a maximum voltage code M_VCODE when the peak luminance is 100 nits.

[0204] Fig. 14B is shown in the power saving mode according to Fig.14A 1 and 2. In this case, the graph compares the voltage level between the power supply voltage AVDD and each of the plurality of gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0205] Fig.14A The peak voltage code P_VCODE shown in Fig.13A The peak voltage code P_VCODE shown in the same "3105"; however, in Fig.14A , the degradation compensation value C_AGE increases from "246" to a value of "587".

[0206] Reference Figure 5 , Fig.14A and Fig. 14B , for the degradation compensation value C_AGE of "587", when the peak voltage code P_VCODE is set to "3105", the maximum voltage calculator 130 outputs "3692" as the maximum voltage code M_VCODE. The output value of "3692" is the maximum voltage code M_VCODE and may correspond to 10.0V.

[0207] In the power saving mode, the voltage controller 150 maintains the voltage levels of the gamma voltages VGMA9, VGMA7, and VGMA5, which are lower than the voltage level of 10.0V corresponding to the maximum voltage code M_VCODE, to be the same as in the normal mode. In addition, the voltage controller 150 may change the voltage levels of the gamma voltages VGMA3 and VGMA1 and the power supply voltage AVDD to 9.6V, 9.7V, and 10.7V, respectively, which are higher than the voltage level of 10.0V corresponding to the maximum voltage code M_VCODE. The voltage controller 150 outputs a voltage control signal VCTRL corresponding to the voltage levels of the power supply voltage AVDD and the gamma voltages VGMA1, VGMA3, VGMA5, VGMA7, and VGMA9.

[0208] When the peak brightness decreases to 100 nits, the voltage controller 150 may further reduce power consumption by decreasing the voltage levels of the gamma voltages VGMA3 and VGMA1 and the power voltage AVDD, which are higher than the voltage level of 10.0 V corresponding to the maximum voltage code M_VCODE.

[0209] The display device having the above configuration can set the voltage levels of the power voltage and the gamma voltage in consideration of the operation mode and the degradation state. Therefore, the power consumption of the display device can be minimized.

[0210] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: Display panel; a drive controller configured to receive an input image signal and output an image data signal based on the input image signal; a voltage generator configured to generate a plurality of gamma voltages in response to a voltage control signal; and a data driving circuit configured to receive the plurality of gamma voltages and provide a data signal corresponding to the image data signal to the display panel, wherein the drive controller operates between a normal mode and a power saving mode, wherein, in the power saving mode, the driving controller generates the voltage control signal for changing a plurality of voltage levels of the plurality of gamma voltages in response to the input image signal and the peak signal, wherein, in the normal mode, at least one of the plurality of gamma voltages has a first voltage level, and Wherein, in the power saving mode, at least one of the plurality of gamma voltages has a second voltage level lower than the first voltage level.

2. The display device according to claim 1, wherein: The drive controller is configured as follows: generating a peak grayscale signal corresponding to the input image signal and the peak signal, generating a maximum voltage code based on a peak voltage code corresponding to the peak grayscale signal and a degradation compensation value corresponding to an operation time, and The voltage control signal corresponding to the maximum voltage code is output.

3. The display device according to claim 2, wherein: The drive controller is configured as follows: When the maximum voltage code is less than the reference value, the power saving mode is used, and When the maximum voltage code is equal to the reference value, the normal mode is operated.

4. The display device according to claim 1, wherein: The voltage generator is configured as follows: A power supply voltage is further generated to be provided to the data driving circuit.

5. The display device according to claim 4, wherein: The drive controller is configured as follows: The voltage control signal for changing a voltage level of the power supply voltage is output in the power saving mode.

6. The display device according to claim 5, wherein: In the power saving mode, the voltage level of the power supply voltage is lower than the voltage level of the power supply voltage in the normal mode.

7. The display device according to claim 1, wherein: The drive controller comprises: a power control module configured to output a peak grayscale signal in response to the peak signal; a peak voltage memory configured to store a peak voltage code corresponding to the peak grayscale signal from the power control module; a degradation compensator configured to provide a degradation compensation value corresponding to the operation time; a maximum voltage calculator configured to output a maximum voltage code based on the peak voltage code from the peak voltage memory and the degradation compensation value from the degradation compensator; and A voltage controller is configured to output the voltage control signal based on the maximum voltage code from the maximum voltage calculator.

8. The display device according to claim 7, wherein: The maximum voltage calculator is configured as: adding the peak voltage code and the degradation compensation value, and The maximum voltage code corresponding to the result of adding the peak voltage code and the degradation compensation value is output.

9. A drive controller, wherein: The drive controller comprises: A power control module configured to output a peak grayscale signal in response to the peak signal; a peak voltage memory configured to store a peak voltage code corresponding to the peak grayscale signal provided from the power control module; a degradation compensator configured to provide a degradation compensation value corresponding to the operation time; a maximum voltage calculator configured to output a maximum voltage code based on the peak voltage code provided from the peak voltage memory and the degradation compensation value provided from the degradation compensator; and A voltage controller is configured to output a voltage control signal for adjusting a plurality of voltage levels of a plurality of gamma voltages based on the maximum voltage code provided from the maximum voltage calculator.

10. The drive controller according to claim 9, wherein: The voltage controller is configured as: When the maximum voltage code is less than the reference value, the system operates in a power saving mode, and When the maximum voltage code is equal to the reference value, the system operates in a normal mode.

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