Row driving output stage circuit, display driving chip and LED display device

Abstract

The invention provides a row driving output stage circuit, a display driving chip and an LED display device, and the row driving output stage circuit is located at the output end of a row driving circuit and is connected with a row of LED lamp beads. The row driving output stage circuit comprises: a primary transistor, the control end of which receives an input signal and the output end of which is connected with the output end of the row driving circuit, and which is conducted according to the effective jump edge of the input signal; the first delay unit delays the effective jump edge of the input signal for a first time to obtain a first delay signal; the control end of the final-stage transistor receives the first delay signal, the output end of the final-stage transistor is connected with the output end of the row driving circuit, and the final-stage transistor is conducted after the primary transistor is conducted. The primary transistor and the final transistor are transistors of the same type, and the effective jump edge represents that the level state of the input signal is changed from invalid to effective. Therefore, the primary transistor is firstly started to release charges of the parasitic capacitance of the output node so as to avoid current overshoot at the starting moment, and meanwhile, the final-stage transistor provides enough current capability for the LED lamp bead after being conducted.

Description

Technical Field

[0001] The present application relates to the field of display drive technology, and in particular to a row drive output stage circuit, a display drive chip and an LED display device. Background Art

[0002] LED display devices usually include an LED light source array and a display driver chip. The LED light source array includes a plurality of LED lamp beads arranged in rows and columns. The display driver chip is divided into a row driver chip and a column driver chip. For the row driver chip, it is connected to the same end of the LED lamp beads in the same row to realize common anode drive or common cathode drive. The row driver chip is responsible for providing driving current to all LED lamp beads on the row when the row is turned on. Therefore, the size of the MOS tube of the output stage in the row driver chip is required to be larger to ensure that sufficient driving current is provided to the LED lamp beads.

[0003] Figure 1 FIG. 4 shows a partial structural diagram of a row driving circuit in the prior art. Figure 1 As shown, the output stage MOS tube of the row driving circuit is a large-sized NMOS tube, which is connected to the cathode of the same row of LED lamp beads (D1, D2...Dm). When the MOS tube is turned on, a path is formed, and current flows through the LED lamp beads. The input signal IN of the row driving circuit needs to pass through a driver chain composed of a series of inverters to increase the driving ability of the inverter step by step to achieve the driving of the output stage MOS tube. At the moment when the output stage MOS tube is turned on, the parasitic capacitance Cs at the output node OUT of the circuit will discharge through the MOS tube, and because the impedance of the MOS tube is very small, a large transient current will be generated on the power supply / ground at the moment of turning on, causing voltage fluctuations on the power supply / ground, thereby affecting the working state of the circuit. Therefore, the current row driving circuit is difficult to control the opening speed of the power tube when it is turned on, and it will produce a large output overshoot that affects the circuit operation. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a row driver output stage circuit, a display driver chip and an LED display device.

[0005] According to one aspect of the present invention, there is provided a row driver output stage circuit, which is located at the output end of the row driver circuit, and the output end of the row driver circuit is connected to the same end of a row of LED lamp beads, wherein the row driver output stage circuit comprises: a primary transistor, whose control end receives an input signal, whose output end is connected to the output end of the row driver circuit, and which is turned on according to the effective transition edge of the input signal; a first delay unit, which delays the effective transition edge of the input signal for a first time to obtain a first delay signal and then outputs it; a final transistor, whose control end receives the first delay signal, whose output end is connected to the output end of the row driver circuit, and which is turned on after the primary transistor is turned on, wherein the primary transistor and the final transistor are transistors of the same type, and the effective transition edge represents that the level state of the input signal changes from invalid to valid.

[0006] Optionally, the row driver output stage circuit further includes: at least one intermediate stage transistor, whose control end is controlled by the input signal, whose output end is connected to the output end of the row driver circuit, and which is turned on before the final stage transistor is turned on, and the at least one intermediate stage transistor is the same type of transistor as the primary transistor.

[0007] Optionally, the row driver output stage circuit also includes: at least one second delay unit, which is correspondingly connected to the at least one intermediate stage transistor, and each second delay unit delays the effective transition edge of the input signal for a second time to obtain a second delay signal and then outputs it to the control end of the corresponding intermediate stage transistor.

[0008] Optionally, the size of the primary transistor is smaller than the size of the final transistor, and the size of the at least one intermediate transistor is smaller than the size of the final transistor.

[0009] Optionally, the row driver output stage circuit further includes: a plurality of enable units, which are respectively connected to a plurality of delay units, the plurality of delay units include the first delay unit and at least one second delay unit, each enable unit is connected between the corresponding delay unit and the control end of the corresponding transistor, receives the input signal, the enable signal and the delay signal to provide a control signal to the corresponding transistor, and the delay signal includes the first delay signal or the second delay signal.

[0010] Optionally, when the enable signal is valid, the enable unit uses the delay signal as the control signal; when the enable signal is invalid, the enable unit uses the input signal as the control signal.

[0011] Optionally, the enabling unit is a logic circuit composed of a plurality of logic gates, and the logic gates include a NAND gate, a NOR gate, a NOT gate, an AND gate, an OR gate or an XOR gate.

[0012] Optionally, the control end of each transistor is connected to a plurality of inverters connected in series, so as to perform signal enhancement processing on the received signal and then provide it to the control end of the transistor.

[0013] Optionally, the first delay unit and each of the second delay units include: a connected switch tube and a current source, the control end of the switch tube receiving the input signal; a capacitor connected between the intermediate node of the switch tube and the current source and the ground end; and an inverter chain, the input end of the inverter chain is connected to the intermediate node of the switch tube and the current source, and the output end of the inverter chain provides a delay signal, and the delay signal includes the first delay signal or the second delay signal.

[0014] Optionally, the switch tubes included in the first delay unit and the second delay unit are of the same type, and the area of ​​the capacitor included in the first delay unit is larger than the area of ​​the capacitor included in the second delay unit.

[0015] Optionally, when the transistors of the same type are NMOS transistors, the effective transition edge is a rising edge; when the transistors of the same type are PMOS transistors, the effective transition edge is a falling edge.

[0016] According to another aspect of the present invention, there is provided a display driver chip, comprising: a power supply; and a plurality of row driver circuits, each row driver circuit being connected to the same end of the same row of LED lamp beads, wherein each of the row driver circuits comprises the above-mentioned row driver output stage circuit.

[0017] According to another aspect of the present invention, there is provided an LED display device, comprising: an LED array, the LED array comprising a plurality of LED lamp beads arranged in an array; and a plurality of row drive circuits, each of the row drive circuits correspondingly controlling a row of LED lamp beads, and each of the row drive circuits comprising the above-mentioned row drive output stage circuit, wherein the row drive output stage circuit allows a stable drive current to flow through the row of LED lamp beads after being fully turned on.

[0018] According to another aspect of the present invention, there is provided a terminal electronic device comprising the above-mentioned row driver output stage circuit.

[0019] The beneficial effects of this application include at least: The embodiment of the present application provides a row drive output stage circuit, a display driver chip and an LED display device, the output stage of the row drive circuit is divided into multiple stages, each stage includes a transistor, so that the row drive output stage circuit includes at least a primary transistor and a final transistor, and the control end of the final transistor is connected to a first delay unit. The primary transistor is controlled to be turned on first according to the input signal to form a charge release path of the parasitic capacitor to slowly pull down the voltage of the output node to avoid current overshoot. The effective jump edge of the input signal is then delayed by the first delay unit, so that the final transistor is turned on after the primary transistor is turned on for a first time, so that the output stage circuit is fully turned on, which is sufficient to carry a large current, and provide the LED lamp beads at the output end with a current path and sufficient current driving capability during normal operation. The output overshoot at the moment of opening can be avoided by the cooperation of the primary transistor and the final transistor, and the output stage can be turned on slowly to control the opening speed.

[0020] Furthermore, the row driver output stage circuit also includes at least one intermediate stage transistor, which is turned on before the final stage transistor. The intermediate stage transistor cooperates with the primary transistor to accurately adjust the voltage drop speed of the output node, thereby adjusting the start-up speed of the output stage.

[0021] Furthermore, an enabling unit is provided before the delay unit, and the effective state of the delay signal can be controlled by the enabling unit. When the enabling signal is valid, the delay signal is provided to the control end of the corresponding transistor to delay the turning on of the transistor; when the enabling signal is invalid, the input signal is provided to the control end of the corresponding transistor to turn on and off the controlled transistor and the primary transistor at the same time, thereby quickly forming a current path for the LED lamp bead in the row driving circuit that requires fast turning on.

[0022] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A partial structural schematic diagram of a row driving circuit in the prior art is shown; Figure 2 shows a schematic circuit diagram of a row driver output stage circuit according to a first embodiment of the present invention; Figure 3 Shows Figure 2 A schematic diagram of waveforms of various signals in a row driver output stage circuit; Figure 4 shows a schematic circuit diagram of a row driver output stage circuit according to a second embodiment of the present invention; Figure 5 shows a schematic circuit diagram of a row driver output stage circuit according to a third embodiment of the present invention; Figure 6 shows a schematic circuit diagram of a row driver output stage circuit according to a fourth embodiment of the present invention; Figure 7 shows a schematic circuit diagram of a row driver output stage circuit according to a fifth embodiment of the present invention; Figure 8 shows a schematic circuit diagram of a row driver output stage circuit according to a sixth embodiment of the present invention; Fig. 9 A partial structural schematic diagram of an LED display device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] In order to facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The drawings provide preferred embodiments of the present application. However, the present application can be implemented in different forms and is not limited to the embodiments described herein.

[0025] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in another way. "Multiple" means two or more than two.

[0026] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0027] Figure 2 FIG. 4 shows a schematic circuit diagram of a row driver output stage circuit according to a first embodiment of the present invention, Figure 3 Shows Figure 2 Schematic diagram of the waveforms of various signals in the row driver output stage circuit.

[0028] and Figure 1 Similarly, the row driving circuit of this embodiment is connected to the same end of a row of LED lamp beads. When the output stage power tube of the row driving circuit is NMOS, the cathodes of a row of LED lamp beads are connected together and connected to the output end of the row driving circuit. Figure 2As shown, the row driver output stage circuit 100 of this embodiment is located at the output end of the row driver circuit (other circuit structures and LED lamp beads of the row driver circuit are not shown). Multi-stage transistors are selected as the output stage of the row driver circuit, and the output signal OUT is provided from the drain of the multi-stage transistors. After the row driver output stage circuit 100 is fully turned on, a stable driving current flows through a row of LED lamp beads.

[0029] like Figure 2 , the row driver output stage circuit 100 of this embodiment includes at least two stages of transistors, namely, a primary transistor M0 and a final transistor M1. The control end of the primary transistor M0 receives the input signal IN, and the output end is connected to the output end of the row driver circuit, that is, the generating end of the output voltage OUT. In this embodiment, the primary transistor M0 is an NMOS tube, whose drain is connected to the output end, the source is grounded, and the gate is controlled by the input signal IN. The primary transistor M0 is turned on and off according to the valid jump edge and the invalid jump edge of the input signal IN. The valid jump edge represents that the level state of the input signal IN changes from invalid to valid, and the invalid jump edge represents that the level state of the input signal IN changes from valid to invalid. That is, the primary transistor M0 is turned on when the input signal IN is valid, and is turned off when the input signal IN is invalid. Here, valid can be a high level, and invalid can be a low level. When the transistor is a PMOS tube, the level state is opposite. A first drive chain 101 is also connected to the control end of the primary transistor M0. The first drive chain 101 includes a plurality of inverters connected in series to perform signal enhancement processing on the received input signal IN before providing it to the control end of the primary transistor M0. The first drive chain 101 may include an even number of inverters, for example, 4, to amplify the signal according to a certain ratio.

[0030] The final transistor M1 is a transistor of the same type as the primary transistor M0, and is also an NMOS transistor. The drain of the final transistor M1 is connected to the output terminal, the source is grounded, and the control terminal is connected to the second drive chain 111, which also includes a plurality of inverters connected in series. A first delay unit 121 is also connected before the second drive chain 111. The first delay unit 121 is used to delay the effective transition edge of the input signal IN by a first time to obtain a first delay signal INDLY1 and then output it. The first delay unit 121 only delays the effective transition edge of the input signal IN by a first time while the invalid transition edge remains unchanged, that is, only delays the rising edge of the input signal IN by a first time to obtain the first delay signal INDLY1. Therefore, the control terminal of the final transistor M1 is similar to receiving the first delay signal INDLY1, which is turned on after the primary transistor M0 is turned on.

[0031] In one embodiment, the first delay unit 121 includes a switch tube P1, a current source A1, a first capacitor C1 and an inverter chain. The output stage of the row drive output stage circuit is an NMOS tube, so the switch tube P1 can be a PMOS tube, whose control end receives the input signal IN, the source receives the power supply voltage V1, and the drain is connected to the inverter chain. The switch tube P1 and the current source A1 are connected in series, and the drain of the switch tube P1 is grounded through the current source A1, that is, the current source A1 is connected between the drain of the switch tube P1 and the ground terminal, and the first capacitor C1 is connected between the middle node of the switch tube P1 and the current source A1 and the ground terminal, that is, the first capacitor C1 is also connected between the drain of the switch tube P1 and the ground terminal. The input end of the inverter chain is connected to the drain of the switch tube P1, and the output end of the inverter chain provides the first delay signal INDLY1. The inverter chain here includes, for example, an odd number of inverters, such as 3 inverters. Then, when the input signal IN is at a low level, the switch tube P1 is turned on. The size of the switch tube P1 is large, and the first capacitor C1 can be quickly charged, so that the input end of the inverter chain is at a high level, the output end is at a low level, and the level state of the first delay signal INDLY1 is at a low level; when the input signal IN is at a high level, the switch tube P1 is turned off, and the first capacitor C1 is discharged through the current source A1. The carrying current of the current source A1 is very small, so that the first capacitor C1 is discharged with a very small current, limiting its discharge speed. The charge on the first capacitor C1 is not completely released until after a period of time. At this time, the output end of the inverter chain becomes a high level, and the level state of the first delay signal INDLY1 is a high level. Therefore, the first delay signal INDLY1 can only delay the rising edge of the input signal IN, while the falling edge remains unchanged, and the effective jump edge is the rising edge.

[0032] Of course, in other embodiments, the switch tube in the first delay unit 121 may also be an NMOS tube, in which case the input end of the current source A1 is connected to the power supply end, the output end is connected to the drain of the NMOS tube, the source of the NMOS tube is grounded, and the connection method of the first capacitor C1 and the inverter chain is the same as above. At this time, the input end of the NMOS tube receives the inverted signal of the input signal IN, and the output end of the inverter chain outputs the inverted signal of the first delay signal, so an inverter needs to be set at the output end of the inverter chain to obtain the required first delay signal INDLY1.

[0033] by Figure 2 Taking the circuit structure shown in the figure as an example, the corresponding signal waveform is as follows Figure 3 As shown, Figure 3In the example, before time t1, the input signal IN is at a low level, the level of the first delay signal INDLY1 is also at a low level, the output stage transistors are not turned on, and the output voltage OUT at the output end is at a high level. At time t1, the input signal IN jumps from a low level to a high level, generating an effective jump edge of the input signal IN, and the first delay signal INDLY1 still maintains a low level. At this time, the primary transistor M0 is turned on, the output voltage OUT begins to slowly decrease, and the final transistor M1 is turned off. Since the size of the primary transistor M0 is small and the discharge is slow, the output voltage will not produce a large downward overshoot at time t1. At time t2, the first capacitor C1 is discharged, the level of the first delay signal INDLY1 is at a high level, and the final transistor M1 begins to turn on. The size of the final transistor M1 is larger than the size of the primary transistor M0, and the on-resistance is very small, so that the output stage is fully turned on, the output voltage OUT is zero, and a current path is formed on the LED lamp bead. Then, the time period t1-t2 is the first time, and a constant current flows through the LED lamp bead between the time period t2-t3. At time t3, the input signal IN changes from high level to low level, generating an invalid transition edge of the input signal IN, and the first delay signal INDLY1 also changes to low level, the primary transistor M0 and the final transistor M1 are both turned off, the output stage circuit is turned off, and the output voltage OUT returns to a high level. Then, a new working cycle is started at time t4, and the previous actions are repeated. The time period t1-t4 is a working cycle.

[0034] Figure 4 FIG. 4 is a schematic circuit diagram of a row driver output stage circuit according to a second embodiment of the present invention. In some embodiments, the row driver output stage circuit may further include an intermediate stage transistor, such as Figure 4 As shown, the row driver output stage circuit 100 of this embodiment is Figure 2 The invention also includes at least one intermediate-stage transistor, the control end of the intermediate-stage transistor is controlled by the input signal IN, the output end is connected to the output end of the row driving circuit, the intermediate-stage transistor is turned on before the final-stage transistor is turned on, and is the same type of transistor as the primary transistor.

[0035] Figure 4In the embodiment, an intermediate-stage transistor M2 is taken as an example, and of course, a plurality of identical intermediate-stage transistors may also be included. The drain of the intermediate-stage transistor M2 is connected to the output end, the source is grounded, and the control end receives the input signal IN through the third drive chain 112 composed of a plurality of inverters, so the intermediate-stage transistor M2 in this embodiment can be turned on and off simultaneously with the primary transistor M0. The sizes of the primary transistor M0 and the intermediate-stage transistor M2 are both smaller than the size of the final-stage transistor M1. After the primary transistor M0 and the intermediate-stage transistor M2 are turned on, the output voltage OUT slowly decreases. And the decreasing speed of the output voltage OUT can be adjusted by adjusting the sizes of the primary transistor M0 and the intermediate-stage transistor M2, thereby adjusting the opening speed of the output stage circuit.

[0036] Figure 5 FIG. 4 shows a schematic circuit diagram of a row driver output stage circuit according to a third embodiment of the present invention. Figure 5 As shown, in this embodiment Figure 4 On the basis of the embodiment, a second delay unit 122 is further added, and each second delay unit is respectively connected to a corresponding intermediate-stage transistor, for example, the second delay unit 122 is connected to the control end of the intermediate-stage transistor M2 through the third driving chain 112. The second delay unit 122 has the same circuit structure and working principle as the first delay unit 121, and the second delay unit 122 delays the effective transition edge of the input signal IN by a second time to obtain a second delay signal INDLY2, and then outputs it to the control end of the corresponding intermediate-stage transistor M2.

[0037] The second delay unit 122 includes a switch tube P1, a current source A1, a second capacitor C2 and an inverter chain. The switch tube P1, the current source A1, the second capacitor C2 and the inverter chain can be exactly the same as those in the first delay unit 121. The switch tube P1 is of the same type as the switch tube P1 in the first delay unit 121, that is, both are PMOS tubes. In addition, the area of ​​the first capacitor C1 included in the first delay unit 121 can be made larger than the area of ​​the second capacitor C2 included in the second delay unit 122, so that the first time is greater than the second time, so that the intermediate stage transistor M2 is turned on before the final stage transistor M1, and is turned on after the primary transistor M0. By adjusting the area of ​​the second capacitor C2 to control the second time, the turn-on time of the intermediate stage transistor M2 can be controlled, thereby controlling the turn-on speed of the output stage circuit. In combination with adjusting the area of ​​the first capacitor C1 to control the first time, the turn-on time of the output stage circuit can be further controlled.

[0038] Figure 6 FIG. 4 shows a schematic circuit diagram of a row driver output stage circuit according to a fourth embodiment of the present invention. Figure 6 As shown, the row driver output stage circuit 100 of this embodiment is Figure 2On the basis of the embodiment, an enabling unit 131 is added, and the enabling unit 131 is connected to the first delay unit 121, and can control the effective state of the first delay signal INDLY1, that is, determine whether the first delay signal INDLY1 is effective. When the row driver output stage circuit 100 includes a multi-stage transistor, for example, including a primary transistor, a final stage transistor and at least one intermediate stage transistor, and the control terminals of the final stage transistor and each intermediate stage transistor are connected to the delay unit, an enabling unit can be set for the delay unit of each transistor. That is, the enabling unit 131 can match the delay unit.

[0039] In this embodiment, the enabling unit 131 is connected between the first delay unit 121 and the control end of the final transistor M1, and the enabling unit 131 receives the input signal IN, the enabling signal EN and the first delay signal INDLY1 to provide the control signal CTRL1 to the final transistor M1. The enabling unit 131 can be connected to the output end of the second driving chain 111, or to the input end of the second driving chain 111, and the specific position is determined according to actual needs. When the enabling signal EN is valid, the enabling unit 131 uses the first delay signal INDLY1 as the control signal CTRL1; and when the enabling signal EN is invalid, the control signal CTRL1 is controlled by the input signal IN, for example, the enabling unit 131 uses the input signal IN as the control signal CTRL1.

[0040] The enabling unit 131 is a logic circuit composed of a plurality of logic gates, wherein the logic gates include a NAND gate, a NOR gate, a NOT gate, an AND gate, an OR gate or an XOR gate. Specifically, the final transistor M1 is an NMOS tube, and the first delay unit 121 is Figure 2 The circuit structure shown in FIG. 1 is used as an example to illustrate that the enabling unit 131 includes a NOT gate O3, an OR gate, and an AND gate. The input end of the NOT gate O3 receives the enable signal EN, the output end is connected to one input end of the OR gate, the other input end of the OR gate receives the first delay signal INDLY1, the output end is connected to one input end of the AND gate, the other input end of the AND gate receives the input signal IN, and the output end provides a control signal CTRL1. In some embodiments, the OR gate can be replaced by a combination of a NOR gate and a NOT gate, and the AND gate can be replaced by a combination of a NAND gate and a NOT gate. For example Figure 6In the embodiment, the enabling unit 131 includes a NOT gate O3, a NOR gate U1, a NOT gate O1, a NAND gate U2, and a NOT gate O2, wherein the NOR gate U1 and the NOT gate O1 are equivalent to an OR gate, and the NAND gate U2 and the NOT gate O2 are equivalent to an AND gate. The NOT gate O3 receives an enable signal EN to obtain an inverted signal ENB of the enable signal, and two input terminals of the NOR gate U1 receive the inverted signal ENB of the enable signal and the first delay signal INDLY1 respectively, and the output of the NOR gate U1 outputs an intermediate signal X through the NOR gate O1, and the output terminal of the NOT gate O1 is connected to an input terminal of the NAND gate U2, and the other input terminal of the NAND gate U2 receives the input signal IN, and the output terminal provides a control signal CTRL1 through the NOR gate O2. Then, when the enable signal EN is invalid, EN=0, ENB=1, the intermediate signal X is at a high level, the output control signal CTRL1 is controlled by the input signal IN, and the primary transistor M0 and the final transistor M1 are turned on at the same time; when the enable signal EN is valid, EN=1, ENB=0, the output control signal CTRL1 is controlled by the first delay signal INDLY1, and the final transistor M1 is turned on with a delay.

[0041] In other embodiments, when the switch tube in the first delay unit 121 is an NMOS tube, the input end of the current source A1 is connected to the power supply end, the output end is connected to the drain of the NMOS tube, and the source of the NMOS tube is grounded. At this time, the input end of the NMOS tube receives the inverted signal of the input signal IN, and an inverter needs to be connected to the output end of the inverter chain of the first delay unit 121 to obtain the first delay signal INDLY1, and then through Figure 6 The enabling unit 131 shown can obtain the control signal. When the switch tube in the first delay unit 121 is an NMOS tube, but the output end of the inverter chain is not connected to an additional inverter, the output end of the inverter chain can be directly connected to the enabling unit. At this time, the structure of the enabling unit also needs to be changed. At this time, the enabling unit can only include an OR gate and an AND gate. And replaced by an OR gate Figure 6 The combination of NAND gate U2 and NOT gate O2 is replaced by AND gate Figure 6 The combination of the NOR gate U1 and the NOR gate O1. The specific circuit structure can be found in the following Figure 8 The circuit structure of the enabling unit 131 is also required. Figure 8 The output end of the circuit structure of the enabling unit 131 shown is also connected to an inverter to obtain the required control signal CTRL1.

[0042] Of course, the first delay unit 121 and the enabling unit 131 may also have other circuit structures and combinations, which will not be described one by one here, and those skilled in the art may infer them based on the above description.

[0043] Figure 7FIG. 4 shows a schematic circuit diagram of a row driver output stage circuit according to a fifth embodiment of the present invention. Figure 7 As shown, in this embodiment, the row driver output stage circuit includes a primary transistor M0, a final transistor M1 and a plurality of intermediate transistors (M2...Mn). Figure 5-Figure 7 In the embodiment, the output ends of the first delay unit 121 and the plurality of second delay units 122 are each connected to an enabling unit 131. That is, the plurality of enabling units are respectively connected to the plurality of delay units, the plurality of delay units include a first delay unit and at least one second delay unit, and each enabling unit is connected between the corresponding delay unit and the control end of the corresponding transistor, receives an input signal, an enabling signal and a delay signal, so as to provide a control signal to the corresponding transistor, and the delay signal includes a first delay signal or a second delay signal. Similarly, a driving chain consisting of a plurality of inverters connected in series can be connected to the control end of each transistor to perform signal enhancement processing on the received signal and then provide it to the control end of the transistor. For each enabling unit 131, when the enabling signal is valid, the enabling unit 131 uses the delay signal as a control signal; when the enabling signal is invalid, the enabling unit 131 uses the input signal as a control signal. Further, the second time in each second delay unit may not be exactly the same, so that the plurality of intermediate-stage transistors may not be turned on at the same time.

[0044] The enabling unit in this embodiment may be Figure 6 The circuit structure shown in, or other circuit structures that can achieve similar functions, are only exemplified here and are not intended to limit the embodiments of the present invention. In this embodiment, multiple enabling units are respectively controlled by multiple enabling signals, and the opening speed of the output stage circuit can be adjusted and controlled by configuring different values ​​of the enabling signal EN.

[0045] Figure 8 FIG. 2 shows a schematic circuit diagram of a row driver output stage circuit according to a sixth embodiment of the present invention. The output stage transistors mentioned above are all NMOS tubes, and in practical applications, the output stage transistors can also be all PMOS tubes. When the output stage transistors are all PMOS tubes, the drains of the PMOS tubes are connected together as the output end of the output stage circuit to provide the output voltage OUT, while the source receives the power supply voltage VDD, and the control end receives the input signal IN or the delay signal through the drive chain. Figure 8 The circuit structure that is the same as that in the above embodiment will not be described in detail here.

[0046] like Figure 8As shown, as an example, the row driver output stage circuit 100 includes a primary transistor M0, a final transistor M1, a first drive chain 101, a second drive chain 111, a first delay unit 121 and an enable unit 131. The first delay unit 121 includes a switch tube N1, a current source A1, a first capacitor C1 and an inverter chain. When the final transistor M1 is a PMOS tube, the switch tube N1 is, for example, an NMOS tube. The switch tube N1 is connected in series with the current source A1, and the source of the switch tube N1 is grounded, and the drain is connected to the power supply terminal through the current source A1. The first capacitor C1 is connected between the middle node of the switch tube N1 and the current source A1 and the ground terminal, that is, the first capacitor C1 is connected between the drain of the switch tube N1 and the ground terminal, and the inverter chain includes an odd number of inverters, for example, three, the input end of the inverter chain is connected to the drain of the switch tube N1, and the output end outputs the first delay signal INDLY1. At this time, the effective transition edge is the falling edge, which is effective during the low level period of the input signal IN and invalid during the high level period.

[0047] When the final transistor M1 is a PMOS tube, the enabling unit 131 includes an AND gate and an OR gate, the two input ends of the AND gate receive the enabling signal EN and the first delay signal INDLY1 respectively, the output end is connected to one input end of the OR gate, the other input end of the OR gate receives the input signal IN, and the output end provides the control signal CTRL1. In some embodiments, the OR gate can be replaced by a combination of a NOR gate and a NOT gate, and the AND gate can be replaced by a combination of a NAND gate and a NOT gate. For example Figure 8 In the embodiment, the enabling unit 131 includes a NAND gate U1, a NOT gate O1, a NOR gate U2 and a NOT gate O2, wherein the NAND gate U1 and the NOT gate O1 are equivalent to an AND gate, and the NOR gate U2 and the NOT gate O2 are equivalent to an OR gate. The two input ends of the NAND gate U1 receive the enable signal EN and the first delay signal INDLY1 respectively, and the output of the NAND gate U1 obtains the intermediate signal X through the NOT gate O1, the output end of the NOT gate O1 is connected to an input end of the NOR gate U2, the other input end of the NOR gate U2 receives the input signal IN, and the output end provides the control signal CTRL1 through the NOT gate O2. Then, when the enable signal EN is invalid, EN=0, the intermediate signal X is at a low level, the output control signal CTRL1 is controlled by the input signal IN, and the primary transistor M0 and the final transistor M1 are turned on at the same time; when the enable signal EN is valid, EN=1, the output control signal CTRL1 is controlled by the first delay signal INDLY1, and the final transistor M1 is turned on with a delay. Other identical circuit structures are not repeated here.

[0048] In other embodiments, Figure 8 The first delay unit 121 in can be replaced by Figure 2The circuit structure of the first delay unit 121 in the embodiment of the present invention is as follows: in this case, the switch tube is a PMOS tube, the control end of the switch tube receives the inverted signal of the input signal IN, the output end of the inverter chain can be connected to another inverter, and the enabling unit is still Figure 8 The circuit structure shown in the enabling unit 131 in FIG. Figure 8 The first delay unit 121 in is replaced by Figure 2 In the first delay unit 121, the control end of the switch tube receives the inverted signal of the input signal IN, and the output end of the inverter chain is directly connected to the enabling unit. Figure 8 The enabling unit in is replaced by Figure 2 The circuit structure of the enabling unit 131 in Figure 2 The output end of the enabling unit 131 is connected to an inverter to obtain the required control signal CTRL1.

[0049] Of course, the present invention also provides a row driving circuit and a display driving chip, the row driving circuit includes the above Figure 2-Figure 8 The row driver output stage circuit shown in any embodiment. The display driver chip is used to drive a display panel, and the display panel is, for example, an LED panel. The display driver chip may include multiple row driver circuits, and each row driver circuit is connected to the same end of the same row of LED lamp beads. The display driver chip may also include a power supply and other circuit structures, such as a discharge circuit, a timing controller, etc.

[0050] Fig. 9 A partial structural schematic diagram of an LED display device according to an embodiment of the present invention is shown.

[0051] like Fig. 9 As shown, this embodiment further provides an LED display device 300, which includes an LED array 320 and a plurality of row drive circuits 310. The LED array 320 includes a plurality of LED lamp beads D arranged in an array. Each row drive circuit 310 controls a row of LED lamp beads, and each row drive circuit 310 includes the row drive output stage circuit 100 of the above embodiment. After the row drive output stage circuit is fully turned on, a stable drive current flows through the corresponding row of LED lamp beads.

[0052] Furthermore, the present invention may also provide a terminal electronic device, which may include the row driver output stage circuit of any of the above embodiments. For example, the terminal electronic device may include Fig. 9 The LED display device described herein, the terminal electronic device may be a mobile phone, a tablet computer, an electronic watch, etc., but is not limited thereto.

[0053] The row drive output stage circuit, display driver chip and LED display device of the embodiment of the present invention divide the output stage of the row drive circuit into multiple stages, each stage includes a transistor, so that the row drive output stage circuit includes at least a primary transistor and a final transistor, and a first delay unit is connected to the control end of the final transistor. The primary transistor is controlled to be turned on first according to the input signal to form a charge release path of the parasitic capacitor to slowly pull down the voltage of the output node to avoid current overshoot. The effective jump edge of the input signal is delayed by the first delay unit, so that the final transistor is turned on after the primary transistor is turned on for a first time, so that the output stage circuit is fully turned on, which is sufficient to carry a large current, and provide a current path and sufficient current driving capability for the LED lamp beads at the output end during normal operation. The output overshoot at the moment of opening is avoided by the cooperation of the primary transistor and the final transistor, and the output stage can be turned on slowly to control the opening speed.

[0054] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A row driver output stage circuit, located at the output end of the row driver circuit, the output end of the row driver circuit is connected to the same end of a row of LED lamp beads, characterized in that: The row driver output stage circuit comprises: A primary transistor, the control end of which receives an input signal, the output end of which is connected to the output end of the row driving circuit, and is turned on according to a valid transition edge of the input signal; A first delay unit, delaying the effective transition edge of the input signal for a first time to obtain a first delayed signal and then outputting it; The final transistor has a control end receiving the first delay signal, an output end connected to the output end of the row driving circuit, and is turned on after the primary transistor is turned on. The primary transistor and the final transistor are transistors of the same type, and the effective transition edge represents that the level state of the input signal changes from invalid to valid.

2. The row driver output stage circuit according to claim 1, characterized in that: Also includes: At least one intermediate stage transistor has a control end controlled by the input signal, an output end connected to the output end of the row driving circuit, and is turned on before the final stage transistor is turned on. The at least one intermediate stage transistor is a transistor of the same type as the primary transistor.

3. The row driver output stage circuit according to claim 2, characterized in that: Also includes: At least one second delay unit is connected to the at least one intermediate stage transistor. Each second delay unit delays the effective transition edge of the input signal for a second time to obtain a second delay signal and then outputs it to the control end of the corresponding intermediate stage transistor.

4. The row driver output stage circuit according to claim 2, characterized in that: The size of the primary stage transistor is smaller than the size of the final stage transistor, and the size of the at least one intermediate stage transistor is smaller than the size of the final stage transistor.

5. The row driver output stage circuit according to claim 3, characterized in that: Also includes: A plurality of enabling units are respectively connected to a plurality of delay units, wherein the plurality of delay units include the first delay unit and the at least one second delay unit. Each enabling unit is connected between the corresponding delay unit and the control terminal of the corresponding transistor, receives the input signal, the enabling signal and the delay signal to provide a control signal to the corresponding transistor, and the delay signal includes the first delay signal or the second delay signal.

6. The row driver output stage circuit according to claim 5, characterized in that: When the enable signal is valid, the enable unit uses the delay signal as the control signal; when the enable signal is invalid, the enable unit uses the input signal as the control signal.

7. The row driver output stage circuit according to claim 5, characterized in that: The enabling unit is a logic circuit composed of a plurality of logic gates, wherein the logic gates include a NAND gate, a NOR gate, a NOT gate, an AND gate, an OR gate or an XOR gate.

8. The row driver output stage circuit according to any one of claims 1 to 7, characterized in that: The control end of each transistor is connected to a plurality of inverters connected in series, so as to perform signal enhancement processing on the received signal and then provide it to the control end of the transistor.

9. The row driver output stage circuit according to claim 3, characterized in that: The first delay unit and each of the second delay units include: A switch tube and a current source connected to each other, wherein a control end of the switch tube receives the input signal; A capacitor connected between an intermediate node between the switch tube and the current source and a ground terminal; and An inverter chain, wherein an input end of the inverter chain is connected to an intermediate node between the switch tube and the current source, and an output end of the inverter chain provides a delayed signal, wherein the delayed signal includes the first delayed signal or the second delayed signal.

10. The row driver output stage circuit according to claim 9, characterized in that: The switch tubes included in the first delay unit and the second delay unit are of the same type, and the area of ​​the capacitor included in the first delay unit is larger than the area of ​​the capacitor included in the second delay unit.

11. The row driver output stage circuit according to claim 1, characterized in that: When the transistors of the same type are NMOS tubes, the effective transition edge is a rising edge; when the transistors of the same type are PMOS tubes, the effective transition edge is a falling edge.

12. A display driver chip, characterized in that: include: power supply; as well as Multiple row drive circuits, each row drive circuit is connected to the same end of the same row of LED lamp beads, Wherein, each of the row driving circuits comprises a row driving output stage circuit according to any one of claims 1-11.

13. An LED display device, characterized in that: include: An LED array, wherein the LED array includes a plurality of LED lamp beads arranged in an array; as well as A plurality of row drive circuits, each row drive circuit correspondingly controls a row of LED lamp beads, Each of the row driving circuits comprises a row driving output stage circuit according to any one of claims 1 to 11, and the row driving output stage circuit allows a stable driving current to flow through the row of LED lamp beads after being fully turned on.

14. A terminal electronic device, characterized in that: include: A row driver output stage circuit according to any one of claims 1 to 11.

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