Scanning driving circuit, display panel and electronic equipment

Abstract

The invention provides a scanning driving circuit, a display panel and electronic equipment, which can reduce power consumption. The first selection module of each stage of scanning driving unit receives a shift signal output by the previous stage of scanning driving unit and receives a shift signal output by the next stage of scanning driving unit; when the Nth-stage scanning driving unit receives shift signals output by the (N-1) th-stage scanning driving unit and the (N + 1) th-stage scanning driving unit, and the Nth-stage scanning driving unit receives a trigger signal, the first selection module controls the scanning signal output module of the Nth-stage scanning driving unit to start to output a scanning signal; the second selection module of each stage of scanning driving unit receives a scanning signal output by the previous stage of scanning driving unit; and when the Mth-stage scanning driving unit receives the scanning signal output by the (M-1) th-stage scanning driving unit and the Mth-stage scanning driving unit receives a cut-off signal, the second selection module controls the scanning signal output module of the Mth-stage scanning driving unit to stop outputting the scanning signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scanning drive circuit, a display panel and an electronic device. Background Art

[0002] The main component of an electronic device to realize the display function is the display panel. The display panel includes a display area and a non-display area. The display area includes a plurality of pixels arranged in an array. Each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is used to drive the light-emitting element to emit light to display an image; the non-display area is provided with a scanning drive circuit for providing a scanning signal to the pixel circuit so that the light-emitting element is lit row by row under the drive of the pixel circuit.

[0003] When current electronic devices display images, generally all areas of the screen have the same refresh frequency, that is, the scanning signals of all rows are refreshed at the same frequency, which makes the power consumption of the display panel relatively high, is not conducive to improving the battery life of the electronic device, and reduces the user experience. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a scanning driving circuit, a display panel and an electronic device, which can reduce power consumption.

[0005] In a first aspect, an embodiment of the present application provides a scan driving circuit, which includes: n scan driving units arranged in cascade, n is a positive integer greater than or equal to 2; the scan driving units include: a first selection module, a second selection module and a scan signal output module; the first selection module of each level of the scan driving unit receives a shift signal output by the first selection module in the previous level of the scan driving unit and receives a shift signal output by the first selection module in the next level of the scan driving unit; when the first selection module of the Nth level of the scan driving unit receives the shift signal output by the first selection module in the (N-1)th level of the scan driving unit and receives the shift signal output by the first selection module in the (N+1)th level of the scan driving unit, and When the first selection module of the Nth level scanning driving unit receives a trigger signal, the first selection module is used to control the scanning signal output module of the Nth level scanning driving unit to start outputting the scanning signal; the second selection module of each level scanning driving unit receives the scanning signal output by the scanning signal output module in the previous level scanning driving unit; when the second selection module of the Mth level scanning driving unit receives the scanning signal output by the scanning signal output module in the (M-1)th level scanning driving unit, and the second selection module of the Mth level scanning driving unit receives a cutoff signal, the second selection module is used to control the scanning signal output module of the Mth level scanning driving unit to stop outputting the scanning signal; N<M, and N is greater than or equal to 1, and M is less than or equal to n.

[0006] The setting of the first selection module and the second selection module can control the time when the scanning signal output module outputs a valid scanning signal, and control the cutoff of the valid scanning signal. In this way, the refresh frequency of local pixels can be controlled, so that the refresh frequency of some areas is higher and the refresh frequency of some areas is lower. There is no need to provide a higher refresh frequency for each area, thereby reducing the power consumption of the display panel.

[0007] Exemplarily, the above scanning signal is, for example, an effective scanning signal, which is a scanning signal that can control the corresponding transistor to be turned on. When the transistor is a P-type transistor, the effective scanning signal is a low-level signal; when the transistor is an N-type transistor, the effective scanning signal is a high-level signal.

[0008] Exemplarily, the above shift signal, trigger signal and cut-off signal are all valid shift signal, valid trigger signal and valid cut-off signal, and the valid shift signal, valid trigger signal and valid cut-off signal are signals that can control the conduction of the corresponding transistor. When the transistor is a P-type transistor, the valid signal is a low-level signal; when the transistor is an N-type transistor, the valid signal is a high-level signal.

[0009] According to the first aspect, a first selection module is electrically connected to a first shift signal input terminal, a second shift signal input terminal, a first clock signal terminal, a trigger signal input terminal, a first level signal receiving terminal, a shift signal output terminal and a first node; a second selection module is electrically connected to a first node, a scan signal input terminal, a first level signal receiving terminal, a second level signal receiving terminal, a cutoff signal input terminal and a second node; the second node and the second level signal receiving terminal are connected; a scan signal output module is electrically connected to the first node, the second node, the first clock signal terminal, the second clock signal terminal, the first level signal receiving terminal, the second level signal receiving terminal and the scan signal output terminal; the first selection module is used to receive a first shift signal received by the first shift signal input terminal, a first clock signal by the first clock signal terminal, a trigger signal input by the trigger signal input terminal and a first level signal received by the first level signal receiving terminal, and output a shift signal through the shift signal output terminal in response to the first shift signal and the second shift signal received by the second shift signal input terminal, and control the signal of the first node; wherein the first shift signal input terminal of the current level scan driving unit is connected to the previous level scan driving unit. The first selection module is used to receive the first level signal received by the first level signal receiving end, the second level signal received by the second level signal receiving end and the first scanning signal received by the scanning signal input end, and control the signal of the first node in response to the cut-off signal input end and the signal at the second node; the first scanning signal is the scanning signal output by the scanning signal output module of the previous level; the scanning signal output module is used to receive the first level signal received by the first level signal receiving end, the signal at the first node and the signal at the second node, the first clock signal received by the first clock signal end and the second clock signal received by the second clock signal end, and control the scanning signal output by the scanning signal output end in response to the first clock signal, the second clock signal and the second level signal received by the second level signal receiving end.

[0010] The first selection module and the second selection module work together to select, process and control the scan signal output by the scan signal output module, so that the refresh frequencies of different areas of the display panel are different.

[0011] According to the first aspect, or any implementation of the first aspect above, the first selection module includes a shift unit and a start scanning unit; the shift unit is electrically connected to the first shift signal input terminal, the second shift signal input terminal, the first clock signal terminal, the first level signal receiving terminal and the shift signal output terminal; the start scanning unit is electrically connected to the trigger signal input terminal, the shift signal output terminal and the first node; the shift unit is used to receive the first shift signal received by the first shift signal input terminal, the first clock signal by the first clock signal terminal and the first level signal received by the first level signal receiving terminal, and output the shift signal through the shift signal output terminal in response to the first shift signal and the second shift signal received by the second shift signal input terminal; the start scanning unit is used to receive the trigger signal input by the trigger signal input terminal, and output the shift signal in response to the shift signal output terminal to control the signal at the first node.

[0012] The shift unit and the start scanning unit work together to complete the shift of the shift signal and the output of the effective scanning signal. Of course, the specific structure of the first selection module is not limited thereto, and those skilled in the art can set it according to actual conditions.

[0013] According to the first aspect, or any implementation of the first aspect above, the shift unit includes an input subunit and an output subunit; the input subunit is electrically connected to the first shift signal input terminal and the third node; the output subunit is electrically connected to the third node, the second shift signal input terminal, the first level signal receiving terminal, the first clock signal terminal and the shift signal output terminal; the input subunit is used to receive the first shift signal received by the first shift signal input terminal, and control the signal of the third node in response to the first shift signal; the output subunit is used to receive the first clock signal at the first clock signal terminal, and control the shift signal output terminal to output the shift signal in response to the signal of the third node; or, the output subunit is used to receive the first level signal at the first level signal receiving terminal, and control the shift signal output terminal to output the shift signal in response to the second shift signal at the second shift signal input terminal.

[0014] The input subunit and the output subunit work together to complete the shifting of the shift signal. Of course, the specific structure of the shift unit is not limited thereto, and those skilled in the art can set it according to actual conditions.

[0015] According to the first aspect, or any implementation of the first aspect above, the input subunit includes a first transistor, a gate of the first transistor and a first electrode of the first transistor are electrically connected to the first shift signal input terminal, and a second electrode of the first transistor is electrically connected to the third node.

[0016] That is, the structure of the input sub-unit is simple, which further simplifies the structure of the scan driving unit, and is beneficial to the narrow frame design of the display panel.

[0017] According to the first aspect, or any implementation of the first aspect above, the output subunit includes a second transistor, a third transistor, a fourth transistor and a first capacitor; the gate of the second transistor, the first electrode of the first capacitor, and the first electrode of the third transistor are all electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, the second electrode of the second transistor, the second electrode of the first capacitor, and the first electrode of the fourth transistor are all electrically connected to the shift signal output terminal, the gate of the third transistor and the gate of the fourth transistor are both electrically connected to the second shift signal input terminal, and the second electrode of the third transistor and the second electrode of the fourth transistor are both electrically connected to the first level signal receiving terminal.

[0018] That is, the output subunit has a simple structure, which further simplifies the structure of the scan drive unit, and is beneficial to the narrow frame design of the display panel.

[0019] According to the first aspect, or any implementation of the first aspect above, the starting scanning unit includes a fifth transistor, the gate of the fifth transistor is electrically connected to the shift signal output terminal, the first electrode of the fifth transistor is electrically connected to the trigger signal input terminal, and the second electrode of the fifth transistor is electrically connected to the first node.

[0020] That is, the structure of the initial scanning unit is simple, which further makes the structure of the scanning driving unit simple, which is beneficial to the narrow frame design of the display panel.

[0021] According to the first aspect, or any implementation of the first aspect above, the second selection module includes a cutoff scanning unit, a first level signal input unit and a second level signal input unit; the cutoff scanning unit is electrically connected to the first node, the scan signal input terminal and the fourth node; the first level signal input unit is electrically connected to the fourth node, the first level signal receiving terminal and the cutoff signal input terminal; the second level signal input unit is electrically connected to the fourth node, the second node and the second level signal receiving terminal; the second signal input unit is used to receive the second level signal received by the second level signal receiving terminal, and control the signal at the fourth node in response to the second level signal; the first signal input unit is used to receive the first level signal received by the first level signal receiving terminal, and change the signal at the fourth node in response to the cutoff signal input by the cutoff signal input terminal; the cutoff scanning unit is used to receive the first scan signal received by the scan signal input terminal, and control the signal at the first node in response to the signal at the fourth node.

[0022] The cut-off scanning unit, the first level signal input unit and the second level signal input unit work together to cut off the output of the effective scanning signal. Of course, the specific structure of the second selection module is not limited thereto, and those skilled in the art can set it according to actual conditions.

[0023] According to the first aspect, or any implementation of the first aspect above, the cut-off scanning unit includes a sixth transistor and a seventh transistor; the gate of the sixth transistor is electrically connected to the fourth node, the gate of the seventh transistor and the first electrode of the seventh transistor are both electrically connected to the scanning signal input terminal, the second electrode of the seventh transistor is electrically connected to the first electrode of the sixth transistor, and the second electrode of the sixth transistor is electrically connected to the first node.

[0024] That is, the structure of the cut-off scanning unit is simple, thereby making the structure of the scanning driving unit simple, which is beneficial to the narrow frame design of the display panel.

[0025] According to the first aspect, or any implementation of the first aspect above, the first level signal input unit includes an eighth transistor, the gate of the eighth transistor is electrically connected to the cut-off signal input terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first level signal receiving terminal.

[0026] That is, the structure of the first level signal input unit is simple, which further simplifies the structure of the scan driving unit, and is beneficial to the narrow frame design of the display panel.

[0027] According to the first aspect, or any implementation of the first aspect above, the second level signal input unit includes a ninth transistor, a gate of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the second level signal receiving end, and a second electrode of the ninth transistor is electrically connected to the fourth node.

[0028] That is, the structure of the second level signal input unit is simple, so that the structure of the scan driving unit is simple, which is beneficial to the narrow frame design of the display panel.

[0029] According to the first aspect, or any implementation of the first aspect above, the scan signal output module includes: an input unit, electrically connected to the first node, the first clock signal terminal and the fifth node; a first control unit, electrically connected to the first clock signal terminal, the second node and the sixth node; a second control unit, electrically connected to the first level signal receiving terminal, the second clock signal terminal, the fifth node and the sixth node; an output unit, electrically connected to the first level signal receiving terminal, the second level signal receiving terminal, the second clock signal terminal, the fifth node, the sixth node and the scan signal output terminal; the input unit is used to receive a signal at the first node, and control the signal of the fifth node in response to the first clock signal received at the first clock signal terminal; the first control unit is used to receive the first The clock signal end receives the first clock signal and the signal at the second node, and controls the signal of the sixth node in response to the signal at the fifth node and the first clock signal received by the first clock signal end; the second control unit is used to receive the first level signal received by the first level signal receiving end, and change the signal of the fifth node in response to the signal at the sixth node and the second clock signal received by the second clock signal end; the output unit is used to receive the first level signal received by the first level signal receiving end, and control the scan signal output by the scan signal output end in response to the signal of the sixth node; or, the output module is used to receive the second clock signal received by the second clock signal end, and control the scan signal output by the scan signal output end in response to the signal of the fifth node.

[0030] The scanning signal output module provided in the embodiment of the present application has fewer signal terminals, and accordingly, fewer signal lines providing signals to the signal terminals, and a simple structure, thereby making the structure of the scanning driving unit simple, which is beneficial to the narrow frame design of the display panel and low cost.

[0031] According to the first aspect, or any implementation of the first aspect above, the input unit includes a tenth transistor; the gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the fifth node.

[0032] The control of the fifth node signal can be realized by one transistor, the structure of the input unit is simple, and thus the structure of the scan driving unit is simple.

[0033] According to the first aspect, or any implementation of the first aspect above, the first control unit includes an eleventh transistor and a twelfth transistor; the gate of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor and the second electrode of the twelfth transistor are both electrically connected to the sixth node; the gate of the twelfth transistor is electrically connected to the fifth node, and the first electrode of the twelfth transistor is electrically connected to the first clock signal terminal.

[0034] The control of the sixth node signal can be achieved through two transistors, the structure of the first control unit is simple, and thus the structure of the scan driving unit is simple.

[0035] According to the first aspect, or any implementation of the first aspect above, the second control unit includes a thirteenth transistor and a fourteenth transistor; the gate of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor; the gate of the fourteenth transistor is electrically connected to the sixth node, and the second electrode of the fourteenth transistor is electrically connected to the first level signal receiving terminal.

[0036] The second control unit has a simple structure, thereby making the structure of the scan driving unit simple.

[0037] According to the first aspect, or any implementation of the first aspect above, the output unit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a second capacitor and a third capacitor; the gate of the fifteenth transistor is electrically connected to the second level signal receiving end, the first electrode of the fifteenth transistor is electrically connected to the fifth node, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the second capacitor and the gate of the sixteenth transistor respectively; the second electrode of the second capacitor, the second electrode of the sixteenth transistor, and the first electrode of the seventeenth transistor are all electrically connected to the scan signal output end; the first electrode of the sixteenth transistor is electrically connected to the second clock signal end; the gate of the seventeenth transistor and the first electrode of the third capacitor are both electrically connected to the sixth node, and the second electrode of the seventeenth transistor and the second electrode of the third capacitor are both electrically connected to the first level signal receiving end.

[0038] The output unit has a simple structure, which further simplifies the structure of the scan driving unit. Moreover, the arrangement of the capacitor makes the gate signals of the fifteenth transistor and the sixteenth transistor more stable.

[0039] According to the first aspect, or any implementation of the first aspect above, the scan drive circuit also includes a first clock signal line and a second clock signal line; the first clock signal end of the odd-numbered scan drive unit is electrically connected to the first clock signal line, and the second clock signal end of the odd-numbered scan drive unit is electrically connected to the second clock signal line; the first clock signal end of the even-numbered scan drive unit is electrically connected to the second clock signal line, and the second clock signal end of the even-numbered scan drive unit is electrically connected to the first clock signal line.

[0040] There is no need to set a separate first clock signal line and a second clock signal line for each scan driving unit, so the number of clock signal lines is reduced and the structure is simple.

[0041] In a second aspect, an embodiment of the present application provides a display panel, comprising a scanning drive circuit of the first aspect and any one of the implementation methods of the first aspect, a plurality of pixels arranged in an array, and a plurality of scanning line groups; the scanning line group comprises at least one scanning signal line; the scanning signal lines of the plurality of scanning line groups are electrically connected to scanning signal output modules of the plurality of scanning drive units, respectively; different pixel rows correspond to different scanning line groups, and each pixel in the same row is electrically connected to the scanning signal line of the same scanning line group; the scanning signal output by the scanning signal output module is provided to the pixel through the scanning signal line.

[0042] The second aspect corresponds to the first aspect and any implementation of the first aspect. The technical effects corresponding to the second aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0043] According to the second aspect, there are two scanning drive circuits, and the two scanning drive circuits include a first scanning drive circuit and a second scanning drive circuit; each row of pixels includes a first pixel group and a second pixel group, and the first pixel group and the second pixel group each include a plurality of pixels; the scanning signal line includes a first scanning signal sub-segment and a second scanning signal sub-segment; each pixel of the first pixel group is electrically connected to the same first scanning signal sub-segment, and each pixel of the second pixel group is electrically connected to the same second scanning signal sub-segment; the scanning signal output by the scanning signal output module of the plurality of scanning drive units in the first scanning drive circuit is provided to each pixel of the first pixel group through the first scanning signal sub-segment, and the scanning signal output by the scanning signal output module of the plurality of scanning drive units in the second scanning drive circuit is provided to each pixel of the second pixel group through the second scanning signal sub-segment.

[0044] The first scan driving circuit can control different areas of the left part of the display area of ​​the display panel to achieve different refresh frequencies, and the second scan driving circuit can control different areas of the right part of the display area of ​​the display panel to achieve different refresh frequencies.

[0045] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising the display panel of the second aspect and any one of the implementations of the second aspect, and the third aspect corresponds to the second aspect and any one of the implementations of the second aspect. The technical effects corresponding to the third aspect can refer to the technical effects corresponding to the second aspect and any one of the implementations of the second aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 One of the application scenarios of an electronic device provided in an embodiment of the present application;

[0047] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0050] Figure 5 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0051] Figure 6 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0052] Figure 7 A schematic diagram of the structure of a scan drive unit provided in an embodiment of the present application;

[0053] Figure 8 A timing diagram of various signals of the scan driving unit provided in an embodiment of the present application starting from the Nth row for scanning;

[0054] Fig. 9 The specific signals of the scanning driving unit ASG at various positions in the first stage provided by the embodiment of the present application;

[0055] Fig.10 The specific signals of the scanning driving unit ASG at each position in the second stage provided in the embodiment of the present application;

[0056] Fig.11 The specific signals at various positions of the scan driving unit ASG provided in the embodiment of the present application in the third stage;

[0057] Fig.12 The specific signals at various positions of the scan driving unit ASG provided in the embodiment of the present application in the Nth stage;

[0058] Fig.13 The specific signals at various positions of the scan driving unit ASG provided in the embodiment of the present application at the (N+1)th stage;

[0059] Fig.14 A timing diagram of various signals of the scan driving unit provided in an embodiment of the present application when the scan ends the scan from the Mth row;

[0060] Fig.15 Specific signals of the (M-1)th level scanning driving unit ASG(M-1) and the Mth level scanning driving unit ASGM at various positions in the (M-1)th stage provided in the embodiment of the present application;

[0061] Fig.16Specific signals of the M-th level scanning driving unit ASGM at each position in the M-th stage provided in the embodiment of the present application;

[0062] Fig.17 A timing diagram of various signals in the scan drive circuit provided in an embodiment of the present application;

[0063] Fig.18 A refreshing process of a display screen provided in an embodiment of the present application;

[0064] Fig.19 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0065] Fig. 20 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0066] Fig.21 This is one of the application scenarios of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0068] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0069] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0070] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0071] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0072] Figure 1 FIG. 1 is a schematic diagram of an exemplary application scenario. Figure 1 As shown, the electronic device 100 displays various contents through the display panel. Figure 1 In the embodiment, the display area of ​​the display panel display content is divided into three areas: a status bar 101, a video playback area 102, and a static content display area 103. The status bar 101 is used to display status information, such as the remaining battery power, time, etc.; the video playback area 102 is used to display dynamic content, such as playing videos, etc.; and the static content display area 103 is used to display static content, such as text, pictures, etc.

[0073] In similar Figure 1 In the illustrated scenario, if the display content of all regions is refreshed at the same refresh rate, the power consumption of the display panel will be relatively high, but the display quality will not be significantly improved.

[0074] Based on this, the embodiments of the present application propose a scan driving circuit, a display panel using the scan driving circuit, and an electronic device using the display panel, wherein the electronic device can be a mobile phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a car computer, a smart wearable device, a smart home device, and other smart terminals including a display panel. The embodiments of the present application do not limit the specific form of the above-mentioned electronic devices.

[0075] By refreshing the displayed content at a relatively low refresh rate for areas where the displayed content remains unchanged or where static content such as text and pictures is displayed, the displayed content is refreshed at a relatively high refresh rate for areas where the displayed content changes in real time or where dynamic content such as videos is displayed. In other words, different refresh rates are selected to refresh the displayed content according to the different displayed content in different areas. In this way, the refresh rate of areas such as areas where the displayed content remains unchanged or where static content such as text and pictures is displayed is relatively low. Since the displayed content in these areas remains unchanged or static content such as text and pictures is displayed, although the refresh rate is reduced, the display quality is not significantly affected, so that the display panel reduces power consumption while maintaining the display quality, thereby improving the battery life of the electronic device.

[0076] The following describes the various structures in the display panel provided by the embodiment of the present application and the principle that different regions can achieve different refresh rates in conjunction with the electronic device, wherein see Figure 2, taking the electronic device being a mobile phone as an example for explanation.

[0077] like Figure 2 As shown, the mobile phone 100 includes a display panel 10, a rear shell 20 and a middle frame 30. The display panel 10, the rear shell 20 and the middle frame 30 can enclose a housing cavity. Structures such as a printed circuit board, a battery and functional devices (not shown in the figure) are arranged in the housing cavity. Functional devices include, for example, a display driver chip and a processor, etc. The display driver chip and the processor are arranged on a printed circuit board, and the electrical connection between the display driver chip and the processor is realized through the printed circuit board. The processor sends a corresponding signal to the display driver chip so that the display driver chip drives the display panel 10 to display.

[0078] The material of the rear cover 20 may include, for example, opaque materials such as plastic, plain leather, and glass fiber; or may include translucent materials such as glass. The material of the rear cover 20 is not limited in the embodiment of the present application.

[0079] The display panel 10 includes, for example, a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, and an LED display panel, among which the LED display panel includes, for example, a Micro-LED display panel, a Mini-LED display panel, etc. The embodiment of the present application does not limit the type of the display panel 10. The following description takes the display panel 10 as an OLED display panel as an example.

[0080] See also Figure 3 , Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 3 As shown, the display panel 10 includes a display area AA and a non-display area NAA, and the non-display area NAA is located on at least one side of the display area AA, wherein: Figure 3 The description is made by taking the non-display area NAA surrounding the display area AA as an example. A plurality of pixels 11 arranged in an array, a plurality of scan line groups 12 and a plurality of data lines 13 are provided in the display area AA of the display panel 10. Each pixel 11 includes a pixel circuit 111 and a display unit (also referred to as a light-emitting element, etc.) 112. The plurality of data lines 13 correspond one-to-one to the pixel circuits 111 in the plurality of columns of pixels 11, that is, the pixel circuit 111 in one column of pixels 11 corresponds to one data line 13. The plurality of scan line groups 12 correspond one-to-one to the pixel circuits 111 in the plurality of rows of pixels 11, that is, the pixel circuit 111 in one row of pixels 11 corresponds to one scan line group 12.

[0081] Combination Figure 4 , Figure 4It is a structural diagram of a pixel circuit. The pixel circuit 111, for example, includes 7T1C (7 transistors and 1 storage capacitor), that is, the pixel circuit 111 may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light emitting control transistors M6 and M7, and a storage capacitor Cst.

[0082] It can be understood that the specific structure of the pixel circuit 111 includes but is not limited to the above examples. In other optional embodiments, the pixel circuit 111 can also be arranged in other ways (i.e., including a larger number of transistors or a smaller number of transistors, and including a larger number of storage capacitors or a smaller number of storage capacitors), as long as the display unit 112 can be driven to emit light.

[0083] The driving transistor M1, the data writing transistor M2, the threshold compensation transistor M3, the reset transistors M4 and M5, and the light emission control transistors M6 and M7 are all transistors with silicon material as an active layer. The silicon material may include polysilicon material, etc. The polysilicon material may include low temperature polysilicon (LTPS) material. The transistor is, for example, a P-type transistor.

[0084] Of course, this is not enough to limit the present application. In other optional embodiments of the present application, the reset transistor M4 and the threshold compensation transistor M3 may be transistors with oxide semiconductor materials as active layers. Among them, the oxide semiconductor material may include indium gallium zinc oxide (IGZO) material, and the transistor is, for example, an N-type transistor. The driving transistor M1, the data writing transistor M2, the reset transistor M5, the light emitting control transistors M6 and M7 are transistors with silicon materials as active layers, and the transistors are, for example, P-type transistors. In other words, the LTPS transistor and the IGZO transistor are integrated on a substrate to form a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display panel 10.

[0085] The embodiments of the present application are all described by taking the driving transistor M1, the data writing transistor M2, the threshold compensation transistor M3, the reset transistors M4 and M5, and the light emitting control transistors M6 and M7 as transistors with LTPS materials as active layers, and the transistors are, for example, P-type transistors.

[0086] Continue to see Figure 4The pixel circuit 111 further includes an initialization signal terminal Vref, a first power terminal PVDD, a second power terminal PVEE, a data signal terminal Data, a first scan signal terminal Scan1, a second scan signal terminal Scan2, a third scan signal terminal Scan3 and a light emitting control signal terminal Emit. The first electrode of the light emitting control transistor M6 is electrically connected to the first power terminal PVDD, the first electrode of the data writing transistor M2 is electrically connected to the data signal terminal Data, the gate of the data writing transistor M2 and the gate of the threshold compensation transistor M3 are both electrically connected to the second scan signal terminal Scan2, the first electrodes of the reset transistors M4 and M5 are respectively electrically connected to the initialization signal terminal Vref (the initialization signal terminals corresponding to the two may be the same or different), the gate of the reset transistor M4 may be electrically connected to the first scan signal terminal Scan1, the gate of the reset transistor M5 may be electrically connected to the third scan signal terminal Scan3, the gates of the light emitting control transistors M6 and M7 may be respectively electrically connected to the light emitting control signal terminal Emit, the light emitting control transistor M7 is electrically connected to the anode of the display unit 112, and the cathode of the display unit 112 is electrically connected to the second power terminal PVEE.

[0087] Continue to see Figure 3 Each scanning line group 12 includes a scanning signal line 121 and a light emitting control signal line 122 .

[0088] The pixel circuits 111 in a column of pixels 11 described above correspond to a data line 13, that is, the data signal terminal Data in the pixel circuits 111 of each pixel 11 in the same column is electrically connected to the same data line 13. The pixel circuits 111 in a row of pixels 11 correspond to a scan line group 12, that is, the second scan signal terminal Scan2 in the pixel circuits 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to the row, the light emission control signal terminal Emit in the pixel circuits 111 of each pixel 11 in the same row is electrically connected to the light emission control signal line 122 corresponding to the row, and the first scan signal terminal Scan1 in the pixel circuits 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to other rows (such as the previous row), and the third scan signal terminal Scan3 in the pixel circuits 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to other rows (such as the next row).

[0089] It should be noted that in order to ensure the simplicity and clarity of the circuit, Figure 3 It is not shown that the first scan signal terminal Scan1 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to other rows, and the third scan signal terminal Scan3 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to other rows.

[0090] That is to say, the scanning signal transmitted by the scanning signal line 121 can control the opening or closing of the data writing transistor M2 and the threshold compensation transistor M3, that is, the scanning signal transmitted by the scanning signal line 121 corresponding to the row where the data writing transistor M2 and the threshold compensation transistor M3 are located can control the opening or closing of the data writing transistor M2 and the threshold compensation transistor M3; the scanning signal transmitted by the scanning signal line 121 corresponding to other rows (such as the previous row) controls the opening or closing of the reset transistor M4, and the scanning signal transmitted by the scanning signal line 121 corresponding to other rows (such as the next row) controls the opening or closing of the reset transistor M5; the light-emitting control signal transmitted by the light-emitting control signal line 122 can control the opening or closing of the light-emitting control transistors M6 and M7 on the light-emitting branch.

[0091] When the scanning signal line 121 provides a scanning signal to the pixel 11 of the corresponding row, the pixel 11 that needs to be refreshed can be selected. The data line 13 provides a data signal to the pixel circuit 111 of the corresponding column, and refreshes the data signal for the pixel 11 selected by the scanning signal. The light-emitting control signal line provides a light-emitting control signal to the pixel 11 of the corresponding row to control the light-emitting time of the pixel 11. The pixel circuit 111 generates a driving current to drive the display unit 112 to emit light under the action of the scanning signal, the light-emitting control signal and the data signal. The specific principle of the pixel circuit 111 generating a driving current to drive the display unit 112 to emit light based on the data signal, the light-emitting control signal and the scanning signal is similar to the principle of the 7T1C pixel circuit in the prior art generating a driving current to drive the display unit to emit light, which will not be repeated here.

[0092] The above-mentioned refreshing of different areas of the display panel is to refresh the pixels 11 in different areas of the display panel, that is, to provide a new data signal to the pixel circuit 111 of the pixel 11 in the area, so that the data signal in the pixel circuit 111 is updated (that is, the potential of the gate of the driving transistor M1 is refreshed), so that the driving current of the driving transistor M1 is refreshed. When the pixel 11 is not refreshed, the data signal in the pixel circuit 111 of the pixel 11 remains the data signal of the previous frame, and the driving current remains the driving current of the previous frame when emitting light. When the pixel 11 is not refreshed, the corresponding transistor remains turned off, no current flows, and thus power consumption is reduced.

[0093] Continue to see Figure 3A driving circuit 14 is provided in the non-display area NAA of the display panel 10, wherein the driving circuit 14 may include, for example, a scanning driving circuit and a light-emitting control driving circuit. The scanning driving circuit includes a plurality of scanning signal output terminals, and the light-emitting control driving circuit includes a plurality of light-emitting control signal output terminals. The plurality of scanning signal output terminals of the scanning driving circuit are electrically connected to the plurality of scanning signal lines 121 of the display area AA in a one-to-one correspondence, and the plurality of light-emitting control signal output terminals of the light-emitting control driving circuit are electrically connected to the light-emitting control signal lines 122 of the display area AA in a one-to-one correspondence. The scanning driving circuit transmits the above-mentioned scanning signal to the scanning signal line 121 through the scanning signal output terminal, and the light-emitting control driving circuit transmits the above-mentioned light-emitting control signal to the light-emitting control signal line 122 through the light-emitting control signal output terminal.

[0094] It should be noted that the driving circuit 14 can be arranged on one side of the display area AA, such as Figure 3 The driving circuit 14 can also be arranged on two opposite sides of the display area AA, that is, the driving circuit 14 is arranged on both opposite sides of the display area AA. Figure 5 As shown. That is to say, the scan drive circuit can be arranged on one side of the display area AA, or on two opposite sides of the display area AA; the light-emitting control drive circuit can be arranged on one side of the display area AA, or on two opposite sides of the display area AA. Exemplarily, when the scan drive circuit in the drive circuit 14 is arranged on two opposite sides of the display area AA (i.e., the scan drive circuit is arranged on both opposite sides of the display area AA), the scan signal output ends of the two scan drive circuits are electrically connected to a scan signal line 121, so as to provide a scan signal to the scan signal line 121. In this way, the voltage drop of the scan signal can be reduced. When the light-emitting control drive circuit in the drive circuit 14 is arranged on two opposite sides of the display area AA (i.e., the light-emitting control drive circuit is arranged on both opposite sides of the display area AA), the light-emitting control signal output ends of the two light-emitting control drive circuits are electrically connected to a light-emitting control signal line 122, so as to provide a light-emitting control signal to the light-emitting control signal line 122. In this way, the voltage drop of the light-emitting control signal can be reduced.

[0095] See also Figure 6 , Figure 6 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Figure 6 As shown, the scanning driving circuit 14a (a driving circuit that provides a scanning signal to the pixel 11) includes n cascaded scanning driving units ASG, for example, it may include n scanning driving units ASG1~ASGn, n≥2, and the specific value of n can be set by technicians in this field according to actual conditions and is not limited here.

[0096] Each level of the scan driving unit ASG includes a first clock signal terminal SCK1, a second clock signal terminal SCK2, a trigger signal input terminal STV, a cut-off signal input terminal Close, a first level signal receiving terminal VGH, a second level signal receiving terminal VGL, a first shift signal input terminal Scan input, a second shift signal input terminal Scan reset, a shift signal output terminal Scanout, a scan signal input terminal GIN, and a scan signal output terminal GOUT.

[0097] Except for the last level scan driving unit ASGn, the scan signal output terminal GOUT of each level scan driving unit ASG is electrically connected to the scan signal input terminal GIN of the adjacent next level scan driving unit ASG. The scan signal input terminal GIN of the first level scan driving unit ASG1 is electrically connected to a scan signal input line (not shown in the figure), and the scan signal input line is used to transmit the scan signal sent by the display driver chip to the scan signal input terminal GIN of the first level scan driving unit ASG1.

[0098] Except for the first-stage scan driving unit ASG1 and the last-stage scan driving unit ASGn, the shift signal output terminal Scan out of each stage of the remaining scan driving units ASG is electrically connected to the first shift signal input terminal Scan input of the adjacent next-stage scan driving unit ASG and is electrically connected to the second shift signal input terminal Scan reset of the adjacent previous-stage scan driving unit ASG. The shift signal output terminal Scan out of the first-stage scan driving unit ASG1 is only electrically connected to the first shift signal input terminal Scan input of the second-stage scan driving unit ASG2, and the shift signal output terminal Scan out of the last-stage scan driving unit ASGn is only electrically connected to the second shift signal input terminal Scan reset of the (n-1)th-stage scan driving unit ASG2. And the first shift signal input terminal Scan input of the first-stage scan driving unit ASG1 is electrically connected to a shift signal line (not shown in the figure), and the shift signal line is used to transmit the shift signal sent by the display driver chip to the first shift signal input terminal Scan input of the first-stage scan driving unit ASG1. In order to reduce the number of signal lines, the scan driving circuit 14a further includes at least one dummy scan driving unit ASG dummy, wherein: Figure 6The description is made by taking the scan driving circuit 14a as an example in which it also includes a virtual scan driving unit ASG dummy. The virtual scan driving unit ASG dummy is cascaded with n cascaded scan driving units ASG, and the second shift signal input terminal Scan reset of the last-stage scan driving unit ASGn is electrically connected to the shift signal output terminal Scan out of the virtual scan driving unit ASG dummy, so as to provide a shift signal for the second shift signal input terminal Scan reset of the last-stage scan driving unit ASGn through the shift signal output terminal Scan out of the virtual scan driving unit ASG dummy. The second shift signal input terminal Scan reset of the virtual scan driving unit ASG dummy is also electrically connected to the scan signal input line, and the scan signal input line is used to transmit the scan signal sent by the display driver chip to the scan signal input terminal GIN of the first-stage scan driving unit ASG1 and the second shift signal input terminal Scan reset of the virtual scan driving unit ASG dummy.

[0099] The dummy scan driving unit ASG dummy is a scan driving unit ASG whose specific circuit structure is the same as that of other scan driving units ASG, but does not provide a scan signal to the pixels 11 of the display area AA.

[0100] The scan driving unit ASG outputs a shift signal through the shift signal output terminal Scan out and provides a scan signal to the scan signal line 121 through the scan signal output terminal GOUT according to the first clock signal input by the first clock signal terminal SCK1, the second clock signal input by the second clock signal terminal SCK2, the trigger signal input by the trigger signal input terminal STV, the cut-off signal input by the cut-off signal input terminal Close, the first level signal input by the first level signal receiving terminal VGH, the second level signal input by the second level signal receiving terminal VGL, the scan signal (also called the first scan signal) output by the previous level scan driving unit ASG input by the scan signal input terminal GIN through the scan signal output terminal GOUT, the shift signal (also called the first shift signal) output by the previous level scan driving unit ASG input by the first shift signal input terminal Scan input through the shift signal output terminal Scan out, and the shift signal (also called the second shift signal) output by the next level scan driving unit ASG input by the second shift signal input terminal Scan reset through the shift signal output terminal Scan out.

[0101] The scanning driving circuit 14a further includes a first clock signal line SCKL1, a second clock signal line SCKL2, a first level signal line VGHL, a second level signal line VGLL, a trigger signal line STVL and a cut-off signal line CloseL located in the non-display area NAA, and the clock signal output by the first clock signal line SCKL1 and the clock signal output by the second clock signal line SCKL2 are two clock signals opposite to each other. The first level signal receiving end VGH of each scanning driving unit ASG in the scanning driving circuit 14a is electrically connected to the same first level signal line VGHL, and the second level signal receiving end VGL of each scanning driving unit ASG in the scanning driving circuit 14a is electrically connected to the same second level signal line VGLL. The first clock signal terminal SCK1 of the odd-numbered scan driving unit ASG is electrically connected to the first clock signal line SCKL1, and the second clock signal terminal SCK2 of the odd-numbered scan driving unit ASG is electrically connected to the second clock signal line SCKL2; the first clock signal terminal SCK1 of the even-numbered scan driving unit ASG is electrically connected to the second clock signal line SCKL2, and the second clock signal terminal SCK2 of the even-numbered scan driving unit ASG is electrically connected to the first clock signal line SCKL1. The trigger signal input terminal STV of each scan driving unit ASG in the scan driving circuit 14a is electrically connected to the same trigger signal line STVL, and the cut-off signal input terminal Close of the scan driving unit ASG is electrically connected to the cut-off signal line CloseL. The first clock signal line SCKL1, the second clock signal line SCKL2, the first level signal line VGHL, the second level signal line VGLL, the trigger signal line STVL and the cut-off signal line CloseL are used to receive the first clock signal, the second clock signal, the first level signal, the second level signal, the trigger signal and the cut-off signal provided by the display driver chip, and respectively transmit the first clock signal, the second clock signal, the first level signal, the second level signal, the trigger signal and the cut-off signal to the signal ends correspondingly connected thereto.

[0102] Combination Figure 7 , Figure 7 The schematic diagram of the structure of a scan driving unit provided in the embodiment of the present application is as follows: The scan driving unit ASG of the scan driving circuit 14 a further includes: a first selection module 141 , a second selection module 142 and a scan signal output module 143 .

[0103] The first selection module 141 includes a shift unit 1411 and a start scanning unit 1412 .

[0104] The shift unit 1411 includes an input subunit 14111 and an output subunit 14112. The input subunit 14111 may include a first transistor T1, a gate of the first transistor T1 and a first electrode of the first transistor T1 are both electrically connected to the first shift signal input terminal Scan input, and a second electrode of the first transistor T1 is electrically connected to a third node N3. The output subunit 14112 may include a second transistor T2, a third transistor T3, a fourth transistor T4 and a first capacitor C1, a gate of the second transistor T2, a first electrode of the first capacitor C1, and a first electrode of the third transistor T3 are both electrically connected to the third node N3, a first electrode of the second transistor T2 is electrically connected to the first clock signal terminal SCK1, a second electrode of the second transistor T2, a second electrode of the first capacitor C1, and a first electrode of the fourth transistor T4 are both electrically connected to the shift signal output terminal Scan out, a gate of the third transistor T3 and a gate of the fourth transistor T4 are both electrically connected to the second shift signal input terminal Scan reset, and a second electrode of the third transistor T3 and a second electrode of the fourth transistor T4 are both electrically connected to the first level signal receiving terminal VGH.

[0105] The start scanning unit 1412 may include a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected to the shift signal output terminal Scan out, a first electrode of the fifth transistor T5 is electrically connected to the trigger signal input terminal STV, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1.

[0106] The second selection module 142 may include an off-scan unit 1421 , a first level signal input unit 1422 , and a second level signal input unit 1423 .

[0107] The cut-off scanning unit 1421 may include a sixth transistor T6 and a seventh transistor T7, the gate of the sixth transistor T6 is electrically connected to the fourth node, the gate of the seventh transistor T7 and the first electrode of the seventh transistor T7 are both electrically connected to the scanning signal input terminal GIN, the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the sixth transistor T6, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0108] The first level signal input unit 1422 includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the cut-off signal input terminal Close, a first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and a second electrode of the eighth transistor T8 is electrically connected to the first level signal receiving terminal VGH.

[0109] The second level signal input unit 1423 includes a ninth transistor T9, a gate of the ninth transistor T9 is electrically connected to the second node N2, a first electrode of the ninth transistor T9 is electrically connected to the second level signal receiving terminal VGL, and a second electrode of the ninth transistor T9 is electrically connected to the fourth node N4. The second node N2 is connected to the second level signal receiving terminal VGL, that is, the signal at the second node N2 is the second level signal received by the second level signal receiving terminal VGL.

[0110] The scan signal output module 143 may include an input unit 1431 , a first control unit 1432 , a second control unit 1433 , and an output unit 1434 .

[0111] The input unit 1431 may include a tenth transistor T10 , a gate of the tenth transistor T10 is electrically connected to the first clock signal terminal SCK1 , a first electrode of the tenth transistor T10 is electrically connected to the first node N1 , and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5 .

[0112] The first control unit 1432 may include an eleventh transistor T11 and a twelfth transistor T12, the gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal SCK1, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode of the eleventh transistor T11 and the second electrode of the twelfth transistor T12 are both electrically connected to the sixth node N6, the gate of the twelfth transistor T12 is electrically connected to the fifth node N5, and the first electrode of the twelfth transistor T12 is electrically connected to the first clock signal terminal SCK1.

[0113] The second control unit 1433 may include a thirteenth transistor T13 and a fourteenth transistor T14, the gate of the thirteenth transistor T13 is electrically connected to the second clock signal terminal SCK2, the first electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5, the second electrode of the thirteenth transistor T13 is electrically connected to the first electrode of the fourteenth transistor T14, the gate of the fourteenth transistor T14 is electrically connected to the sixth node N6, and the second electrode of the fourteenth transistor T14 is electrically connected to the first level signal receiving terminal VGH.

[0114] The output unit 1434 may include a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a second capacitor C2 and a third capacitor C3, the gate of the fifteenth transistor T15 is electrically connected to the second level signal receiving terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the fifth node N5, the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the second capacitor C1 and the gate of the sixteenth transistor T16, respectively, the second electrode of the second capacitor C2, the second electrode of the sixteenth transistor T16, and the first electrode of the seventeenth transistor T17 are all electrically connected to the scan signal output terminal GOUT, the first electrode of the sixteenth transistor T16 is electrically connected to the second clock signal terminal SCK2, the gate of the seventeenth transistor T17 and the first electrode of the third capacitor C3 are both electrically connected to the sixth node N6, and the second electrode of the seventeenth transistor T17 and the second electrode of the third capacitor C3 are electrically connected to the first level signal receiving terminal VGH.

[0115] The structure of the scan driving unit ASG of the scan driving circuit 14 is specifically introduced above. It should be noted that the structures of the first selection module 141, the second selection module 142 and the scan signal output module 143 are not limited to the above examples. Those skilled in the art can set the specific structures of the first selection module 141, the second selection module 142 and the scan signal output module 143 according to actual conditions. As long as the scan signal output module of the Nth level scan driving unit is controlled by the first selection module 141 to start outputting the scan signal, and the scan signal output module of the Mth level scan driving unit is controlled by the second selection module to stop outputting the scan signal, the control of the refresh frequency of different areas of the display panel is achieved within the protection scope of the present application.

[0116] The following is an introduction to the working process of the scan driving unit ASG of the scan driving circuit 14a to realize partial scanning. The description is made by taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 as P-type transistors, and the first level signal received by the first level signal receiving terminal VGH is a high level signal, and the second level signal received by the second level signal receiving terminal VGL is a low level signal as an example.

[0117] First, a specific description will be given of a process in which the scanning driving circuit 14a starts scanning from the Nth row.

[0118] Figure 8The timing diagram of each signal of the scanning driving unit starting from the Nth row is shown. Figure 7 The working process of the scan driving unit 14a of the scan driving circuit 14 shown in FIG.

[0119] In the first stage T1, i.e. the low level shift signal input stage: see Fig. 9 , Fig. 9 Specific signals at various positions of the scan drive unit ASG in the first stage, wherein the thick solid line represents the first level signal, i.e., a high level signal; and the thick dotted line represents the second level signal, i.e., a low level signal. The shift signal transmitted by the shift signal line received by the first shift signal input terminal Scan input of the first-stage scan drive unit ASG1 (the shift signal sent to the shift signal line by the display driver chip side) changes from a high level to a low level, the first transistor T1 is turned on, and the low level shift signal received by the first shift signal input terminal Scan input is written to the third node N3, the third node N3 is pulled down, the first capacitor C1 is charged, and the second transistor T2 is turned on. Since the first clock signal received by the second transistor T2 is a high level signal at this time, the shift signal output terminal Scan out outputs a high level signal. At this time, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off. Since the sixth transistor T6 is normally open, the low level signal is written to the fourth node N4, the sixth transistor T6 is in a conducting state, and the high level signal of the scan signal input terminal GIN makes the signal at the N1 node a high level signal.

[0120] In the second stage T2, i.e. the low level shift signal output stage: see Fig.10 , Fig.10 Specific signals at various positions of the scan driving unit ASG in the second stage, wherein the thick solid line represents the first level signal, i.e., the high level signal; the thick dotted line represents the second level signal, i.e., the low level signal. Due to the existence of the first capacitor C1, the second transistor T2 is still turned on, so when the first clock signal received by the second transistor T2 changes from a high level signal to a low level signal, the shift signal output terminal Scan out outputs a low level signal.

[0121] It can be understood that the low-level signal output by the shift signal output terminal Scan out can be written to the first shift signal input terminal Scan input of the next-level scan driving unit ASG, so that the next-level scan driving unit ASG starts the steps of the first stage T1 until the first clock signal received by the second transistor T2 of the next-level scan driving unit ASG is a low-level signal, and the shift signal output terminal Scan out of the next-level scan driving unit ASG outputs a low-level signal. It can be understood here that at this time, the first clock signal terminal SCK1 of the scan driving unit ASG of this level is a low-level signal, and the first clock signal terminal SCK1 of the scan driving unit ASG of the next row is a high-level signal. In this way, the scan driving circuit 14a starts to output low-level signals in sequence from the shift signal output terminal Scan out of the first-level scan driving unit ASG1 to achieve shifting. When shifting to the N-th scan driving unit ASGN, the shift signal output terminal Scan out of the N-th scan driving unit ASGN outputs a low-level signal.

[0122] In the third stage T3, i.e. the low level shift signal cut-off stage: see Fig.11 , Fig.11 Specific signals at various positions of the scan driving unit ASG in the third stage, wherein the thick solid line represents the first level signal, i.e., the high level signal; the thick dotted line represents the second level signal, i.e., the low level signal. When the shift signal output terminal Scan out of the next level scan driving unit ASG outputs a low level signal, the second shift signal input terminal Scan reset of the current level scan driving unit ASG receives the low level shift signal, the third transistor T3 and the fourth transistor T4 are turned on, the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 receive the high level signal at the first level signal receiving terminal VGH, and the signal output by the shift signal output terminal Scanout changes from a low level signal to a high level signal, and remains a high level signal.

[0123] That is to say, the above process is followed to shift in sequence. However, during the shifting process, the scan signal output terminal GOUT of the shifted scan driving unit ASG outputs a high-level signal. Accordingly, the P-type transistors (data writing transistors M2 and threshold compensation transistors M3) in the pixel circuit 111 of the corresponding pixel row (the row corresponding to the scan signal line 121 electrically connected to the scan driving unit ASG of this level) cannot be driven to turn on (i.e., work), that is, the pixel row corresponding to the shifted scan driving unit ASG is not refreshed, such as the first pixel row corresponding to the first-level scan driving unit ASG1 to the (N-1)th pixel row corresponding to the (N-1)th level scan driving unit ASG(N-1) are not refreshed.

[0124] In order to realize the refresh of the N-th pixel row corresponding to the N-th scanning driving unit ASGN, when shifting to the N-th scanning driving unit ASGN, the signal transmitted by the trigger signal line STVL electrically connected to the trigger signal input terminal STV of each scanning driving unit ASG changes from a high level to a low level. Based on the low level signal input by the trigger signal input terminal STV, the scanning signal output terminal GOUT of the N-th scanning driving unit ASGN outputs a low level signal to drive the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the N-th pixel row to turn on (i.e., work), that is, the N-th pixel row is refreshed.

[0125] Specifically, in the Nth stage TN, that is, the trigger signal low level input stage: see Fig.12 , Fig.12 Specific signals at various positions of the scan driving unit ASG in the Nth stage, wherein the thick solid line represents the first level signal, i.e., the high level signal; the thick dotted line represents the second level signal, i.e., the low level signal. As can be seen from the foregoing, when shifting to the Nth level scan driving unit ASGN, the shift signal output terminal Scan out of the Nth level scan driving unit ASGN outputs a low level signal. The low level signal at the shift signal output terminal Scan out turns on the fifth transistor T5. Since the signal input by the trigger signal input terminal STV is a low level signal at this time, the low level signal input by the trigger signal input terminal STV is written to the first node N1, and the signal at the first node N1 is pulled low. Since the first clock signal received by the first clock signal terminal SCK1 changes from a high level to a low level, and the second clock signal received by the second clock signal terminal SCK2 changes from a low level to a high level, the tenth transistor T10 and the eleventh transistor T11 are turned on, and the low level signal input by the trigger signal input terminal STV is written to the fifth node N5, the signal at the fifth node N5 is pulled low, the twelfth transistor T12 is turned on, and the sixth node N6 is at a low level. The thirteenth transistor T13 is turned off, and the high level cannot be written to the sixth node N6 through the thirteenth transistor T13. The low level signal at the fifth node N5 turns on the sixteenth transistor T16, and the low level at the sixth node N6 turns on the seventeenth transistor T17, and the scan signal output by the scan signal output terminal GOUT is at a high level at this time.

[0126] In the (N+1)th stage T(N+1), that is, the stage where the scanning signal output terminal outputs a low level: see Fig.13 , Fig.13Specific signals at various positions of the scan driving unit ASG in the (N+1)th stage, wherein the thick solid line represents a first level signal, i.e., a high level signal; and the thick dotted line represents a second level signal, i.e., a low level signal. The first clock signal received by the first clock signal terminal SCK1 changes from a low level to a high level, and the second clock signal received by the second clock signal terminal SCK2 changes from a high level to a low level. The tenth transistor T10 and the eleventh transistor T11 are turned off, the fifth node N5 maintains a low level, the twelfth transistor T12 continues to be turned on, and the high level of the first clock signal is written to the sixth node N6. The low level of the fifth node N5 turns on the sixteenth transistor T16, and the high level of the sixth node N6 turns off the seventeenth transistor T17. The low level of the second clock signal is transmitted to the scan signal output terminal GOUT through the sixteenth transistor T16, that is, the scan signal output by the scan signal output terminal GOUT is at a low level at this time, so as to drive the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the corresponding pixel row (the row corresponding to the scan signal line 121 electrically connected to the scan driving unit ASGN of this level) to turn on (that is, work), that is, the Nth pixel row is refreshed.

[0127] It can be understood that the scan signal (low-level signal) output by the scan signal output terminal GOUT can be written to the scan signal input terminal GIN of the next-level scan driving unit ASG, so that the next-level scan driving unit ASG starts the steps of the Nth stage TN, until the first clock signal received by the first clock signal terminal SCK1 of the next-level scan driving unit ASG changes from a low level to a high level, and the second clock signal received by the second clock signal terminal SCK2 changes from a high level to a low level, the scan signal output terminal GOUT of the next-level scan driving unit ASG outputs a low-level signal. In this way, the scan driving circuit 14a starts to output low-level signals in sequence from the scan signal output terminal GOUT of the N-level scan driving unit ASGN, and realizes the sequential shifting of the scan signal. That is, the refresh of the Nth pixel row corresponding to the N-level scan driving unit ASGN, the (N+1)th pixel row corresponding to the (N+1)-level scan driving unit ASGN, the (N+2)th pixel row corresponding to the (N+2)-level scan driving unit ASGN, ..., and other pixel rows is realized.

[0128] In the (N+2)th stage T(N+2), i.e., the stage where the scan signal output terminal outputs a high level: the first clock signal received by the first clock signal terminal SCK1 changes from a high level to a low level, the second clock signal received by the second clock signal terminal SCK2 changes from a low level to a high level, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the high level signal input by the trigger signal input terminal STV is written into the fifth node N5, the twelfth transistor T12 is turned off, and the low level signal received by the second level signal receiving terminal VGL is written into the sixth node N6. The high level at the fifth node N5 turns off the sixteenth transistor T16, and the low level at the sixth node N6 turns on the seventeenth transistor T17. The scan signal output by the scan signal output terminal GOUT is a high level signal at this time. At this time, the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the corresponding pixel row are turned off.

[0129] The above describes the process of starting scanning from the Nth row. It should be noted that N can be any number, for example, scanning can be started from the fourth row, the fourteenth row, the fortieth row, and so on.

[0130] The specific process of the scanning driving circuit 14a ending scanning from the Mth row is described below, where M is greater than N.

[0131] Fig.14 The timing diagram of each signal of the scanning driving unit ending scanning from the Mth row is shown. Figure 7 The operation process of the scan driving unit ASG of the scan driving circuit 14a shown in FIG.

[0132] In the (M-1)th stage T(M-1), that is, the stage where the scanning signal output terminal outputs a high level: see Fig.15 , Fig.15 Specific signals of the (M-1)th scanning driving unit ASG(M-1) and the Mth scanning driving unit ASGM at various positions in the (M-1)th stage, wherein the thick solid line represents a first level signal, i.e., a high level signal; and the thick dotted line represents a second level signal, i.e., a low level signal. The scanning signal output terminal GOUT of the (M-1)th scanning driving unit ASG(M-1) outputs a scanning signal (low level signal).

[0133] At the same time, the scan signal (low level signal) outputted from the scan signal output terminal GOUT of the (M-1)th scan driving unit ASG(M-1) can be written to the scan signal input terminal GIN of the Mth scan driving unit ASGM, so that the Mth scan driving unit ASGM starts to output a low level scan signal. However, in order to end the scan of the Mth pixel row, that is, in order to make the scan signal output terminal GOUT of the Mth scan driving unit ASGM not output a low level scan signal. In the (M-1)th stage T(M-1), the signal transmitted from the cut-off signal line CloseL received by the cut-off signal input terminal Close changes from the high level signal of the (M-2)th stage T(M-2) to a low level signal. At this time, the eighth transistor T8 of the Mth scan driving unit ASGM is turned on, and the high level signal received by the first level signal receiving terminal VGH is written to the gate of the sixth transistor T6 through the eighth transistor T8. The sixth transistor T6 is turned off, and the low level signal received by the scan signal input terminal GIN of the Mth scan driving unit ASGM cannot be written to the first node N1.

[0134] Since the first clock signal received by the first clock signal terminal SCK1 of the M-th level scanning driving unit ASGM is at a low level, and the second clock signal received by the second clock signal terminal SCK2 is at a high level, the tenth transistor T10 and the eleventh transistor T11 are turned on, and the sixth node N6 is at a low level. The low level at the sixth node N6 turns on the seventeenth transistor T17, and the scanning signal output by the scanning signal output terminal GOUT is at a high level at this time.

[0135] In the Mth stage TM, that is, the stage where the scanning signal output terminal outputs a high level and maintains: Fig.16 , Fig.16It is the specific signal of each position of the M-th level scanning driving unit ASGM in the M-th stage, wherein the thick solid line represents the first level signal, i.e., the high level signal; the thick dotted line represents the second level signal, i.e., the low level signal. The signal received by the cut-off signal input terminal Close changes from a low level signal to a high level signal, at which time, the eighth transistor T8 is cut off. Since the first clock signal received by the first clock signal terminal SCK1 is at a high level, the second clock signal received by the second clock signal terminal SCK2 is at a low level, the tenth transistor T10 and the eleventh transistor T11 are cut off, and due to the (M-1)-th stage T(M-1), the low-level first clock signal received by the first clock signal terminal SCK1 of the M-th level scanning driving unit ASGM is written to the third capacitor C3, so that the signal at the sixth node N6 continues to maintain a low level signal, and the low level signal at the sixth node N6 turns on the seventeenth transistor T17, and the scanning signal output by the scanning signal output terminal GOUT is still at a high level at this time. At the same time, the voltage across the second capacitor C2 changes from a low level signal to a high level signal, and the high level signal at the fifth node N5 turns off the sixteenth transistor T16.

[0136] It can be known from the working process of the above-mentioned scanning driving unit ASG that, through the scanning driving circuit 14a provided in the embodiment of the present application, it is possible to realize scanning from the Nth pixel row to the Mth pixel row, that is, to complete the refresh of the Nth pixel row to the Mth pixel row, while the pixel rows before the Nth pixel row and the pixel rows after the Mth pixel row are not refreshed.

[0137] It should be understood that Fig.14 This is only an example of how to control each row of pixels 11 to end refreshing through the scanning driving unit ASG. In practical applications, the waveform and timing of each signal are not limited to Fig.14 For example, it may also be that after the cutoff signal input terminal Close receives a signal that changes from a high level signal to a low level signal, it may remain at a low level, and in the next frame, the cutoff signal input terminal Close receives a signal that changes from a low level signal to a high level signal.

[0138] Combination Fig.17 , Fig.17 FIG. 1 shows a timing diagram of various signals in the scan drive circuit 14a. Fig.17 In order to better contrast the shift signal and the scan signal, the shift signal received by the first shift signal input terminal Scan input of each stage and the scan signal output by the scan signal output terminal GOUT of each stage are adjacent to each other, and in order to distinguish the shift signal received by the first shift signal input terminal Scan input of each stage, a thin line is used to represent the shift signal, and the scan signal output by the scan signal output terminal GOUT of each stage is represented by a thick line.

[0139] Depend on Fig.17It can be seen that in the shift stage: when the shift signal received at the first shift signal input terminal Scan input of the first-stage scan driving unit ASG1 is a low-level signal, the first-stage scan driving unit ASG1 outputs a low-level shift signal to the first shift signal input terminal Scaninput of the next-stage (i.e., the second-stage) scan driving unit ASG2 through the shift signal output terminal Scan out of this stage; when the first shift signal input terminal Scaninput of the second-stage scan driving unit ASG2 receives a low-level shift signal, the second-stage scan driving unit ASG2 outputs a low-level shift signal to the first shift signal input terminal Scan input of the next-stage (i.e., the third-stage) scan driving unit ASG3 through the shift signal output terminal Scan out of this stage; ...; when the first shift signal input terminal Scaninput of the (N-1)-stage scan driving unit ASG(N-1) receives a low-level shift signal, the (N-1)-stage scan driving unit ASG(N-1) outputs a low-level shift signal to the first shift signal input terminal Scan input of the next-stage (i.e., the third-stage) scan driving unit ASG3 through the shift signal output terminal Scan out of this stage. out outputs a low-level shift signal to the first shift signal input terminal Scan input of the next level (i.e., the Nth level) scan driver ASGN, that is, the shift signal is shifted from the first level scan driver ASG1 to the Nth level scan driver ASG in sequence. At the same time (i.e., in the shifting stage), the scan signal output terminal GOUT of the first level scan driver ASG1 to the (N-1)th level scan driver ASG(N-1) is a high-level signal, and the scan signal cannot drive the P-type transistors (data writing transistors M2 and threshold compensation transistors M3) in the pixel circuit 111 of the first pixel row to the Nth pixel row to turn on (i.e., work). In other words, the pixel rows corresponding to the first level scan driver ASG1 to the (N-1)th level scan driver ASG(N-1) are not refreshed.

[0140] Depend on Fig.17It can be known that in the scanning stage: when the shift signal received at the first shift signal input terminal Scaninput of the N-th level scanning driving unit ASGN is a low-level signal, the N-th level scanning driving unit ASGN outputs a low-level shift signal to the first shift signal input terminal Scaninput of the next level (i.e., the N+1-th level) scanning driving unit ASG(N+1) through the shift signal output terminal Scan out of this level; ...; when the first shift signal input terminal Scan input of the (M-1)-th level scanning driving unit ASG(M-1) outputs a low-level shift signal to the first shift signal input terminal Scan input of the next level (i.e., the M-th level) scanning driving unit ASGN through the shift signal output terminal Scan out of this level; when the first shift signal input terminal Scan input of the M-th level scanning driving unit ASGM receives a low-level shift signal, the M-th level scanning driving unit ASGM outputs a low-level shift signal to the first shift signal input terminal Scan input of the next level (i.e., the M-th level) scanning driving unit ASGM through the shift signal output terminal Scan out of this level. out outputs a low-level shift signal to the first shift signal input terminal Scaninput of the next level (i.e., the M+1 level) scan driving unit ASG(M+1). That is, the shift signal is shifted from the N-level scan driving unit ASGN to the (M+1)-level scan driving unit ASG in sequence. At the same time, when the shift signal shifts to the first shift signal input terminal Scan input of the (N-1)-level scan driving unit ASG(N-1), the signal input by the trigger signal input terminal STV changes from a high-level signal to a low-level signal.When the signal input by the trigger signal input terminal STV is a low-level signal, and the second clock signal terminal SCK2 receives the second clock signal as a low-level signal, the N-th level scan driving unit ASGN outputs a low-level scan signal to the N-th pixel row corresponding to the N-th level scan driving unit ASGN through the scan signal output terminal GOUT of this level, and at the same time, outputs the low-level scan signal to the scan driving unit ASG(N+1) of the next level (i.e., the N+1 level); when the (N+1)-th level scan driving unit ASG(N+1) receives a low-level scan signal, the (N+1)-th level scan driving unit ASG(N+1) outputs a low-level scan signal to the (N+1)-th pixel row corresponding to the (N+1)-th level scan driving unit ASG(N+1) through the scan signal output terminal GOUT of this level, and at the same time, the (N+1)-th level scan driving unit ASG(N+1) outputs a low-level scan signal to the (N+1)-th pixel row corresponding to the (N+1)-th level scan driving unit ASG(N+1) through the scan signal output terminal GOUT of this level. +2) outputs a low-level scan signal; ...; when the (M-1)-th level scan driving unit ASG(M-1) receives the low-level scan signal, the (M-1)-th level scan driving unit ASG(M-1) outputs the low-level scan signal to the (M-1)-th pixel row corresponding to the (M-1)-th level scan driving unit ASG(M-1) through the scan signal output terminal GOUT of this level, and at the same time, the (M-1)-th level scan driving unit ASG(M-1) outputs the low-level scan signal to the next level (i.e., the M-th level) scan driving unit ASGM through the scan signal output terminal GOUT of this level; when the M-th level scan driving unit ASGM receives the low-level scan signal, the M-th level scan driving unit ASGM outputs the low-level scan signal to the M-th pixel row corresponding to the M-th level scan driving unit ASGM through the scan signal output terminal GOUT of this level, and at the same time, outputs the low-level scan signal to the next level (i.e., the M+1-th level) scan driving unit ASG(M+1). The scanning signal is sequentially shifted from the Nth level scanning driving unit ASGN to the (M+1)th level scanning driving unit ASG(M+1). When the scanning signal output terminal GOUT of the scanning driving unit ASG outputs a low-level scanning signal to the corresponding pixel row, the low-level signal can drive the P-type transistor (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the corresponding pixel row to turn on (i.e., work), thereby realizing the refresh from the Nth pixel row to the Mth pixel row.

[0141] Depend on Fig.17It can be seen that in the scanning stop stage: when the M-th level scanning driving unit ASGM outputs a low-level scanning signal to the M-th pixel row corresponding to the M-th level scanning driving unit ASGM through the scanning signal output terminal GOUT of this level, and at the same time, outputs a low-level scanning signal to the scanning driving unit ASG(M+1) of the next level (i.e., the M+1-th level), the signal received by the cut-off signal input terminal Close changes from a low-level signal to a high-level signal. When the signal received by the cut-off signal input terminal Close is a high-level signal, the scanning signal output by the scanning signal output terminal GOUT of the (M+1)-th level scanning driving unit ASG(M+1) changes to a high-level scanning signal. At this time, the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the (M+1)-th pixel row are turned off, and refreshing cannot be achieved.

[0142] It can be seen that in the scan driving circuit 14a, when the shift signal received at the first shift signal input terminal Scan input of the first-level scan driving unit ASG1 is a low-level signal, the shifting starts. At this time, only the shifting occurs, and the signal output from the scan signal output terminal GOUT is a high-level signal, which cannot open the corresponding pixel row and still maintains the data signal of the previous frame; until the signal input from the trigger signal input terminal STV changes from a high-level signal to a low-level signal, the signal output from the scan signal output terminal GOUT of the scan driving unit ASG that is shifted becomes a low-level signal, which can realize the refresh of the corresponding pixel row; when the signal received from the cut-off signal input terminal Close changes from a low-level signal to a high-level signal, the signal output from the scan signal output terminal GOUT of the scan driving unit ASG that is shifted becomes a high-level signal, and the signals output from the scan signal output terminal GOUT of the subsequent scan driving unit ASG are all high-level signals. Accordingly, the pixel row corresponding to the subsequent scan driving unit ASG cannot be refreshed and still maintains the data signal of the previous frame. In this way, the refresh rates of the pixel rows corresponding to the scanning driving unit ASG before the N-th scanning driving unit ASGN, the pixel rows corresponding to the scanning driving unit ASG after the M-th scanning driving unit ASGM, and the pixel rows corresponding to the scanning driving unit ASG between the N-th scanning driving unit ASGN and the M-th scanning driving unit ASGM are different.

[0143] It should be understood that Fig.17 This is only an example of how to control whether each row of pixels 11 is refreshed and thus control the refresh rate of each row of pixels through the scanning driving unit ASG. Fig.17 The waveform and timing of each signal in the Fig.15 shown.

[0144] Based on the above structure and working process, Figure 1The process of achieving different refresh rates in the status bar 101, video play area 102, and static content display area 103 is introduced. Here, the refresh rate of the status bar 101 is 1 Hz, the refresh rate of the video play area 102 is 60 Hz, and the refresh rate of the static content display area 103 is 30 Hz.

[0145] See also Fig.18 , Fig.18 A refresh process of a display screen provided in an embodiment of the present application, wherein the refresh process is a process in which a display driver chip provides a data signal to a display panel. Fig.18As shown, in the first frame, the scan driving circuit 14a completes the scanning of all pixel rows, that is, the trigger signal input by the trigger signal input terminal STV needs to output a low-level signal from the first-level scan driving unit ASG1 until all pixel rows are scanned, and the signal received by the cut-off signal input terminal Close changes from a low-level signal to a high-level signal, that is, in the first frame, all refreshes of the status bar 101, the video playback area 102, and the static content display area 103 are completed; in the second frame, the scan driving circuit 14a needs to complete the scanning of the pixel rows where the video playback area 102 and the static content display area 103 are located, that is, when the shift signal is shifted to the pixel rows where the video playback area 102 and the static content display area 103 are located When the upper level scanning driving unit ASG corresponding to the scanning driving unit ASG of the first pixel row in the video playback area 102 is switched off, the trigger signal input terminal STV starts to output a low level signal until the pixel rows where the video playback area 102 and the static content display area 103 are located are scanned, and the signal received by the cut-off signal input terminal Close changes from a low level signal to a high level signal, that is, in the second frame, the local refresh of the two areas of the video playback area 102 and the static content display area 103 is completed; in the third frame, the scanning driving circuit 14a needs to complete the scanning of the pixel row where the video playback area 102 is located, that is, when the shift signal is shifted to the upper level scanning driving unit ASG corresponding to the first pixel row in the pixel row where the video playback area 102 is located, When the first-level scanning driving unit ASG is used, the trigger signal input by the trigger signal input terminal STV starts to output a low-level signal until the pixel rows where the video playback area 102 is located are scanned, and the signal received by the cut-off signal input terminal Close changes from a low-level signal to a high-level signal, that is, in the third frame, a local refresh of an area of ​​the video playback area 102 is completed; in the fourth frame, the scanning driving circuit 14a needs to complete the scanning of the pixel rows where the video playback area 102 and the static content display area 103 are located, that is, when the shift signal shifts to the scanning driving unit ASG of the previous level corresponding to the first pixel row in the pixel rows where the video playback area 102 and the static content display area 103 are located, the trigger signal input terminal ST The trigger signal of V input starts to output a low-level signal until the pixel rows where the video playback area 102 and the static content display area 103 are located are scanned, and the signal received by the cut-off signal input terminal Close changes from a low-level signal to a high-level signal, that is, the local refresh of the video playback area 102 and the static content display area 103 is completed in the fourth frame; ...; that is, the refresh method of the second frame and the third frame is cycled in sequence until the sixty-first frame, and then the refresh method of the first frame to the sixtieth frame is cycled again, and different refresh rates are displayed in different areas in turn, that is, the refresh frequency of the status bar 101 is 1hz, the refresh frequency of the video playback area 102 is 60hz, and the refresh frequency of the static content display area 103 is 30hz.

[0146] It should be noted that the above refresh frequencies are only examples and do not constitute a limitation of the present application. Those skilled in the art can set the trigger signal input by the trigger signal input terminal STV and the cutoff signal received by the cutoff signal input terminal Close according to actual conditions, so as to achieve different refresh frequencies for different areas.

[0147] It should also be noted that the above example is an example of three areas corresponding to different refresh frequencies, but it does not constitute a limitation on the present application. In other optional embodiments of the present application, four areas may correspond to different refresh frequencies, five areas may correspond to different refresh frequencies, etc., and the refresh frequencies of two non-adjacent areas may be the same, etc., as long as the trigger signal input by the trigger signal input terminal STV and the cutoff signal received by the cutoff signal input terminal Close are changed.

[0148] As can be seen from the above content, the scan driving circuits can be arranged on two opposite sides of the display area AA (that is, the scan driving circuits are arranged on both opposite sides of the display area AA), and the scan signal output ends of the two scan driving circuits are electrically connected to a scan signal line 121 to provide scan signals to the scan signal line 121. In other words, see Fig.19 , Fig.19 A schematic diagram of the structure of another display panel provided in an embodiment of the present application. There are two scan drive circuits 14a, and the two scan drive circuits 14a include a first scan drive circuit 14a1 and a second scan drive circuit 14a2. The scan signal output ends of the first scan drive circuit 14a1 and the second scan drive circuit 14a2 are both electrically connected to a scan signal line 121 to provide scan signals to the scan signal line 121.

[0149] Optional, see Fig. 20 , Fig. 20 A schematic diagram of the structure of another display panel provided in an embodiment of the present application is provided to clearly demonstrate the invention. Fig. 20 Only the scanning signal line 121 is shown, and the light emission control signal line 122 is not shown. Fig. 20As shown, each scanning signal line 121 includes a first scanning signal sub-segment 121a and a second scanning signal sub-segment 121b; each row of pixels 11 includes a first pixel group and a second pixel group, and the first pixel group and the second pixel group each include a plurality of pixels 11. Each pixel 11 of the first pixel group is electrically connected to the first scanning signal sub-segment 121a in the scanning signal line 121, and each pixel 11 of the second pixel group located in the same pixel row as the first pixel group is electrically connected to the second scanning signal sub-segment 121b in the scanning signal line 121. The scanning signals output by the scanning signal output modules of the plurality of scanning driving units ASG in the first scanning driving circuit 14a1 are provided to the pixels 11 of the first pixel group through the first scanning signal sub-segment 121a, and the scanning signals output by the scanning signal output modules of the plurality of scanning driving units ASG in the second scanning driving circuit 14a2 are provided to the pixels 11 of the second pixel group through the second scanning signal sub-segment 121b. Exemplarily, each pixel 11 of the first pixel group in the first row of pixels is electrically connected to the first scan signal sub-segment 121a in the first scan signal line 121, and each pixel 11 of the second pixel group in the first row of pixels is electrically connected to the second scan signal sub-segment 121b in the first scan signal line 121. The scan signal output by the scan signal output module of the first-level scan driving unit ASG1 in the first scan driving circuit 14a1 is provided to each pixel 11 of the first pixel group in the first row of pixels through the first scan signal sub-segment 121a in the first scan signal line 121, and the scan signal output by the scan signal output module of the first-level scan driving unit ASG1 in the second scan driving circuit 14a2 is provided to each pixel 11 of the second pixel group in the first row of pixels through the second scan signal sub-segment 121b in the first scan signal line 121; ...; each pixel 11 of the first pixel group in the N-th row of pixels is electrically connected to the first scan signal sub-segment 121a in the N-th scan signal line 121, and each pixel 11 of the second pixel group in the N-th row of pixels is electrically connected to the second scan signal sub-segment 121b in the N-th scan signal line 121. The scan signal output by the scan signal output module of the N-th level scan driving unit ASGN in the first scan driving circuit 14a1 is provided to each pixel 11 of the first pixel group in the N-th row of pixels through the first scan signal sub-segment 121a in the N-th scan signal line 121, and the scan signal output by the scan signal output module of the N-th level scan driving unit ASGN in the second scan driving circuit 14a2 is provided to each pixel 11 of the second pixel group in the N-th row of pixels through the second scan signal sub-segment 121b in the N-th scan signal line 121.

[0150] That is, the left and right parts of the display area AA of the display panel 10 are controlled by the first scan driving circuit 14a1 and the second scan driving circuit 14a2 respectively.

[0151] In this case, if Fig.21 As shown, Fig.21 One of the application scenarios of an electronic device provided in an embodiment of the present application, according to the above-mentioned refresh method, the first scan drive circuit 14a1 can control different areas of the left part of the display panel display area AA to achieve different refresh frequencies, such as achieving different refresh frequencies of area 101, area 102, area 103, area 104 and area 105 in the left part of the display panel display area AA, and the second scan drive circuit 14a2 can control different areas of the right part of the display panel display area AA to achieve different refresh frequencies, such as achieving different refresh frequencies of area 106, area 107 and area 108 in the right part of the display panel display area AA.

[0152] In summary, through the scanning drive circuit provided in the embodiment of the present application, the pixels 11 in different areas of the display panel 10 refresh data signals at different refresh rates, that is, different areas of the display panel 10 refresh the display content at different refresh rates. For areas where the display pictures / texts do not change, the display content can be refreshed at a lower refresh rate, for example, refreshing the display content at a refresh rate of 1Hz or 10Hz. For areas that display videos and other real-time changes, the display content can be refreshed at a higher refresh rate, for example, refreshing the display content at a refresh rate of 60Hz. In this way, since the refresh rate of the display panel 10 is reduced, the power consumption of the display panel is reduced.

[0153] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A scanning driving circuit, characterized in that: include: n scan driving units arranged in cascade, where n is a positive integer greater than or equal to 2; The scan driving unit comprises: a first selection module, a second selection module and a scan signal output module; The first selection module of each level of scan driving unit receives the shift signal output by the first selection module in the previous level of scan driving unit and receives the shift signal output by the first selection module in the next level of scan driving unit; When the first selection module of the Nth level scan driving unit receives the shift signal output by the first selection module in the (N-1)th level scan driving unit and receives the shift signal output by the first selection module in the (N+1)th level scan driving unit, and the first selection module of the Nth level scan driving unit receives the trigger signal, the first selection module is used to control the scan signal output module of the Nth level scan driving unit to start outputting the scan signal; The second selection module of each level of scanning driving unit receives the scanning signal output by the scanning signal output module in the previous level of scanning driving unit; When the second selection module of the Mth-stage scan driving unit receives the scan signal output by the scan signal output module in the (M-1)th-stage scan driving unit, and the second selection module of the Mth-stage scan driving unit receives the cut-off signal, the second selection module is used to control the scan signal output module of the Mth-stage scan driving unit to stop outputting the scan signal; N<M, and N is greater than or equal to 1, and M is less than or equal to n.

2. The scanning driving circuit according to claim 1, characterized in that: The first selection module is electrically connected to the first shift signal input terminal, the second shift signal input terminal, the first clock signal terminal, the trigger signal input terminal, the first level signal receiving terminal, the shift signal output terminal and the first node; A second selection module is electrically connected to the first node, the scan signal input terminal, the first level signal receiving terminal, the second level signal receiving terminal, the cutoff signal input terminal and the second node; the second node is connected to the second level signal receiving terminal; a scanning signal output module, electrically connected to the first node, the second node, the first clock signal terminal, the second clock signal terminal, the first level signal receiving terminal, the second level signal receiving terminal and the scanning signal output terminal; The first selection module is used to receive the first shift signal received by the first shift signal input terminal, the first clock signal by the first clock signal terminal, the trigger signal input by the trigger signal input terminal, and the first level signal received by the first level signal receiving terminal, and output a shift signal through the shift signal output terminal in response to the first shift signal and the second shift signal received by the second shift signal input terminal, as well as a signal controlling the first node; wherein the first shift signal input terminal of the current level scan driving unit is electrically connected to the shift signal output terminal of the previous level scan driving unit, the second shift signal input terminal is electrically connected to the shift signal output terminal of the next level scan driving unit, the first shift signal is the shift signal output by the shift signal output terminal of the previous level scan driving unit, and the second shift signal is the shift signal output by the shift signal output terminal of the next level scan driving unit; The second selection module is used to receive the first level signal received by the first level signal receiving end, the second level signal received by the second level signal receiving end, and the first scanning signal received by the scanning signal input end, and control the signal of the first node in response to the cut-off signal input by the cut-off signal input end and the signal at the second node; the first scanning signal is the scanning signal output by the scanning signal output module of the previous stage; The scanning signal output module is used to receive the first level signal received by the first level signal receiving end, the signal at the first node and the signal at the second node, the first clock signal received by the first clock signal end, and the second clock signal received by the second clock signal end, and control the scanning signal output by the scanning signal output end in response to the first clock signal, the second clock signal and the second level signal received by the second level signal receiving end.

3. The scanning driving circuit according to claim 2, characterized in that: The first selection module includes a shift unit and a start scanning unit; The shift unit is electrically connected to the first shift signal input terminal, the second shift signal input terminal, the first clock signal terminal, the first level signal receiving terminal and the shift signal output terminal; The start scanning unit, the trigger signal input terminal, the shift signal output terminal and the first node are electrically connected; The shift unit is used to receive the first shift signal received by the first shift signal input terminal, the first clock signal by the first clock signal terminal, and the first level signal received by the first level signal receiving terminal, and output a shift signal through the shift signal output terminal in response to the first shift signal and the second shift signal received by the second shift signal input terminal; The start scanning unit is used to receive the trigger signal input from the trigger signal input terminal, and output a shift signal in response to the shift signal output terminal, so as to control the signal at the first node.

4. The scanning driving circuit according to claim 3, characterized in that: The shift unit includes an input subunit and an output subunit; The input subunit is electrically connected to the first shift signal input terminal and the third node; The output subunit is electrically connected to the third node, the second shift signal input terminal, the first level signal receiving terminal, the first clock signal terminal and the shift signal output terminal; The input subunit is used to receive the first shift signal received by the first shift signal input terminal, and control the signal of the third node in response to the first shift signal; The output subunit is used to receive the first clock signal of the first clock signal terminal, and in response to the signal of the third node, control the shift signal output terminal to output a shift signal; Alternatively, the output subunit is used to receive the first level signal from the first level signal receiving end, and in response to the second shift signal from the second shift signal input end, control the shift signal output end to output a shift signal.

5. The scanning driving circuit according to claim 4, characterized in that: The input subunit includes a first transistor, a gate of the first transistor and a first electrode of the first transistor are both electrically connected to the first shift signal input terminal, and a second electrode of the first transistor is electrically connected to the third node.

6. The scanning driving circuit according to claim 4, characterized in that: The output subunit includes a second transistor, a third transistor, a fourth transistor and a first capacitor; The gate of the second transistor, the first electrode of the first capacitor, and the first electrode of the third transistor are all electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, the second electrode of the second transistor, the second electrode of the first capacitor, and the first electrode of the fourth transistor are all electrically connected to the shift signal output terminal, the gate of the third transistor and the gate of the fourth transistor are both electrically connected to the second shift signal input terminal, and the second electrode of the third transistor and the second electrode of the fourth transistor are both electrically connected to the first level signal receiving terminal.

7. The scan driving circuit according to any one of claims 3 to 6, characterized in that: The start scanning unit includes a fifth transistor, a gate of the fifth transistor is electrically connected to the shift signal output terminal, a first electrode of the fifth transistor is electrically connected to the trigger signal input terminal, and a second electrode of the fifth transistor is electrically connected to the first node.

8. The scanning driving circuit according to any one of claims 2 to 7, characterized in that: The second selection module includes a cut-off scanning unit, a first level signal input unit and a second level signal input unit; The cut-off scanning unit is electrically connected to the first node, the scanning signal input terminal and the fourth node; The first level signal input unit is electrically connected to the fourth node, the first level signal receiving terminal and the cutoff signal input terminal; The second level signal input unit is electrically connected to the fourth node, the second node and the second level signal receiving end; The second signal input unit is used to receive the second level signal received by the second level signal receiving end, and control the signal at the fourth node in response to the second level signal; The first signal input unit is used to receive the first level signal received by the first level signal receiving end, and change the signal at the fourth node in response to the cut-off signal input by the cut-off signal input end; The cut-off scanning unit is used to receive the first scanning signal received by the scanning signal input terminal, and control the signal at the first node in response to the signal at the fourth node.

9. The scanning driving circuit according to claim 8, characterized in that: The cut-off scanning unit includes a sixth transistor and a seventh transistor; the gate of the sixth transistor is electrically connected to the fourth node, the gate of the seventh transistor and the first electrode of the seventh transistor are both electrically connected to the scanning signal input terminal, the second electrode of the seventh transistor is electrically connected to the first electrode of the sixth transistor, and the second electrode of the sixth transistor is electrically connected to the first node.

10. The scan driving circuit according to claim 8, characterized in that: The first level signal input unit includes an eighth transistor, a gate of the eighth transistor is electrically connected to the cutoff signal input terminal, a first electrode of the eighth transistor is electrically connected to the fourth node, and a second electrode of the eighth transistor is electrically connected to the first level signal receiving terminal.

11. The scanning driving circuit according to claim 8, characterized in that: The second level signal input unit includes a ninth transistor, a gate of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the second level signal receiving end, and a second electrode of the ninth transistor is electrically connected to the fourth node.

12. The scanning driving circuit according to any one of claims 2 to 11, characterized in that: The scanning signal output module comprises: an input unit, electrically connected to the first node, the first clock signal terminal and the fifth node; A first control unit, electrically connected to the first clock signal terminal, the second node and the sixth node; A second control unit, electrically connected to the first level signal receiving terminal, the second clock signal terminal, the fifth node and the sixth node; an output unit, electrically connected to the first level signal receiving end, the second level signal receiving end, the second clock signal end, the fifth node, the sixth node and the scan signal output end; The input unit is used to receive the signal at the first node, and control the signal of the fifth node in response to the first clock signal received by the first clock signal terminal; The first control unit is used to receive the first clock signal received by the first clock signal terminal and the signal at the second node, and control the signal of the sixth node in response to the signal at the fifth node and the first clock signal received by the first clock signal terminal; The second control unit is used to receive the first level signal received by the first level signal receiving end, and change the signal of the fifth node in response to the signal at the sixth node and the second clock signal received by the second clock signal end; The output unit is used to receive the first level signal received by the first level signal receiving end, and control the scan signal output by the scan signal output end in response to the signal of the sixth node; or, the output module is used to receive the second clock signal received by the second clock signal end, and control the scan signal output by the scan signal output end in response to the signal of the fifth node.

13. The scanning driving circuit according to claim 12, characterized in that: The input unit includes a tenth transistor; A gate of the tenth transistor is electrically connected to the first clock signal terminal, a first electrode of the tenth transistor is electrically connected to the first node, and a second electrode of the tenth transistor is electrically connected to the fifth node.

14. The scanning driving circuit according to claim 12, characterized in that: The first control unit includes an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor and the second electrode of the twelfth transistor are both electrically connected to the sixth node; A gate of the twelfth transistor is electrically connected to the fifth node, and a first electrode of the twelfth transistor is electrically connected to the first clock signal terminal.

15. The scan driving circuit according to claim 12, characterized in that: The second control unit includes a thirteenth transistor and a fourteenth transistor; The gate of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor; A gate electrode of the fourteenth transistor is electrically connected to the sixth node, and a second electrode of the fourteenth transistor is electrically connected to the first level signal receiving terminal.

16. The scan driving circuit according to claim 12, characterized in that: The output unit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a second capacitor and a third capacitor; The gate of the fifteenth transistor is electrically connected to the second level signal receiving terminal, the first electrode of the fifteenth transistor is electrically connected to the fifth node, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the second capacitor and the gate of the sixteenth transistor respectively; The second electrode of the second capacitor, the second electrode of the sixteenth transistor, and the first electrode of the seventeenth transistor are all electrically connected to the scan signal output terminal; The first electrode of the sixteenth transistor is electrically connected to the second clock signal terminal; The gate of the seventeenth transistor and the first electrode of the third capacitor are both electrically connected to the sixth node, and the second electrode of the seventeenth transistor and the second electrode of the third capacitor are both electrically connected to the first level signal receiving end.

17. The scan driving circuit according to claim 2, characterized in that: Also includes a first clock signal line and a second clock signal line; The first clock signal terminal of the odd-numbered scan driving unit is electrically connected to the first clock signal line, and the second clock signal terminal of the odd-numbered scan driving unit is electrically connected to the second clock signal line; the first clock signal terminal of the even-numbered scan driving unit is electrically connected to the second clock signal line, and the second clock signal terminal of the even-numbered scan driving unit is electrically connected to the first clock signal line.

18. A display panel, characterized in that: comprising at least one scanning driving circuit as claimed in any one of claims 1 to 17, a plurality of pixels arranged in an array and a plurality of scanning line groups; The scan line group includes at least one scan signal line; the scan signal lines of the plurality of scan line groups are electrically connected to the scan signal output modules of the plurality of scan driving units respectively; Different pixel rows correspond to different scan line groups, and each pixel in the same row is electrically connected to a scan signal line of the same scan line group; the scan signal output by the scan signal output module is provided to the pixel through the scan signal line.

19. The display panel according to claim 18, characterized in that: The number of the scan driving circuits is two, and the two scan driving circuits include a first scan driving circuit and a second scan driving circuit; Each row of the pixels includes a first pixel group and a second pixel group, and the first pixel group and the second pixel group each include a plurality of pixels; The scanning signal line comprises a first scanning signal sub-line segment and a second scanning signal sub-line segment; Each pixel of the first pixel group is electrically connected to the same first scan signal sub-segment, and each pixel of the second pixel group is electrically connected to the same second scan signal sub-segment; The scanning signal output by the scanning signal output module of the multiple scanning driving units in the first scanning driving circuit is provided to each pixel of the first pixel group through the first scanning signal sub-segment, and the scanning signal output by the scanning signal output module of the multiple scanning driving units in the second scanning driving circuit is provided to each pixel of the second pixel group through the second scanning signal sub-segment.

20. An electronic device, characterized in that: Comprising the display panel as claimed in claim 18 or 19.

Images