Driving chip of display panel, display panel and display device

Abstract

The embodiment of the invention provides a driving chip of a display panel, the display panel and a display device.In the driving chip, a data interface module is used for receiving display data transmitted by a host; the data input end of any one of the N algorithm processing modules is electrically connected with the target data signal line, and the data output end of any one of the N algorithm processing modules is electrically connected with the target data signal line; the control module is used for controlling at least one target algorithm processing module in the N algorithm processing modules to be in an enabled state when the data interface module receives the display data; the algorithm processing modules in the N algorithm processing modules are used for receiving the display data and adjusting the display data under the condition that the algorithm processing modules are in the enabled state, and transmitting the adjusted display data to the random access memory through a target data signal line; the random access memory is used for storing the adjusted display data. According to the embodiment of the invention, the power consumption of the driving chip can be effectively reduced.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a display panel driver chip, a display panel, and a display device. Background Art

[0002] With the rapid development of display technology, full-screen displays have become a trend in mobile display devices such as mobile phones. Organic Light Emitting Diodes (OLEDs) and flat-panel displays based on technologies such as LEDs have become mainstream in consumer electronics, including mobile phones, televisions, laptops, and desktop computers, due to their advantages of high image quality, power efficiency, thinness, and wide application range. However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0003] The embodiments of the present application provide a display device and a display adjustment method, which can effectively reduce the power consumption of a driver chip, thereby effectively enhancing the overall market competitiveness of the chip and even the panel.

[0004] In a first aspect, an embodiment of the present application provides a driver chip for a display panel, the driver chip including a data interface module, a control module, N algorithm processing modules, a random access memory, and a target data signal line, where N is a positive integer;

[0005] The data interface module is electrically connected to the random access memory via a target data signal line, and the data interface module is used to receive display data transmitted by the host;

[0006] The data input end of any algorithm processing module among the N algorithm processing modules is electrically connected to the target data signal line, and the data output end of any algorithm processing module among the N algorithm processing modules is electrically connected to the target data signal line;

[0007] The control module is configured to control at least one target algorithm processing module among the N algorithm processing modules to be in an enabled state when the data interface module receives the display data, so that the target algorithm processing module adjusts at least part of the display data;

[0008] Any one of the N algorithm processing modules is used for receiving display data and adjusting the display data when in an enabled state, and transmitting the adjusted display data to a random access memory through a target data signal line;

[0009] The random access memory is used to store the adjusted display data, so that the display panel displays the target picture based on the adjusted display data.

[0010] According to the implementation scheme of the first aspect of the present application, each of the N algorithm processing modules includes an enable control terminal; the control module is electrically connected to the enable control terminal of each of the N algorithm processing modules respectively; the control module is used to provide a valid level to the enable control terminal of the target algorithm processing module when the data interface module receives display data.

[0011] According to the implementation of the first aspect of the present application, the control module is configured to send a non-valid level to the enable control terminal of each of the N algorithm processing modules when the data interface module does not receive the display data.

[0012] According to the implementation of the first aspect of the present application, the control module is used to provide a non-valid level to the enable control terminal of the algorithm processing module other than the target algorithm processing module among the N algorithm processing modules when the data interface module receives the display data.

[0013] According to the implementation of the first aspect of the present application, the driver chip also includes N first switch modules corresponding one-to-one to the N algorithm processing modules; the control end of the first switch module is electrically connected to the control module, the first end of the first switch module is electrically connected to the target data signal line, and the second end of the first switch module is electrically connected to the data input end of the corresponding algorithm processing module; the algorithm processing module is used to receive display data and adjust the display data when the control module provides a conduction level to the control end of the first switch module.

[0014] According to the implementation scheme of the first aspect of the present application, the control module is used to provide a cutoff level to the control end of the first switch module corresponding to each of the N algorithm processing modules when the data interface module does not receive display data; the algorithm processing module is used to shut down when the control module provides the cutoff level to the control end of the corresponding first switch module, so that the algorithm processing module is in a non-enabled state.

[0015] According to an implementation of the first aspect of the present application, the first switching module includes a first transistor; the control end of the first transistor is electrically connected to the control module, the first end of the first transistor is electrically connected to the target data signal line, and the second end of the first transistor is electrically connected to the data input end of the corresponding algorithm processing module; the algorithm processing module is used to receive display data and adjust the display data when the control module provides a conduction level to the control end of the first transistor.

[0016] According to the implementation of the first aspect of the present application, the driver chip also includes N second switch modules corresponding one to one to the N algorithm processing modules; the control end of the second switch module is electrically connected to the control module, the first end of the second switch module is electrically connected to the target data signal line, and the second end of the second switch module is electrically connected to the data output end of the corresponding algorithm processing module; the algorithm processing module is used to transmit the adjusted display data to the target data signal line through the second switch module when the control module provides a conduction level to the control end of the second switch module.

[0017] According to the implementation scheme of the first aspect of the present application, the control module is used to provide a cutoff level to the control end of the second switch module corresponding to each of the N algorithm processing modules when the data interface module does not receive display data; the algorithm processing module is used to shut down when the control module provides the cutoff level to the control end of the corresponding second switch module, so that the algorithm processing module is in a non-enabled state.

[0018] According to the implementation of the first aspect of the present application, the second switching module includes a second transistor; the control end of the second transistor is electrically connected to the control module, the first end of the second transistor is electrically connected to the target data signal line, and the second end of the second transistor is electrically connected to the data output end of the corresponding algorithm processing module; the algorithm processing module is used to transmit the adjusted display data to the target data signal line through the second transistor when the control module provides a conduction level to the control end of the second transistor.

[0019] According to the implementation scheme of the first aspect of the present application, when the display data of the display screen required to be displayed on the display panel is updated, the data interface module receives the updated display data transmitted by the host; the control module is used to control at least one of the N algorithm processing modules to be enabled when the data interface module receives the updated display data, so that the enabled algorithm processing module adjusts at least part of the display data.

[0020] According to the implementation of the first aspect of the present application, when the display data of the display screen required by the display panel is not updated, the random access memory is used to provide the stored adjusted display data to the display panel so that the display panel maintains the target screen based on the adjusted display data.

[0021] According to an embodiment of the first aspect of the present application, the random access memory is used to provide the stored adjusted display data to the display panel according to the self-refresh frequency of the display panel.

[0022] According to the implementation of the first aspect of the present application, the data interface module is a data interface that supports the mobile industry processor interface MIPI or the serial peripheral interface SPI communication protocol.

[0023] According to the implementation scheme of the first aspect of the present application, the display data includes first sub-display data and second sub-display data, and at least one target algorithm processing module includes a first algorithm processing module and / or a second algorithm processing module; the control module is used to control the first algorithm processing module and the second algorithm processing module to be in an enabled state when the data interface module receives the display data; the first algorithm processing module is used to adjust the first sub-display data according to the first algorithm processing rule to obtain adjusted first sub-display data; the second algorithm processing module is used to adjust the second sub-display data according to the second algorithm processing rule to obtain adjusted second sub-display data.

[0024] According to an implementation of the first aspect of the present application, the display area corresponding to the first sub-display data does not overlap with the display area corresponding to the second sub-display data.

[0025] According to an embodiment of the first aspect of the present application, the first algorithm processing module is further configured to transmit the adjusted first sub-display data to the target data signal line; the second algorithm processing module is further configured to transmit the adjusted second sub-display data to the target data signal line;

[0026] According to an implementation of the first aspect of the present application, the first algorithm processing module is configured to perform edge algorithm processing on the first sub-display data to obtain adjusted first sub-display data.

[0027] According to the implementation of the first aspect of the present application, the second algorithm processing module is used to perform in-plane edge algorithm processing on the second sub-display data to obtain adjusted second sub-display data.

[0028] According to the implementation scheme of the first aspect of the present application, at least one target algorithm processing module also includes a third algorithm processing module; the third algorithm processing module is used to obtain the adjusted first sub-display data and the adjusted second sub-display data, and adjust the adjusted first sub-display data and the adjusted second sub-display data according to the third algorithm processing rules to obtain the adjusted display data.

[0029] According to the implementation of the first aspect of the present application, the first algorithm processing module is used to store the adjusted first sub-display data in the first cache, and the second algorithm processing module is used to store the adjusted second sub-display data in the second cache; the third algorithm processing module is used to call the data in the first cache and the second cache to obtain the adjusted first sub-display data and the adjusted second sub-display data.

[0030] According to an implementation of the first aspect of the present application, the third algorithm processing module is used to perform brightness compensation on the adjusted first sub-display data and the adjusted second sub-display data.

[0031] According to the implementation of the first aspect of the present application, the driver chip also includes a gamma module; the data input end of the random access memory is electrically connected to the target data signal line, the data output end of the random access memory is electrically connected to the first end of the gamma module, and the second end of the gamma module is electrically connected to the display panel; a preset gamma curve is stored in the gamma module; the gamma module is used to call the adjusted display data stored in the random access memory, convert the adjusted display data into a data voltage according to the preset gamma curve, and then send the data voltage to the display panel.

[0032] According to an implementation of the first aspect of the present application, the display data and the adjusted display data are grayscale data;

[0033] According to an embodiment of the first aspect of the present application, the display panel includes a plurality of sub-pixels arranged in an array, and the adjusted display data includes grayscale values ​​of the plurality of sub-pixels;

[0034] The gamma module is used for converting the grayscale values ​​of the plurality of sub-pixels into data voltages of the plurality of sub-pixels according to a preset gamma curve, and providing the data voltages of the plurality of sub-pixels to the plurality of sub-pixels accordingly.

[0035] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display panel, which is electrically connected to the driving chip of the display panel as described in any one of the embodiments of the first aspect.

[0036] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, which includes a display panel as described in any one of the embodiments of the second aspect.

[0037] From the above description, it can be seen that the driver chip, display panel, and display device of a display panel according to an embodiment of the present application, by placing the random access memory after the algorithm processing module, each algorithm processing module can process the display data independently or collaboratively under the control of the control module, thereby achieving the display data transmitted by the mainboard being processed once by the designated target algorithm processing module and then stored in the random access memory. In this way, when the mainboard data does not change, the display panel can directly retrieve data from the random access memory to continuously display the target screen during self-refresh. The algorithm processing module does not need to repeatedly process the same display data when the mainboard data is not updated, thereby effectively achieving the purpose of reducing power consumption, which is conducive to improving the competitiveness of the driver chip.

[0038] Compared to the prior art, the driver chip, display panel, and display device of a display panel according to an embodiment of the present application, in a low refresh mode such as AOD, the data retrieved from the random access memory does not need to be processed by the algorithm module each time the panel self-refreshes. Whether the algorithm processing module works or not is only related to whether the mainboard updates and transmits the display data to the data interface module. That is, when the content of the display panel display remains unchanged, the algorithm processing module does not need to be enabled for data processing. It only needs to retrieve data from the rear random access memory to meet the panel self-refresh requirements, thereby fully reducing the chip power consumption. In addition, each algorithm processing module is connected in parallel with the target data signal line and is enabled by the control module. The control module can flexibly control the specified algorithm processing module to be enabled according to the actual data processing requirements. The unnecessary algorithm processing modules can be controlled to be closed to avoid the display data passing through, thereby achieving the purpose of further reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 This is a schematic diagram of the structure of a driver chip provided in an embodiment of the present application;

[0041] Figure 2 This is a schematic structural diagram of another driver chip provided in an embodiment of the present application;

[0042] Figure 3 This is a schematic structural diagram of another driver chip provided in an embodiment of the present application;

[0043] Figure 4 This is a schematic structural diagram of another driver chip provided in an embodiment of the present application;

[0044] Figure 5 This is a schematic structural diagram of another driver chip provided in an embodiment of the present application;

[0045] Figure 6 This is a schematic structural diagram of another driver chip provided in an embodiment of the present application;

[0046] Figure 7 This is a schematic structural diagram of another driver chip provided in an embodiment of the present application;

[0047] Figure 8 is a structural diagram of a display panel provided in an embodiment of the present application;

[0048] Figure 9It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0050] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0051] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0052] It should be noted that the transistors in the embodiments of the present application can be either N-type transistors or P-type transistors. For N-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second electrodes of the transistor are conductive, and when the gate of the N-type transistor is at a low level, the first and second electrodes of the transistor are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first and second electrodes of the transistor are conductive, and when the control terminal of the P-type transistor is at a high level, the first and second electrodes of the transistor are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control terminal, and depending on the signal of the gate of each transistor and its type, the first electrode of the transistor can serve as the source and the second electrode as the drain, or the first electrode can serve as the drain and the second electrode as the source, without distinction being made herein. In addition, the on-level and off-level in the embodiments of the present invention are both general terms. The on-level refers to any level that can turn the transistor on, and the off-level refers to any level that can turn the transistor off / on.

[0053] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0054] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0056] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0057] As mentioned above, with the rapid development of display technology in related technologies, the requirements for larger display areas and longer all-weather (AOD, Always On Display) time have become increasingly prominent. The AOD mode is the "always display" or "constantly bright display" mode. The larger the display area of ​​the display panel, the greater the load, the greater the current demand, and the higher the driving capability requirement for the power supply. Longer standby time requires lower power consumption requirements for the panel. In view of the slow development of battery technology, the requirements for the power consumption of the main control chip are getting higher and higher, which has become one of the main problems facing the display panel industry. At present, the reduction of chip power consumption is mainly solved by improving the process, but the improvement of the process also places higher requirements on chip production equipment. Therefore, how to effectively reduce the power consumption demand of the panel is one of the performance issues that the industry urgently needs to improve.

[0058] The inventors of this application have discovered that, because the existing driver chip (DDIC, Display Driver Integrated Circuit) uses internal RAM (Random Access Memory) to connect to each algorithm data processing unit in sequence, with the RAM in front and the main algorithm processing in the back, a single series connection method is used. Therefore, each time the display panel is refreshed, it needs to undergo algorithm processing and synchronously pass through unused algorithm processing units, resulting in a problem of high power consumption of the DDIC unit.

[0059] Existing driver integrated circuits (DDICs) utilize a circuit connection method that sequentially connects internal random access memory (RAM) to various algorithm modules. Because the RAM is placed in front, and the algorithm modules are connected in a single series arrangement behind the RAM, every time the display panel is refreshed, data sent from the RAM must be processed by the algorithm. The algorithm circuit modules must operate for each refresh of the display panel, increasing the DDIC's power consumption.

[0060] To address the above technical issues, the embodiments of the present application provide a display panel driver chip, a display panel, and a display device, which can effectively reduce the power consumption of the driver chip, thereby helping to enhance the market competitiveness of display panels. It should be noted that the embodiments provided in this application are not intended to limit the scope of the disclosure of this application.

[0061] The following first introduces the driver chip of the display panel provided in the embodiment of the present application.

[0062] Figure 1The figure shows a schematic diagram of the structure of a driver chip provided in an embodiment of the present application. The display panel 200 can be an AMOLED (Active-matrix organic light emitting diode), an OLED, or other, and this application does not impose strict restrictions on this. The driver chip 100 and the display panel 200 can be bonded together through relevant processes, or the display panel 200 can also have the driver chip 100 embedded therein, and this embodiment does not impose strict restrictions on this.

[0063] It should be noted that, in actual applications, the display panel 200 and the driver chip 100 work in conjunction with each other. The driver chip 100 is typically packaged together with the display panel 200 in a module. This module may include a flexible printed circuit board (FPCB) or other types of connection methods to achieve electrical connection with the display panel 200.

[0064] like Figure 1 As shown, an embodiment of the present application provides a driver chip 100 for a display panel 200. The driver chip 100 includes a data interface module 10, a control module 30, N algorithm processing modules 20, a random access memory 40, and a target data signal line DL, where N is a positive integer. The random access memory 40 can be, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM), and is not strictly limited here.

[0065] The data interface module 10 is electrically connected to the random access memory 40 via a target data signal line DL. The data interface module 10 is used to receive display data transmitted from a host.

[0066] The data input terminal IN of any algorithm processing module 20 among the N algorithm processing modules 20 is electrically connected to the target data signal line DL, and the data output terminal OUT of any algorithm processing module 20 among the N algorithm processing modules 20 is electrically connected to the target data signal line DL.

[0067] The above-mentioned control module 30 is used to control at least one target algorithm processing module (for example, algorithm processing module 1) among the N algorithm processing modules 20 to be in an enabled state when the data interface module 10 receives display data, so that the target algorithm processing module adjusts at least part of the display data.

[0068] Any algorithm processing module 20 among the N algorithm processing modules 20 is used to receive display data and adjust the display data when in an enabled state, and transmit the adjusted display data to the random access memory 40 through the target data signal line DL.

[0069] The random access memory 40 is used to store the adjusted display data so that the display panel 200 displays the target image based on the adjusted display data. The above display data can be, for example, grayscale data or brightness data corresponding to each sub-pixel of the display panel, which is not strictly limited here.

[0070] It should be noted that among the above-mentioned N algorithm processing modules 20, the data processing functions undertaken by different algorithm processing modules 20 are different. Data processing functions such as demura compensation, gamma correction, IR drop (voltage drop) compensation, anti-burn-in processing or overdrive compensation are not strictly limited here and can be set according to the actual display requirements of the display panel.

[0071] In one example, there is an algorithm processing module 20 that performs demura compensation on the display data according to a preset compensation algorithm to compensate for the uneven display of the screen; there is also an algorithm processing module 20 that can be used to detect and compensate for IR Drop according to a built-in algorithm, thereby compensating for the uneven brightness problem caused by uneven current distribution.

[0072] In different display scenarios, the algorithm processing required for display data may be different. Therefore, in this application, the above-mentioned structural setting is used to enable each algorithm processing module 20 to process display data independently or collaboratively realize the processing of display data under the flexible control of the control module 30.

[0073] It should also be noted that the display data processed by different algorithm processing modules 20 may be different. For example, there may be an algorithm processing module 20 that only processes a specified portion of the display data, or there may be an algorithm processing module that processes all of the display data. There is no strict restriction here, and specific settings can be made according to the functions of different algorithm processing modules 20.

[0074] The embodiment of the present application provides a driver chip 100 for a display panel 200. By placing a random access memory 40 behind the algorithm processing module 20, each algorithm processing module 20 can independently process display data or collaboratively process display data under the control of the control module 30. This ensures that display data transmitted from the motherboard is processed once by a designated target algorithm processing module and then stored in the random access memory 40. In this way, when the motherboard data remains unchanged, the display panel 200 can directly retrieve data from the random access memory 40 to continuously display the target screen during self-refresh. The algorithm processing module 20 does not need to repeatedly process the same display data when the motherboard data is not updated, thereby effectively reducing power consumption and improving the driver chip 100's driving competitiveness.

[0075] Compared to the prior art, in a driver chip 100 for a display panel 200 according to an embodiment of the present application, in a low refresh mode such as AOD, the data retrieved from the random access memory 40 does not need to be processed by the algorithm module each time the panel self-refreshes. Whether the algorithm processing module 20 works or not is only related to whether the mainboard updates and transmits the display data to the data interface module 10. That is, when the display screen content of the display panel 200 remains unchanged, the algorithm processing module 20 does not need to be enabled for data processing. It only needs to retrieve data from the rear random access memory 40 to meet the panel self-refresh requirements, thereby fully reducing the chip power consumption. In addition, each algorithm processing module 20 is connected in parallel with the target data signal line DL and is controlled and enabled by the control module 30. The control module 30 can flexibly control the specified algorithm processing module 20 to be enabled according to the actual data processing requirements. The unnecessary algorithm processing module 20 can be controlled to be closed to avoid the display data passing through, thereby achieving the purpose of further reducing power consumption.

[0076] Please continue to see Figure 1 According to some embodiments of the present application, optionally, each of the N algorithm processing modules 20 includes an enable control terminal EN.

[0077] The control module 30 is electrically connected to the enable control terminal EN of each of the N algorithm processing modules 20. The control module 30 is configured to provide a valid level to the enable control terminal EN of the target algorithm processing module when the data interface module 10 receives display data.

[0078] According to some embodiments of the present application, the control module 30 is optionally configured to send a non-active level to the enable control terminal EN of each of the N algorithm processing modules 20 when the data interface module 10 does not receive the display data. For example, the active level is high and the non-active level is low.

[0079] According to some embodiments of the present application, optionally, the control module 30 is used to provide a non-valid level to the enable control terminal EN of the algorithm processing module 20 other than the target algorithm processing module among the N algorithm processing modules 20 when the data interface module 10 receives display data.

[0080] See Figure 2 , Figure 2 This is a schematic diagram of the structure of another driver chip provided in an embodiment of the present application. Figure 2 As shown, according to some embodiments of the present application, optionally, the driver chip 100 further includes N first switch modules 101 corresponding one-to-one to the N algorithm processing modules 20 .

[0081] The control end of the first switch module 101 is electrically connected to the control module 30 , the first end of the first switch module 101 is electrically connected to the target data signal line DL, and the second end of the first switch module 101 is electrically connected to the data input end IN of the corresponding algorithm processing module 20 .

[0082] The algorithm processing module 20 is configured to receive display data and adjust the display data when the control module 30 provides a conduction level to the control terminal of the first switch module 101 .

[0083] According to some embodiments of the present application, optionally, the control module 30 is used to provide a cutoff level to the control end of the first switch module 101 corresponding to each of the N algorithm processing modules 20 when the data interface module 10 does not receive display data.

[0084] The algorithm processing module 20 is configured to be turned off when the control module 30 provides a cutoff level to the control terminal of the corresponding first switch module 101 , so that the algorithm processing module 20 is in a disabled state.

[0085] More specifically, Figure 3 This is a schematic diagram of the structure of another driver chip provided in the embodiment of the present application. Figure 3 As shown, according to some embodiments of the present application, optionally, in order to more reasonably implement data reception control of the corresponding algorithm processing module 20 through the above-mentioned first switch module 101, the above-mentioned first switch module 101 may specifically include a first transistor.

[0086] The control end of the first transistor is electrically connected to the control module 30 , the first end of the first transistor is electrically connected to the target data signal line DL, and the second end of the first transistor is electrically connected to the data input end IN of the corresponding algorithm processing module 20 .

[0087] Accordingly, the algorithm processing module 20 is configured to receive the display data and adjust the display data when the control module 30 provides a conduction level to the control terminal of the first transistor.

[0088] The transistor type of the above-mentioned first transistor is, for example, a bipolar junction transistor (BJT), a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT), etc., which is not strictly limited in this embodiment.

[0089] See below Figure 4 , Figure 4 This is a schematic diagram of the structure of another driver chip provided in the embodiment of the present application. Figure 4 As shown, according to some embodiments of the present application, optionally, the driver chip 100 further includes N second switch modules 102 corresponding one-to-one to the N algorithm processing modules 20 .

[0090] The control end of the second switch module 102 is electrically connected to the control module 30 , the first end of the second switch module 102 is electrically connected to the target data signal line DL, and the second end of the second switch module 102 is electrically connected to the data output end OUT of the corresponding algorithm processing module 20 .

[0091] The algorithm processing module 20 is configured to transmit the adjusted display data to the target data signal line DL through the second switch module 102 when the control module 30 provides a conduction level to the control terminal of the second switch module 102 .

[0092] According to some embodiments of the present application, optionally, the control module 30 is used to provide a cutoff level to the control end of the second switch module 102 corresponding to each of the N algorithm processing modules 20 when the data interface module 10 does not receive display data.

[0093] The algorithm processing module 20 is configured to be turned off when the control module 30 provides a cutoff level to the control terminal of the corresponding second switch module 102 , so that the algorithm processing module 20 is in a disabled state.

[0094] Please continue to see Figure 4More specifically, in order to more reasonably implement data transmission control of the corresponding algorithm processing module 20 through the second switch module 102, the second switch module 102 may include a second transistor M2. The second transistor M2 may be, for example, a bipolar transistor, a metal oxide semiconductor field effect transistor, etc., which is not strictly limited in this embodiment.

[0095] The control end of the second transistor M2 is electrically connected to the control module 30 , the first end of the second transistor M2 is electrically connected to the target data signal line DL, and the second end of the second transistor M2 is electrically connected to the data output end OUT of the corresponding algorithm processing module 20 .

[0096] The algorithm processing module 20 is configured to transmit the adjusted display data to the target data signal line DL through the second transistor M2 when the control module 30 provides a conduction level to the control terminal of the second transistor M2 .

[0097] According to some embodiments of the present application, optionally, in combination with actual display scenarios, more specifically, when the display panel 200 needs to update the display data of the display screen, the data interface module 10 receives the updated display data transmitted by the host.

[0098] The control module 30 can be electrically connected to the data interface module 10 and detect the data reception status of the data interface module 10. Thus, when the control module 30 detects that the data interface module 10 has received updated display data, it controls at least one of the N algorithm processing modules 20 to be enabled, so that the enabled algorithm processing module 20 adjusts at least part of the display data.

[0099] According to some embodiments of the present application, when the display data of the display screen required to be displayed by the display panel 200 is not updated, the random access memory 40 is used to provide the stored adjusted display data to the display panel 200 so that the display panel 200 maintains the target screen based on the adjusted display data.

[0100] According to some embodiments of the present application, optionally, the random access memory 40 is configured to provide the stored adjusted display data to the display panel 200 according to a self-refresh frequency of the display panel 200 .

[0101] In this embodiment, by placing the random access memory 40 behind the algorithm processing module 20, each algorithm processing module 20 can process the display data independently or collaboratively under the control of the control module 30, thereby achieving the display data transmitted by the mainboard being processed once by the designated target algorithm processing module and then stored in the random access memory 40.

[0102] In this way, under the condition that the mainboard data does not change (equivalent to the display screen content of the display panel 200 not changing), the display panel 200 can directly retrieve data from the random access memory 40 to continuously display the target screen during self-refresh. The algorithm processing module 20 does not need to repeatedly process the same display data multiple times when the mainboard data is not updated, thereby effectively achieving the purpose of reducing power consumption, which is beneficial to improving the driving competitiveness of the driver chip 100.

[0103] In addition, each algorithm processing module 20 is connected in parallel with the target data signal line DL and is controlled and enabled by the control module 30. The control module 30 can flexibly control the specified algorithm processing module 20 to be enabled according to actual data processing requirements. The unnecessary algorithm processing module 20 can be controlled to be turned off to avoid displaying data passing through, thereby effectively achieving the purpose of further reducing power consumption.

[0104] According to some embodiments of the present application, optionally, in combination with the data communication scenario in actual display technology, the data interface module 10 is a data interface that supports the mobile industry processor interface MIPI (Mobile Industry Processor Interface) or the serial peripheral interface SPI (Serial Peripheral Interface) communication protocol.

[0105] That is to say, in this embodiment, the driver chip 100 is provided with a data interface, and the data interface can communicate and transmit data with the mainboard based on the MIPI communication protocol or the SPI communication protocol, thereby effectively ensuring the reliability of display data transmission.

[0106] See below Figure 5 , Figure 5 This is a schematic diagram of the structure of another driver chip provided in the embodiment of the present application. Figure 5 As shown, in some possible embodiments, optionally, the display data includes first sub-display data and second sub-display data.

[0107] The aforementioned at least one target algorithm processing module includes a first algorithm processing module 21 and / or a second algorithm processing module 22. The first algorithm processing module 21 and the second algorithm processing module 22 can perform parallel data processing, thereby facilitating improving the algorithm processing efficiency of display data.

[0108] More specifically, the display area corresponding to the first sub-display data does not overlap with the display area corresponding to the second sub-display data. In one example, the first sub-display data may be display data corresponding to sub-pixels in the edge region of the panel, and the second sub-display data may be display data corresponding to sub-pixels in the center region excluding the edge region.

[0109] The control module 30 is configured to control the first algorithm processing module 21 and the second algorithm processing module 22 to be in an enabled state when the data interface module 10 receives display data.

[0110] The first algorithm processing module 21 can be used to adjust the first sub-display data according to the first algorithm processing rule to obtain adjusted first sub-display data. The second algorithm processing module 22 can be used to adjust the second sub-display data according to the second algorithm processing rule to obtain adjusted second sub-display data.

[0111] According to some embodiments of the present application, optionally, the first algorithm processing module 21 is further used to transmit the adjusted first sub-display data to the target data signal line DL; the second algorithm processing module 22 is further used to transmit the adjusted second sub-display data to the target data signal line DL.

[0112] It should be noted that if the adjusted first sub-display data and the adjusted second sub-display data do not require further algorithm processing, they can be directly transmitted via the target data signal line DL and stored in the random access memory 40. Conversely, if the adjusted first sub-display data and the adjusted second sub-display data do not require further algorithm processing, they can be directly transmitted via the target data signal line DL to the subsequent algorithm processing module 20.

[0113] Among them, regarding the accurate reception and transmission timing of different display data under different algorithm processing modules, the control module 30 can perform precise timing control, or it can be achieved by setting the data reading address through a program, etc., and this application does not make strict restrictions here.

[0114] More specifically, in some examples, the first algorithm processing module 21 may be configured to perform edge algorithm processing on the first sub-display data to obtain adjusted first sub-display data. The second algorithm processing module 22 may be configured to perform in-plane edge algorithm processing on the second sub-display data to obtain adjusted second sub-display data.

[0115] See below Figure 6 , Figure 6 This is a schematic diagram of the structure of another driver chip provided in the embodiment of the present application. Figure 6 As shown, in some other possible embodiments, optionally, at least one target algorithm processing module further includes a third algorithm processing module 23.

[0116] The third algorithm processing module 23 may be configured to obtain the adjusted first sub-display data and the adjusted second sub-display data, and adjust the adjusted first sub-display data and the adjusted second sub-display data according to the third algorithm processing rule to obtain adjusted display data.

[0117] According to some embodiments of the present application, the first algorithm processing module 21 is optionally configured to store the adjusted first sub-display data in a first cache (flash), and the second algorithm processing module 22 is configured to store the adjusted second sub-display data in a second cache (flash). The first cache may be a cache area set in the first algorithm processing module 21, and the second cache may be a cache area set in the second algorithm processing module 22, and this application does not impose strict limitations.

[0118] The third algorithm processing module 23 is configured to retrieve data from the first buffer and the second buffer to obtain the adjusted first sub-display data and the adjusted second sub-display data.

[0119] It should be supplemented that the third algorithm processing module 23 may be pre-configured with a related program for selectively reading the cached data in the first cache and the second cache.

[0120] According to some embodiments of the present application, optionally, the third algorithm processing module 23 is configured to perform demura on the adjusted first sub-display data and the adjusted second sub-display data.

[0121] In this embodiment, the algorithm processing module 20 connects data in serial and parallel. In the case of parallel processing that can be performed in parallel by the algorithm processing module (such as the edge algorithm and the in-plane edge algorithm, which do not affect each other and can be performed in parallel), the data that needs to be processed serially is processed serially in order. The algorithm processing modules 20 that are not needed can be controlled to be turned off, thereby realizing the on-demand activation of the corresponding algorithm processing modules 20 according to the algorithm requirements of the application. Therefore, regardless of the mode of the display panel 200, since the data stored in the random access memory 40 is all data after algorithm processing, as long as the host has no need to update the data, then when the display panel 200 self-refreshes, the algorithm modules that do not need to be activated can be bypassed each time the display panel 200 self-refreshes, thereby effectively reducing the power consumption of the driver chip 100.

[0122] In other words, by placing the RAM 40 at the end of the algorithm processing module 20, the problem of high power consumption caused by the need to fully activate the algorithm processing module 20 and perform algorithm calculations during each panel self-refresh in low-frequency modes such as AOD is avoided. Furthermore, each algorithm processing module 20 is individually electrically connected to the target data signal line DL to receive data in parallel. Multiple algorithm processing modules 20 can be activated as needed by the control module 30, and display data does not pass through unnecessary algorithm processing modules 20, further reducing chip power consumption.

[0123] See below Figure 7 , Figure 7 This is a schematic diagram of the structure of another driver chip provided in the embodiment of the present application. Figure 7 As shown, according to some embodiments of the present application, more specifically, the driver chip 100 may further include a gamma module 50 .

[0124] The data input terminal IN of the random access memory 40 is electrically connected to the target data signal line DL, the data output terminal OUT of the random access memory 40 is electrically connected to the first end of the gamma module 50, and the second end of the gamma module 50 is electrically connected to the display panel 200; the gamma module 50 stores a preset gamma curve, which can specifically be, for example, the correspondence between grayscale data and data voltage.

[0125] The gamma module 50 is used to retrieve the adjusted display data stored in the random access memory 40 , convert the adjusted display data into data voltages according to a preset gamma curve, and then send the data voltages to the display panel 200 .

[0126] According to some embodiments of the present application, optionally, the display data and the adjusted display data are grayscale data.

[0127] According to some embodiments of the present application, optionally, the display panel 200 includes a plurality of sub-pixels arranged in an array, and the adjusted display data includes grayscale values ​​of the plurality of sub-pixels;

[0128] The gamma module 50 is configured to convert the grayscale values ​​of the plurality of sub-pixels into data voltages of the plurality of sub-pixels according to a preset gamma curve, and provide the data voltages of the plurality of sub-pixels to the plurality of sub-pixels accordingly.

[0129] Based on the driver chip 100 provided in the above embodiments, the present application also provides a display panel 200, which includes the driver chip 100 provided in any of the above embodiments of the present application, or, in more scenarios, the display panel 200 is electrically connected (Bonding) to the driver chip 100 provided in any of the above embodiments of the present application.

[0130] Please refer to Figure 8 , Figure 8 A schematic structural diagram of a display panel provided in an embodiment of the present application. Figure 8 The display panel 200 provided may be AMOLED, OLED or other. Those skilled in the art should understand that in other implementations of the present application, the display panel may also be a micro light emitting diode display panel, a quantum dot display panel, etc.

[0131] Based on the display panel provided in the above embodiment, the present application also provides a display device, including the driver chip 100 provided in the above embodiment and the display panel 200 provided in the present application. Figure 9 , Figure 9 A schematic structural diagram of a display device provided in an embodiment of the present application. Figure 9 The provided display device 1000 includes the driver chip 100 provided in any of the aforementioned embodiments of the present application and the display panel 200 described in the aforementioned embodiments. Figure 9 In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It is understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the driver chip 100 and the display panel 200 provided in the embodiment of the present application. For details, please refer to the specific description of the display panel 200 in the above embodiments, and this embodiment will not be repeated here.

[0132] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other unless there is any contradiction.

[0133] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in accordance with the present application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

[0134] Those skilled in the art should understand that the above embodiments are illustrative rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to identify names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A driver chip for a display panel, characterized in that: The driving chip includes a data interface module, a control module, N algorithm processing modules, a random access memory and a data signal line, where N is a positive integer; The data interface module is electrically connected to the random access memory via the target data signal line, and the data interface module is used to receive display data transmitted by the host; A data input end of any algorithm processing module among the N algorithm processing modules is electrically connected to the target data signal line, and a data output end of any algorithm processing module among the N algorithm processing modules is electrically connected to the target data signal line; The control module is used for controlling at least one target algorithm processing module among the N algorithm processing modules to be in an enabled state when the data interface module receives the display data, so that the target algorithm processing module adjusts at least part of the display data; Any algorithm processing module among the N algorithm processing modules is used for receiving the display data and adjusting the display data when in an enabled state, and transmitting the adjusted display data to the random access memory through the target data signal line; The random access memory is used to store the adjusted display data, so that the display panel displays a target picture based on the adjusted display data.

2. The driver chip according to claim 1, characterized in that: Each of the N algorithm processing modules includes an enabling control terminal; The control module is electrically connected to the enable control terminal of each of the N algorithm processing modules respectively; The control module is used for providing a valid level to the enable control terminal of the target algorithm processing module when the data interface module receives the display data; Preferably, the control module is used for sending a non-valid level to the enable control terminal of each of the N algorithm processing modules when the data interface module does not receive the display data; Preferably, the control module is used for providing a non-valid level to the enable control terminals of the algorithm processing modules other than the target algorithm processing module among the N algorithm processing modules when the data interface module receives the display data.

3. The driver chip according to claim 1, characterized in that: The driving chip further includes N first switch modules corresponding one-to-one to the N algorithm processing modules; The control end of the first switch module is electrically connected to the control module, the first end of the first switch module is electrically connected to the target data signal line, and the second end of the first switch module is electrically connected to the corresponding data input end of the algorithm processing module; The algorithm processing module is used for receiving the display data and adjusting the display data when the control module provides a conduction level to the control end of the first switch module; Preferably, the control module is used for providing a cutoff level to the control end of the first switch module corresponding to each algorithm processing module in the N algorithm processing modules when the data interface module does not receive the display data; The algorithm processing module is used to shut down when the control module provides a cut-off level to the control end of the corresponding first switch module, so that the algorithm processing module is in a disabled state; Preferably, the first switch module comprises a first transistor; The control end of the first transistor is electrically connected to the control module, the first end of the first transistor is electrically connected to the target data signal line, and the second end of the first transistor is electrically connected to the corresponding data input end of the algorithm processing module; The algorithm processing module is used for receiving the display data and adjusting the display data when the control module provides a conduction level to the control terminal of the first transistor.

4. The driver chip according to claim 1 or 3, characterized in that: The driving chip further includes N second switch modules corresponding one-to-one to the N algorithm processing modules; The control end of the second switch module is electrically connected to the control module, the first end of the second switch module is electrically connected to the target data signal line, and the second end of the second switch module is electrically connected to the corresponding data output end of the algorithm processing module; The algorithm processing module is used for transmitting the adjusted display data to the target data signal line through the second switch module when the control module provides a conduction level to the control end of the second switch module; Preferably, the control module is used for providing a cutoff level to the control end of the second switch module corresponding to each algorithm processing module in the N algorithm processing modules when the data interface module does not receive the display data; The algorithm processing module is used to shut down when the control module provides a cut-off level to the control end of the corresponding second switch module, so that the algorithm processing module is in a disabled state; Preferably, the second switch module comprises a second transistor; The control end of the second transistor is electrically connected to the control module, the first end of the second transistor is electrically connected to the target data signal line, and the second end of the second transistor is electrically connected to the corresponding data output end of the algorithm processing module; The algorithm processing module is used for transmitting the adjusted display data to the target data signal line through the second transistor when the control module provides a conduction level to the control end of the second transistor.

5. The driver chip according to claim 1, characterized in that: In the case where the display data of the display screen required by the display panel is updated, the data interface module receives the updated display data transmitted by the host; The control module is used for controlling at least one algorithm processing module among the N algorithm processing modules to be enabled when the data interface module receives the updated display data, so that the enabled algorithm processing module adjusts at least part of the display data; Preferably, when the display data of the display picture required to be displayed by the display panel is not updated, the random access memory is used to provide the stored adjusted display data to the display panel, so that the display panel maintains the target picture based on the adjusted display data; Preferably, the random access memory is used to provide the stored adjusted display data to the display panel according to the self-refresh frequency of the display panel; Preferably, the data interface module is a data interface supporting the mobile industry processor interface MIPI or serial peripheral interface SPI communication protocol.

6. The driver chip according to claim 1, characterized in that: The display data includes first sub-display data and second sub-display data, and the at least one target algorithm processing module includes a first algorithm processing module and / or a second algorithm processing module; The control module is used for controlling the first algorithm processing module and the second algorithm processing module to be in an enabled state when the data interface module receives the display data; The first algorithm processing module is used to adjust the first sub-display data according to a first algorithm processing rule to obtain adjusted first sub-display data; the second algorithm processing module is used to adjust the second sub-display data according to a second algorithm processing rule to obtain adjusted second sub-display data; Preferably, the display area corresponding to the first sub-display data does not overlap with the display area corresponding to the second sub-display data; Preferably, the first algorithm processing module is further used to transmit the adjusted first sub-display data to the target data signal line; the second algorithm processing module is further used to transmit the adjusted second sub-display data to the target data signal line; Preferably, the first algorithm processing module is used to perform edge algorithm processing on the first sub-display data to obtain the adjusted first sub-display data; Preferably, the second algorithm processing module is used for performing in-plane edge algorithm processing on the second sub-display data to obtain the adjusted second sub-display data.

7. The driver chip according to claim 6, characterized in that: The at least one target algorithm processing module also includes a third algorithm processing module; The third algorithm processing module is used to obtain the adjusted first sub-display data and the adjusted second sub-display data, and adjust the adjusted first sub-display data and the adjusted second sub-display data according to the third algorithm processing rule to obtain the adjusted display data; Preferably, the first algorithm processing module is used to store the adjusted first sub-display data in a first cache, and the second algorithm processing module is used to store the adjusted second sub-display data in a second cache; The third algorithm processing module is used to retrieve the data in the first cache and the second cache to obtain the adjusted first sub-display data and the adjusted second sub-display data; Preferably, the third algorithm processing module is used for performing brightness compensation on the adjusted first sub-display data and the adjusted second sub-display data.

8. The driver chip according to claim 1, characterized in that: The driving chip further includes a gamma module; a data input end of the random access memory is electrically connected to the target data signal line, a data output end of the random access memory is electrically connected to a first end of the gamma module, and a second end of the gamma module is electrically connected to the display panel; The gamma module stores a preset gamma curve; The gamma module is used to retrieve the adjusted display data stored in the random access memory, convert the adjusted display data into a data voltage according to the preset gamma curve, and then send the data voltage to the display panel; Preferably, the display data and the adjusted display data are grayscale data; Preferably, the display panel comprises a plurality of sub-pixels arranged in an array, and the adjusted display data comprises grayscale values ​​of the plurality of sub-pixels; The gamma module is used for converting the grayscale values ​​of the plurality of sub-pixels into data voltages of the plurality of sub-pixels according to the preset gamma curve, and providing the data voltages of the plurality of sub-pixels to the plurality of sub-pixels accordingly.

9. A display panel, characterized in that: The display panel is electrically connected to the driving chip according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the driving chip according to any one of claims 1 to 8 and the display panel according to claim 9.

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