Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises: a substrate; a driving circuit layer, wherein the driving circuit layer is arranged on the substrate; a plurality of pixel driving circuits which are arranged in an array mode in the first direction and the second direction are formed on the driving circuit layer, each pixel driving circuit is used for being connected with at least one light-emitting element, and each pixel driving circuit comprises a driving transistor, a first light-emitting control transistor and a bias transistor; the driving circuit layer is also provided with a first power supply signal line, and the first light-emitting control transistor is connected between the first power supply signal line and the first electrode of the driving transistor; the bias transistor is connected between the first power supply signal line and the first pole of the driving transistor; the bias transistor is used for initializing the first pole of the driving transistor. The pixel density of the array substrate can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, array substrates are used more and more widely, and correspondingly, the requirements for array substrates are also getting higher and higher.

[0003] However, in the related art, the array substrate has the problem of low pixel density. Summary of the invention

[0004] The invention provides an array substrate, a display panel and a display device to improve the pixel density of the array substrate.

[0005] According to one aspect of the present invention, an array substrate is provided, characterized in that the array substrate comprises:

[0006] substrate;

[0007] A driving circuit layer, wherein the driving circuit layer is arranged on the substrate; the driving circuit layer is formed with a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, each pixel driving circuit is used to connect at least one light-emitting element, and the pixel driving circuit includes a driving transistor, a first light-emitting control transistor and a bias transistor; the driving circuit layer is also provided with a first power signal line, the first light-emitting control transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is used to initialize the first electrode of the driving transistor.

[0008] Optionally, the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the substrate, and the first power signal line is arranged in the fourth conductive layer;

[0009] Preferably, the active structure of each transistor in the pixel driving circuit is arranged in the active layer, the control electrode of each transistor is arranged in the first conductive layer, and the first electrode and the second electrode of each transistor are arranged in the third conductive layer;

[0010] Preferably, the first power signal line is a mesh structure.

[0011] Optionally, the pixel driving circuit further includes a first initialization transistor and a second light emitting control transistor; the pixel driving circuit is correspondingly provided with an enable signal line, a first scanning signal line and a first initialization signal line extending along the first direction and arranged along the second direction;

[0012] The second light-emitting control transistor is connected between the second electrode of the driving transistor and the corresponding light-emitting element; the first initialization transistor is connected between the corresponding light-emitting element and the first initialization signal line;

[0013] The control electrode of the first light emitting control transistor and the control electrode of the second light emitting control transistor are electrically connected to the enable signal line; the control electrode of the first initialization transistor and the control electrode of the bias transistor are electrically connected to the first scanning signal line;

[0014] Preferably, the channel structure of the first light emission control transistor and the channel structure of the first initialization transistor are collinear and both extend along the second direction;

[0015] Preferably, along the first direction, the channel structure of the bias transistor is located between the channel structure of the first light emission control transistor and the channel structure of the second light emission control transistor; along the second direction, the channel structure of the bias transistor is located between the enable signal line and the first initialization signal line.

[0016] Optionally, the first electrode of the bias transistor is electrically connected to the first electrode of the drive transistor, and the second electrode of the bias transistor is electrically connected to the first power signal line; the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the drive transistor, and the second electrode of the first light-emitting control transistor is electrically connected to the first power signal line;

[0017] Preferably, the channel structure of the driving transistor, the channel structure of the first light emission control transistor and the channel structure of the second light emission control transistor are an integrated structure; the channel structure of the bias transistor is independent of the channel structure of the driving transistor;

[0018] Preferably, along the second direction, the first electrode of the bias transistor is located between the second electrode of the bias transistor and the channel structure of the driving transistor; along the second direction, the first electrode of the first light emission control transistor is located between the second electrode of the first light emission control transistor and the channel structure of the driving transistor;

[0019] Preferably, the pixel driving circuit includes a first connection structure and a second connection structure; the first electrode of the bias transistor is electrically connected to the first electrode of the first light emission control transistor through the first connection structure; the second electrode of the bias transistor is electrically connected to the second electrode of the first light emission control transistor through the second connection structure;

[0020] Preferably, the first connection structure and the second connection structure are in the same layer;

[0021] Preferably, the first electrode of the first initialization transistor is used to connect the light emitting element, and the second electrode of the first initialization transistor is electrically connected to the first initialization signal line; along the second direction, the first electrode of the first initialization transistor is located between the second electrode of the first initialization transistor and the channel structure of the driving transistor;

[0022] Preferably, along the second direction, the channel structure of the bias transistor is located between the channel structure of the first initialization transistor and the channel structure of the driving transistor.

[0023] Optionally, the plurality of pixel driving circuits include a plurality of pixel driving circuit groups arranged in an array along a first direction and a second direction, each of the pixel driving circuit groups includes two pixel driving circuits arranged along the first direction; the pixel driving circuits in the pixel driving circuit group are mirror images of each other;

[0024] Preferably, the pixel driving circuit comprises a storage capacitor, a first electrode of the storage capacitor is electrically connected to the first power signal line, and a second electrode of the storage capacitor is electrically connected to the control electrode of the driving transistor; in the pixel driving circuit group, the first electrode of the storage capacitor in each of the pixel driving circuits is electrically connected to the first power signal line through a common via hole;

[0025] Preferably, along the first direction, the shared via hole is located at the center of the pixel driving circuit group;

[0026] Preferably, the portion of the first power signal line corresponding to the pixel driving circuit includes a first portion extending along the second direction, a second portion extending along the first direction, and a third portion; wherein the second portion and the third portion are respectively connected to two ends of the first portion; along the thickness direction of the array substrate, the orthographic projection of the second electrode of the bias transistor on the substrate is located within the orthographic projection of the first portion on the substrate;

[0027] Preferably, the pixel driving circuit includes a second connection structure; the second electrode of the bias transistor is electrically connected to the second electrode of the first light-emitting control transistor through the second connection structure; along the first direction, the second connection structures of two adjacent pixel driving circuits located in different pixel driving circuit groups are connected.

[0028] Optionally, the pixel driving circuit includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the first power signal line, and a second electrode of the storage capacitor is electrically connected to a control electrode of the driving transistor; the first electrode of the storage capacitor and the first initialization signal line are arranged in different layers;

[0029] Preferably, the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the substrate, the first electrode of the storage capacitor is arranged in the second conductive layer, and the first initialization signal line is arranged in the third conductive layer.

[0030] Optionally, the pixel driving circuit further includes a second initialization transistor, and the driving circuit layer is further provided with a second initialization signal line extending along the first direction and arranged along the second direction; a first electrode of the second initialization transistor is electrically connected to the second initialization signal line, a second electrode of the second initialization transistor is electrically connected to a control electrode of the driving transistor, and a control electrode of the second initialization transistor is electrically connected to the second scanning signal line;

[0031] Preferably, along the second direction, the second initialization signal line is located between the second scanning signal line and the channel structure of the driving transistor;

[0032] Preferably, the pixel driving circuit further comprises a threshold compensation transistor and a data writing transistor; the driving circuit layer is further provided with a data line extending along the second direction and a third scanning signal line extending along the first direction; the first electrode of the data writing transistor is electrically connected to the data line, the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the control electrode of the data writing transistor is electrically connected to the third scanning signal line; the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the threshold compensation transistor is electrically connected to the control electrode of the driving transistor, and the control electrode of the threshold compensation transistor is electrically connected to the third scanning signal line;

[0033] Preferably, along the first direction, the first electrode of the second initialization transistor is arranged between the control electrode of the driving transistor and the second electrode of the second initialization transistor;

[0034] Preferably, the pixel driving circuit comprises a fourth connection structure extending along the second direction, and the first electrode of the second initialization transistor is electrically connected to the second initialization signal line through the fourth connection structure;

[0035] Preferably, the threshold compensation transistor is a dual-gate transistor;

[0036] Preferably, the pixel driving circuit is correspondingly provided with a shielding structure, and along the thickness direction of the array substrate, the orthographic projection of the dual-gate node of the dual-gate transistor on the substrate is located within the orthographic projection of the shielding structure on the substrate.

[0037] Optionally, the channel structure of the driving transistor is linear.

[0038] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate as described above.

[0039] According to another aspect of the present invention, a display device is provided, comprising the display panel as described above.

[0040] The technical solution of the embodiment of the present invention adopts an array substrate including a substrate; a driving circuit layer, the driving circuit layer is arranged on the substrate; the driving circuit layer is formed with a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, each pixel driving circuit is used to connect at least one light-emitting element, and the pixel driving circuit includes a driving transistor, a first light-emitting control transistor and a bias transistor; the driving circuit layer is also provided with a first power signal line, the first light-emitting control transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is used to initialize the first electrode of the driving transistor. The bias transistor is connected to the first power signal line, and there is no need to set an additional signal line for the bias transistor, thereby reducing the number of signal lines in the array substrate, which is conducive to improving the pixel density.

[0041] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram of a film layer structure of an array substrate provided in an embodiment of the present invention;

[0044] Figure 2 for Figure 1 A partial enlarged view of

[0045] Figure 3 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention;

[0046] Figure 4 A cross-sectional view of an array substrate provided by an embodiment of the present invention;

[0047] Figure 5 for Figure 2 Schematic diagram of the structure of the active layer;

[0048] Figure 6 for Figure 2 A schematic structural diagram of the first conductive layer;

[0049] Figure 7 for Figure 2 A schematic structural diagram of the second conductive layer;

[0050] Figure 8 for Figure 2 A schematic diagram of the structure of the third conductive layer;

[0051] Fig. 9 for Figure 2 A schematic structural diagram of the fourth conductive layer;

[0052] Fig.10 for Figure 2 A schematic diagram of the structure of the active layer, the third conductive layer and the inorganic holes;

[0053] Fig.11 for Figure 2 Schematic diagram of the structure of the third conductive layer, the fourth conductive layer and the organic hole;

[0054] Fig.12 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] Just as the array substrate of the related art has the problem of low pixel density, the inventors have found through careful research that the reason for this technical problem is that: a plurality of pixel driving circuits are provided in the array substrate. In order to reduce the leakage of the pixel driving circuit, more transistors and signal lines need to be provided, which makes the area required for the pixel driving circuit larger, limiting the improvement of the pixel density.

[0058] In view of the above technical problems, the present invention proposes the following solutions:

[0059] Figure 1 A schematic diagram of a film layer structure of an array substrate provided in an embodiment of the present invention, Figure 2 for Figure 1 A partial enlarged view of Figure 3 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention, Figure 4 A cross-sectional view of an array substrate provided by an embodiment of the present invention, referring to Figures 1 to 4 The array substrate includes a substrate Sub; a driving circuit layer, which is disposed on the substrate Sub; the driving circuit layer is formed with a plurality of pixel driving circuits arranged in an array along a first direction X and a second direction Y, each pixel driving circuit is used to connect at least one light-emitting element, and the pixel driving circuit includes a driving transistor T1, a first light-emitting control transistor T5 and a bias transistor T8; the driving circuit layer is also provided with a first power signal line ELVDD, the first light-emitting control transistor T5 is connected between the first power signal line ELVDD and the first electrode of the driving transistor T1; the bias transistor T8 is connected between the first power signal line ELVDD and the first electrode of the driving transistor T1; the bias transistor T8 is used to initialize the first electrode of the driving transistor T1.

[0060] Specifically, the light emitting element 11 can be manufactured on the array substrate to form a display panel. The substrate Sub of the array substrate can be a rigid substrate made of materials such as glass, or a flexible substrate made of materials such as polyimide. The driving circuit layer is formed on the substrate Sub. Of course, a buffer layer can also be provided between the driving circuit layer and the substrate Sub to reduce the difficulty of preparing the driving circuit layer and improve the yield of the driving circuit layer.

[0061] A plurality of pixel driving circuits arranged in an array are provided in the driving circuit layer, wherein the first direction X intersects with the second direction Y. For example, the first direction X may be a row direction, and the second direction Y may be a column direction; of course, the first direction X may be a column direction, and the second direction Y may be a row direction. The pixel driving circuit is used to drive the light-emitting element, and the light-emitting element 11 may be an OLED (Organic Light Emitting Diode), a Micro-LED (Micro Light Emitting Diode), or a mini-LED (mini Light Emitting Diode), etc.

[0062] The driving transistor T1 in the pixel driving circuit is used to generate a driving current according to the data voltage of its control electrode, so as to drive the corresponding light-emitting element to emit light. The first light-emitting control transistor T5 is used to be turned on during the light-emitting stage, so as to provide a loop for the driving current generated by the driving transistor T1, so that the driving current is transmitted to the light-emitting element. In order to reduce leakage, the first electrode of the driving transistor T1 is initialized by the bias transistor T8 after the data writing stage and before the light-emitting stage. In the related art, the bias transistor T8 and the first initialization transistor T5 are connected to different signal lines, so that the number of signal lines in the array substrate is large, thereby limiting the increase in pixel density. In this embodiment, the bias transistor T8 and the first light-emitting control transistor T5 are both connected to the first power signal line ELVDD, and there is no need to set an additional signal line for the bias transistor T8, so that the number of signal lines in the array substrate can be reduced, thereby improving the pixel density. It should be noted that the first power signal line ELVDD can be a power signal line that provides a high-level signal.

[0063] The technical solution of this embodiment adopts an array substrate including a substrate; a driving circuit layer, the driving circuit layer is arranged on the substrate; the driving circuit layer is formed with a plurality of pixel driving circuits arranged in an array along the first direction and the second direction, each pixel driving circuit is used to connect at least one light-emitting element, and the pixel driving circuit includes a driving transistor, a first light-emitting control transistor and a bias transistor; the driving circuit layer is also provided with a first power signal line, the first light-emitting control transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is used to initialize the first electrode of the driving transistor. The bias transistor is connected to the first power signal line, and there is no need to set an additional signal line for the bias transistor, thereby reducing the number of signal lines in the array substrate, which is conducive to improving the pixel density.

[0064] For the convenience of subsequent description, the specific structure, working principle and film structure of the pixel driving circuit are first introduced as a whole. Of course, the pixel driving circuit described below is only an example, and the pixel driving circuit can have various variations.

[0065] like Figure 3 As shown, the pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a storage capacitor Cst, a second initialization transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a first initialization transistor T7 and a bias transistor T8. The first electrode of the bias transistor T8 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the bias transistor T8 is electrically connected to the first power signal line ELVDD, and the control electrode of the bias transistor T8 is electrically connected to the first scanning signal line SP3; the first electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the first light-emitting control transistor T5 is electrically connected to the first power signal line ELVDD, and the control electrode of the first light-emitting control transistor T5 is electrically connected to the enable signal line EM; the second light-emitting control transistor T6 is connected between the second electrode of the driving transistor T1 and the corresponding light-emitting element 11, and specifically, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light-emitting control transistor T6 is electrically connected to the anode of the corresponding light-emitting element 11, and the control electrode of the second light-emitting control transistor T6 is electrically connected to the enable signal line EM; the first electrode of the data writing transistor T2 is electrically connected to the data line Data, the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, and the control electrode of the data writing transistor T2 is electrically connected to the third scanning signal line SP2; The first electrode of the threshold compensation transistor T3 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the control electrode of the driving transistor T1, and the control electrode of the threshold compensation transistor T3 is electrically connected to the third scanning signal line SP3; the first electrode of the storage capacitor Cst is electrically connected to the first power signal line ELVDD, and the second electrode of the storage capacitor Cst is electrically connected to the control electrode of the driving transistor T1; the first initialization transistor T7 is connected between the corresponding light-emitting element 11 and the first initialization signal line Vref2, specifically, the first electrode of the first initialization transistor T7 is connected to the light-emitting element 11, the second electrode of the first initialization transistor T7 is electrically connected to the first initialization signal line Vref2, and the control electrode of the first initialization transistor T7 is electrically connected to the first scanning signal line SP3; the first electrode of the second initialization transistor T4 is electrically connected to the second initialization signal line Vref1, the second electrode of the second initialization transistor T4 is electrically connected to the control electrode of the driving transistor T1, and the control electrode of the second initialization transistor T4 is electrically connected to the second scanning signal line SP1; the cathode of the light-emitting element 11 is electrically connected to the second power signal line ELVSS.

[0066] The operation process of the pixel driving circuit may include a first initialization phase, a data writing phase, a second initialization phase and a light emitting phase;

[0067] In the first initialization stage, the second scanning signal line SP1 controls the second initialization transistor T4 to be turned on, and the second initialization signal line Vref1 initializes the voltage of the control electrode of the driving transistor T1.

[0068] In the data writing stage, the third scanning signal line SP2 controls the threshold compensation transistor T3 and the data writing transistor T2 to be turned on; the data voltage on the data line Data is written into the control electrode of the driving transistor T1 through the data writing transistor T2 and the threshold compensation transistor T3, and the threshold compensation process of the driving transistor T1 is completed in this stage.

[0069] In the second initialization stage, the first scanning signal line SP3 controls the bias transistor T8 and the first initialization transistor T7 to be turned on, thereby initializing the first electrode of the driving transistor T1 to improve leakage, and initializing the anode of the light emitting element 11 to improve the display unevenness.

[0070] Optionally, the driving circuit layer includes an active layer Act, a first conductive layer M1, a second conductive layer M2, a third conductive layer SD1 and a fourth conductive layer SD4 stacked in sequence; a gate insulating layer is also provided between the active layer Act and the first conductive layer M1; an interlayer insulating layer is also provided between the first conductive layer M1 and the second conductive layer M2; an inorganic layer is also provided between the second conductive layer M2 and the third conductive layer SD1, and an organic layer is also provided between the third conductive layer SD1 and the fourth conductive layer SD2. The active layer Act is used to set the active structure of each transistor in the pixel driving circuit, the first conductive layer M1 is used to set the control electrode of each transistor and the second electrode of the storage capacitor Cst, the second conductive layer M2 is used to set the first electrode of the storage capacitor Cst, and the third conductive layer SD1 is used to set the first electrode and the second electrode of each transistor. Of course, it should be noted that one of the first electrode and the second electrode of the transistor is a source electrode and the other is a drain electrode; the control electrode of the transistor is a gate electrode. The film layer where each signal line corresponding to the pixel driving circuit is located will be described later.

[0071] Optionally, the first power signal line ELVDD is a mesh structure.

[0072] Specifically, the first power signal line ELVDD may be disposed in the fourth conductive layer SD2 . The first power signal line ELVDD is a mesh structure, which may reduce the impedance of the first power signal line ELVDD, thereby reducing the power consumption of the array substrate.

[0073] Optionally, Figure 5 for Figure 2The schematic diagram of the active layer structure is shown in Figure 2. Figure 6 for Figure 2 Schematic diagram of the structure of the first conductive layer, Figure 7 for Figure 2 Schematic diagram of the structure of the second conductive layer, Figure 8 for Figure 2 Schematic diagram of the structure of the third conductive layer, Fig. 9 for Figure 2 Schematic diagram of the structure of the fourth conductive layer, Fig.10 for Figure 2 A schematic diagram of the structure of the active layer, the third conductive layer and the inorganic holes; Fig.11 for Figure 2 Schematic diagram of the structure of the third conductive layer, the fourth conductive layer and the organic hole; reference Figures 1 to 11 Each row of pixel driving circuit pairs of the array substrate is provided with an enable signal line EM, a first scanning signal line SP3 and a first initialization signal line Vref2 extending along the row direction and arranged along the column direction.

[0074] Specifically, each row of pixel driving circuits is correspondingly provided with an enable signal line EM, a first scanning signal line SP3 and a first initialization signal line Vref2. That is to say, the pixel driving circuits in the same row are connected to the same enable signal line EM, the same first scanning signal line SP3, and the same first initialization signal line Vref2. The enable signal line EM and the first scanning signal line SP3 can be provided in the first conductive layer M1 to facilitate electrical connection with the control electrodes of the corresponding transistors.

[0075] Optionally, the channel structure of the first light emission control transistor T5 and the channel structure of the first initialization transistor T7 are collinear and both extend along the second direction Y.

[0076] Optionally, along the first direction X, the channel structure of the bias transistor T8 is located between the channel structure of the first emission control transistor T5 and the channel structure of the second emission control transistor T6; along the second direction Y, the channel structure of the bias transistor T8 is located between the enable signal line EM and the first initialization signal line Vref2.

[0077] Specifically, in the pixel driving circuit, along the row direction, the first light emitting control transistor T5 and the first initialization transistor T7 are located at one edge of the area where the pixel driving circuit is located. And along the column direction, a column of pixel driving circuits is connected to a data line Data, and the data line Data is correspondingly arranged at another edge of the pixel driving circuit along the row direction. Figure 2As shown, for the pixel driving circuit, in the area defined by the data line Data, the enable signal line EM, the first initialization signal line Vref2 and the straight line where the channel structure of the second light emitting control transistor T6 is located, this position has more space. In this embodiment, the channel structure of the bias transistor T8 is arranged at this position, and compared with the pixel driving circuit without the bias transistor T8, the space occupied by the pixel driving circuit will not become too large. In other words, by arranging the bias transistor T8 at this position, the space utilization rate of the pixel driving circuit is higher, the structure is more compact, and it is more conducive to improving the pixel density of the array substrate.

[0078] Optionally, refer to Figure 2 and Figure 5 The channel structure of the driving transistor T1, the channel structure of the first light emission control transistor T5 and the channel structure of the second light emission control transistor T6 are an integrated structure; the channel structure of the bias transistor T8 is independent of the channel structure of the driving transistor T1.

[0079] Specifically, along the column direction, the first electrode of the first light-emitting control transistor T5 is arranged between the second electrode of the first light-emitting control transistor T5 and the channel structure of the driving transistor. The enable signal line EM and the first scanning signal line SP3 both extend along the row direction, and the channel structure of the bias transistor T8 needs to overlap with the first scanning signal line SP3. In this embodiment, the channel structure of the bias transistor T8 is independently arranged, so that the enable signal line EM does not need to overlap with the channel structure of the bias transistor T8, and no parasitic transistor is generated, thereby improving the stability of the operation of the pixel driving circuit. It should be noted that the channel structure described herein is a portion of the corresponding transistor that is located in the active layer and is used to form a channel. In addition to the channel structure of each transistor, the active layer also includes doped portions on both sides of the channel structure, and a connecting portion used as a conductor, etc.

[0080] Optionally, along the second direction Y, the first electrode of the bias transistor T8 is located between the second electrode of the bias transistor T8 and the channel structure of the driving transistor T1. This arrangement makes the first electrode of the bias transistor T8 closer to the first electrode of the driving transistor T1, which is more convenient for setting the connection line between the bias transistor T8 and the driving transistor T1, that is, the length of the wiring can be reduced, thereby further improving the pixel density.

[0081] Optionally, refer to Figure 2 and Figure 8The pixel driving circuit includes a first connection structure L1 and a second connection structure L2; a first electrode of the bias transistor T8 is electrically connected to a first electrode of the first light-emitting control transistor T5 through the first connection structure L1; a second electrode of the bias transistor T8 is electrically connected to a second electrode of the first light-emitting control transistor T5 through the second connection structure L2. The first connection structure L1 and the second connection structure L2 can both be in a zigzag shape, and the first connection structure L1 is L-shaped, and the second connection structure L2 is Z-shaped. The first connection structure L1 and the second connection structure L2 can be arranged in the same layer, such as both being arranged in the third conductive layer SD1.

[0082] Optionally, refer to Figure 2 and Figure 8 , along the second direction Y, the second electrode of the first initialization transistor T7 is located between the second electrode of the first initialization transistor T7 and the channel structure of the driving transistor T1. Along the second direction Y, the channel structure of the bias transistor T8 is located between the channel structure of the first initialization transistor T7 and the channel structure of the driving transistor T1.

[0083] Specifically, the first initialization transistor T7 needs to be electrically connected to the first initialization signal line Vref2, while the bias transistor T8 does not need to be electrically connected to the first initialization signal line Vref2. Therefore, the configuration of this embodiment can avoid the channel structure of the bias transistor T8 from overlapping with the first initialization signal line Vref2, and can also make the structure of the pixel driving circuit more compact. Figure 2 As shown, the first scanning signal line SP3 may be a "X"-shaped structure.

[0084] Optionally, refer to Figure 1 The plurality of pixel driving circuits include a plurality of pixel driving circuit groups PX arranged in an array along a first direction X and a second direction Y, each pixel driving circuit group PX includes two pixel driving circuits arranged along the first direction; the pixel driving circuits in the pixel driving circuit group are mirror images of each other.

[0085] Specifically, for the convenience of distinction, the two pixel driving circuits in the pixel driving circuit group PX are defined as a first pixel driving circuit PX1 and a second pixel driving circuit PX2, respectively. The first pixel driving circuit PX1 and the second pixel driving circuit PX are mirror images of each other, that is, the two pixel driving circuits are symmetrical along the center line. In this way, the first pixel driving circuit PX1 and the second pixel driving circuit PX2 can share part of the structure, thereby reducing the area required for the pixel driving circuit group PX and further improving the pixel density of the array substrate.

[0086] Optionally, refer to Figure 2 , Figure 7 , Figure 8 and Fig.11, in the pixel driving circuit group, the first pole Cst1 of each storage capacitor Cst is electrically connected to the first power signal line ELVDD through a common via.

[0087] Specifically, in the same pixel driving circuit group, the first poles Cst1 of two storage capacitors Cst are of an integral structure and are electrically connected to the first power signal line ELVDD through a common via, which can reduce the number of vias in the array substrate, thereby further improving the pixel density of the array substrate.

[0088] Optionally, the above-mentioned common via may include a first inorganic via H1, the first inorganic via H1 connects the first pole of the storage capacitor Cst to the third connection structure L3, and the third connection structure L3 is disposed on the third conductive layer SD1. The first organic via H2 connects the third connection structure L3 to the first power signal line ELVDD.

[0089] Optionally, the above-mentioned common via is located at the center of the pixel driving circuit group PX. With this setting, the lengths of the connection lines between the first power signal line ELVDD and each storage capacitor Cst are close, which is beneficial to improving the display uniformity.

[0090] Optionally, refer to Fig. 9 , the part of the first power signal line ELVDD corresponding to the pixel driving circuit includes a first part 21 extending along the second direction Y, a second part 22 extending along the first direction X, and a third part 23; wherein, the second part 22 and the third part 23 are respectively connected to both ends of the first part 21; along the thickness direction of the array substrate, the positive projection of the second pole of the bias transistor T8 on the substrate is located within the positive projection of the first part 21 on the substrate.

[0091] Specifically, in this embodiment, the first part 21, the second part 22, and the third part 23 form a "匚"-shaped structure, so that the first part 21 overlaps with the second pole of the bias transistor T8. The part of the first power signal line ELVDD corresponding to the pixel driving circuit group is also an axisymmetric structure. The second parts 22 corresponding to the same pixel driving circuit group are connected into an integral structure, and the first inorganic via overlaps with this integral structure; the third parts 23 corresponding to the same pixel driving circuit group are connected into an integral structure. The first parts, the second parts, and the third parts in the pixel driving circuit group form a "口"-shaped structure. The part of the first power signal line ELVDD corresponding to the pixel driving circuit further includes a fourth part 24, and the fourth part 24 extends along the second direction Y and is used to connect the "口"-shaped structures adjacent to it along the second direction.

[0092] Optionally, the second connection structures L2 of two adjacent pixel driving circuits located in different pixel driving circuit groups are connected along the first direction X. By connecting the corresponding second connection structures L2, the first power signal lines ELVDD are connected into a mesh structure as a whole.

[0093] Optionally, refer to Figure 2 , Figure 7 and Figure 8 The first electrode Cst1 of the storage capacitor Cst is disposed at a different layer from the first initialization signal line Vref2.

[0094] Specifically, in the related art, the first electrode of the storage capacitor Cst and the first initialization signal line are arranged in the same layer. Since the first electrode of the storage capacitor Cst has a larger area, in order to reduce interference, the distance between the first initialization signal line and the first electrode of the storage capacitor needs to be set farther, which also leads to a larger area for the pixel driving circuit. In this embodiment, the first initialization signal line Vref1 and the first electrode Cst1 of the storage capacitor Cst are in different layers. Along the second direction Y, the distance between the first initialization signal line Vref1 and the storage capacitor Cst1 can be set closer, thereby further reducing the area of ​​the pixel driving circuit.

[0095] Optionally, the first initialization signal line Vref2 is disposed in the third conductive layer SD1. The third conductive layer SD1 may be a laminated metal structure, which may reduce the impedance of the first initialization signal line Vref2, thereby reducing the voltage drop and improving display uniformity. The laminated metal structure may be a TiAlTi structure.

[0096] Optionally, the second initialization signal line Vref1 is disposed in the third conductive layer SD1, which can reduce the impedance of the second initialization signal line Vref1, thereby reducing the voltage drop and improving the display uniformity.

[0097] Optionally, refer to Figure 2 , the second initialization signal line Vref1 is located between the second scanning signal line SP1 and the channel structure of the driving transistor T1.

[0098] Optionally, along the first direction, the first electrode of the second initialization transistor T4 is arranged between the control electrode of the driving transistor T1 and the second electrode of the second initialization transistor T4. This arrangement makes the distance between the control electrode of the driving transistor T1 and the data line Data longer, which can reduce signal crosstalk.

[0099] Optionally, refer to Figure 2 and Figure 8The pixel driving circuit further includes a fourth connection structure L4 extending along the second direction Y, and the first electrode of the second initialization transistor T4 is connected to the second initialization signal line Vref1 through the fourth connection structure L4. Along the first direction X, the fourth connection structure L4 is arranged between the data line Data and the control electrode of the driving transistor T1, which is equivalent to arranging a shielding structure with a fixed potential between the data line Data and the control electrode of the driving transistor T1, thereby reducing interference between the two.

[0100] Optionally, the fourth connection structure L4 and the second initialization signal line Vref1 are an integrated structure.

[0101] Optionally, the threshold compensation transistor T3 is a dual-gate transistor, so that leakage current can be reduced.

[0102] Optionally, refer to Figure 2 and Figure 7 The pixel driving circuit is correspondingly provided with a shielding structure L5. Along the thickness direction of the array substrate, the orthographic projection of the dual-gate node of the dual-gate transistor on the substrate is located within the orthographic projection of the shielding structure L5 on the substrate.

[0103] Specifically, the shielding structure L5 can be disposed on the second conductive layer M2 and connected to the second initialization signal line Vref1 through an inorganic hole. The risk of interference of the signal on the double gate node can be reduced by the shielding structure L5. The shielding structure L5 can be disposed in the central area of ​​the pixel driving circuit group along the first direction.

[0104] Optionally, refer to Figure 5 , the channel structure L6 of the driving transistor T1 is in a straight line shape. The channel structure of the driving transistor T1 is the area where the active layer overlaps with the second electrode Cst2 of the storage capacitor Cst. The channel structure L6 is set as a straight line. Compared with the "J"-shaped design in the related art, the area occupied by the channel structure L6 in the second direction Y can be reduced, that is, the area of ​​the pixel driving circuit can be reduced.

[0105] The embodiment of the present invention further provides a display panel, the display panel includes the array substrate provided by any embodiment of the present invention, and the display panel also includes a light emitting element. Since the display panel provided by the embodiment of the present invention includes the array substrate provided by any embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0106] The embodiment of the present invention further provides a display device, such as Fig.12 As shown, Fig.12A schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device includes a display panel provided in an embodiment of the present invention. The display device may be a mobile phone, a tablet computer, an MP3, an MP4, a videophone, a personal digital assistant, a smart watch, a smart helmet or other wearable device. Since it includes the display panel provided in an embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0107] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0108] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A driving circuit layer, wherein the driving circuit layer is arranged on the substrate; the driving circuit layer is formed with a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, each pixel driving circuit is used to connect at least one light-emitting element, and the pixel driving circuit includes a driving transistor, a first light-emitting control transistor and a bias transistor; the driving circuit layer is also provided with a first power signal line, the first light-emitting control transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is connected between the first power signal line and the first electrode of the driving transistor; the bias transistor is used to initialize the first electrode of the driving transistor.

2. The array substrate according to claim 1, characterized in that: The driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the substrate, and the first power signal line is arranged in the fourth conductive layer; Preferably, the active structure of each transistor in the pixel driving circuit is arranged in the active layer, the control electrode of each transistor is arranged in the first conductive layer, and the first electrode and the second electrode of each transistor are arranged in the third conductive layer; Preferably, the first power signal line is a mesh structure.

3. The array substrate according to claim 1, characterized in that: The pixel driving circuit further includes a first initialization transistor and a second light emitting control transistor; the pixel driving circuit is correspondingly provided with an enable signal line, a first scanning signal line and a first initialization signal line extending along the first direction and arranged along the second direction; The second light-emitting control transistor is connected between the second electrode of the driving transistor and the corresponding light-emitting element; the first initialization transistor is connected between the corresponding light-emitting element and the first initialization signal line; The control electrode of the first light emitting control transistor and the control electrode of the second light emitting control transistor are electrically connected to the enable signal line; the control electrode of the first initialization transistor and the control electrode of the bias transistor are electrically connected to the first scanning signal line; Preferably, the channel structure of the first light emission control transistor and the channel structure of the first initialization transistor are collinear and both extend along the second direction; Preferably, along the first direction, the channel structure of the bias transistor is located between the channel structure of the first light emission control transistor and the channel structure of the second light emission control transistor; along the second direction, the channel structure of the bias transistor is located between the enable signal line and the first initialization signal line.

4. The array substrate according to claim 3, characterized in that: The first electrode of the bias transistor is electrically connected to the first electrode of the drive transistor, and the second electrode of the bias transistor is electrically connected to the first power signal line; the first electrode of the first light emission control transistor is electrically connected to the first electrode of the drive transistor, and the second electrode of the first light emission control transistor is electrically connected to the first power signal line; Preferably, the channel structure of the driving transistor, the channel structure of the first light emission control transistor and the channel structure of the second light emission control transistor are an integrated structure; the channel structure of the bias transistor is independent of the channel structure of the driving transistor; Preferably, along the second direction, the first electrode of the bias transistor is located between the second electrode of the bias transistor and the channel structure of the driving transistor; along the second direction, the first electrode of the first light emission control transistor is located between the second electrode of the first light emission control transistor and the channel structure of the driving transistor; Preferably, the pixel driving circuit includes a first connection structure and a second connection structure; the first electrode of the bias transistor is electrically connected to the first electrode of the first light emission control transistor through the first connection structure; the second electrode of the bias transistor is electrically connected to the second electrode of the first light emission control transistor through the second connection structure; Preferably, the first connection structure and the second connection structure are in the same layer; Preferably, the first electrode of the first initialization transistor is used to connect the light emitting element, and the second electrode of the first initialization transistor is electrically connected to the first initialization signal line; along the second direction, the first electrode of the first initialization transistor is located between the second electrode of the first initialization transistor and the channel structure of the driving transistor; Preferably, along the second direction, the channel structure of the bias transistor is located between the channel structure of the first initialization transistor and the channel structure of the driving transistor.

5. The array substrate according to claim 4, characterized in that: The plurality of pixel driving circuits include a plurality of pixel driving circuit groups arranged in an array along a first direction and a second direction, each of the pixel driving circuit groups includes two pixel driving circuits arranged along the first direction; the pixel driving circuits in the pixel driving circuit group are mirror images of each other; Preferably, the pixel driving circuit comprises a storage capacitor, a first electrode of the storage capacitor is electrically connected to the first power signal line, and a second electrode of the storage capacitor is electrically connected to the control electrode of the driving transistor; In the pixel driving circuit group, the first electrode of the storage capacitor in each of the pixel driving circuits is electrically connected to the first power signal line through a common via hole; Preferably, along the first direction, the shared via hole is located at the center of the pixel driving circuit group; Preferably, the portion of the first power signal line corresponding to the pixel driving circuit includes a first portion extending along the second direction, a second portion extending along the first direction, and a third portion; wherein the second portion and the third portion are respectively connected to two ends of the first portion; along the thickness direction of the array substrate, the orthographic projection of the second electrode of the bias transistor on the substrate is located within the orthographic projection of the first portion on the substrate; Preferably, the pixel driving circuit includes a second connection structure; the second electrode of the bias transistor is electrically connected to the second electrode of the first light-emitting control transistor through the second connection structure; along the first direction, the second connection structures of two adjacent pixel driving circuits located in different pixel driving circuit groups are connected.

6. The array substrate according to claim 3, characterized in that: The pixel driving circuit comprises a storage capacitor, a first electrode of the storage capacitor is electrically connected to the first power signal line, and a second electrode of the storage capacitor is electrically connected to the control electrode of the driving transistor; the first electrode of the storage capacitor is arranged at a different layer from the first initialization signal line; Preferably, the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the substrate, the first electrode of the storage capacitor is arranged in the second conductive layer, and the first initialization signal line is arranged in the third conductive layer.

7. The array substrate according to claim 1, characterized in that: The pixel driving circuit further includes a second initialization transistor, and the driving circuit layer is further provided with a second initialization signal line extending along the first direction and arranged along the second direction; the first electrode of the second initialization transistor is electrically connected to the second initialization signal line, the second electrode of the second initialization transistor is electrically connected to the control electrode of the driving transistor, and the control electrode of the second initialization transistor is electrically connected to the second scanning signal line; Preferably, along the second direction, the second initialization signal line is located between the second scanning signal line and the channel structure of the driving transistor; Preferably, the pixel driving circuit further comprises a threshold compensation transistor and a data writing transistor; the driving circuit layer is further provided with a data line extending along the second direction and a third scanning signal line extending along the first direction; the first electrode of the data writing transistor is electrically connected to the data line, the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the control electrode of the data writing transistor is electrically connected to the third scanning signal line; the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the threshold compensation transistor is electrically connected to the control electrode of the driving transistor, and the control electrode of the threshold compensation transistor is electrically connected to the third scanning signal line; Preferably, along the first direction, the first electrode of the second initialization transistor is arranged between the control electrode of the driving transistor and the second electrode of the second initialization transistor; Preferably, the pixel driving circuit comprises a fourth connection structure extending along the second direction, and the first electrode of the second initialization transistor is electrically connected to the second initialization signal line through the fourth connection structure; Preferably, the threshold compensation transistor is a dual-gate transistor; Preferably, the pixel driving circuit is correspondingly provided with a shielding structure, and along the thickness direction of the array substrate, the orthographic projection of the dual-gate node of the dual-gate transistor on the substrate is located within the orthographic projection of the shielding structure on the substrate.

8. The array substrate according to claim 1, characterized in that: The channel structure of the driving transistor is in a linear shape.

9. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9.

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