Display panel, compensation circuit and compensation method thereof, controller and display device

Abstract

The invention provides a compensation circuit of a display panel, relates to the technical field of display, and can improve the yield of display products. The display panel comprises a pixel circuit, a data signal line and a driving circuit, wherein the data signal line is used for transmitting a data signal; the compensation circuit comprises a gating sub-circuit which is electrically connected between a driving circuit and a data signal line, the gating sub-circuit comprises a first path and a second path which are connected, and the first path and the second path are both electrically connected with the data signal line; one end of the compensation signal line is electrically connected with the second path, and the other end of the compensation signal line is electrically connected with the driving circuit; the gating sub-circuit is used for controlling the first path to be switched on and controlling the second path to be switched off under the action of a compensation control signal and a data signal, so that the data signal is transmitted to the pixel circuit through the first path and / or a data signal line; or, the gating sub-circuit is used for controlling the first path to be cut off and controlling the second path to be switched on under the action of the compensation control signal and the potential on the data signal line, so that the compensation signal is transmitted to the pixel circuit through the second path.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to a compensation circuit of a display panel, a display panel, a compensation method of a display panel, a controller and a display device. Background Art

[0002] In a display panel, a driving circuit is used to transmit a driving signal and a data signal to a pixel circuit, and the pixel circuit is used to present image information corresponding to the data signal under the drive of the driving signal. In order to enhance the aesthetics of the display panel and increase the proportion of the display area, the frame of the display panel is narrowed or the film layer is stacked and thinned. However, there is a bending process in the production process of the display panel. After bending, the data signal line is prone to breakage, thereby affecting the data signal transmission and causing bright lines to appear on the display panel. Such bright line products are judged as unqualified products during testing, resulting in reduced product yield and increased cost losses.

[0003] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, a compensation circuit of a display panel is provided, wherein the display panel comprises a pixel circuit, a data signal line and a driving circuit, wherein the data signal line is electrically connected between the pixel circuit and the driving circuit, and the data signal line is used to transmit a data signal;

[0006] The compensation circuit comprises:

[0007] a gating subcircuit, the gating subcircuit being electrically connected between the driving circuit and the data signal line, the gating subcircuit comprising a first path and a second path connected to each other, the first path and the second path being both electrically connected to the data signal line;

[0008] a compensation control signal line, one end of which is electrically connected to the gating subcircuit, the other end of which is electrically connected to the driving circuit, and the compensation control signal line is used to transmit a compensation control signal output by the driving circuit;

[0009] a compensation signal line, one end of which is electrically connected to the second path, the other end of which is electrically connected to the drive circuit, and the compensation signal line is used to transmit a compensation signal output by the drive circuit;

[0010] The gating subcircuit is used for controlling the first path to be turned on and the second path to be turned off under the action of the compensation control signal and the data signal, so that the data signal is transmitted to the pixel circuit via the first path and / or the data signal line; or,

[0011] The gating subcircuit is used for controlling the first path to be cut off and the second path to be turned on under the action of the compensation control signal and the potential on the data signal line, so that the compensation signal is transmitted to the pixel circuit via the second path.

[0012] In some embodiments, the compensation signal line includes a compensation signal transmission line and a compensation signal connection line, the compensation signal connection line is electrically connected to the gating subcircuit and the compensation signal transmission line, respectively, and the compensation signal transmission line is electrically connected to the driving circuit;

[0013] The compensation circuit includes k groups of the gating sub-circuits, each group of the gating sub-circuits corresponding to the same compensation signal connection line electrically connected, wherein k is a natural number greater than 0.

[0014] In some embodiments, a length direction of the compensation signal transmission line intersects with a length direction of the compensation signal connection line.

[0015] In some embodiments, at least one group of the gating subcircuits are electrically connected to the pixel circuits in the same row.

[0016] In some embodiments, the display area of ​​the display panel includes a first area, a second area, and a third area, the first area, the second area, and the third area are arranged along a first direction, the first direction intersects with the length direction of the compensation signal transmission line, the second area is located between the first area and the third area, and the compensation signal transmission line is set in the second area.

[0017] In some embodiments, a line width of the compensation signal transmission line is greater than a line width of the data signal line.

[0018] In some embodiments, the display area of ​​the display panel includes a fourth area, a fifth area, and a sixth area, the fourth area, the fifth area, and the sixth area are arranged along a second direction, the second direction intersects with the length direction of the compensation signal connection line, the fifth area is located between the fourth area and the sixth area, the sixth area is located between the fifth area and the driving circuit, and the selection subcircuit is set in the fifth area and / or the sixth area.

[0019] In some embodiments, the gating subcircuit includes a first unit, a second unit, and a third unit, the third unit includes the first path and the second path, and the node connecting the first path and the second path includes a fourth node and a fifth node;

[0020] The first end of the first unit is electrically connected to a compensation control signal line, the compensation control signal line is used to transmit the compensation control signal, the second end of the first unit and the data signal line are both electrically connected to the fourth node, the third end of the first unit is electrically connected to the first end of the second unit, and the second end of the second unit is electrically connected to the fifth node;

[0021] The first unit is used for controlling the second unit to provide a control potential signal to the third unit under the action of the compensation control signal and the potential on the data signal line;

[0022] The first path and the second path are both used to be turned on or off under the action of the control potential signal, wherein when the first path is turned on, the second path is turned off; when the second path is turned on, the first path is turned off.

[0023] In some embodiments, the second unit includes a third path and a fourth path, and the connection point between the third path and the fourth path includes a sixth node and a seventh node; the third end of the first unit is electrically connected to the sixth node, and the seventh node is electrically connected to the fifth node;

[0024] The third path is used to access a first constant voltage, and the fourth path is used to access a second constant voltage. When the third path is turned on and the fourth path is turned off, the control potential signal is the first constant voltage. When the third path is turned off and the fourth path is turned on, the control potential signal is the second constant voltage.

[0025] In some embodiments, the second unit includes a first transistor and a second transistor, the first unit includes a third transistor, the first path includes a fourth transistor, and the second path includes a fifth transistor;

[0026] The gate of the first transistor and the gate of the second transistor are both connected to the sixth node, the gate of the third transistor is electrically connected to the compensation control signal line, the first electrode of the third transistor is electrically connected to the sixth node, and the second electrode of the third transistor is electrically connected to the fourth node;

[0027] The first electrode of the first transistor is used to access a first constant voltage, the first electrode of the second transistor is used to access a second constant voltage, and the second electrode of the first transistor and the second electrode of the second transistor are both connected to the seventh node;

[0028] The gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the fifth node, the first electrode of the fourth transistor and the first electrode of the fifth transistor are both electrically connected to the fourth node, the second electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fifth transistor is electrically connected to the compensation signal line.

[0029] In some embodiments, the second unit includes a second capacitor, a first end of the second capacitor is electrically connected to the seventh node, and a second end of the second capacitor is electrically connected to the fifth node; and / or,

[0030] The first transistor and the fifth transistor are transistors of the same type, and the second transistor and the fourth transistor are transistors of the same type.

[0031] In some embodiments, the effective level start point of the compensation control signal is before the start point of the test pulse of the data signal, and the effective level end point of the compensation control signal is after the end point of the test pulse of the data signal.

[0032] In a second aspect, a display panel is provided, comprising:

[0033] A pixel circuit, a data signal line, a driving circuit and the compensation circuit described in the first aspect;

[0034] The compensation circuit is electrically connected to the pixel circuit, the data signal line and the driving circuit respectively.

[0035] In a third aspect, a compensation method for a display panel is provided, which is applied to the compensation circuit of the display panel according to the first aspect, and the compensation method includes:

[0036] When there is an abnormality in the data signal line, controlling the driving circuit to output the compensation control signal and the compensation signal, wherein the compensation signal corresponds to the data signal transmitted by the data signal line with the abnormality;

[0037] Under the action of the compensation control signal and the potential on the data signal line, the first path is cut off and the second path is turned on, so that the gating module transmits the compensation signal to the pixel circuit.

[0038] In a fourth aspect, a controller is provided, comprising:

[0039] a memory storing a computer program;

[0040] A processor is used to call the computer program in the memory, wherein the computer program is used to execute the compensation method as described in the third aspect.

[0041] In a fifth aspect, a display device is provided, comprising the display panel as described in the second aspect and / or the controller as described in the fourth aspect.

[0042] The compensation circuit of the display panel of the present invention, other advantages, objectives and features of the present invention will be reflected in part through the following description, and in part will be understood by those skilled in the art through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0045] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0046] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0047] Figure 2 A schematic partial structural diagram of a display module provided in an embodiment of the present application;

[0048] Figure 3 A schematic circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0049] Figure 4A driving timing diagram of a pixel circuit provided in an embodiment of the present application;

[0050] Figure 5 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0051] Figure 6 A schematic circuit diagram of a compensation circuit for a display panel provided in an embodiment of the present application;

[0052] Figure 7 A schematic structural diagram of a gating subcircuit provided in an embodiment of the present application;

[0053] Figure 8 A schematic structural diagram of another gating subcircuit provided in an embodiment of the present application;

[0054] Fig. 9 A driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0055] Fig.10 A schematic flow chart of a compensation method for a display panel provided in an embodiment of the present application;

[0056] Fig.11 A schematic structural block diagram of a controller provided in an embodiment of the present application;

[0057] Fig.12 A schematic structural block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0059] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0060] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0061] With the continuous development of display technology, display panels have been widely used in the mobile phone market, and the requirements for product effects and low costs are getting higher and higher. For the current extremely narrow frame and stacked thinning design, after the bending process, the data signal line is prone to breakage, resulting in linear defects, such as bright line defects. After being assembled into a full module, the product will be tested, and such linear defective products will be judged as defective products and then scrapped, resulting in reduced yield and cost losses.

[0062] In a first aspect of the present application, a compensation circuit for a display panel is provided. Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application. For example, Figure 1 As shown, the display panel 100 may include a pixel circuit 110, a data signal line 120 and a driving circuit 130. The data signal line 120 is electrically connected between the pixel circuit 110 and the driving circuit 130. The data signal line 120 is used to transmit a data signal V data .

[0063] Exemplary, reference Figure 1 The pixel circuit 110 can drive the sub-pixels to display, the sub-pixels are arranged in an array, and the pixel circuit 110 is arranged in an array. The data signal line 120 extends along the second direction Y, and the plurality of data signal lines 120 are arranged along the first direction X. The data signal line 120 can provide a data signal V to the pixel circuit 110. dataOne data signal line 120 may be connected to one column of pixel circuits or two columns of pixel circuits arranged along the second direction Y, which is not specifically limited in the embodiment of the present application.

[0064] Exemplary, reference Figure 1 The display panel 100 includes a bending portion 101, which is a portion of the display panel for bending. The driving circuit 130 can be integrated in the display panel 100; the driving circuit 130 can also be a driving chip, which is bound and connected to the binding area of ​​the display panel by binding. The data signal line 120 can cross the bending portion 101 and connect to the driving circuit 130.

[0065] Figure 2 A schematic partial structural diagram of a display module provided in an embodiment of the present application. For example, refer to Figure 2 , the display module may include a cover plate CG, an optical adhesive T-OCA, a polarizer T-POL, a display panel 100, a buffer material layer U-Film, a first support layer SCF, a second support layer Bending Spacer and a protective material layer MCL. The cover plate CG is provided with an ink layer CG-P, and the ink layer CG-P may be black ink, which may block light, and the shape of the corresponding part of the bending portion 101 may be blocked from the cover plate CG. The optical adhesive T-OCA may be used to adhere the cover plate and the polarizer. The bending portion 101 of the display panel may bend the end away from the display area AA to the side of the display panel away from the display side D. The display panel connected to the end of the bending portion 101 away from the display area AA may be bound with a flexible circuit board, and the flexible circuit board is provided on the side of the display panel away from the display side D. A protective material layer MCL may be provided on the surface of the bending portion 101 to enhance the stress of the bending portion. The bending portion 101 has a bending radius R, and the distance between the bending portion 101 and the edge of the cover plate CG after bending is expressed as L.

[0066] Exemplary, reference Figure 1 and Figure 2 The data signal line 120 crosses the area corresponding to the bending portion 101. During or after the bending process of the bending portion 101, it is easy to cause damage to the line in the bending portion 120, such as breakage of the data signal line or other signal lines, which will cause abnormal data signal transmission or other signal transmission abnormalities.

[0067] For example, OLED (Organic Light Emitting Display) panels have been widely used in mobile phones. Semiconductor processes include two solutions: LTPO (Low Temperature Polycrystalline Oxide) and LTPS (Low Temperature Poly-silicon). LTPO has lower power consumption but higher cost. The pixel circuit in the LTPO solution can include circuit structures such as 7T1C (7 transistors and 1 capacitor) and 8T1C circuits. Because the 8T1C circuit has initial signal adjustment, it can have better frequency cutting effect and flickering effect.

[0068] Figure 3 A schematic circuit diagram of a pixel circuit provided in an embodiment of the present application. For example, refer to Figure 3 , the pixel circuit is an 8T1C circuit structure, the pixel circuit includes 8 transistors and 1 capacitor, the pixel circuit includes a first capacitor C1, a first drive tube T1, a second drive tube T2, a third drive tube T3, a fourth drive tube T4, a fifth drive tube T5, a sixth drive tube T6, a seventh drive tube T7 and an eighth drive tube T8. The drive tube includes a gate, a first electrode and a second electrode, the first electrode can be one of a source and a drain, and the second electrode can be the other of a source and a drain. One end of the first capacitor C1 is connected to the first node N1, and the other end is used to access the first power supply signal VDD. The first node N1 is connected to the gate of the third drive tube T3, the second drive tube T2 is connected between the first node N1 and the third node N3, and the gate of the second drive tube T2 is used to access the second gate signal Gate_N. The third driving tube T3 is connected between the second node N2 and the third node N3, the second electrode of the first driving tube T1 is connected to the third node N3, the second electrode of the first driving tube T1 is used to receive the first initial signal Vinit1, and the gate of the first driving tube T1 is used to receive the first reset signal P-Reset. The gate of the sixth driving tube T6 is used to receive the enable signal EM, the first electrode of the sixth driving tube T6 is connected to the third node N3, the second electrode of the sixth driving tube T6 is connected to the anode of the light-emitting device, and the cathode of the light-emitting device is used to receive the second power supply signal VSS. The gate of the seventh driving tube T7 is used to receive the second reset signal H-Reset, the second electrode of the seventh driving tube T7 is connected to the anode of the light-emitting device, and the first electrode of the seventh driving tube T7 is used to receive the second initial signal Vinit2. The gate of the fourth driving tube T4 is used to receive the fourth gate signal Gate_P, and the first electrode of the fourth driving tube T4 is used to receive the data signal V data, the second electrode of the fourth driving tube T4 is connected to the second node N2. The gate of the eighth driving tube T8 is used to receive the second reset signal H-Reset, the first electrode of the eighth driving tube T8 is used to receive the third initial signal Vinit3, and the second electrode of the eighth driving tube T8 is connected to the second node N2. The first electrode of the fifth driving tube T5 is used to receive the first power supply signal VDD, the second electrode of the fifth driving tube T5 is connected to the second node N2, and the gate of the fifth driving tube T5 is used to receive the enable signal EM.

[0069] Exemplary, reference Figure 3 The type of the second driving tube T2 of the pixel circuit can be N-type, and the types of the remaining driving tubes can be P-type.

[0070] Figure 4 A driving timing diagram of a pixel circuit provided in an embodiment of the present application. For example, refer to Figure 3 and Figure 4 The display panel includes a scan driving circuit, which is electrically connected to the driving circuit 130 and the pixel circuit 110. The scan driving circuit can receive a driving signal from the driving circuit 130, and the driving signal includes a synchronization signal TE, a first driving signal ESTV-P, a second driving signal RSTV-H, a third driving signal GSTV-P, a fourth driving signal GSTV-N and a fifth driving signal RSTV-P, wherein the synchronization signal TE is used to limit the time synchronization of each frame. The scan driving circuit can be arranged on two opposite sides of the display area. The scan driving circuit can process the received driving signal and output the scan driving signal. The scan driving signal may include an enable signal EM, a second reset signal H-Reset, a fourth gate signal Gate_P, a second gate signal Gate_N and a first reset signal P-Reset. The phase of the enable signal EM is the same as the phase of the first driving signal ESTV-P, the phase of the second reset signal H-Reset is the same as the phase of the second driving signal RSTV-H, the phase of the fourth gate signal Gate_P is the same as the phase of the third driving signal GSTV-P, the phase of the second gate signal Gate_N is the same as the phase of the fourth driving signal GSTV-N, and the phase of the first reset signal P-Reset is the same as the phase of the fifth driving signal RSTV-P.

[0071] Exemplary, reference Figures 1 to 4 In the case where the data signal line 120 is broken due to the bending process, the data signal line 120 cannot normally transmit the data signal V data , in V data When the data signal V is not transmitted normally, the third driving tube T3 in the pixel circuit cannot obtain the normal data signal V from the fourth driving tube T4. data , that is, the V received by the P-type T3data =0, then V data When N2 is transmitted to the gate of T3 via T2, T3 can be controlled to be turned on. In the lighting stage, T5 and T6 are also turned on, so VDD can reach the anode of the light-emitting device via T5, T3 and T6, and the light-emitting device can be illuminated. In the case that the broken data signal line cannot provide the data signal to the connected light-emitting device, the light-emitting device is always on, which can easily cause poor display bright lines, resulting in poor display panel and affecting the yield of the display panel.

[0072] Figure 5 A schematic structural diagram of another display panel provided in an embodiment of the present application; Figure 6 A schematic circuit diagram of a compensation circuit of a display panel provided in an embodiment of the present application. For example, Figure 5 and Figure 6 As shown, the compensation circuit 140 of the display panel 100 may include: a gating subcircuit 141, a compensation control signal line 142 and a compensation signal line 143. The gating subcircuit 141 is electrically connected between the driving circuit 130 and the data signal line 120. The gating subcircuit 141 includes a first path 141-1 and a second path 141-2 connected to each other, and the first path 141-1 and the second path 141-2 are both electrically connected to the data signal line 120. One end of the compensation control signal line 142 is electrically connected to the gating subcircuit 141, and the other end of the compensation control signal line 142 is electrically connected to the driving circuit 130. The compensation control signal line 142 is used to transmit the compensation control signal EN output by the driving circuit 130. One end of the compensation signal line 143 is electrically connected to the second path 141-2, and the other end of the compensation signal line is electrically connected to the driving circuit 130. The compensation signal line 143 is used to transmit the compensation signal Sr output by the driving circuit 130.

[0073] Exemplary, reference Figure 5 , the display panel 100 includes a plurality of sub-pixels arranged in an array, and the sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels. A row of sub-pixels arranged along the first direction X is a row of sub-pixels, and sub-pixels arranged along the second direction Y are a column of sub-pixels. R1,1 represents the red sub-pixel in the 1st row and the 1st column, G1,1 represents the green sub-pixel in the 1st row and the 1st column, B1,1 represents the blue sub-pixel in the 1st row and the 1st column, Gm-1,n represents the green sub-pixel in the m-1th row and the nth column, Gm,n represents the green sub-pixel in the mth row and the nth column, and so on, n is used to represent the number of the sub-pixel column, m represents the number of the sub-pixel row, and both m and n are natural numbers greater than 0.

[0074] Exemplary, reference Figure 5The display panel 100 further includes a scanning signal line for providing a scanning signal to the pixel circuit 110. The first row scanning signal GT1 is used to drive the first row of sub-pixels, and the mth row scanning signal GTm is used to drive the mth row of sub-pixels. Each sub-pixel has a corresponding pixel circuit 110, and the pixel circuit 110 is used to drive the sub-pixel display under the action of the scanning signal and the data signal.

[0075] refer to Figure 6 , the selection subcircuit 141 can be used to control the first path 141-1 to be turned on and the second path 141-2 to be turned off under the joint action of the compensation control signal EN and the data signal, so that the data signal Sn of the nth column is transmitted to the pixel circuit 110 via the first path 141-1; the data signal Sn of the nth column can also be transmitted to the pixel circuit 110 via the data signal line 120 at the same time; the data signal Sn of the nth column can also be transmitted to the pixel circuit 110 via the data signal line 120 alone. At the same time, the second path 141-2 is turned off, and the compensation signal Sr will not be transmitted to the pixel circuit 110 via the second path 141-2, or the compensation signal Sr is an invalid signal and will not affect the normal driving of the pixel circuit. At this time, all data signal lines 120 can transmit data signals normally, and the data signal is a valid high-level signal. The nth column can be any column of pixel circuits. The data signal Sn of the nth column is used to drive the pixel circuit 110 of the nth column. When there is no abnormality in the data signal line 120 , for example, no breakage, the data signal line 120 can normally transmit the data signal to drive the pixel circuit 110 .

[0076] refer to Figure 6The selection subcircuit 141 is used to control the first path 141-1 to be turned off and the second path 141-2 to be turned on under the combined effect of the compensation control signal EN and the potential on the data signal line 120, so that the compensation signal Sr is transmitted to the pixel circuit 110 via the second path 141-2. When an abnormality occurs to the data signal line 120, that is, the data signal cannot be transmitted normally, for example, when the data signal line is broken, the n-th column data signal Sn transmitted by the data signal line 120 is an invalid signal (no signal, equivalent to 0), that is, the potential on the abnormal data signal line is 0, the compensation control signal EN and the invalid n-th column data signal Sn can control the first path 141-1 to be turned off, and the second path 141-2 to be turned on, then the compensation signal Sr can be transmitted to the pixel circuit 110 via the second path 141-2, that is, the compensation signal Sr can be transmitted to the corresponding n-th column pixel circuit via the second path 141-2 and the data signal line. The compensation signal may be a signal value that is the same as the data signal. The compensation signal is a substitute signal for the data signal transmitted by the abnormal data signal line, and can normally drive the pixel circuit so that the display panel can display normally and avoid display defects caused by the breakage of the data signal line. It should be noted that although the abnormal data signal line 120 has an abnormality such as a breakage, if the breakage abnormality occurs in the area where the bending portion 101 is located, the data signal line in the area where the pixel circuit is located can normally transmit the signal provided by the selection subcircuit 141.

[0077] It should be noted that the compensation circuit can repair abnormal problems of abnormal data signal lines by providing compensation signals. What is repaired is not the abnormal data signal line, but the signal replacement transmission function for the abnormal signal line that cannot transmit the signal, thereby improving the yield of the corresponding subsequent products of the display panel and avoiding cost losses.

[0078] Exemplarily, the pin connected to the driving circuit corresponding to the compensation signal Sr can be used as a replacement pin for the pin connected to the driving circuit corresponding to any abnormal data signal line, thereby repairing the bright line defect corresponding to the abnormal data signal line.

[0079] For example, in the event that any data signal line is broken, inside the driving circuit, the output of the pin corresponding to the abnormal data signal line will be cut off, and the data signal originally output to the abnormal data signal line will be transferred (transmission channel changed) to the pin corresponding to the compensation signal line, and output to the corresponding pixel circuit in the form of a compensation signal to achieve bright line defect repair.

[0080] Exemplary, reference Figure 6The compensation control signal EN can be provided by the driving circuit 130. The driving circuit can generate and send the compensation control signal EN when any data signal line is detected to be broken. The compensation control signal can be provided to the pixel circuit through the compensation circuit to avoid the problem that the corresponding connected pixel circuit cannot be driven normally due to abnormal breakage of the data signal line. The abnormal breakage of the data signal line can be caused by the bending process, or by the breakage of the line caused by foreign matter in the film layer, etc.

[0081] Exemplary, reference Figure 5 and Figure 6 In the driving process of each frame of the display panel, each data signal line 120 will receive a pulse in the pre-charging stage of each frame, that is, the test pulse of the data signal. The pre-charging stage is the pre-charging period before the lighting stage of the light-emitting device. The time segment corresponding to the effective level timing of the compensation control signal EN will include the test pulse period of the data signal, so that each data signal line 120 can be realized with its own voltage, that is, the voltage of the data signal, that is, the pulse amplitude of the test pulse is the voltage of the data signal provided by the driving circuit. In the case that one of the data signal lines 120 is broken, the selection sub-circuit 141 cannot receive the high level on the data signal line, that is, the effective voltage value of the test pulse of the data signal, that is, Sn. Then, the pin providing Sn can be controlled in the driving circuit to input Sn to the pin for outputting the compensation signal Sr, so as to provide the compensation signal Sr to the selection sub-circuit 141. It is a process of re-establishing a signal path, that is, cutting off the original Sn output path and establishing a path for outputting Sr. Then, within a certain error range, Sn=Sr.

[0082] It should be noted that the driving circuit may reserve a certain number of blank pins, which may be used as pins for outputting the compensation signal Sr.

[0083] The compensation circuit of the display panel provided in the embodiment of the present application is provided with a gating subcircuit, a compensation control signal line and a compensation signal line, wherein the gating subcircuit includes a first path and a second path, and the gating subcircuit is connected between the data signal line and the driving circuit. When there is no abnormality in the data signal line, the gating subcircuit can, under the joint action of the data signal and the compensation control signal, not affect the normal transmission of the data signal to the pixel point circuit, and does not affect the normal display of the display panel. When the data signal line in the area where the bending portion is located is broken, the gating subcircuit provides the compensation signal to the pixel circuit under the action of the abnormal potential and the compensation control signal on the invalid data signal line, thereby repairing the abnormal data signal line that cannot provide the data signal, avoiding the poor display caused by the broken data signal line, thereby improving the yield of the back-end products of the display panel and avoiding cost losses.

[0084] In some embodiments, reference Figure 5 The compensation signal line 143 may include a compensation signal transmission line 143-1 and a compensation signal connection line 143-2, wherein the compensation signal connection line 143-2 is electrically connected to the selection sub-circuit 141 and the compensation signal transmission line 143-1, respectively, and the compensation signal transmission line 143-1 is electrically connected to the driving circuit 130. The compensation signal transmission line 143-1 may be used to transmit the compensation signal Sr output by the driving circuit 130 to the compensation signal connection line 143-2, and the compensation signal connection line 143-2 may provide the received compensation signal Sr to the plurality of selection sub-circuits 141.

[0085] Exemplary, reference Figure 5 , the compensation circuit 140 may include a plurality of gating sub-circuits 141, and the plurality of gating sub-circuits 141 may be arranged along the length direction of the compensation signal connection line 143-2. ​​The length direction of the compensation signal transmission line 143-1 intersects with the length direction of the compensation signal connection line 143-2. ​​The length direction of the compensation signal transmission line 143-1 is different from the length direction of the compensation signal connection line 143-2, so that the compensation signal Sr can be more easily transmitted to the plurality of gating sub-circuits 141 through one compensation signal transmission line 143-1 and one compensation signal connection line.

[0086] Exemplary, reference Figure 5 , each data signal line 120 is connected to a column of pixel circuits 110, and each scanning signal line is connected to a row of pixel circuits 110. A plurality of gating subcircuits 141 are arranged in a row along the first direction X, and the gating subcircuits 141 are connected one-to-one with the data signal lines 120, that is, one gating subcircuit 141 can compensate and repair one data signal line 120, and one gating subcircuit 141 can compensate and repair one column of pixel circuits 110. The length direction of the compensation signal transmission line 143-1 can be the same as the second direction Y, and the length direction of the compensation signal connection line 143-2 can be the same as the first direction X, and the length direction of the compensation signal transmission line 143-1 can be the same as the length direction of the data signal line 120.

[0087] In some examples, the length direction of the compensation signal transmission line 143-1 can be the same as the length direction of the data signal line 120, and the compensation signal transmission line 143-1 and the data signal line 120 are both connected to the driving circuit 130, then the compensation signal transmission line 143-1 and the data signal line 120 need to cross the area where the bending portion 101 is located to connect to the driving circuit, then the compensation signal transmission line 143-1 also has the risk of bending and breaking. In order to reduce the bending and breaking of the compensation signal transmission line 143-1, the line width of the compensation signal transmission line 143-1 can be set to be greater than the line width of the data signal line 120. Since the number of data signal lines 120 is large and the wiring space is limited, the line width of the data signal line 120 cannot be too wide. The number of compensation signal transmission lines 143-1 can be only one, and the line width can be widened to ensure that it is not easy to break and ensure the compensation repair effect.

[0088] In some embodiments, reference Figure 5 , the display area of ​​the display panel 100 includes a first area 102, a second area 103 and a third area 104, the first area 102, the second area 103 and the third area 104 are arranged along a first direction X, the first direction X intersects with the length direction of the compensation signal transmission line 143-1, the second area 103 is located between the first area 102 and the third area 104, that is, the second area 103 is the middle area, the first area 102 and the third area 104 are the areas on both sides of the first direction, and the compensation signal transmission line 143-1 is arranged in the second area 103. Due to the position area restriction on both sides of the display area in the first direction X, that is, in Figure 5 As shown in the lower left and lower right corners, the data signal line 120 needs to be connected to the drive circuit 130 by turning, which increases the risk of line bending damage. Therefore, the compensation signal transmission line 143-1 is set in the second area 103 to avoid the bending of the wiring in the lower left and lower right corner areas. The compensation signal transmission line 143-1 does not need to be bent or the bending angle is small to avoid bending damage.

[0089] In some embodiments, reference Figure 5The display area of ​​the display panel 100 may include a fourth area 105, a fifth area 106 and a sixth area 107. The fourth area 105, the fifth area 106 and the sixth area 107 are arranged along the second direction Y, the second direction Y intersects with the length direction of the compensation signal connection line 143-2, the fifth area 106 is located between the fourth area 105 and the sixth area 107, the sixth area 107 is located between the fifth area 106 and the driving circuit 130, the gating subcircuit 141 is arranged in the fifth area 106; the gating subcircuit 141 may also be arranged in the sixth area 107; the gating subcircuit 141 may be arranged in both the fifth area 106 and the sixth area 107. The fifth area 106 and the sixth area 107 are closer to the driving circuit 130 than the fourth area 105. Placing the gating subcircuit 141 close to the area of ​​the driving circuit 130 can avoid signal attenuation caused by the excessive length of the compensation signal transmission line 143-1.

[0090] In some implementations, the compensation circuit 140 includes k groups of gating sub-circuits, each group of gating sub-circuits corresponding to the same compensation signal connection line 143 - 2 electrically connected, wherein k is a natural number greater than 0, and k≤m.

[0091] In some examples, reference Figure 5 , k=1, a group of gating subcircuits is set in the display panel, and the number of gating subcircuits 141 in this group of gating subcircuits is the total number of data signal lines. This group of gating subcircuits is arranged in a row, and the gating subcircuits 141 in this row can be set between pixel circuits in adjacent rows.

[0092] In some examples, the number of gating subcircuits in each group of gating subcircuits may be different or the same. For example, the number of the gating subcircuits in the first group is p1, the number of the gating subcircuits in the second group is p2, and so on. The sum of p1, p2, ..., pk-1 and pk may be equal to the number of data signal lines 120, which can ensure that each data signal line 120 is connected to a gating subcircuit 141, and the drive repair of the abnormal data signal line can be achieved. The data signal corresponding to the abnormal data signal line is provided to the corresponding pixel circuit again through the gating subcircuit 141 to obtain a normal display image and reduce display product defects.

[0093] In some examples, at least one set of gating subcircuits is electrically connected to the pixel circuits of the same row.

[0094] Exemplarily, k=m, each row of pixel circuits corresponds to a group of gating sub-circuits, and each gating sub-circuit 141 of each group of gating sub-circuits is connected to a data signal line 120, which can ensure that the compensation signal is provided to the corresponding pixel circuit.

[0095] In some embodiments, Figure 7This is a schematic structural diagram of a gating subcircuit provided in an embodiment of the present application. Figure 7 As shown, the gating subcircuit 141 includes a first unit 144, a second unit 145 and a third unit 146, the third unit 146 includes a first path 141-1 and a second path 141-2, and the nodes connected between the first path 141-1 and the second path 141-2 include a fourth node N4 and a fifth node N5. The first end 401 of the first unit 144 is electrically connected to the compensation control signal line 142, and the compensation control signal line 142 is used to transmit the compensation control signal EN, the second end 402 of the first unit 144 and the data signal line 120 are both electrically connected to the fourth node N4, the third end 403 of the first unit 144 is electrically connected to the first end 501 of the second unit 145, and the second end 502 of the second unit 145 is electrically connected to the fifth node N5. The first unit 144 is used to control the second unit 145 to provide a control potential signal to the third unit 146 under the action of the compensation control signal EN and the potential on the data signal line 120. The first path 141-1 and the second path 141-2 are both used to be turned on or off under the control of the potential signal, wherein when the first path 141-1 is turned on, the second path 141-2 is turned off; when the second path 141-2 is turned on, the first path 141-1 is turned off. When the first path 141-1 is turned on and the second path 141-2 is turned off, the compensation signal Sr will not be transmitted to the fourth node N4, that is, the compensation signal Sr will not be transmitted to the data signal line 120, and the n-th column data signal Sn on the data signal line 120 can be transmitted to the fourth node N4 through the first path 141-1, that is, the data signal line 120 can short-circuit the first path 141-1, and will not affect the driving of the pixel circuit by the data signal. When the first path 141-1 is turned off and the second path 141-2 is turned off, the compensation signal Sr can be transmitted to the fourth node N4 through the second path 141-2, and then transmitted to the data signal line, then the compensation signal Sr can replace the data signal that the abnormal data signal line cannot transmit, and then drive the pixel circuit normally.

[0096] In some embodiments, reference Figure 7, the second unit 145 includes a third path 145-1 and a fourth path 145-2, and the connection point between the third path 145-1 and the fourth path 145-2 includes a sixth node N6 and a seventh node N7; the third path 145-1 is used to access the first constant voltage VGL, and the fourth path 145-2 is used to access the second constant voltage VGH, the potential of the second constant voltage VGH is greater than the first constant voltage VGL, the second constant voltage VGH is a high level signal, and the first constant voltage VGL is a low level signal. The third end 403 of the first unit 144 is electrically connected to the sixth node N6, and the seventh node N7 is electrically connected to the fifth node N5. The first unit 144 can transmit a signal to the sixth node N6 of the second unit 145 under the action of the compensation control signal EN and the potential of the data signal line 120, and the first unit 144 can control the conduction or cutoff of the third path 145-1 and the fourth path 145-2; when the third path 145-1 is turned on, the fourth path 145-2 is turned off. When the third path 145 - 1 is turned off, the fourth path 145 - 2 is turned on.

[0097] refer to Figure 7 When the third path 145-1 is turned on and the fourth path 145-2 is turned off, the first constant voltage VGL is transmitted to the fifth node N5 through the third path 145-1, and the control potential signal is the first constant voltage VGL. When the third path 145-1 is turned off and the fourth path 145-2 is turned on, the second constant voltage VGH is transmitted to the fifth node N5 through the fourth path 145-2, and the control potential signal is the second constant voltage VGH.

[0098] In some examples, Figure 8 This is a schematic structural diagram of another gating subcircuit provided in an embodiment of the present application. Figure 8, the second unit 145 includes a first transistor T01 and a second transistor T02, the first unit 144 includes a third transistor T03, the first path 141-1 includes a fourth transistor T04, and the second path 141-2 includes a fifth transistor T05. The gate of the first transistor T01 and the gate of the second transistor T02 are both connected to the sixth node N6, the gate of the third transistor T03 is electrically connected to the compensation control signal line 142, the first electrode of the third transistor T03 is electrically connected to the sixth node N6, and the second electrode of the third transistor T03 is electrically connected to the fourth node N4. The first electrode of the transistor is one of the source and the drain, and the second electrode is the other of the source and the drain. The first electrode of the first transistor T01 is used to access the first constant voltage VGL, the first electrode of the second transistor T02 is used to access the second constant voltage VGH, and the second electrode of the first transistor T01 and the second electrode of the second transistor T02 are both connected to the seventh node N7. The gate of the fourth transistor T04 and the gate of the fifth transistor T05 are both electrically connected to the fifth node N5, the first electrode of the fourth transistor T04 and the first electrode of the fifth transistor T05 are both electrically connected to the fourth node N4, the second electrode of the fourth transistor T04 is electrically connected to the data signal line 120, and the second electrode of the fifth transistor T05 is electrically connected to the compensation signal line 143.

[0099] In some examples, reference Figure 8 The second unit 145 includes a second capacitor Cst, a first end of the second capacitor Cst is electrically connected to the seventh node N7, and a second end of the second capacitor Cst is electrically connected to the fifth node N5.

[0100] In some examples, the first transistor T01 and the fifth transistor T05 are transistors of the same type, and the second transistor T02 and the fourth transistor T04 are transistors of the same type.

[0101] It should be noted that the type of the third transistor T03 can be P-type or N-type, without specific limitation.

[0102] Exemplary, reference Figure 8 The first transistor T01 and the fifth transistor T05 are both P-type transistors Pmos, and the second transistor T02 and the fourth transistor T04 are both N-type transistors Nmos.

[0103] In some embodiments, the effective level start point of the compensation control signal is before the start point of the test pulse of the data signal, and the effective level end point of the compensation control signal is after the test pulse end point of the data signal.

[0104] Fig. 9 A driving timing diagram of another pixel circuit provided in an embodiment of the present application. For example, refer to Fig. 9, when all data signal lines are intact, in the pre-charge stage T0 of each frame display picture, the compensation control signal EN is pulled low, then the P-type third transistor T03 is turned on, and the high level of the test pulse pulse of the n-th column data signal Sn enters the gate of the first transistor T01 and the second transistor T02, so that T02 of Nmos is turned on, T01 is turned off, then Cst is charged with a high voltage, so that T04 is turned on, T05 is turned off, then Sr does not enter N4, that is, Sr does not enter the N4 data signal line 120, the normal Sn is not affected, and the pixel circuit is driven normally. When a data signal line is broken, that is, the n-th column data signal line is broken, there is no test pulse in the pre-charge stage T0 of each frame display picture, at this time T01 and T05 are turned on, Sr enters the n-th column data signal line, and the repair is completed.

[0105] Exemplarily, when all data signal lines are not broken, in the pre-charge stage T0 of each frame display picture, the compensation control signal EN is pulled high, then the N-type third transistor T03 is turned on, and the high level of the test pulse pulse of the n-th column data signal Sn enters the gate of the first transistor T01 and the second transistor T02, so that T02 of Nmos is turned on and T01 is turned off, then Cst is charged with a high voltage, so that T04 is turned on and T05 is turned off, then Sr does not enter N4, that is, Sr does not enter the N4 data signal line 120, the normal Sn is not affected, and the pixel circuit is driven normally. When a data signal line is broken, that is, the n-th column data signal line is broken, there is no test pulse in the pre-charge stage T0 of each frame display picture, at this time T01 and T05 are turned on, Sr enters the n-th column data signal line, and the repair is completed.

[0106] Exemplary, reference Figure 8 , the effective level starting point a2 of the compensation control signal EN (the starting point of the falling edge of the low level) is before the starting point a1 of the test pulse of the n-th column data signal Sn (the starting point of the rising edge of the high level), and the effective level end point b2 of the compensation control signal EN (the end point of the rising edge of the low level) is after the end point b1 of the test pulse of the n-th column data signal Sn (the end point of the falling edge of the high level). In the display driving process, the effective level period of the compensation control signal EN includes the effective level period of the test pulse of the data signal, which can ensure that the test pulse enters the gating submodule.

[0107] In a second aspect, an embodiment of the present application provides a display panel, referring to Figure 5 The display panel includes: a pixel circuit 110, a data signal line 120, a driving circuit 130 and a compensation circuit 140 as described in the first aspect; the compensation circuit 140 is electrically connected to the pixel circuit 110, the data signal line 120 and the driving circuit 130 respectively.

[0108] The display panel provided by the embodiment of the present application is provided with a compensation circuit, wherein the compensation circuit includes a gating subcircuit, a compensation control signal line and a compensation signal line, the gating subcircuit includes a first path and a second path, and the gating subcircuit is connected between the data signal line and the driving circuit. When there is no abnormality in the data signal line, the gating subcircuit can, under the joint action of the data signal and the compensation control signal, not affect the normal transmission of the data signal to the pixel point circuit, and does not affect the normal display of the display panel. When the data signal line in the area where the bending portion is located is broken, the gating subcircuit provides the compensation signal to the pixel circuit under the action of the abnormal potential and the compensation control signal on the invalid data signal line, thereby repairing the abnormal data signal line that cannot provide the data signal, avoiding the poor display caused by the broken data signal line, thereby improving the yield of the back-end products of the display panel and avoiding cost losses.

[0109] In a third aspect, an embodiment of the present application provides a compensation method for a display panel, which is applied to the compensation circuit of the display panel as described in the first aspect. Fig.10 The following is a schematic flow chart of a compensation method for a display panel provided in an embodiment of the present application. Fig.10 As shown, the compensation method includes:

[0110] S201: When there is an abnormality in the data signal line, control the driving circuit to output a compensation control signal and a compensation signal, wherein the compensation signal corresponds to the data signal transmitted by the data signal line with the abnormality.

[0111] S202: Under the action of the compensation control signal and the potential on the data signal line, the first path is cut off and the second path is turned on, so that the selection module transmits the compensation signal to the pixel circuit.

[0112] Exemplary, reference Figure 5 and Figure 6In the driving process of each frame of the display panel, each data signal line 120 will receive a pulse in the pre-charging stage of each frame, that is, the test pulse of the data signal. The pre-charging stage is the pre-charging period before the lighting stage of the light-emitting device. The time segment corresponding to the effective level timing of the compensation control signal EN will include the test pulse period of the data signal, so that each data signal line 120 can be realized with its own voltage, that is, the voltage of the data signal, that is, the pulse amplitude of the test pulse is the voltage of the data signal provided by the driving circuit. In the case that one of the data signal lines 120 is broken, the selection sub-circuit 141 cannot receive the high level on the data signal line, that is, the effective voltage value of the test pulse of the data signal, that is, Sn. Then, the pin providing Sn can be controlled in the driving circuit to input Sn to the pin for outputting the compensation signal Sr, so as to provide the compensation signal Sr to the selection sub-circuit 141. It is a process of re-establishing a signal path, that is, cutting off the original Sn output path and establishing a path for outputting Sr. Then, within a certain error range, Sn=Sr.

[0113] In some examples, the display panel compensation method further includes:

[0114] Automatic optical inspection is performed on the display panel or display module in the illuminated state to confirm whether the display panel or display module has display defects, wherein the display defects may include bright line defects caused by abnormal breakage of data signal lines, and the bright lines can be detected in the inspection result display in the automatic optical inspection.

[0115] When display failure is detected and the display failure is a linear failure in the column direction, the column data signal can be further transmitted to the pixel circuit of the column via the compensation circuit to normally drive the pixel circuit of the column for display driving, thereby repairing the failure caused by the data signal line.

[0116] Fourthly, Fig.11 This is a schematic structural block diagram of a controller provided in an embodiment of the present application. Fig.11 As shown, a controller 300 includes: a memory 310 storing a computer program; a processor 320 for calling the computer program in the memory 310, and the computer program is used to execute the compensation method as described in the third aspect.

[0117] Exemplarily, the controller 300 may be integrated into a driving circuit or a control main board connected to the display panel.

[0118] Fifthly, Fig.12 This is a schematic structural block diagram of a display device provided in an embodiment of the present application. Fig.12 As shown, a display device includes the display panel 1000 as described in the second aspect.

[0119] In some examples, the display device includes a controller as described in the fourth aspect.

[0120] The display device provided by the embodiment of the present application is provided with a compensation circuit in the display panel, wherein the compensation circuit includes a gating subcircuit, a compensation control signal line and a compensation signal line, the gating subcircuit includes a first path and a second path, and the gating subcircuit is connected between the data signal line and the driving circuit. When there is no abnormality in the data signal line, the gating subcircuit can, under the joint action of the data signal and the compensation control signal, not affect the normal transmission of the data signal to the pixel point circuit, and does not affect the normal display of the display panel. When the data signal line in the area where the bending portion is located is broken, the gating subcircuit provides the compensation signal to the pixel circuit under the action of the abnormal potential on the invalid data signal line and the compensation control signal, thereby repairing the abnormal data signal line that cannot provide the data signal, avoiding the poor display caused by the broken data signal line, thereby improving the yield of the back-end products of the display panel and avoiding cost losses.

[0121] The display device provided in the embodiment of the present application may include a television, a computer, a smart phone, a smart wearable device, a laptop computer, a tablet computer, etc. The smart wearable device may include a smart watch, an AR (augmented reality) device, a VR (virtual reality) device, etc.

[0122] In the several embodiments provided in the present application, it should be understood that the disclosed devices and / or equipment can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0123] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0124] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0125] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0126] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A compensation circuit for a display panel, characterized in that: The display panel comprises a pixel circuit, a data signal line and a driving circuit, wherein the data signal line is electrically connected between the pixel circuit and the driving circuit, and the data signal line is used to transmit a data signal; The compensation circuit comprises: a gating subcircuit, the gating subcircuit being electrically connected between the driving circuit and the data signal line, the gating subcircuit comprising a first path and a second path connected to each other, the first path and the second path being both electrically connected to the data signal line; a compensation control signal line, one end of which is electrically connected to the gating subcircuit, the other end of which is electrically connected to the driving circuit, and the compensation control signal line is used to transmit a compensation control signal output by the driving circuit; a compensation signal line, one end of which is electrically connected to the second path, the other end of which is electrically connected to the drive circuit, and the compensation signal line is used to transmit a compensation signal output by the drive circuit; The gating subcircuit is used for controlling the first path to be turned on and the second path to be turned off under the action of the compensation control signal and the data signal, so that the data signal is transmitted to the pixel circuit via the first path and / or the data signal line; or, The gating subcircuit is used for controlling the first path to be cut off and the second path to be turned on under the action of the compensation control signal and the potential on the data signal line, so that the compensation signal is transmitted to the pixel circuit via the second path.

2. The compensation circuit of the display panel according to claim 1, characterized in that: The compensation signal line comprises a compensation signal transmission line and a compensation signal connection line, the compensation signal connection line is electrically connected to the gating subcircuit and the compensation signal transmission line respectively, and the compensation signal transmission line is electrically connected to the driving circuit; The compensation circuit includes k groups of the gating sub-circuits, each group of the gating sub-circuits corresponding to the same compensation signal connection line electrically connected, wherein k is a natural number greater than 0.

3. The compensation circuit of the display panel according to claim 2, characterized in that: The length direction of the compensation signal transmission line intersects with the length direction of the compensation signal connection line.

4. The compensation circuit of the display panel according to claim 3, characterized in that: At least one group of the gating subcircuits is electrically connected to the pixel circuits in the same row.

5. The compensation circuit of a display panel according to any one of claims 2 to 4, characterized in that: The display area of ​​the display panel includes a first area, a second area and a third area, the first area, the second area and the third area are arranged along a first direction, the first direction intersects with the length direction of the compensation signal transmission line, the second area is located between the first area and the third area, and the compensation signal transmission line is set in the second area.

6. The compensation circuit of a display panel according to any one of claims 2 to 4, characterized in that: The line width of the compensation signal transmission line is greater than the line width of the data signal line.

7. The compensation circuit of a display panel according to any one of claims 2 to 4, characterized in that: The display area of ​​the display panel includes a fourth area, a fifth area and a sixth area, the fourth area, the fifth area and the sixth area are arranged along a second direction, the second direction intersects with the length direction of the compensation signal connection line, the fifth area is located between the fourth area and the sixth area, the sixth area is located between the fifth area and the driving circuit, and the selection subcircuit is arranged in the fifth area and / or the sixth area.

8. The compensation circuit of the display panel according to claim 1, characterized in that: The gating subcircuit comprises a first unit, a second unit and a third unit, the third unit comprises the first path and the second path, and the nodes connecting the first path and the second path comprise a fourth node and a fifth node; The first end of the first unit is electrically connected to a compensation control signal line, the compensation control signal line is used to transmit the compensation control signal, the second end of the first unit and the data signal line are both electrically connected to the fourth node, the third end of the first unit is electrically connected to the first end of the second unit, and the second end of the second unit is electrically connected to the fifth node; The first unit is used for controlling the second unit to provide a control potential signal to the third unit under the action of the compensation control signal and the potential on the data signal line; The first path and the second path are both used to be turned on or off under the action of the control potential signal, wherein when the first path is turned on, the second path is turned off; when the second path is turned on, the first path is turned off.

9. The compensation circuit of the display panel according to claim 8, characterized in that: The second unit includes a third path and a fourth path, and the connection point between the third path and the fourth path includes a sixth node and a seventh node; the third end of the first unit is electrically connected to the sixth node, and the seventh node is electrically connected to the fifth node; The third path is used to access a first constant voltage, and the fourth path is used to access a second constant voltage. When the third path is turned on and the fourth path is turned off, the control potential signal is the first constant voltage. When the third path is turned off and the fourth path is turned on, the control potential signal is the second constant voltage.

10. The compensation circuit of the display panel according to claim 9, characterized in that: The second unit includes a first transistor and a second transistor, the first unit includes a third transistor, the first path includes a fourth transistor, and the second path includes a fifth transistor; The gate of the first transistor and the gate of the second transistor are both connected to the sixth node, the gate of the third transistor is electrically connected to the compensation control signal line, the first electrode of the third transistor is electrically connected to the sixth node, and the second electrode of the third transistor is electrically connected to the fourth node; The first electrode of the first transistor is used to access a first constant voltage, the first electrode of the second transistor is used to access a second constant voltage, and the second electrode of the first transistor and the second electrode of the second transistor are both connected to the seventh node; The gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the fifth node, the first electrode of the fourth transistor and the first electrode of the fifth transistor are both electrically connected to the fourth node, the second electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fifth transistor is electrically connected to the compensation signal line.

11. The compensation circuit of the display panel according to claim 10, characterized in that: The second unit includes a second capacitor, a first end of the second capacitor is electrically connected to the seventh node, and a second end of the second capacitor is electrically connected to the fifth node; and / or, The first transistor and the fifth transistor are transistors of the same type, and the second transistor and the fourth transistor are transistors of the same type.

12. The compensation circuit of the display panel according to claim 1, characterized in that: The effective level starting point of the compensation control signal is before the starting point of the test pulse of the data signal, and the effective level ending point of the compensation control signal is after the ending point of the test pulse of the data signal.

13. A display panel, characterized in that: include: A pixel circuit, a data signal line, a driving circuit, and a compensation circuit as claimed in any one of claims 1 to 12; The compensation circuit is electrically connected to the pixel circuit, the data signal line and the driving circuit respectively.

14. A compensation method for a display panel, characterized in that: A compensation circuit applied to a display panel according to any one of claims 1 to 12, wherein the compensation method comprises: When there is an abnormality in the data signal line, controlling the driving circuit to output the compensation control signal and the compensation signal, wherein the compensation signal corresponds to the data signal transmitted by the data signal line with the abnormality; Under the action of the compensation control signal and the potential on the data signal line, the first path is cut off and the second path is turned on, so that the gating module transmits the compensation signal to the pixel circuit.

15. A controller, characterized in that: include: a memory storing a computer program; A processor, configured to call the computer program in the memory, wherein the computer program is configured to execute the compensation method as claimed in claim 14.

16. A display device, characterized in that: Includes the display panel as claimed in claim 13 and / or the controller as claimed in claim 15.

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