Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a pixel circuit and a light-emitting element, the pixel circuit comprises a first light-emitting control module, a driving module and a compensation module. The driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the first light-emitting control module is connected between a first power supply voltage end and a first end of the driving transistor, and a second end of the driving transistor is connected with the light-emitting element; the compensation module is connected between the grid electrode and the first end of the driving transistor; in the compensation stage, the first light emitting control module, the driving module and the compensation module are started, and the threshold voltage of the driving transistor is compensated. In the invention, before the light-emitting element emits light, the threshold voltage Vth of the driving transistor is written into the Vgs of the driving transistor in advance, and when the light-emitting element emits light, the Vth is counteracted, so that the influence of Vth offset of the driving transistor on the driving current of the light-emitting element can be eliminated, and the display effect is improved.

Description

[0001] This application is a divisional application with the application date of November 1, 2022, application number 202211358212.8, and the name of the invention being “A display panel and a display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] In a display panel, the pixel circuit provides the driving current required for display to the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage. It is an indispensable element in most self-luminous display panels.

[0004] However, in existing display panels, as the usage time increases, the internal characteristics of the driving transistor in the pixel circuit slowly change, causing the threshold voltage of the driving transistor to drift, thereby affecting the comprehensive characteristics of the driving transistor and further affecting the display uniformity. Summary of the invention

[0005] The present invention provides a display panel and a display device to solve the problem that the threshold voltage drift of the existing driving transistor affects the display.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising:

[0007] Pixel circuit and light emitting element;

[0008] The pixel circuit includes a first light emitting control module, a driving module and a compensation module;

[0009] The driving module is used to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0010] The first light emitting control module is connected between a first power supply voltage terminal and a first terminal of the driving transistor, and a second terminal of the driving transistor is connected to the light emitting element;

[0011] The compensation module is connected between the gate and the first end of the driving transistor;

[0012] The working process of the pixel circuit includes a compensation stage. In the compensation stage, the first light emitting control module, the driving module and the compensation module are turned on to compensate for the threshold voltage of the driving transistor.

[0013] According to another aspect of the present invention, a display device is provided, comprising the display panel as described above.

[0014] In the present invention, the driving module provides a driving current for the light-emitting element, and the driving module includes a driving transistor; the first light-emitting control module is connected between the first power supply voltage terminal and the first terminal of the driving transistor, and the second terminal of the driving transistor is connected to the light-emitting element; the compensation module is connected between the gate and the first terminal of the driving transistor; in the compensation stage, the first light-emitting control module, the driving module and the compensation module are turned on to compensate for the threshold voltage of the driving transistor. In the present invention, before the light-emitting element emits light, the threshold voltage Vth of the driving transistor is written into the Vgs of the driving transistor in advance, and when the light-emitting element emits light, the Vth pre-written in Vgs and the Vth in the driving current formula of the light-emitting element offset each other, which can eliminate the influence of the Vth offset of the driving transistor on the driving current of the light-emitting element and improve the display uniformity.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 It is a schematic diagram of the drift of the Id-Vg curve of the driving transistor;

[0019] Figure 3 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 7 is a timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0024] Figure 8is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] Fig. 9 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.10 is a schematic diagram of a pixel provided by an embodiment of the present invention;

[0027] Fig.11 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Figure 1 1 is a schematic diagram of a display panel provided by an embodiment of the present invention. The display panel provided by this embodiment includes: a pixel circuit 11 and a light-emitting element 12; the pixel circuit 11 includes a first light-emitting control module 13, a driving module 14 and a compensation module 15; the driving module 14 is used to provide a driving current for the light-emitting element 12, and the driving module 14 includes a driving transistor M0; the first light-emitting control module 13 is connected between the first power supply voltage terminal PVDD and the first terminal N2 of the driving transistor M0, and the second terminal N3 of the driving transistor M0 is connected to the light-emitting element 12; the compensation module 15 is connected between the gate N1 and the first terminal N2 of the driving transistor M0; the working process of the pixel circuit 11 includes a compensation stage, in which the first light-emitting control module 13, the driving module 14 and the compensation module 15 are turned on to compensate for the threshold voltage of the driving transistor M0.

[0031] It should be noted that Figure 1 Only the key structures in the above-mentioned implementation mode are schematically shown, and the entire structure of the circuit operation is not included. The complete circuit structure will be gradually shown later in the description of this embodiment.

[0032] In this embodiment, the pixel circuit 11 includes a driving module 14, and the driving module 14 is coupled to the light-emitting element 12. The driving module 14 includes a driving transistor M0, and the driving transistor M0 includes a gate N1, a first terminal N2, and a second terminal N3. The second terminal N3 of the driving transistor M0 is connected to the light-emitting element 12. The driving transistor M0 includes an on state and an off state. During a partial time period when the driving transistor M0 is turned on, the driving module 14 provides a driving current for the light-emitting element 12. The driving transistor M0 can be an NMOS transistor, and the first terminal N2 of the driving transistor M0 is a drain, and the second terminal N3 of the driving transistor M0 is a source and connected to the light-emitting element 12. A high-level signal input to the gate N1 of the driving transistor M0 can turn on the driving transistor M0, and a low-level signal input to the gate N1 of the driving transistor M0 can turn off the driving transistor M0. In other embodiments, the driving transistor may be a PMOS transistor, in which case the first end of the driving transistor is the source, the second end of the driving transistor is the drain and connected to the light emitting element, a low level signal is input to the gate of the driving transistor to turn on the driving transistor, and a high level signal is input to the gate of the driving transistor to turn off the driving transistor. It can be understood that the source and drain of the transistor are not constant, but will change as the driving state of the transistor changes.

[0033] The pixel circuit 11 includes a first light-emitting control module 13. A first end of the first light-emitting control module 13 is connected to a first power supply voltage end PVDD, a second end of the first light-emitting control module 13 is connected to a first end N2 of a driving transistor M0, and a control end of the first light-emitting control module 13 is connected to a first light-emitting signal end EM1. The first light-emitting signal provided by the first light-emitting signal end EM1 is a pulse signal, and the first light-emitting signal can turn on or off a transmission path between the first end and the second end of the first light-emitting control module 13. An effective pulse of the first light-emitting signal can turn on a transmission path between the first end and the second end of the first light-emitting control module 13, and then the first voltage signal provided by the first power supply voltage end PVDD is written into the first end N2 of the driving transistor M0; an invalid pulse of the first light-emitting signal can turn off a transmission path between the first end and the second end of the first light-emitting control module 13, and then the first voltage signal provided by the first power supply voltage end PVDD is not written into the first end N2 of the driving transistor M0. Under the control of the first light-emitting signal, the first light-emitting control module 13 selectively provides a first voltage signal to the first end N2 of the driving transistor M0, and the first voltage signal provided by the first power supply voltage end PVDD is a constant voltage signal. The optional first power supply voltage terminal PVDD provides a high level signal.

[0034] The pixel circuit 11 includes a compensation module 15. The first end of the compensation module 15 is connected to the first end N2 of the driving transistor M0, the second end of the compensation module 15 is connected to the gate N1 of the driving transistor M0, and the control end of the compensation module 15 is connected to the first scanning signal end S1. The first scanning signal provided by the first scanning signal end S1 is a pulse signal, and the first scanning signal can turn on or off the transmission path of the first end and the second end of the compensation module 15. The effective pulse of the first scanning signal can turn on the transmission path of the first end and the second end of the compensation module 15, that is, the transmission path of the first end N2 and the gate N1 of the driving transistor M0 is turned on, so as to adjust the voltage between the first end N2 and the gate N1 of the driving transistor M0 and compensate the threshold voltage of the driving transistor M0; the invalid pulse of the first scanning signal can turn off the transmission path of the first end and the second end of the compensation module 15, that is, the transmission path of the first end N2 and the gate N1 of the driving transistor M0 is disconnected. Under the control of the first scanning signal, the compensation module 15 is selectively turned on, and the compensation module 15 is used to compensate the threshold voltage of the driving transistor M0 when it is turned on.

[0035] The light emitting element 12 may be an organic light emitting element, but is not limited thereto. In other embodiments, the light emitting element may be other types of light emitting elements, such as a micro LED light emitting element.

[0036] The working process of the pixel circuit 11 includes a compensation stage. In the compensation stage, the first light emitting control module 13, the driving module 14 and the compensation module 15 are turned on to compensate for the threshold voltage of the driving transistor M0.

[0037] In the compensation stage, the first light-emitting signal provided by the first light-emitting signal terminal EM1 is a valid pulse, which makes the transmission path between the first end and the second end of the first light-emitting control module 13 conductive, and the first voltage signal provided by the first power supply voltage terminal PVDD is written into the first end N2 of the driving transistor M0. At the same time, the first scanning signal provided by the first scanning signal terminal S1 is a valid pulse, which makes the transmission path between the first end and the second end of the compensation module 15 conductive, that is, the transmission path between the first end N2 and the gate N1 of the driving transistor M0 is conductive. Based on this, the first voltage signal pvdd provided by the first power supply voltage terminal PVDD is written into the first end N2 of the driving transistor M0, and then written into the gate N1 of the driving transistor M0 through the turned-on compensation module 15, so that the gate N1 and the first end N2 of the driving transistor M0 are both charged to pvdd. The optional driving transistor M0 is an NMOS transistor. When the first power supply voltage terminal PVDD provides a high level signal, the gate N1 of the driving transistor M0 is charged to pvdd, and the driving transistor M0 is turned on to charge the second terminal N3 of the driving transistor M0. After the second terminal N3 of the driving transistor M0 is charged to (pvdd-Vth), the driving transistor M0 is turned off. It can be seen that Vgs of the driving transistor M0 = pvdd-(pvdd-Vth) = Vth, and Vth is the threshold voltage of the driving transistor M0.

[0038] Figure 2 It is a schematic diagram of the drift of the Id-Vg curve of the driving transistor. Figure 2 As shown, the Vth of the driving transistor M0 in the Id-Vg curve is offset, which will affect the driving current Id flowing into the light-emitting element 12, thereby affecting the display uniformity. The driving current formula flowing into the light-emitting element 12 is Id = k (Vgs-Vth) 2 , k is a coefficient. In this embodiment, before the light-emitting element 12 emits light, when the pixel circuit 11 is in the compensation stage, the Vth of the driving transistor M0 is written into the Vgs of the driving transistor M0, that is, Vgs includes Vth; when the light-emitting element 12 emits light, according to Id=k(Vgs-Vth) 2 , the Vth pre-written in Vgs and the Vth in the driving current formula cancel each other out, so that the Vth of the driving transistor M0 no longer affects the driving current Id flowing into the light-emitting element 12. When calculating the driving current Id of the light-emitting element 12, the Vth of the driving transistor M0 is eliminated, so even if the Vth of the driving transistor M0 is offset, it will not affect the driving current Id flowing into the light-emitting element 12, thereby eliminating the influence of the Vth offset of the driving transistor M0 on the driving current of the light-emitting element 12 and improving display uniformity.

[0039] In the present invention, the driving module provides a driving current for the light-emitting element, and the driving module includes a driving transistor; the first light-emitting control module is connected between the first power supply voltage terminal and the first terminal of the driving transistor, and the second terminal of the driving transistor is connected to the light-emitting element; the compensation module is connected between the gate and the first terminal of the driving transistor; in the compensation stage, the first light-emitting control module, the driving module and the compensation module are turned on to compensate for the threshold voltage of the driving transistor. In the present invention, before the light-emitting element emits light, the threshold voltage Vth of the driving transistor is written into the Vgs of the driving transistor in advance, and when the light-emitting element emits light, the Vth pre-written in Vgs and the Vth in the driving current formula of the light-emitting element offset each other, which can eliminate the influence of the Vth offset of the driving transistor on the driving current of the light-emitting element and improve the display uniformity.

[0040] Figure 3 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present invention. Figure 3 As shown, the optional first light-emitting control module 13 includes a first transistor M1, which is connected between the first power supply voltage terminal PVDD and the first terminal N2 of the driving transistor M0, and the control terminal of the first transistor M1 is connected to the first light-emitting signal terminal EM1; the compensation module 15 includes a second transistor M2, which is connected between the gate N1 and the first terminal N2 of the driving transistor M0, and the control terminal of the second transistor M2 is connected to the first scanning signal terminal S1.

[0041] In this embodiment, the first transistor M1 can be selected as an NMOS transistor; in other embodiments, the first transistor can also be selected as a PMOS transistor. The first light-emitting signal provided by the first light-emitting signal terminal EM1 is a pulse signal, and the first transistor M1 is an NMOS transistor. The high level of the first light-emitting signal is a valid pulse that can turn on the first transistor M1, and the low level of the first light-emitting signal is an invalid pulse that can turn off the first transistor M1. When the first transistor M1 is turned on, the first voltage signal provided by the first power supply voltage terminal PVDD is written into the first terminal N2 of the driving transistor M0.

[0042] The second transistor M2 may be an NMOS transistor; in other embodiments, the second transistor may be a PMOS transistor. The first scanning signal provided by the first scanning signal terminal S1 is a pulse signal, and the second transistor M2 is an NMOS transistor. The high level of the first scanning signal is a valid pulse that can turn on the second transistor M2, and the low level of the first scanning signal is an invalid pulse that can turn off the second transistor M2. When the second transistor M2 is turned on, the transmission path between the first terminal N2 of the driving transistor M0 and the gate N1 is turned on.

[0043] The driving transistor M0 can be an NMOS transistor. In the compensation stage, the first light emitting signal is a valid pulse to turn on the first transistor M1, the first scanning signal is a valid pulse to turn on the second transistor M2, and the first voltage signal pvdd provided by the first power supply voltage terminal PVDD is written into the first terminal N2 and the gate N1 of the driving transistor M0 to turn on the driving transistor M0. In the compensation stage, the first terminal N2 and the gate N1 of the driving transistor M0 are charged to pvdd, and the second terminal N3 of the driving transistor M0 is charged to pvdd-Vth, and Vgs of the driving transistor M0 = pvdd-(pvdd-Vth) = Vth.

[0044] Figure 4 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present invention. Figure 4 As shown, the optional pixel circuit 11 also includes: a data writing module 16, which is connected between the data signal terminal VDATA and the gate N1 of the driving transistor M0; the data writing module 16 is used to enable the data signal terminal VDATA to provide a data signal to the gate N1 of the driving transistor M0 when it is turned on; in the compensation stage, the data writing module 16 is turned off.

[0045] In this embodiment, the pixel circuit 11 includes a data writing module 16, a first end of the data writing module 16 is connected to the data signal end VDATA, a second end of the data writing module 16 is connected to the gate N1 of the driving transistor M0, and a control end of the data writing module 16 is connected to the second scanning signal end S2. The second scanning signal provided by the second scanning signal end S2 is a pulse signal, and the second scanning signal can turn on or off the transmission path between the first end and the second end of the data writing module 16. The valid pulse of the second scanning signal can turn on the transmission path between the first end and the second end of the data writing module 16, and the data signal provided by the data signal end VDATA is written into the gate N1 of the driving transistor M0. The invalid pulse of the second scanning signal can disconnect the transmission path between the first end and the second end of the data writing module 16, and the data signal provided by the data signal end VDATA is not written into the gate N1 of the driving transistor M0. Under the control of the second scanning signal, the data writing module 16 selectively writes the data signal into the gate N1 of the driving transistor M0.

[0046] In the compensation stage, the second scanning signal provided by the second scanning signal terminal S2 is an invalid pulse, so that the transmission path between the first end and the second end of the data writing module 16 is disconnected, and the data signal provided by the data signal terminal VDATA does not affect the potential of the gate N1, the first end N2 and the second end N3 of the driving transistor M0, ensuring that in the compensation stage, the Vth of the driving transistor M0 is pre-written into Vgs, realizing the association between Vgs and Vth.

[0047] The optional data writing module 16 includes a third transistor M3 , which is connected between the data signal terminal VDATA and the gate N1 of the driving transistor M0 , and a control terminal of the third transistor M3 is connected to the second scanning signal terminal S2 .

[0048] The third transistor M3 can be an NMOS transistor; in other embodiments, the third transistor can also be a PMOS transistor. The second scan signal provided by the second scan signal terminal S2 is a pulse signal, and the third transistor M3 is an NMOS transistor. The high level of the second scan signal is a valid pulse that can turn on the third transistor M3, and the low level of the second scan signal is an invalid pulse that can turn off the third transistor M3. When the third transistor M3 is turned on, the data signal is written to the gate N1 of the driving transistor M0. In the compensation stage, the second scan signal is an invalid pulse that turns off the third transistor M3. In the compensation stage, the first terminal N2 and the gate N1 of the driving transistor M0 are pvdd, and the second terminal N3 of the driving transistor M0 is charged to pvdd-Vth, and Vgs of the driving transistor M0 is pvdd-(pvdd-Vth)=Vth.

[0049] The working process of the optional pixel circuit 11 also includes: a data writing phase performed after the compensation phase; in the data writing phase, the data writing module 16 is turned on, and the first light emitting control module 13 and the compensation module 15 are turned off.

[0050] In the data writing stage, the first light signal provided by the first light signal terminal EM1 is an invalid pulse, so that the transmission path between the first end and the second end of the first light control module 13 is turned off; the first scan signal provided by the first scan signal terminal S1 is an invalid pulse, so that the transmission path between the first end and the second end of the compensation module 15 is turned off; the second scan signal provided by the second scan signal terminal S2 is a valid pulse, so that the transmission path between the first end and the second end of the data writing module 16 is turned on. Based on this, the data signal Vdata provided by the data signal terminal VDATA is written into the gate N1 of the driving transistor M0, so that the driving transistor M0 is turned on, the first end N2 of the driving transistor M0 is maintained at pvdd, and the second end N3 of the driving transistor M0 is maintained at pvdd-Vth. It can be seen that Vgs of the driving transistor M0 = Vdata-(pvdd-Vth).

[0051] The optional pixel circuit 11 further includes: a first capacitor C1 and a second capacitor C2; the first capacitor C1 is connected between the gate N1 and the second terminal N3 of the driving transistor M0; the second capacitor C2 is connected between the second terminal N3 of the driving transistor M0 and the first power supply voltage terminal PVDD. The ratio of the charge amount of the first capacitor C1 to the charge amount of the second capacitor C2 is less than 1:50.

[0052] In the compensation stage, the first voltage signal pvdd provided by the first power supply voltage terminal PVDD is written into the gate N1 of the driving transistor M0. In the data writing stage, the data signal Vdata provided by the data signal terminal VDATA is written into the gate N1 of the driving transistor M0. Then the gate N1 of the driving transistor M0 is converted to Vdata by pvdd, and the voltage increment of the gate N1 of the driving transistor M0 is (Vdata-pvdd)*[c1 / (c1+c2)]. The ratio of the charge amount c1 of the first capacitor C1 to the charge amount c2 of the second capacitor C2 is less than 1:50, then c1 is much smaller than c2, and the voltage increment of the gate N1 of the driving transistor M0 is very small and can be ignored. Based on this, the data writing stage is entered from the compensation stage, and under the coupling of the capacitor, the second terminal N3 of the driving transistor M0 maintains pvdd-Vth.

[0053] Figure 5 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present invention. Figure 5 As shown, the optional pixel circuit 11 also includes: a second light-emitting control module 17, which is connected between the second end N3 of the driving transistor M0 and the light-emitting element 12; the second light-emitting control module 17 is used to enable the driving module 14 to provide a driving current to the light-emitting element 12 when it is turned on; in the compensation stage, the second light-emitting control module 17 is turned off.

[0054] In this embodiment, the pixel circuit 11 includes a second light-emitting control module 17, a first end of the second light-emitting control module 17 is connected to the second end N3 of the driving transistor M0, a second end of the second light-emitting control module 17 is connected to the light-emitting element 12, and a control end of the second light-emitting control module 17 is connected to the second light-emitting signal end EM2. The second light-emitting signal provided by the second light-emitting signal end EM2 is a pulse signal, and the second light-emitting signal can turn on or off the transmission path between the first end and the second end of the second light-emitting control module 17. The valid pulse of the second light-emitting signal can turn on the transmission path between the first end and the second end of the second light-emitting control module 17, and the driving module 14 provides a driving current for the light-emitting element 12. The invalid pulse of the second light-emitting signal can disconnect the transmission path between the first end and the second end of the second light-emitting control module 17, and the light-emitting element 12 does not emit light. Under the control of the second light-emitting signal, the second light-emitting control module 17 selectively provides a driving current for the light-emitting element 12. In the compensation stage and the data writing stage, the second light-emitting signal provided by the second light-emitting signal end EM2 is an invalid pulse, which disconnects the transmission path between the first end and the second end of the second light-emitting control module 17, and does not affect the potential of the second end N3 of the driving transistor M0.

[0055] The optional second light emitting control module 17 includes a fourth transistor M4 , which is connected between the second terminal N3 of the driving transistor M0 and the light emitting element 12 , and a control terminal of the fourth transistor M4 is connected to the second light emitting signal terminal EM2 .

[0056] The fourth transistor M4 may be an NMOS transistor; in other embodiments, the fourth transistor may be a PMOS transistor. The second light emitting signal provided by the second light emitting signal terminal EM2 is a pulse signal, and the fourth transistor M4 is an NMOS transistor. The high level of the second light emitting signal is a valid pulse that can turn on the fourth transistor M4, and the low level of the second light emitting signal is an invalid pulse that can turn off the fourth transistor M4. When the fourth transistor M4 is turned on, it provides a driving current for the light emitting element 12.

[0057] In the compensation stage, the second light emitting signal is an invalid pulse to turn off the fourth transistor M4. In the compensation stage, the first terminal N2 and the gate N1 of the driving transistor M0 are pvdd, the second terminal N3 of the driving transistor M0 is charged to pvdd-Vth, and Vgs of the driving transistor M0 = pvdd-(pvdd-Vth) = Vth.

[0058] In the data writing stage, the second light emitting signal is an invalid pulse to turn off the fourth transistor M4. In the data writing stage, the second end N3 of the driving transistor M0 is maintained at pvdd-Vth.

[0059] The working process of the optional pixel circuit 11 includes: a non-light-emitting stage and a light-emitting stage; in the non-light-emitting stage, the second light-emitting control module 17 is turned off; in the light-emitting stage, the first light-emitting control module 13, the driving module 14 and the second light-emitting control module 17 are turned on, and the compensation module 15 is turned off. In the non-light-emitting stage, the second light-emitting signal provided by the second light-emitting signal terminal EM2 is an invalid pulse, so that the transmission path between the first terminal and the second terminal of the second light-emitting control module 17 is turned off, and the light-emitting element 12 does not emit light.

[0060] In the light-emitting stage, the first light-emitting signal provided by the first light-emitting signal terminal EM1 is a valid pulse, the first scan signal provided by the first scan signal terminal S1 is an invalid pulse, the second scan signal provided by the second scan signal terminal S2 is an invalid pulse, and the second light-emitting signal provided by the second light-emitting signal terminal EM2 is a valid pulse, so that the transmission path between the first and second ends of the compensation module 15 is disconnected, the transmission path between the first and second ends of the data writing module 16 is disconnected, the transmission path between the first and second ends of the first light-emitting control module 13 is turned on, and the transmission path between the first and second ends of the second light-emitting control module 17 is turned on. The gate N1 of the driving transistor M0 is kept at Vdata, then the driving transistor M0 is turned on, the driving module 14 provides a driving current to the light-emitting element 12, and the light-emitting element 12 emits light.

[0061] The optional pixel circuit 11 further includes: a first capacitor C1 and a second capacitor C2; the first capacitor C1 is connected between the gate N1 and the second terminal N3 of the driving transistor M0; the second capacitor C2 is connected between the second terminal N3 of the driving transistor M0 and the first power supply voltage terminal PVDD. The ratio of the charge amount of the first capacitor C1 to the charge amount of the second capacitor C2 is less than 1:50.

[0062] In the light-emitting stage, the first voltage signal pvdd of the first power supply voltage terminal PVDD is written into the first terminal N2 and the second terminal N3 of the driving transistor M0, and the second terminal N3 of the driving transistor M0 is raised. Based on the first capacitor C1, the potential of the gate N1 of the driving transistor M0 is also coupled and raised. Therefore, the Vgs of the driving transistor M0 remains unchanged as the Vgs in the data writing stage, that is, Vgs=Vdata-(pvdd-Vth). The potential of the second terminal N3 of the driving transistor M0 is equal to the sum of the voltage of N4 and PVSS. The voltage of the N4 node is the voltage Voled of the light-emitting element 12, so the voltage of N3 is Voled+PVSS, and the light-emitting element 12 emits light.

[0063] According to the driving current formula of the light emitting element 12, Id=k(Vgs-Vth) is obtained. 2 =K(Vdata-pvdd) 2 , eliminating the influence of Vth offset on the driving current of the light-emitting element 12, thereby improving the display effect.

[0064] Optionally, the compensation phase is performed in a part of the non-luminous phase. In the non-luminous phase, the pixel circuit 11 performs the compensation phase, so that the second terminal N3 of the driving transistor M0 is pvdd-Vth. In the non-luminous phase, the pixel circuit 11 also performs the data writing phase, so that the gate N1 of the driving transistor M0 is Vdata.

[0065] Figure 6 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present invention. Figure 6 As shown, the optional pixel circuit 11 also includes: an initialization module 18, which is connected between the initialization signal terminal VREF and the light-emitting element 12; the working process of the pixel circuit 11 also includes: an initialization stage; in the initialization stage, the initialization module 18 is turned on, and the initialization signal terminal VREF provides an initialization signal for the light-emitting element 12.

[0066] In this embodiment, the pixel circuit 11 includes an initialization module 18, a first end of the initialization module 18 is connected to the initialization signal end VREF, a second end of the initialization module 18 is connected to the light emitting element 12, and a control end of the initialization module 18 is connected to the third scan signal end S3. The third scan signal provided by the third scan signal end S3 is a pulse signal, and the third scan signal can turn on or off the transmission path between the first end and the second end of the initialization module 18. The valid pulse of the third scan signal can turn on the transmission path between the first end and the second end of the initialization module 18, and then initialize the light emitting element 12. The invalid pulse of the third scan signal can disconnect the transmission path between the first end and the second end of the initialization module 18, and then the light emitting element 12 is not initialized. Under the control of the third scan signal, the initialization module 18 selectively initializes the light emitting element 12. In the initialization stage, the third scan signal provided by the third scan signal end S3 is a valid pulse, which turns on the transmission path between the first end and the second end of the initialization module 18, and the third scan signal initializes the light emitting element 12.

[0067] The optional initialization module 18 includes a fifth transistor M5 , which is connected between the initialization signal terminal VREF and the light emitting element 12 , and a control terminal of the fifth transistor M5 is connected to the third scan signal terminal S3 .

[0068] The fifth transistor M5 can be an NMOS transistor; in other embodiments, the fifth transistor can be a PMOS transistor. The third scan signal provided by the third scan signal terminal S3 is a pulse signal, and the fifth transistor M5 is an NMOS transistor. The high level of the third scan signal is a valid pulse that can turn on the fifth transistor M5, and the low level of the third scan signal is an invalid pulse that can turn off the fifth transistor M5. When the fifth transistor M5 is turned on, the initialization signal Vref provided by the initialization signal terminal VREF initializes the light emitting element 12.

[0069] The initialization phase can be optionally performed in part of the non-luminous phase. In the non-luminous phase, the second luminous control module 17 is turned off, and the pixel circuit 11 performs the initialization phase, which will not affect the potential of the three terminals of the driving transistor M0, nor will it affect the normal luminescence of the luminous element 12 in the luminous phase.

[0070] At least part of the time period of the optional compensation phase may overlap with at least part of the time period of the initialization phase. The compensation phase and the initialization phase may be performed simultaneously, that is, the threshold voltage of the driving transistor M0 is compensated and the light emitting element 12 is initialized at the same time. In other embodiments, part of the time period of the optional compensation phase may overlap with part of the time period of the initialization phase.

[0071] The optional first scan signal terminal S1 is multiplexed as the third scan signal terminal S3. When the first scan signal terminal S1 is multiplexed as the third scan signal terminal S3, the number of signal lines for driving the pixel circuit 11 can be reduced, and a narrow border can be achieved.

[0072] Figure 7 It is a timing schematic diagram of the pixel circuit provided by an embodiment of the present invention. Combining Figure 6 and Figure 7 as shown, the working process of the pixel circuit 11 includes a compensation stage T1, a data writing stage T2, and a light emitting stage T3 that are sequentially executed.

[0073] Before T1, in stage T0, for the display of the previous frame, the light emitting element 12 emits light.

[0074] In stage T1, M0, M1, M2, and M5 are turned on, M3 and M4 are turned off, the voltage of N1 is equal to the voltage of N2 which is pvdd, the N3 node is charged to pvdd - Vth, such that Vgs = pvdd - (pvdd - Vth) = Vth, and then M0 is turned off.

[0075] In stage T2, M0 and M3 are turned on, M1, M2, M4, and M5 are turned off, the voltage of N1 changes from pvdd to Vdata, the voltage increment of N1 is (Vdata - pvdd)*[c1 / (c1 + c2)], and since c1 << c2, the voltage increment of N1 is very small and hardly affects the voltage of the N3 node, so N3 remains pvdd - Vth, and Vgs = Vdata - (pvdd - Vth).

[0076] In stage T3, M0, M1, and M4 are turned on, M2, M3, and M5 are turned off. At this time, the potential of the N3 node is raised, and the potential of the N1 node is also raised through coupling by C1. So the Vgs of M0 basically remains unchanged, that is, Vgs = Vdata - (pvdd - Vth), the voltage of the N3 node is equal to the voltage of the N4 node which is Voled + PVSS, and the light emitting element 12 emits light.

[0077] According to the driving current formula of the light emitting element 12, it can be known that Id = k(Vgs - Vth) 2 = K(Vdata - pvdd) 2 , eliminating the influence of Vth offset on the driving current of the light emitting element 12, thereby improving the display effect.

[0078] Figure 8 It is a schematic diagram of another display panel provided by an embodiment of the present invention, Fig. 9 It is a schematic diagram of another display panel provided by an embodiment of the present invention. As Figure 8 and Fig. 9As shown, the optional display panel includes a display area 21 and a non-display area 22; the display area 21 includes a plurality of rows of pixels 23 arranged along a column direction, and the pixels 23 include a pixel circuit and a light-emitting element; the non-display area 22 includes a first driving circuit 24, and the first driving circuit 24 includes a cascaded first driving unit 25; the first-level first driving unit 25 provides a first driving signal to the control terminal S2 of the data writing module of a row of pixels 23.

[0079] In this embodiment, the display area 21 includes a plurality of rows of pixels 23 arranged along the column direction, and the plurality of rows of pixels 23 are sequentially marked as the first row P1, the second row P2, the third row P3, and so on along the column direction. The first driving circuit 24 includes cascaded first driving units 25, and the cascade direction of the cascaded first driving units 25 is parallel to the column direction. The cascaded first driving units 25 along the column direction are sequentially marked as the first stage scan1, the second stage scan2, the third stage scan3, and so on. The first stage first driving unit 25 provides a first driving signal to the control terminal S2 of the data writing module of a row of pixels 23.

[0080] Combination Figure 6 As shown, the control terminal S2 of the data writing module 16 is the second scanning signal terminal S2 connected to the control terminal of the third transistor M3, and the first driving signal is the second scanning signal. That is, the first driving unit 25 provides the second scanning signal to the third transistor M3 for data writing in a row of pixels 23, so as to control the third transistor M3 to turn on so that the pixel circuit 11 enters the data writing stage, or to control the third transistor M3 to turn off.

[0081] Optionally, the first driving unit 25 further provides a first driving signal to the control terminal S1 of the compensation module of the next row of pixels 23. Figure 6 As shown, the control terminal S1 of the compensation module is the first scanning signal terminal S1 connected to the control terminal of the second transistor M2. The first driving signal is multiplexed into the first scanning signal of the next row, and the first driving unit 25 provides the first scanning signal to the second transistor M2 used for compensation in the next row of pixels 23 to control the second transistor M2 to turn on so that the pixel circuit 11 enters the compensation stage, or to control the second transistor M2 to turn off.

[0082] As described above, the first driving unit 25 provides the first driving signal to two adjacent rows of pixels 23, and the first driving unit 25 adopts a 1-drive-2 design, which reduces the number of first driving units 25 in the non-display area 22 and realizes a narrow frame.

[0083] refer to Figure 8 and Fig. 9As shown, the optional display panel includes a display area 21 and a non-display area 22; the display area 21 includes a plurality of rows of pixels 23 arranged along a column direction, and the pixels 23 include a pixel circuit and a light-emitting element; the non-display area 22 includes a second driving circuit 26, and the second driving circuit 26 includes a cascaded second driving unit 27; the first-level second driving unit 27 provides a first light-emitting signal to the control terminal EM2 of the second light-emitting control module of a row of pixels 23.

[0084] In this embodiment, the display area 21 includes a plurality of rows of pixels 23 arranged along the column direction, and the plurality of rows of pixels 23 are sequentially marked as the first row P1, the second row P2, the third row P3, and so on along the column direction. The second driving circuit 26 includes cascaded second driving units 27, and the cascade direction of the cascaded second driving units 27 is parallel to the column direction. The second driving units 27 cascaded along the column direction are sequentially marked as the first stage emit1, the second stage emit2, the third stage emit3, and so on. The first stage second driving unit 27 provides a second driving signal to the control terminal EM2 of the second light emitting control module of a row of pixels 23.

[0085] Combination Figure 6 As shown, the control terminal EM2 of the second light-emitting control module is the second light-emitting signal terminal EM2 connected to the control terminal of the fourth transistor M4, and the second driving signal is the second light-emitting signal. That is, the first-level second driving unit 27 provides the second light-emitting signal to the fourth transistor M4 used for controlling light emission in a row of pixels 23, so as to control the fourth transistor M4 to turn on so that the pixel circuit 11 enters the light-emitting stage, or to control the fourth transistor M4 to turn off so that the pixel circuit 11 enters the non-light-emitting stage.

[0086] The optional first-level second driving unit 27 further provides a second driving signal to the control terminal EM1 of the first light emitting control module of the next row of pixels 23 .

[0087] Combination Figure 6 As shown, the control terminal EM1 of the first light-emitting control module is the first light-emitting signal terminal EM1 connected to the control terminal of the first transistor M1. The second driving signal is multiplexed into the first light-emitting signal of the next row, and the first-level second driving unit 27 provides the first light-emitting signal to the first transistor M1 for controlling light emission in the next row of pixels 23 to control the first transistor M1 to turn on or off.

[0088] As described above, the first-level second driving unit 27 provides the second driving signal to two adjacent rows of pixels 23, and the first-level second driving unit 27 adopts a 1-drive-2 design, which reduces the number of second driving units 27 in the non-display area 22 and realizes a narrow frame.

[0089] Fig.10 is a schematic diagram of a pixel provided by an embodiment of the present invention. Fig.10As shown, the display panel includes pixels in the i-th row. The control end of the data writing module 16 of the pixels in the i-th row receives the first driving signal provided by the i-th first driving unit Scan-i, and the control end of the compensation module 15 of the pixels in the i-th row receives the first driving signal provided by the i-1-th first driving unit Scan-(i-1). The control end of the second light emitting control module 17 of the pixels in the i-th row receives the second driving signal provided by the i-th second driving unit Emit-i, and the control end of the first light emitting control module 13 of the pixels in the i-th row receives the second driving signal provided by the i-1-th second driving unit Emit-(i-1).

[0090] Based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the aforementioned display panel. The display panel may be an organic light emitting display panel or a micro LED display panel, but is not limited thereto. Fig.11 is a schematic diagram of a display device provided by an embodiment of the present invention, such as Fig.11 As shown, the display device 1 can be optionally applied to electronic devices such as smart phones, tablet computers, etc. It can be understood that the above embodiment only provides a partial structure of the display panel and the pixel circuit, and the display panel also includes other structures, which will not be described one by one here.

[0091] In the embodiment of the present invention, a pixel circuit is provided that can compensate for the threshold voltage of the driving transistor, thereby eliminating the influence of the threshold voltage drift of the driving transistor on the display and improving the display effect. Specifically, the Vth of the driving transistor is stored in Vgs in advance before the light-emitting stage; when the light-emitting stage comes, due to the coupling of the capacitor, Vgs remains unchanged, that is, Vth is still in Vgs, according to the driving current formula of the light-emitting element Id = k (Vgs-Vth) 2 , offsetting Vth, thus eliminating the influence of Vth offset on the driving current of the light-emitting element and improving the uniformity of the display effect.

[0092] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Pixel circuit and light emitting element; The pixel circuit includes a first light emitting control module, a driving module and a compensation module; The driving module is used to provide a driving current for the light emitting element, and the driving module includes a driving transistor; The first light emitting control module is connected between a first power supply voltage terminal and a first terminal of the driving transistor, and a second terminal of the driving transistor is connected to the light emitting element; One end of the compensation module is connected to the first end of the driving transistor, and the working process of the pixel circuit includes a compensation stage, in which the first light-emitting control module, the driving module and the compensation module are turned on to compensate for the threshold voltage of the driving transistor; The pixel circuit further includes: a first capacitor and a second capacitor; The first capacitor is connected between the gate and the second end of the driving transistor; The second capacitor is connected between the second terminal of the driving transistor and the first power supply voltage terminal.

2. The display panel according to claim 1, characterized in that: The first light emitting control module comprises a first transistor, the first transistor is connected between the first power supply voltage terminal and the first terminal of the driving transistor, and the control terminal of the first transistor is connected to the first light emitting signal terminal; The compensation module includes a second transistor, the second transistor is connected between the gate of the driving transistor and the first end, and the control end of the second transistor is connected to the first scanning signal end.

3. The display panel according to claim 1, characterized in that: The pixel circuit further includes: a data writing module, the data writing module being connected between the data signal terminal and the gate of the driving transistor; The data writing module is used to enable the data signal terminal to provide a data signal to the gate of the driving transistor when it is turned on; During the compensation phase, the data writing module is turned off.

4. The display panel according to claim 3, characterized in that: The data writing module comprises a third transistor, the third transistor is connected between the data signal terminal and the gate of the driving transistor, and the control terminal of the third transistor is connected to the second scanning signal terminal.

5. The display panel according to claim 3, characterized in that: The operation process of the pixel circuit further includes: a data writing phase performed after the compensation phase; In the data writing stage, the data writing module is turned on, and the first light emitting control module and the compensation module are turned off.

6. The display panel according to claim 1, characterized in that: The pixel circuit further includes: a second light emitting control module connected between the second end of the driving transistor and the light emitting element; The second light emitting control module is used to enable the driving module to provide the driving current to the light emitting element when it is turned on; During the compensation phase, the second light emitting control module is turned off.

7. The display panel according to claim 6, characterized in that: The second light emitting control module comprises a fourth transistor, the fourth transistor is connected between the second end of the driving transistor and the light emitting element, and the control end of the fourth transistor is connected to the second light emitting signal end.

8. The display panel according to claim 6, characterized in that: The working process of the pixel circuit includes: a non-luminous phase and a luminous phase; In the non-light-emitting stage, the second light-emitting control module is turned off; In the light-emitting stage, the first light-emitting control module, the driving module and the second light-emitting control module are turned on, and the compensation module is turned off.

9. The display panel according to claim 8, characterized in that: The compensation phase is performed during a partial period of the non-light emitting phase.

10. The display panel according to claim 2, characterized in that: The pixel circuit further includes: an initialization module connected between the initialization signal terminal and the light emitting element; The working process of the pixel circuit also includes: an initialization stage; In the initialization stage, the initialization module is turned on, and the initialization signal terminal provides an initialization signal to the light emitting element.

11. The display panel according to claim 10, characterized in that: The initialization module includes a fifth transistor, the fifth transistor is connected between the initialization signal terminal and the light emitting element, and the control terminal of the fifth transistor is connected to the third scanning signal terminal.

12. The display panel according to claim 11, characterized in that: The first scanning signal terminal is multiplexed as the third scanning signal terminal.

13. The display panel according to claim 10, characterized in that: At least a partial time period of the compensation phase overlaps with at least a partial time period of the initialization phase.

14. The display panel according to claim 1, characterized in that: A ratio of the charge amount of the first capacitor to the charge amount of the second capacitor is less than 1:

50.

15. The display panel according to claim 1, characterized in that: The pixel circuit includes at least one transistor, and the transistor is an NMOS transistor or a PMOS transistor.

16. The display panel according to claim 1, characterized in that: The first power supply voltage terminal provides a high level signal.

17. The display panel according to claim 3, characterized in that: The display panel includes a display area and a non-display area; The display area includes a plurality of rows of pixels arranged along a column direction, and the pixels include the pixel circuit and the light-emitting element; The non-display area includes a first driving circuit, and the first driving circuit includes a cascaded first driving unit; The first driving unit of the first level provides a first driving signal to the control end of the data writing module of a row of pixels.

18. The display panel according to claim 17, characterized in that: The first driving unit of the first level further provides the first driving signal to the control terminal of the compensation module of the pixels in the next row.

19. The display panel according to claim 6, characterized in that: The display panel includes a display area and a non-display area; The display area includes a plurality of rows of pixels arranged along a column direction, and the pixels include the pixel circuit and the light-emitting element; The non-display area includes a second driving circuit, and the second driving circuit includes a cascaded second driving unit; The first-level second driving unit provides a second driving signal to the control end of the second light emitting control module of a row of pixels.

20. The display panel according to claim 19, characterized in that: The first-level second driving unit further provides the second driving signal to the control terminal of the first light emitting control module of the pixels in the next row.

21. A display device, characterized in that: A display panel comprising any one of claims 1-20.

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