Display device

Abstract

A display device includes: pixels each connected to a corresponding scan line among scan lines, a corresponding data line among data lines, and a corresponding emission control line among emission control lines; and an emission driver supplying an emission control signal to the emission control line. During an active region of a frame, the transmission control signals include a first transmission control signal having a first width and a second transmission control signal having a second width.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0142363, filed on October 23, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure generally relates to a display device and a method of driving the display device. Background Art

[0003] As information technology develops, the importance of display devices, which are connecting media between users and information, increases. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0004] In recent display devices, it is desired to provide users with a high-speed driving function of images that change at a high frame frequency and a low-speed driving function of images that change at a low frame frequency. It is desired to provide images with similar brightness and minimize flicker when the display device is driven at high and low frequencies. Summary of the invention

[0005] The embodiment provides a display device which can minimize a brightness difference in one frame and a method of driving the display device.

[0006] Embodiments also provide a display device that can minimize a brightness difference when the display device is driven at a relatively high frequency and a relatively low frequency, and a method of driving the display device.

[0007] In an embodiment of the present disclosure, a display device is provided, comprising: pixels, each of which is connected to a corresponding scan line among the scan lines, a corresponding data line among the data lines, and a corresponding emission control line among the emission control lines; and an emission driver, supplying an emission control signal to the emission control line, wherein, during an effective area of ​​a frame, the emission control signal comprises a first emission control signal having a first width and at least one second emission control signal having a second width.

[0008] In an embodiment, the emission driver may supply a first emission control signal during a writing period in the active region in which a data signal is supplied to a pixel, and supply a second emission control signal during a period other than the writing period in the active region.

[0009] In an embodiment, the second width may be set to a relatively wide width compared to the first width.

[0010] In an embodiment, the emission driver may further supply a third emission control signal having a third width during a period other than the writing period in the active region.

[0011] In an embodiment, the third width may be set to a relatively wide width compared to the first width, and the second width and the third width may be set to widths equal to or different from each other.

[0012] In an embodiment, the second emission control signal may be supplied as a second active area emission control signal in the active area, and the third emission control signal may be supplied as a fourth active area emission control signal in the active area.

[0013] In an embodiment, the second emission control signal may be supplied as a second active area emission control signal in the active area, and the third emission control signal may be supplied as a third active area emission control signal in the active area.

[0014] In an embodiment, the display device may further include: a timing controller to control the emission driver. The timing controller may include a storage unit to store information of the first width, the second width, and the third width.

[0015] In an embodiment, the timing controller may further include: a brightness determiner that determines brightness in units of one frame corresponding to the input data.

[0016] In an embodiment, the timing controller may change the position at which the second emission control signal and the third emission control signal are supplied corresponding to the brightness change.

[0017] In an embodiment, when the brightness of one frame is determined to be relatively high brightness, the timing controller may supply the second emission control signal as the second active area emission control signal in the active area and supply the third emission control signal as the third active area emission control signal in the active area.

[0018] In an embodiment, when the brightness of one frame is determined to be relatively low brightness, the timing controller may supply the second emission control signal as the third active area emission control signal in the active area and supply the third emission control signal as the fourth active area emission control signal in the active area.

[0019] In an embodiment, the timing controller may change the second width of the second emission control signal and the third width of the third emission control signal corresponding to the brightness.

[0020] In an embodiment, the timing controller may increase the width of the second emission control signal and the third emission control signal when the brightness of a frame is determined to be relatively high brightness, and reduce the width of the second emission control signal and the third emission control signal when the brightness of a frame is determined to be relatively low brightness.

[0021] In an embodiment, the second width may be set to a width narrower than the first width, and the emission driver may supply the first emission control signal at a predetermined period during an active region and a blank region of one frame.

[0022] In an embodiment, the display device may further include a timing controller controlling the emission driver, and the timing controller may change a position at which the second emission control signal is supplied in units of at least one frame.

[0023] In an embodiment of the present disclosure, a method for driving a display device is provided, the display device including pixels whose emission time is controlled corresponding to an emission control signal, the method comprising: supplying an emission control signal having a first width and an emission control signal having a second width different from the first width during an effective area of ​​a frame; and supplying an emission control signal having the first width during a blank area of ​​a frame.

[0024] In an embodiment, the second width may be set to a relatively wide width compared to the first width.

[0025] In an embodiment, the length of the second width may be changed corresponding to the brightness of one frame.

[0026] In an embodiment, the emission control signal having the first width may be supplied at a predetermined period in the effective area and the blank area. The second width may be set to a width narrower than the first width, and the position at which the emission control signal having the second width is supplied may be changed in units of at least one frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

[0028] Figure 1 is a diagram illustrating an embodiment of a display device according to the present disclosure.

[0029] Figure 2 It is a graphic Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0030] Figure 3 is a diagram illustrating an embodiment of a pixel according to the present disclosure.

[0031] Figure 4 The diagram shows the drive during the write period. Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0032] Figure 5 The diagram shows the driving during the sustain period. Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0033] Figure 6 is a diagram illustrating brightness for one frame period.

[0034] Fig. 7A and Figure 7B is a diagram illustrating an embodiment of an emission control signal supplied during an active region.

[0035] Figure 8 It is a graphic Figure 1 An embodiment of a timing controller is shown in FIG.

[0036] Fig. 9 is a diagram illustrating the brightness of a display device for one frame period.

[0037] Fig.10 is a diagram illustrating an embodiment of a method of setting a width of an emission control signal according to the present disclosure.

[0038] Fig.11 is a graph illustrating flicker characteristics of an embodiment of the present disclosure and a comparative example.

[0039] Fig.12 is a graph illustrating luminance difference characteristics of an embodiment of the present disclosure and a comparative example.

[0040] Fig.13 It is a graphic Figure 1 An embodiment of a timing controller is shown in FIG.

[0041] FIG. 14A to FIG. 16B is a diagram illustrating an embodiment of a disabled emission control signal corresponding to the control of a timing controller.

[0042] Fig.17A and Fig. 17B is a diagram illustrating an embodiment of an emission control signal supplied during one frame period. DETAILED DESCRIPTION

[0043] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described in the specification.

[0044] Parts not related to the description will be omitted to clearly describe the present disclosure, and throughout the specification, the same or similar constituent elements will be referred to by the same reference numerals. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0045] In addition, for better understanding and ease of description, the size and thickness of each component illustrated in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clear description, the thickness of several parts and regions is exaggerated.

[0046] In the description, the expression "equal" may mean "substantially equal." That is, it may mean equal to the extent that those skilled in the art can understand equality. Other expressions may be expressions in which "substantially" is omitted.

[0047] Some embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections or other electronic circuits. This can be formed by semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, blocks, units and / or modules are programmed and controlled by software to perform the various functions discussed in the present disclosure, and can be optionally driven by firmware and / or software. In addition, each block, each unit and / or each module can be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions of blocks, units and / or modules and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions of blocks, units and / or modules. In some embodiments, blocks, units and / or modules can be physically divided into two or more discrete blocks, two or more units and / or two or more modules without departing from the scope of the present disclosure. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, more complex units and / or more complex modules without departing from the scope of the present disclosure.

[0048] The term "connection" between two components may include both electrical connection and physical connection, but the present disclosure is not necessarily limited thereto. For example, the term "connection" used based on a circuit diagram may mean electrical connection, and the term "connection" used based on a cross-sectional view or a plan view may mean physical connection.

[0049] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0050] In the accompanying drawings, dimensions may be exaggerated for ease of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0051] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense, unless specifically defined as such herein.

[0053] The present disclosure is not limited to the embodiments disclosed below, and can be implemented in various forms. Each embodiment disclosed below can be embodied independently, or combined with at least one other embodiment before being embodied.

[0054] Figure 1 is a diagram illustrating an embodiment of a display device according to the present disclosure. Figure 2 It is a graphic Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0055] refer to Figure 1 , the display device 100 in the embodiment of the present disclosure may include a pixel unit 110 (or a panel), a timing controller 120 , a scan driver 130 , a data driver 140 , an emission driver 150 , and a power supply unit 160 .

[0056] The display device 100 can display images at various image refresh rates (e.g., driving frequency or screen refresh rate) according to driving conditions. The image refresh rate means the frequency at which a data signal is written to a driving transistor of a pixel PX. In an embodiment, for example, the image refresh rate may also be referred to as a screen scan rate or a screen refresh rate, and indicates the frequency at which a display image is reproduced within one second.

[0057] In an embodiment, the output frequency of the data driver 140 for one horizontal line (for example, pixels PX connected to the same scan line may be classified as one horizontal line (or pixel line)) and / or the output frequency of the second scan driver 134 outputting the second scan signal (or write scan signal) may be determined corresponding to the image refresh rate. In an embodiment, for example, the image refresh rate for driving a moving image may be a frequency of about 60 Hertz (Hz) or higher (for example, about 120 Hz or about 240 Hz, etc.).

[0058] In an embodiment, for example, the display device 100 may display images corresponding to various image refresh rates of about 1 Hz to about 240 Hz. However, this is merely exemplary, and the display device 100 may also display images at an image refresh rate of about 240 Hz or higher (e.g., about 480 Hz).

[0059] The pixel unit 110 may include pixels PX connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, fourth scan lines SL41, SL42, ... and SL4n, data lines DL1, DL2, ... and DLm, emission control lines EL1, EL2, ... and ELo, and power lines PL1, PL2, PL3, PL4 and PL5 (n, m and o are natural numbers greater than 2).

[0060] In an embodiment, a pixel PXij (refer to Figure 3 ) may be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk, and the j-th data line DLj (i is a positive integer less than n, j is a positive integer less than m, and k is a positive integer less than o). Here, k is a natural number equal to or less than i and greater than zero. In an embodiment, when each of the emission control lines EL1 to ELo is connected to the pixels PX disposed at one horizontal row, k may be a natural number equal to i. In an embodiment, when each of the emission control lines EL1 to ELo is connected to the pixels PX disposed at at least two horizontal rows, k may be a natural number less than i and greater than zero.

[0061] When the enabled first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX may be selected in units of horizontal rows, and each of the pixels PX selected by the enabled first scan signal may be supplied with a data signal from a data line (any one of DL1 to DLm) connected to each of the pixels PX. The pixels PX supplied with the data signal may generate light having a predetermined brightness corresponding to a voltage of the data signal.

[0062] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. At least one scan start signal and a clock signal required to drive the scan driver 130 may be included in the scan driving signal SCS. The scan driver 130 may generate an enabled first scan signal, an enabled second scan signal, an enabled third scan signal, and an enabled fourth scan signal while shifting the scan start signal corresponding to the clock signal.

[0063] To this end, the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Figure 2 At least some of the scan drivers 132, 134, 136 and 138 may be integrated into one driving circuit or one module, etc., according to the design.

[0064] The first scan driver 132 may receive the first scan start signal FLM1 and generate an enabled first scan signal while shifting the first scan start signal FLM1 corresponding to the clock signal. The first scan driver 132 may sequentially supply the enabled first scan signal to the first scan lines SL11 to SL1n. In an embodiment, the first scan driver 132 may supply the enabled first scan signal during a writing period in an effective area of ​​one frame.

[0065] The second scan driver 134 may receive the second scan start signal FLM2 and generate an enabled second scan signal while shifting the second scan start signal FLM2 corresponding to the clock signal. The second scan driver 134 may sequentially supply the enabled second scan signal to the second scan lines SL21 to SL2n. In an embodiment, the second scan driver 134 may supply the enabled second scan signal during a writing period in an effective area of ​​one frame.

[0066] The third scan driver 136 may receive the third scan start signal FLM3 and generate an enabled third scan signal while shifting the third scan start signal FLM3 corresponding to the clock signal. The third scan driver 136 may sequentially supply the enabled third scan signal to the third scan lines SL31 to SL3n. In an embodiment, the third scan driver 136 may supply the enabled third scan signal during a writing period in an effective area of ​​one frame.

[0067] The fourth scan driver 138 may receive the fourth scan start signal FLM4 and generate an enabled fourth scan signal while shifting the fourth scan start signal FLM4 corresponding to the clock signal. The fourth scan driver 138 may sequentially supply the enabled fourth scan signal to the fourth scan lines SL41 to SL4n. In an embodiment, the fourth scan driver 138 may supply the enabled fourth scan signal during a write period in an effective area of ​​one frame. In an embodiment, the fourth scan driver 138 may supply the enabled fourth scan signal during a maintenance period included in an effective area and a blank area of ​​one frame.

[0068] In an embodiment, for example, the fourth scan driver 138 may perform one scan (i.e., supply at least one enabled fourth scan signal) during a write period of one frame, and perform at least one scan according to the image refresh rate during a maintenance period of one frame. When the image refresh rate is reduced (i.e., when the frame length is extended), the blank area of ​​one frame is extended, and thus the number of maintenance periods included in the blank area may increase. That is, when the image refresh rate is reduced, the number of times the operation of supplying the enabled fourth scan signal is repeated may increase.

[0069] Each of the enabled first scan signal, the enabled second scan signal, the enabled third scan signal, and the enabled fourth scan signal may be set to a gate-on voltage so that a transistor included in the pixel PX may be turned on. Figure 3 Each of the enabled first scan signal GW, the enabled second scan signal GC, the enabled third scan signal GI, and the enabled fourth scan signal GB of the P-type transistor shown in may be set to a relatively low level voltage.

[0070] exist Figure 2 , the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 are respectively connected to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4. However, the present disclosure is not limited thereto. In an embodiment, at least two scan lines (at least two of SL1, SL2, SL3, and SL4) among the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 may be driven by one scan driver.

[0071] The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required to drive the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. In an embodiment, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may supply a data signal in units of one horizontal period.

[0072] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. An emission start signal and a clock signal required to drive the emission driver 150 may be included in the emission driving signal ECS. The emission driver 150 may generate an inhibited emission control signal (or an emission control signal of a relatively high level) EM (reference signal) while shifting the emission start signal corresponding to the clock signal. Figure 3 ).

[0073] like Figure 2 As shown in , the emission driver 150 may receive the emission start signal EFLM and generate a disabled emission control signal EM while shifting the emission start signal EFLM corresponding to the clock signal. The emission driver 150 may sequentially supply the disabled emission control signal EM to the emission control lines EL1 to ELo. The disabled emission control signal EM may be set to a gate-off voltage so that the transistor included in the pixel PX may be turned off. In an embodiment, the gate-off voltage supplied to the pixel PX may be turned off. Figure 3 The disabled emission control signal EM of the P-type transistor shown in can be set to a relatively high level voltage.

[0074] In an embodiment, the emission driver 150 may supply the prohibited emission control signal EM during the write period and the maintenance period of one frame. In an embodiment, for example, the emission driver 150 may perform one scan during the write period of one frame, and perform at least one scan according to the image refresh rate during the maintenance period of one frame. When the image refresh rate is reduced (that is, when the frame length is extended), the blank area of ​​one frame is extended, and thus the number of maintenance periods included in the blank area may increase. That is, when the image refresh rate is reduced, the number of times the operation of supplying the prohibited emission control signal EM is repeated may increase.

[0075] The timing controller 120 may receive input data Din and a control signal CS from a host system through an interface. In an embodiment, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (“GPU”), a central processing unit (“CPU”), and an application processor (“AP”) included in the host system. Various signals including a clock signal may be included in the control signal CS.

[0076] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0077] The timing controller 120 may rearrange the input data Din to be suitable for the specification of the display device 100. In addition, the timing controller 120 may generate output data Dout by correcting the input data Din, and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din corresponding to an optical measurement result measured during processing.

[0078] The power supply unit 160 may generate various power supplies required to drive the display device 100. In an embodiment, the power supply unit 160 may generate a first driving power supply VDD, a second driving power supply VSS, a first initialization power supply Vint1, a second initialization power supply Vint2, and a bias power supply Vbias.

[0079] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that is supplied with a driving current from the pixel PX. During a period in which the pixel PX is set to be in an emission state, the first driving power source VDD may be set to a voltage higher than a voltage of the second driving power source VSS.

[0080] The first initialization power source Vint1 may be a power source for initializing the gate electrode of the driving transistor included in each of the pixels PX. The first initialization power source Vint1 may be set to a voltage lower than the voltage of the data signal. The second initialization power source Vint2 may be a power source for initializing the light emitting element LD included in each of the pixels PX (refer to Figure 3 ). The second initialization power supply Vint2 may be set to a voltage that turns off the light emitting element LD. The bias power supply Vbias may be a power supply for applying a conduction bias voltage to a driving transistor included in each of the pixels PX.

[0081] The first driving power VDD generated by the power supply unit 160 may be supplied to the first power line PL1, the second driving power VSS generated by the power supply unit 160 may be supplied to the second power line PL2, the first initialization power Vint1 generated by the power supply unit 160 may be supplied to the third power line PL3, the second initialization power Vint2 generated by the power supply unit 160 may be supplied to the fourth power line PL4, and the bias power Vbias generated by the power supply unit 160 may be supplied to the fifth power line PL5. The first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, and the fifth power line PL5 may be commonly connected to the pixel PX, but the present disclosure is not limited thereto.

[0082] In an embodiment, the first power line PL1 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the fifth power line PL5 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. That is, in an embodiment of the present disclosure, the pixel PX may be connected to any one of the multiple power lines of the first power line PL1, any one of the multiple power lines of the second power line PL2, any one of the multiple power lines of the third power line PL3, any one of the multiple power lines of the fourth power line PL4, and any one of the multiple power lines of the fifth power line PL5.

[0083] In an embodiment of the present disclosure, the display device 100 may include a flat display device, a bent display device in which a portion of the pixel unit 110 can be bent, a flexible display device in which a portion of the pixel unit 110 can be folded or bent, and a stretchable display device in which a portion of the pixel unit 110 can be expanded / contracted.

[0084] In an embodiment of the present disclosure, the display device 100 is a device that displays a moving image or a still image, and may include portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), smart watches, watch phones, portable multimedia players ("PMPs"), navigation systems, and ultra mobile computers ("UMPCs"). In an embodiment of the present disclosure, the display device 100 may include electronic devices such as televisions, notebook computers, monitors, billboards, and Internet of Things ("IoT") devices.

[0085] Figure 3 is a diagram illustrating an embodiment of a pixel according to the present disclosure. Figure 3 , a pixel PXij disposed on an i-th horizontal row and a j-th vertical column will be illustrated.

[0086] refer to Figure 3 , the pixel PXij in the embodiment of the present disclosure may be connected to the corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk and DLj. In an embodiment, for example, the pixel PXij may be connected to the i-th first scan line SL1i (hereinafter also referred to as the first scan line SL1i), the i-th second scan line SL2i (hereinafter also referred to as the second scan line SL2i), the i-th third scan line SL3i (hereinafter also referred to as the third scan line SL3i), the i-th fourth scan line SL4i (hereinafter also referred to as the fourth scan line SL4i), the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXij may be further connected to the first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4 and the fifth power line PL5.

[0087] The pixel PXij in the embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0088] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. In an embodiment, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the seventh transistor M7, the third node N3, the first transistor M1, the second node N2, and the sixth transistor M6, and the second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0089] The light emitting element LD may be selected as an organic light emitting diode ("OLED"). In addition, the light emitting element LD may be selected as an inorganic light emitting diode ("LED") such as a micro LED or a quantum dot LED. In addition, the light emitting element LD may be an element composed of a combination of an organic material and an inorganic material. Figure 3 In the embodiment, the pixel PXij is shown to include a single light emitting element LD. However, in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series / parallel.

[0090] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor Cst.

[0091] A first electrode of the first transistor M1 (or driving transistor) may be connected to the second node N2, and a second electrode of the first transistor M1 may be connected to the third node N3. In addition, a gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1.

[0092] The second transistor M2 may be connected between the jth data line DLj and the second node N2. In addition, the gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. When the enabled first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned on to electrically connect the jth data line DLj and the second node N2 to each other.

[0093] The third transistor M3 may be connected between the first node N1 and the third node N3. In addition, the gate electrode of the third transistor M3 may be electrically connected to the second scan line SL2i. When the enabled second scan signal GC is supplied to the second scan line SL2i, the third transistor M3 may be turned on to electrically connect the first node N1 and the third node N3 to each other. That is, when the third transistor M3 is turned on, the first transistor M1 may be connected in a diode form.

[0094] A first electrode of the fourth transistor M4 may be connected to the first node N1, and a second electrode of the fourth transistor M4 may be electrically connected to the third power line PL3. In addition, a gate electrode of the fourth transistor M4 may be electrically connected to the third scan line SL3i. When the enabled third scan signal GI is supplied to the third scan line SL3i, the fourth transistor M4 may be turned on to supply the voltage of the first initialization power supply Vint1 to the first node N1.

[0095] The first electrode of the fifth transistor M5 may be electrically connected to the first electrode of the light emitting element LD, and the second electrode of the fifth transistor M5 may be electrically connected to the fourth power line PL4. In addition, the gate electrode of the fifth transistor M5 may be electrically connected to the fourth scan line SL4i. When the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, the fifth transistor M5 may be turned on to supply the voltage of the second initialization power supply Vint2 to the first electrode of the light emitting element LD.

[0096] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitor of the light emitting element LD is discharged (or removed), accidental micro-emission can be prevented. Therefore, the black performance capability of the pixel PXij can be improved.

[0097] A first electrode of the sixth transistor M6 may be electrically connected to the first power line PL1, and a second electrode of the sixth transistor M6 may be connected to the second node N2. In addition, a gate electrode of the sixth transistor M6 may be electrically connected to the kth emission control line ELk. The sixth transistor M6 may be turned off when a disabled emission control signal EM is supplied to the kth emission control line ELk, and turned on when an enabled emission control signal EM is supplied to the kth emission control line ELk.

[0098] The seventh transistor M7 may be connected between the third node N3 and the first electrode of the light emitting element LD. In addition, the gate electrode of the seventh transistor M7 may be electrically connected to the kth emission control line ELk. The seventh transistor M7 may be turned off when the disabled emission control signal EM is supplied to the kth emission control line ELk, and turned on when the enabled emission control signal EM is supplied to the kth emission control line ELk.

[0099] A first electrode of the eighth transistor M8 (or the bias transistor) may be electrically connected to the fifth power line PL5, and a second electrode of the eighth transistor M8 may be connected to the second node N2. In addition, a gate electrode of the eighth transistor M8 may be electrically connected to the fourth scan line SL4i. When the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, the eighth transistor M8 may be turned on to electrically connect the fifth power line PL5 and the second node N2 to each other.

[0100] The storage capacitor Cst may be connected between the first power line PL1 and the first node N1. The storage capacitor Cst may store a voltage applied to the first node N1.

[0101] exist Figure 3 In the figure, the first to eighth transistors M1 to M8 are implemented by P-type transistors. However, the present disclosure is not limited thereto. Some transistors (eg, M3 and M4) among the first to eighth transistors M1 to M8 may be implemented by N-type transistors.

[0102] Figure 4 The diagram shows the drive during the write period. Figure 3 The writing period WP may be included in the effective area of ​​the frame.

[0103] refer to Figure 3 and Figure 4, the writing period WP may include a first period P1, a second period P2, a third period P3, and a fourth period P4. The first period P1 to the third period P3 may be set as non-emission periods, and the fourth period P4 may be set as an emission period.

[0104] During the first period P1 to the third period P3, the disabled emission control signal EM may be supplied to the kth emission control line ELk. When the disabled emission control signal EM is supplied to the kth emission control line ELk, the sixth transistor M6 and the seventh transistor M7 may be turned off. When the sixth transistor M6 and the seventh transistor M7 are turned off, the electrical connection between the first power line PL1 and the light emitting element LD may be blocked, and thus, the light emitting element LD may be set to be in a non-emission state.

[0105] During the first period P1, the enabled third scan signal GI may be supplied to the third scan line SL3i. When the enabled third scan signal GI is supplied to the third scan line SL3i, the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, the voltage of the first initialization power supply Vint1 of the third power line PL3 may be supplied to the first node N1. When the voltage of the first initialization power supply Vint1 is supplied to the first node N1, the first transistor M1 may be set to be in a strong on bias state.

[0106] During the second period P2, the enabled second scan signal GC may be supplied to the second scan line SL2i, and thus, the third transistor M3 may be turned on. When the third transistor M3 is turned on, the first transistor M1 may be diode-connected.

[0107] In the writing region P_W overlapping with the second period P2, the enabled first scan signal GW may be supplied to the first scan line SL1i. When the enabled first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data signal from the j-th data line DLj may be supplied to the second node N2. Since the form in which the first transistor M1 is diode-connected is maintained by the turned-on third transistor M3, the first node N1 may have a voltage obtained by compensating for the threshold voltage of the first transistor M1 in the data signal.

[0108] During the third period P3, the enabled fourth scan signal GB may be supplied to the fourth scan line SL4i. When the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, the fifth transistor M5 and the eighth transistor M8 may be turned on. When the fifth transistor M5 is turned on, the voltage of the second initialization power supply Vint2 may be supplied to the first electrode of the light emitting element LD, and thus, the light emitting element LD may be initialized. When the eighth transistor M8 is turned on, the voltage of the bias power supply Vbias may be supplied to the second node N2. When the voltage of the bias power supply Vbias is supplied to the second node N2, the first transistor M1 may be set to be in a conduction bias state.

[0109] In the fourth period P4, the emission control signal (or the emission control signal of a relatively low level) EM enabled may be supplied to the kth emission control line ELk, so that the sixth transistor M6 and the seventh transistor M7 are turned on. When the sixth transistor M6 and the seventh transistor M7 are turned on, a current flow path from the first power line PL1 to the second power line PL2 via the sixth transistor M6, the first transistor M1, the seventh transistor M7 and the light emitting element LD may be formed. According to the operation of the first transistor M1, a driving current corresponding to the voltage of the first node N1 may flow through the light emitting element LD, and the light emitting element LD may emit light at a brightness corresponding to the driving current.

[0110] Figure 5 The diagram shows the driving during the sustain period. Figure 3 The waveform diagram of an embodiment of the method of the pixel shown in . The maintenance period MP is a period of light emission while maintaining the voltage of the previously supplied data signal, and may be a period of displaying an image without changing any frame. In an embodiment, one frame may include one write period WP in the effective area of ​​the frame and a plurality of maintenance periods MP in the effective area and the blank area of ​​the frame. A plurality of maintenance periods MP may be continuously set after the write period WP.

[0111] Compared with the write period WP, ​​in the maintenance period MP, the threshold voltage compensation operation and the data write operation can be omitted, and the operation of applying a bias voltage to the first transistor M1 and the operation of initializing the light emitting element LD can be performed. The maintenance period MP can be set to have a length similar to that of the write period WP. The maintenance period MP can include a first period P1a, a second period P2a, a third period P3a, and a fourth period P4a.

[0112] refer to Figure 3 and Figure 5In the first to third periods P1a to P3a, the disabled emission control signal EM may be supplied to the kth emission control line ELk. When the disabled emission control signal EM is supplied to the kth emission control line ELk, the sixth transistor M6 and the seventh transistor M7 may be turned off, and thus, the light emitting element LD may be set to be in a non-emission state.

[0113] In the first period P1a to the third period P3a, the enabled first scan signal GW, the enabled second scan signal GC, and the enabled third scan signal GI may not be supplied (or the disabled scan signals GW, GC, and GI may be supplied). Therefore, in the first period P1a to the third period P3a, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be set to be in a cut-off state.

[0114] In the third period P3a, the enabled fourth scan signal GB may be supplied to the fourth scan line SL4i. When the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, the fifth transistor M5 and the eighth transistor M8 may be turned on.

[0115] When the fifth transistor M5 is turned on, the voltage of the second initialization power supply Vint2 can be supplied to the first electrode of the light emitting element LD, and thus, the light emitting element LD can be initialized. When the eighth transistor M8 is turned on, the voltage of the bias power supply Vbias can be supplied to the second node N2. When the voltage of the bias power supply Vbias is supplied to the second node N2, the first transistor M1 can be set to be in a conduction bias state.

[0116] Since one frame includes a writing period WP and a sustaining period MP, the above-described display device 100 in the embodiment of the present disclosure may be driven at various driving frequencies (various frame frequencies).

[0117] Figure 6 is a diagram illustrating brightness for one frame period. Figure 6 In , the brightness of the pixels set on a horizontal line is plotted. Figure 6 In , the portion indicated by Cycle may mean a period in which a pixel emits light and does not emit light in response to one emission control signal EM. Figure 6 , it is assumed that the display device 100 is driven at about 48 Hz, and ten disabled emission control signals EM are supplied during one frame period.

[0118] In an embodiment, four prohibited emission control signals (also referred to as first to fourth active area emission control signals, respectively) EM may be supplied in the active area Active Area. In an embodiment, the active area Active Area may include one writing period WP and three maintenance periods MP. Regardless of the image refresh rate, the active area Active Area may be set to have the same length, and therefore, regardless of the image refresh rate, the number of prohibited emission control signals EM supplied in the active area Active Area (e.g., 4) may be set to be constant.

[0119] In an embodiment, six disabled emission control signals EM may be supplied in the blank area Blank Area. In an embodiment, the blank area Blank Area may include six maintenance periods MP. The length of the blank area Blank Area may be differently set corresponding to the image refresh rate, and therefore, the number of disabled emission control signals EM supplied in the blank area Blank Area may be differently set corresponding to the image refresh rate.

[0120] refer to Figure 6 During one frame period, the brightness of a predetermined horizontal line may increase during a predetermined period and then decrease continuously. In an embodiment, the brightness of a predetermined horizontal line may increase during periods 1Cycle and 2Cycle of the active area Active Area and gradually decrease after the start point of period 3Cycle.

[0121] In an embodiment, the first transistor M1 may be configured to Figure 4 In the first period P1 of the writing period WP described in the embodiment of the present invention, the first transistor M1 is in a strongly on-biased state. In this case, the characteristic curve of the first transistor M1 can be changed (e.g., negatively offset), and while the characteristic curve of the first transistor M1 returns to the original position during a predetermined period (e.g., period 1Cycle and 2Cycle), the brightness of the predetermined horizontal line can be gradually increased (e.g., the brightness of the predetermined horizontal line can be gradually increased during period 1Cycle and 2Cycle). In addition, after period 3Cycle, the brightness of the predetermined horizontal line can be gradually reduced by the leakage current of the third transistor M3 and the fourth transistor M4.

[0122] When a relatively large brightness difference is set on a predetermined horizontal line during one frame period, this may be recognized as flicker by the user. In an embodiment of the present disclosure, the width of the disabled emission control signal EM supplied in the active area Active Area may be controlled to minimize the brightness difference on the predetermined horizontal line.

[0123] Fig. 7A and Figure 7B is a diagram illustrating an embodiment of an emission control signal supplied during an active region.

[0124] refer to Figure 6 and Fig. 7A During one frame period, the brightness of a predetermined horizontal line can be set to be the highest in the period 3Cycle. Therefore, when the brightness of the period 3Cycle is reduced, the brightness difference of the predetermined horizontal line can be minimized, and thus, the display quality can be improved.

[0125] In addition, when the brightness increases at the initial stage of the active area Active Area, a brightness difference with the blank area Blank Area of ​​the previous frame may occur. Therefore, when the brightness of the period 2Cycle is reduced, the brightness difference between the previous frame and the current frame is minimized, and thus, the display quality can be improved.

[0126] To this end, in an embodiment of the present disclosure, at least two disabled emission control signals EM having different widths may be supplied in the active area Active Area.

[0127] In an embodiment, the disabled emission control signal EM supplied in the write period WP of the active area Active Area may be set to have a first width W1. The disabled emission control signal EM having the first width W1 may also be referred to as a first emission control signal EM1. The disabled emission control signal EM having the first width W1 may also be supplied in the sustain period MP of the blank area Blank Area.

[0128] In an embodiment, at least one disabled emission control signal EM supplied in the active area Active Area and in the maintenance period MP after the write period WP may have a width different from the first width W1. In an embodiment, the second disabled emission control signal EM supplied in the active area Active Area (or supplied in the first maintenance period MP) may be set to have a second width W2. The disabled emission control signal EM with the second width W2 may also be referred to as the second emission control signal EM2. In an embodiment, the fourth disabled emission control signal EM supplied in the active area Active Area may be set to have a third width W3. The disabled emission control signal EM with the third width W3 may also be referred to as the third emission control signal EM3.

[0129] Each of the second width W2 and the third width W3 may be set to a relatively wide (or long) width compared to the first width W1. In addition, the second width W2 and the third width W3 may be equal to or different from each other. Fig. 7A, a portion drawn by a black hatched line in the disabled emission control signal EM may mean a widened width (or period) compared to the disabled emission control signal EM having the first width W1.

[0130] In an embodiment, when the second disabled emission control signal EM supplied in the active area Active Area is set to have the second width W2, the initial brightness of the active area Active Area is reduced, and thus, the brightness difference from the blank area Blank Area of ​​the previous frame may be minimized.

[0131] In an embodiment, when the fourth disabled emission control signal EM supplied in the active area Active Area is set to have the third width W3, the brightness of the period 3Cycle is reduced, and thus, the brightness difference in one frame may be minimized.

[0132] exist Fig. 7A In FIG. 1 , it is described that the widths of the second disabled emission control signal EM and the fourth disabled emission control signal EM supplied in the active area Active Area are widened. However, the present disclosure is not limited thereto.

[0133] In an embodiment, Figure 7B As shown in FIG. 1 , the widths of the second disabled emission control signal EM and the third disabled emission control signal EM supplied in the active area Active Area can be set to be relatively wide. When the width of the third disabled emission control signal EM is set to the third width W3, the brightness of the period 2Cycle and / or the period 3Cycle is reduced, and therefore, the brightness difference in one frame can be minimized.

[0134] Figure 8 It is a graphic Figure 1 An embodiment of a timing controller is shown in FIG. Figure 8 , only components necessary for describing the present disclosure will be illustrated.

[0135] refer to Figure 8 , the timing controller 120 may include a storage unit (eg, memory) 122 . Figures 6 to 7B Information of the first width W1, second width W2, and third width W3 shown in FIG. 1 may be stored in the storage unit 122. The first width W1, second width W2, and third width W3 stored in the storage unit 122 may correspond to the width (length, time) of the disabled emission control signal EM.

[0136] In an embodiment, when Fig. 7AWhen the disabled emission control signal EM is supplied as shown in , the timing controller 120 may supply the emission start signal EFLM having the first width W1 during the writing period WP (or the first emission control signal EM1 corresponding to the frame). Then, the emission driver 150 may supply the disabled emission control signal EM having the first width W1 to the emission control lines EL1 to ELo.

[0137] The timing controller 120 may supply the emission start signal EFLM having the second width W2 corresponding to the second disabled emission control signal EM. Then, the emission driver 150 may supply the disabled emission control signal EM having the second width W2 to the emission control lines EL1 to ELo.

[0138] The timing controller 120 may supply the emission start signal EFLM having the third width W3 corresponding to the fourth disabled emission control signal EM. Then, the emission driver 150 may supply the disabled emission control signal EM having the third width W3 to the emission control lines EL1 to ELo.

[0139] The timing controller 120 may supply the emission start signal EFLM corresponding to the third disabled emission control signal EM and other disabled emission control signals EM supplied in the blank area BlankArea Then, the emission driver 150 may supply the disabled emission control signal EM having the first width W1 to the emission control lines EL1 to ELo.

[0140] Fig. 9 is a diagram illustrating the brightness of a display device for one frame period. Fig. 9 , various display devices are driven at about 48 Hz, and ten disabled emission control signals EM are supplied during one frame period.

[0141] refer to Fig. 9 , although the same data signal is supplied to the display device, the display device may have different brightness during one frame period. When the display device has different brightness, Fig. 7A and Figure 7B The second width W2 and the third width W3 shown in FIG. 1 may be set differently for each display device.

[0142] In the embodiment, the second width W2 and the third width W3 are set to be the same for each display device, and the characteristics of the display device cannot be reflected. Therefore, in the embodiment of the present disclosure, the second width W2 and the third width W3 can be set by reflecting the characteristics of the display device.

[0143] Fig.10 is a diagram illustrating an embodiment of a method of setting a width of an emission control signal according to the present disclosure. Fig.10The setting of the width of the emission control signal EM shown in FIG. 1 may be set for each display device 100 through multi-time programming ("MTP"). The width of the emission control signal EM may be set during the process.

[0144] refer to Fig.10 , first, the width of the standard disabled emission control signal EM may be loaded (operation S1000). In an embodiment, the width of the standard disabled emission control signal EM may be set to a first width W1. In operation S1000, the width of the standard disabled emission control signal EM may be loaded by the timing controller 120. The width of the standard disabled emission control signal EM may be pre-stored in the storage unit 122. In operation S1000, the width of the standard disabled emission control signal EM may be set by a separate processing device electrically connected to the timing controller 120 during processing.

[0145] After the standard disabled emission control signal EM width is loaded in operation S1000, the width of at least one disabled emission control signal EM among second to fourth disabled emission control signals EM supplied in the active area Active Area may be changed (operation S1002).

[0146] In an embodiment, in operation S1002, as Fig. 7A As shown in , the width of each of the second disabled emission control signal EM (or EM2) and the fourth disabled emission control signal EM (or EM3) can be changed. In an embodiment, in operation S1002, as shown in FIG. Figure 7B As shown in FIG. 1 , the width of each of the second disabled emission control signal EM (or EM2 ) and the third disabled emission control signal EM (or EM3 ) may be changed.

[0147] After the width of the disabled emission control signal EM is changed in operation S1002, it may be determined whether each of the brightness and the flicker is below a threshold value while measuring the pixel unit 110 (operation S1004). In operation S1004, the brightness may mean a brightness difference between frames corresponding to a change in the image refresh rate. In operation S1004, the flicker may mean a brightness difference in one frame.

[0148] When each of the brightness and flicker is determined to be below the threshold in operation S1004, the width of the corresponding disabled emission control signal EM may be stored in the storage unit 122 (operation S1006). When each of the brightness and flicker exceeds the threshold in operation S1004, operations S1000 to S1004 may be repeated.

[0149] Fig.11 is a diagram illustrating flicker characteristics of an embodiment of the present disclosure and a comparative example. Fig.11 In , flicker can mean the brightness difference in a frame corresponding to the passage of time. Fig.11 In FIG. 1 , flicker characteristics obtained by examining ten display devices are shown. Fig.11 In , the value (or threshold) that satisfies the flicker characteristic may be -60 decibels (dB) or lower. Fig.11 In the embodiment, the “embodiment” may mean a case where the width of each of the second disabled emission control signal EM and the fourth disabled emission control signal EM supplied in the active area Active Area is set differently with respect to each display device. Fig.11 In the description, the “comparative example” may mean a case where the widths of the disabled emission control signals EM supplied in the active area Active Area are all set to be the same.

[0150] refer to Fig.11 In the case of the present disclosure, the flicker characteristic of the display device can be set to a threshold value or lower. That is, in the display device in the embodiment of the present disclosure, the brightness difference in one frame period can be minimized, and therefore, the display quality can be improved.

[0151] The flicker characteristics of some of the display devices of the comparative example may exceed the threshold value. When the flicker characteristics exceed the threshold value, the brightness difference in one frame period may be recognized by the user. When the flicker characteristics exceed the threshold value, the display device may be determined as a defective product, and therefore, the manufacturing cost may increase.

[0152] Fig.12 is a diagram illustrating the brightness difference characteristics of the embodiment of the present disclosure and the comparative example. Fig.12 In , the brightness difference may mean the brightness difference between frames corresponding to the change in the image refresh rate. Fig.12 In FIG. 1 , the brightness difference characteristics obtained by inspecting ten display devices are shown. Fig.12 In , the value (or threshold) satisfying the brightness difference characteristic may be about 0.030 nit / Hz or less. Fig.12 In the embodiment, the “embodiment” may mean a case where the width of each of the second disabled emission control signal EM and the fourth disabled emission control signal EM supplied in the active area Active Area is set differently with respect to each display device. Fig.12 In the description, the “comparative example” may mean a case where the widths of the disabled emission control signals EM supplied in the active area ActiveArea are all set to be the same.

[0153] refer to Fig.12In the case of the present disclosure, the brightness difference characteristic of the display device can be set to a threshold value or lower. That is, regardless of the change in the image refresh rate, the display device in the embodiment of the present disclosure can generate similar brightness in each frame, and therefore, the display quality can be improved.

[0154] The brightness difference characteristic of some of the display devices of the comparative example may exceed the threshold value. When the brightness difference characteristic exceeds the threshold value, the brightness difference corresponding to the change in the image refresh rate may be recognized by the user. When the brightness difference characteristic exceeds the threshold value, the display device may be determined as a defective product, and therefore, the manufacturing cost may increase.

[0155] Fig.13 It is a graphic Figure 1 An embodiment of a timing controller is shown in FIG. FIG. 14A to FIG. 16B is a diagram illustrating an embodiment of a disabled emission control signal corresponding to the control of a timing controller.

[0156] exist Fig.13 In the figure, only the components necessary for describing the present disclosure will be illustrated. Fig.13 In this section, we will briefly describe Figure 8 The parts shown in the figure are repeated parts.

[0157] refer to Fig.13 , the timing controller 120 may include a storage unit 122 and a brightness determiner 124 .

[0158] Fig. 7A , Figure 7B , Fig.14A and Fig. 14B The information of the first width W1, the second width W2, and the third width W3 shown in FIG. 1 may be stored in the storage unit 122. In addition, FIG. 15A to FIG. 17B Information of the second widths W2 a , W2 b , and W2 c and the third widths W3 a and W3 b shown in FIG. 1 may be stored in the storage unit 122 .

[0159] The brightness determiner 124 may determine the brightness in units of frames using the input data Din. In an embodiment, the brightness determiner 124 may calculate an on-pixel ratio ("OPR") of the input data Din, and determine the brightness in units of frames based on the OPR. The OPR may be a ratio of the number of pixels PX activated based on the input data Din to the number of pixels PX included in the pixel unit 110. In an embodiment, the brightness determiner 124 may determine the brightness in units of frames using the grayscale value of the input data Din. In the brightness determiner 124, various methods currently known in the art may be used as a method of determining the brightness.

[0160] In an embodiment, the brightness determiner 124 may determine a relatively high brightness, a medium brightness, and a relatively low brightness in units of frames. In an embodiment, for example, when the OPR is above 90%, the brightness determiner 124 may determine the brightness of the current frame as a relatively high brightness. In an embodiment, for example, when the OPR is below 10%, the brightness determiner 124 may determine the brightness of the current frame as a relatively low brightness. In an embodiment, for example, when the OPR exceeds approximately 10% and is less than approximately 90%, the brightness determiner 124 may determine the brightness of the current frame as a medium brightness. However, the above-mentioned values ​​of approximately 90% and approximately 10% are merely illustrative and may be experimentally and differently set.

[0161] The timing controller 120 may change the brightness determined in units of frames in the brightness determiner 124 as follows: Fig.14A and Fig. 14B The positions (eg, timing or time, etc.) at which the second emission control signal EM2 and the third emission control signal EM3 are supplied are shown in FIG.

[0162] In an embodiment, when the brightness of the frame is determined as a relatively high brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2) supplied in the active area Active Area to have a second width W2, and set the third disabled emission control signal EM (or EM3) supplied in the active area Active Area to have a third width W3, as shown in FIG. Fig.14A When the brightness of the frame is determined to be relatively high brightness, the width of the second disabled emission control signal EM and the width of the third disabled emission control signal EM may be set relatively wide so that the brightness difference corresponding to the change in the image refresh rate may be minimized.

[0163] In an embodiment, when the brightness of the frame is determined as a relatively low brightness in the brightness determiner 124, the timing controller 120 may set the third disabled emission control signal EM (or EM2) supplied in the active area Active Area to have the second width W2, and set the fourth disabled emission control signal EM (or EM3) supplied in the active area Active Area to have the third width W3, as shown in FIG. Fig. 14B When the brightness of the frame is determined to be relatively low brightness, the width of the third disabled emission control signal EM and the width of the fourth disabled emission control signal EM may be set to be relatively wide so that the flicker may be minimized.

[0164] In an embodiment, when the brightness of the frame is determined as the medium brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2) supplied in the active area Active Area to have the second width W2, and set the fourth disabled emission control signal EM (or EM3) supplied in the active area Active Area to have the third width W3, as shown in FIG. Fig. 7A as shown in .

[0165] In an embodiment, when the brightness of the frame is determined as a relatively high brightness in the brightness determiner 124, the timing controller 120 may change the widths of the second emission control signals EM2a and EM2b and the third emission control signals EM3a and EM3b, such as Fig.15A and Fig. 15B as shown in .

[0166] In an embodiment, when the brightness of the frame is determined as a relatively high brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2a) supplied in the active area Active Area to have the second width W2a, and set the fourth disabled emission control signal EM (or EM3a) supplied in the active area Active Area to have the third width W3a, as shown in FIG. Fig.15A As shown in . Fig. 7A Compared with the second width W2 shown in FIG. 1 , the second width W2a may be set to a relatively wide width. Fig. 7A The third width W3a may be set to a relatively wide width compared to the third width W3 shown in . The second width W2a and the third width W3a may be set to widths equal to or different from each other. When the brightness of the frame is determined to be relatively high brightness, the width of the second emission control signal EM2a and the width of the third emission control signal EM3a may be set to be relatively wide by considering the brightness difference corresponding to the change in the image refresh rate.

[0167] In an embodiment, when the brightness of the frame is determined as a relatively low brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2b) supplied in the active area Active Area to have the second width W2b, and set the fourth disabled emission control signal EM (or EM3b) supplied in the active area Active Area to have the third width W3b, as shown in FIG. Fig. 15B As shown in . Fig. 7A Compared with the second width W2 shown in FIG. , the second width W2b may be set to a narrow width. Fig. 7AThe third width W3b may be set to a narrow width compared to the third width W3 shown in . The second width W2b and the third width W3b may be set to widths equal to or different from each other. In addition, each of the second width W2b and the third width W3b may be set to a width wider than the first width W1. When the brightness of the frame is determined to be relatively low brightness, the width of the second emission control signal EM2b and the width of the third emission control signal EM3b may be set to be narrow by taking flicker into consideration.

[0168] In an embodiment, when the brightness of the frame is determined as the medium brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2) supplied in the active area Active Area to have the second width W2, and set the fourth disabled emission control signal EM (or EM3) supplied in the active area Active Area to have the third width W3, as shown in FIG. Fig. 7A As shown in . The second width W2 may be set to a width narrower than the second width W2a and wider than the second width W2b. The third width W3 may be set to a width narrower than the third width W3a and wider than the third width W3b.

[0169] exist Fig.15A and Fig. 15B In the figure, each of the second emission control signals EM2a and EM2b is supplied as the second emission control signal EM in the active area Active Area, and each of the third emission control signals EM3a and EM3b is supplied as the fourth emission control signal EM in the active area Active Area. However, the present disclosure is not limited thereto. In an embodiment, each of the second emission control signals EM2a and EM2b may be supplied as the second emission control signal in the active area ActiveArea, and each of the third emission control signals EM3a and EM3b may be supplied as the third emission control signal in the active area Active Area.

[0170] The timing controller 120 may change the positions at which the second emission control signals EM2c and EM2d and the third emission control signals EM3c and EM3d are supplied and change the widths of the second emission control signals EM2c and EM2d and the third emission control signals EM3c and EM3d corresponding to the brightness determined in units of frames in the brightness determiner 124, as shown in FIG. Fig.16A and Fig. 16B as shown in .

[0171] In an embodiment, when the brightness of the frame is determined as a relatively high brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2c) supplied in the active area Active Area to have the second width W2a, and set the third disabled emission control signal EM (or EM3c) supplied in the active area Active Area to have the third width W3a, such as Fig.16A as shown in .

[0172] In an embodiment, when the brightness of the frame is determined as a relatively low brightness in the brightness determiner 124, the timing controller 120 may set the third disabled emission control signal EM (or EM2d) supplied in the active area Active Area to have the second width W2b, and set the fourth disabled emission control signal EM (or EM3d) supplied in the active area Active Area to have the third width W3b, as shown in FIG. Fig. 16B as shown in .

[0173] In an embodiment, when the brightness of the frame is determined as the medium brightness in the brightness determiner 124, the timing controller 120 may set the second disabled emission control signal EM (or EM2) supplied in the active area Active Area to have the second width W2, and set the fourth disabled emission control signal EM (or EM3) supplied in the active area Active Area to have the third width W3, as shown in FIG. Fig. 7A as shown in .

[0174] Fig.17A and Fig. 17B is a diagram illustrating an embodiment of an emission control signal supplied during one frame period.

[0175] refer to Fig.17A and Fig. 17B , under the control of the timing controller 120 , the emission driver 150 may supply the disabled emission control signal EM having at least two different widths during an active area Active Area of ​​one frame.

[0176] In an embodiment, the emission driver 150 may supply the first emission control signal EM1 having the first width W1 and the second emission control signal EM2e having the second width W2c. The second width W2c may be set to a narrow width compared to the first width W1.

[0177] The first emission control signal EM1 may be supplied at the same cycle (or the same interval) during the active area Active Area and the blank area Blank Area of ​​one frame. The second emission control signal EM2e may be supplied between the first emission control signals EM1 during the active area Active Area of ​​one frame. In an embodiment, the second emission control signal EM2e may be supplied between the first first emission control signal EM1 and the second first emission control signal EM1 (or period 1Cycle) and between the third first emission control signal EM1 and the fourth first emission control signal EM1 (or period 3Cycle).

[0178] When the second emission control signal EM2e is supplied in period 1Cycle, the initial brightness of the active area Active Area is reduced, and thus, the brightness difference with the blank area Blank Area of ​​the previous frame can be minimized. When the second emission control signal EM2e is supplied in period 3Cycle, the brightness difference in one frame can be minimized.

[0179] In addition, in an embodiment of the present disclosure, the emission driver 150 may change the position at which the second emission control signal EM2e is supplied in units of at least one frame. Fig.17A The second emission control signal EM2e and Fig. 17B The second emission control signal EM2e shown in FIG. 1 may be supplied at different positions (or different times) during the active area Active Area. When the position at which the second emission control signal EM2e is supplied is changed in units of at least one frame, flickering may be additionally reduced or prevented.

[0180] In a display device and a method of driving the display device according to the present disclosure, the width of an emission control signal supplied in an active area is controlled so that a brightness difference (or flicker) in one frame and a brightness difference caused by a change in an image refresh rate can be minimized.

[0181] Furthermore, in the display device and the method of driving the display device according to the present disclosure, the width of the emission control signal supplied in the active area is controlled corresponding to the brightness of one frame, so that the display quality can be improved.

[0182] Embodiments have been disclosed herein, and, although predetermined terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the date of filing this application, features, characteristics, and / or elements described in connection with a specific embodiment may be used alone or in any combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: pixels, each connected to a corresponding scan line among the scan lines, a corresponding data line among the data lines, and a corresponding emission control line among the emission control lines; as well as an emission driver, supplying an emission control signal to the emission control line, During the effective area of ​​one frame, the emission control signal includes a first emission control signal having a first width and a second emission control signal having a second width.

2. The display device according to claim 1, wherein: The launch driver: supplying the first emission control signal during a writing period in the active area in which a data signal is supplied to the pixel; and The second emission control signal is supplied during a period other than the writing period in the effective area.

3. The display device according to claim 1, wherein: The second width is set to be a relatively wide width compared to the first width.

4. The display device according to claim 2, wherein: The emission driver further supplies a third emission control signal having a third width during the period except the writing period in the active region.

5. The display device according to claim 4, wherein: The third width is set to a relatively wide width compared to the first width, and the second width and the third width are set to widths equal to or different from each other.

6. The display device according to claim 4, wherein: The second emission control signal is supplied as a second active area emission control signal in the active area, and The third emission control signal is supplied as a fourth active area emission control signal in the active area.

7. The display device according to claim 4, wherein: The second emission control signal is supplied as a second active area emission control signal in the active area, and The third emission control signal is supplied as a third active area emission control signal in the active area.

8. The display device according to claim 4, further comprising: A timing controller controls the emission driver, Wherein, the timing controller comprises a storage unit, in which information of the first width, the second width and the third width is stored; and The timing controller further comprises a brightness determiner, and the brightness determiner determines the brightness in units of the frame corresponding to the input data.

9. The display device according to claim 8, wherein: The timing controller changes a position at which the second emission control signal and the third emission control signal are supplied corresponding to the brightness.

10. The display device according to claim 8, wherein: The timing controller changes the second width of the second emission control signal and the third width of the third emission control signal corresponding to the brightness.

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