Open-loop residual amplifier circuit applied to assembly line successive approximation type ADC (Analog to Digital Converter)

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an open-loop residual amplifier circuit applied to a pipelined successive approximation type ADC. Comprising a differential input circuit, a tail current circuit, a third PMOS (P-channel Metal Oxide Semiconductor) tube Mp3, a fourth PMOS tube Mp4, a third NMOS (N-channel Metal Oxide Semiconductor) tube Mn3 and a fourth NMOS tube Mn4, the third PMOS tube Mp3, the fourth PMOS tube Mp4, the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are all connected with the differential input circuit; the tail current circuit is connected with the third NMOS tube Mn3 and the fourth NMOS tube Mn4; a high open-loop gain does not need to be designed, a complex common-mode voltage detection circuit is not needed, the circuit structure is simple, the circuit design difficulty is reduced, the circuit is a dynamic circuit, the circuit power consumption is greatly reduced, and the circuit is suitable for low-power-consumption ADC design; the analog-to-digital converter adopts a push-pull input mode, greatly improves the input transconductance, has the characteristic of large bandwidth, and is suitable for high-speed ADC (Analog-to-Digital Converter) design.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an open-loop residual amplifier circuit applied to a pipeline successive approximation ADC. Background Art

[0002] High-speed and high-precision analog-to-digital converters (ADCs) have developed rapidly in recent years. Single-channel ADCs with an accuracy of more than 12 bits and a conversion speed of several hundred million samples per second are in great demand in various mixed signal processing systems. Pipeline SAR ADC is a popular architecture in the field of analog-to-digital converter design in recent years. It combines pipeline ADC and successive approximation ADC, which can take advantage of the high-speed and high-precision characteristics of pipeline ADC and the low power consumption, small area and easy integration of successive approximation ADC.

[0003] With the continuous advancement of CMOS technology, the performance indicators of pipelined successive approximation ADCs are also continuously improving. However, the bottleneck that hinders further performance improvement is the residual amplifier (RA) between each sub-ADC. The main function of the residual amplifier is to accurately linearly amplify the residual signal generated after the quantization of the previous sub-ADC, and use it for the next quantization of the next sub-ADC. Therefore, the gain accuracy, linearity, speed and power consumption of the residual amplifier are the design difficulties of highly accurate pipelined successive approximation ADCs.

[0004] The residual amplifier used in pipelined successive approximation ADC is mainly divided into open-loop structure and closed-loop structure. Overall, the closed-loop residual amplifier has the following problems:

[0005] 1) In order to meet the design requirements of sampling rate in the design of high-speed ADC, more advanced manufacturing processes are generally used. However, in the advanced CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing process, the channel length of transistors is getting smaller and smaller, and the intrinsic gain is getting smaller and smaller, which makes it more difficult to design an operational amplifier with large open-loop gain. If the open-loop gain is not large enough, it will affect the closed-loop gain accuracy, linearity and stability of the closed-loop residual amplifier.

[0006] 2) The output common-mode instability of the operational amplifier in the closed-loop residual amplifier will affect the circuit performance. More seriously, it may cause the transistor to enter the linear region and the amplifier cannot achieve the amplification function. Therefore, a CMFB (Commenmode feed back) circuit is required to stabilize the output common-mode voltage of the amplifier, which increases the difficulty of circuit design.

[0007] In the structure of the open-loop residual amplifier, according to the signal processing method, it is divided into an incompletely established open-loop amplifier and a fully established open-loop amplifier. The conversion speed of the incompletely established open-loop amplifier circuit is slow and the accuracy is limited by the control accuracy of the integration time. The fully established open-loop amplifier does not require a complex detection circuit and fully amplifies the signal to the required amplification factor to achieve stability. Summary of the invention

[0008] In view of the shortcomings of the prior art, the present invention proposes an open-loop residual amplifier circuit applied to a pipeline successive approximation ADC, the circuit comprising: a differential input circuit, a tail current circuit, a third PMOS tube Mp3, a fourth PMOS tube Mp4, a third NMOS tube Mn3 and a fourth NMOS tube Mn4;

[0009] The third PMOS tube Mp3, the fourth PMOS tube Mp4, the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS tube Mn3 and the fourth NMOS tube Mn4.

[0010] Preferably, the differential input circuit includes a first NMOS tube Mn1, a second NMOS tube Mn2, a fifth NMOS tube Mn5, a sixth NMOS tube Mn6, a first PMOS tube Mp1, a second PMOS tube Mp2, a fifth PMOS tube Mp5 and a sixth PMOS tube Mp6; the gates of the second NMOS tube Mn2, the fifth NMOS tube Mn5, the second PMOS tube Mp2 and the fifth PMOS tube Mp5 are all connected to the first input signal VIP; the gates of the first NMOS tube Mn1, the sixth NMOS tube Mn6, the first PMOS tube Mp1 and the sixth PMOS tube Mp6 are all connected to the second input signal VIN; the source of the first PMOS tube Mp1 is connected to the source of the fifth PMOS tube Mp5 and the drain of the third PMOS tube Mp3, and the drain of the first PMOS tube Mp1 is connected to the third PMOS tube Mp5. The gate of the S tube Mp3, the drain of the first NMOS tube Mn1 and the gate of the third NMOS tube Mn3; the source of the second PMOS tube Mp2 is connected to the source of the sixth NMOS tube Mn6 and the drain of the fourth PMOS tube Mp4, and the drain of the second PMOS tube Mp2 is connected to the gate of the fourth NMOS tube Mn4, the drain of the second NMOS tube Mn2 and the gate of the fourth NMOS tube Mn4; the source of the first NMOS tube Mn1 is connected to the source of the fifth NMOS tube Mn5 and the drain of the third PMOS tube Mp3; the source of the second NMOS tube Mn2 is connected to the source of the sixth PMOS tube Mp6 and the drain of the fourth NMOS tube Mn4; the drain of the fifth PMOS tube Mp5 is connected to the drain of the fifth NMOS tube Mn5, and the drain of the sixth PMOS tube Mp6 is connected to the drain of the sixth PMOS tube Mp6.

[0011] Furthermore, the drain of the fifth PMOS transistor Mp5 is also connected to one end of the first capacitor through the first switch, and the drain of the sixth PMOS transistor Mp6 is also connected to one end of the second capacitor through the second switch; the other ends of the first capacitor and the second capacitor are both grounded.

[0012] Furthermore, the drain of the fifth PMOS tube Mp5 and the drain of the sixth PMOS tube Mp6 are also connected to both ends of the resistor respectively, and the fifth PMOS tube Mp5, the fifth NMOS tube Mn5, the sixth PMOS tube Mp6, the sixth PMOS tube Mp6 and the resistor R1 form a push-pull output circuit.

[0013] Preferably, the tail current circuit includes a seventh PMOS tube Mp7 and a seventh NMOS tube Mn7; the source of the seventh PMOS tube Mp7 is connected to the power supply VDD, and the drain of the seventh PMOS tube Mp7 is connected to the drain of the seventh NMOS tube Mn7, the source of the third NMOS tube Mn3 and the source of the fourth NMOS tube Mn4; the gate of the seventh PMOS tube Mp7 and the gate of the seventh NMOS tube Mn7 are both adjacent to the clock signal EN, and the source of the seventh NMOS tube Mn7 is grounded.

[0014] Preferably, the source of the third PMOS transistor Mp3 and the source of the fourth PMOS transistor Mp4 are both connected to the power supply VDD.

[0015] The beneficial effects of the present invention are:

[0016] (1) The present invention adopts an open-loop residual amplifier, and the open-loop gain is the amplification factor of the residual amplifier. It is not necessary to design a very high open-loop gain, thereby reducing the difficulty of circuit design.

[0017] (2) The differential input circuit structure of the present invention adopts a differential folded voltage follower (DFVF) structure, which enables the residual amplifier circuit to achieve higher linearity when the input swing is larger.

[0018] (3) The present invention is a fully built-up residual amplifier and does not require a complex timing control circuit.

[0019] (4) The present invention is a dynamic circuit with a simple circuit structure, which greatly reduces the circuit power consumption and is suitable for low-power ADC design.

[0020] (5) Compared with the traditional open-loop residual amplifier, the open-loop residual amplifier circuit proposed in the present invention can improve the linearity of the circuit.

[0021] (6) The present invention has a large bandwidth and is suitable for high-speed pipeline successive approximation ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the circuit structure of an open-loop residual amplifier applied to a pipelined successive approximation ADC in the present invention;

[0023] Figure 2 The timing diagram of the open-loop residual amplifier circuit used in the pipeline successive approximation ADC of the present invention is shown in FIG. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The present invention proposes an open-loop residual amplifier circuit applied to a pipeline successive approximation ADC, which adopts an open-loop residual amplifier, and the open-loop gain is the amplification factor of the residual amplifier. It is not necessary to design a very high open-loop gain, which reduces the difficulty of circuit design. Figure 1 As shown, the circuit includes: a differential input circuit, a tail current circuit, a third PMOS tube Mp3, a fourth PMOS tube Mp4, a third NMOS tube Mn3 and a fourth NMOS tube Mn4;

[0026] The third PMOS tube Mp3, the fourth PMOS tube Mp4, the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS tube Mn3 and the fourth NMOS tube Mn4.

[0027] In this embodiment, the differential input circuit includes a first NMOS tube Mn1, a second NMOS tube Mn2, a fifth NMOS tube Mn5, a sixth NMOS tube Mn6, a first PMOS tube Mp1, a second PMOS tube Mp2, a fifth PMOS tube Mp5 and a sixth PMOS tube Mp6; the gates of the second NMOS tube Mn2, the fifth NMOS tube Mn5, the second PMOS tube Mp2 and the fifth PMOS tube Mp5 are all connected to the first input signal VIP; the gates of the first NMOS tube Mn1, the sixth NMOS tube Mn6, the first PMOS tube Mp1 and the sixth PMOS tube Mp6 are all connected to the second input signal VIN; the source of the first PMOS tube Mp1 is connected to the source of the fifth PMOS tube Mp5 and the drain of the third PMOS tube Mp3, and the drain of the first PMOS tube Mp1 is connected to the third PMOS tube Mp4. The gate of the MOS tube Mp3, the drain of the first NMOS tube Mn1 and the gate of the third NMOS tube Mn3; the source of the second PMOS tube Mp2 is connected to the source of the sixth NMOS tube Mn6 and the drain of the fourth PMOS tube Mp4, and the drain of the second PMOS tube Mp2 is connected to the gate of the fourth NMOS tube Mn4, the drain of the second NMOS tube Mn2 and the gate of the fourth NMOS tube Mn4; the source of the first NMOS tube Mn1 is connected to the source of the fifth NMOS tube Mn5 and the drain of the third PMOS tube Mp3; the source of the second NMOS tube Mn2 is connected to the source of the sixth PMOS tube Mp6 and the drain of the fourth NMOS tube Mn4; the drain of the fifth PMOS tube Mp5 is connected to the drain of the fifth NMOS tube Mn5, and the drain of the sixth PMOS tube Mp6 is connected to the drain of the sixth PMOS tube Mp6.

[0028] In this circuit, N-type MOS tube and P-type MOS tube are input at the same time, which increases the input transconductance and the bandwidth of the amplifier.

[0029] Furthermore, the drain of the fifth PMOS transistor Mp5 is also connected to one end of the first capacitor through the first switch, and the drain of the sixth PMOS transistor Mp6 is also connected to one end of the second capacitor through the second switch; the other ends of the first capacitor and the second capacitor are both grounded.

[0030] Furthermore, the drain of the fifth PMOS tube Mp5 and the drain of the sixth PMOS tube Mp6 are also connected to both ends of the resistor respectively, and the fifth PMOS tube Mp5, the fifth NMOS tube Mn5, the sixth PMOS tube Mp6, the sixth PMOS tube Mp6 and the resistor R1 form a push-pull output circuit.

[0031] In the circuit, a first resistor is connected in parallel between two output terminals, and the output amplification factor can be adjusted by adjusting the resistance value of the first resistor to achieve the required amplification factor.

[0032] The tail current circuit includes a seventh PMOS tube Mp7 and a seventh NMOS tube Mn7; the source of the seventh PMOS tube Mp7 is connected to the power supply VDD, and the drain of the seventh PMOS tube Mp7 is connected to the drain of the seventh NMOS tube Mn7, the source of the third NMOS tube Mn3 and the source of the fourth NMOS tube Mn4; the gate of the seventh PMOS tube Mp7 and the gate of the seventh NMOS tube Mn7 are both adjacent to the clock signal EN, and the source of the seventh NMOS tube Mn7 is grounded.

[0033] The path of the tail current circuit is controlled by the EN clock. When the EN clock signal is high, the circuit works normally. When the EN clock signal is low, the current in the circuit is almost zero, thus forming a dynamic open-loop residual amplifier, which greatly reduces the average power consumption of the amplifier.

[0034] In the present invention, the first NMOS tube and the third NMOS tube are connected to form a folded voltage follower (Flipped Voltage Follower, FVF), which provides a current output with good linearity. The fifth NMOS tube is added to form a differential folded voltage follower (Differential Flipped Voltage Follower, DFVF), which improves the nonlinear problem. After the upper left corner is connected, the current will be converted into a voltage output, thereby obtaining a voltage output with good linearity, and then combined with the right half to form a fully differential output circuit. The gate of Mn5 is connected to VIP and Mn1 to form a set of differential pair inputs, the source of Mn5 is connected to the source of Mn1, and the drain of Mn5 is connected to the load capacitor CL through a switch. Further adding a PMOS tube part is consistent with the connection method of the NMOS tube, so as to complete an impedance matching of the NMOS and PMOS tubes. The NMOS tube and the POMOS tube are simultaneously used as differential pair tubes, and the input signal is simultaneously input from the differential pair tubes to achieve a higher transconductance, thereby improving the bandwidth of the circuit proposed by the present invention. The two output ports are connected in parallel with an R1 resistor to adjust the value of the load resistor to achieve the open-loop gain and bandwidth required by the design. One end of the switch S1 is connected to the negative output end, and the other end is connected to the upper board of the next-stage load capacitor. One end of the switch S2 is connected to the positive output end, and the other end is connected to the upper board of the next-stage load capacitor. By controlling the opening and closing of the switch by the CLK clock, a set of non-overlapping clocks is formed with the EN clock. The CLK clock reaches the rising edge first, and switches S1 and S2 are turned on first, connecting the load capacitor CL to the output end of the open-loop residual amplifier. The EN clock reaches the rising edge later, and the tail current source circuit is turned on. The entire open-loop residual amplifier starts to work, and the residual signal generated after the quantization of the previous stage Sub-ADC is stably amplified. The CLK clock reaches the falling edge first, and switches S1 and S2 are disconnected first. The charge of the upper board of the load capacitor is locked. The EN clock reaches the falling edge later, and the open-loop residual amplifier stops working. The power consumption of the open-loop residual amplifier in one working cycle is reduced.

[0035] like Figure 2 As shown, the CLK clock needs to reach a high level before the EN clock, the S1 and S2 switches need to be closed first, and the load capacitor is connected before the amplifier works normally. After the signal amplification is completed, the S1 and S2 switches need to be disconnected first, and then the amplifier stops working. In this way, the amplifier will not affect the subsequent circuit when it stops working.

[0036] In summary, the present invention proposes an open-loop residual amplifier circuit applied to a pipeline successive approximation ADC, which adopts a fully established open-loop residual amplifier, and the open-loop gain is the amplification factor of the residual amplifier. It is not necessary to design a very high open-loop gain, and it is not necessary to have a complex common-mode voltage detection circuit, which reduces the difficulty of circuit design. In addition, the present invention has a dynamic circuit and a simple circuit structure, which greatly reduces the power consumption of the circuit and is suitable for low-power ADC design. The present invention is a push-pull input method, which greatly improves the input transconductance and has the characteristics of a large bandwidth, and is suitable for high-speed ADC design.

[0037] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An open-loop residual amplifier circuit for a pipelined successive approximation ADC, characterized in that: include: A differential input circuit, a tail current circuit, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a third NMOS transistor Mn3 and a fourth NMOS transistor Mn4; The third PMOS tube Mp3, the fourth PMOS tube Mp4, the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS tube Mn3 and the fourth NMOS tube Mn4.

2. The open-loop residual amplifier circuit for pipelined successive approximation ADC according to claim 1, characterized in that: The differential input circuit includes a first NMOS tube Mn1, a second NMOS tube Mn2, a fifth NMOS tube Mn5, a sixth NMOS tube Mn6, a first PMOS tube Mp1, a second PMOS tube Mp2, a fifth PMOS tube Mp5 and a sixth PMOS tube Mp6; the gates of the second NMOS tube Mn2, the fifth NMOS tube Mn5, the second PMOS tube Mp2 and the fifth PMOS tube Mp5 are all connected to the first input signal VIP; the gates of the first NMOS tube Mn1, the sixth NMOS tube Mn6, the first PMOS tube Mp1 and the sixth PMOS tube Mp6 are all connected to the second input signal VIN; the source of the first PMOS tube Mp1 The source of the fifth PMOS tube Mp5 is connected to the drain of the third PMOS tube Mp3, the drain of the first PMOS tube Mp1 is connected to the gate of the third PMOS tube Mp3, the drain of the first NMOS tube Mn1 and the gate of the third NMOS tube Mn3; the source of the second PMOS tube Mp2 is connected to the source of the sixth NMOS tube Mn6 and the drain of the fourth PMOS tube Mp4, the drain of the second PMOS tube Mp2 is connected to the gate of the fourth NMOS tube Mn4, the drain of the second NMOS tube Mn2 and the gate of the fourth NMOS tube Mn4; the source of the first NMOS tube Mn1 is connected to the source of the fifth NMOS tube Mn5 and the drain of the third PMOS tube Mp3; The source of the second NMOS transistor Mn2 is connected to the source of the sixth PMOS transistor Mp6 and the drain of the fourth NMOS transistor Mn4; The drain of the fifth PMOS transistor Mp5 is connected to the drain of the fifth NMOS transistor Mn5 , and the drain of the sixth PMOS transistor Mp6 is connected to the drain of the sixth PMOS transistor Mp6 .

3. The open-loop residual amplifier circuit for pipelined successive approximation ADC according to claim 2, characterized in that: The drain of the fifth PMOS transistor Mp5 is also connected to one end of the first capacitor through the first switch, and the drain of the sixth PMOS transistor Mp6 is also connected to one end of the second capacitor through the second switch; the other ends of the first capacitor and the second capacitor are both grounded.

4. The open-loop residual amplifier circuit for pipelined successive approximation ADC according to claim 2, characterized in that: The drain of the fifth PMOS tube Mp5 and the drain of the sixth PMOS tube Mp6 are also connected to both ends of the resistor respectively. The fifth PMOS tube Mp5, the fifth NMOS tube Mn5, the sixth PMOS tube Mp6, the sixth PMOS tube Mp6 and the resistor form a push-pull output circuit.

5. The open-loop residual amplifier circuit for pipelined successive approximation ADC according to claim 1, characterized in that: The tail current circuit includes a seventh PMOS tube Mp7 and a seventh NMOS tube Mn7; the source of the seventh PMOS tube Mp7 is connected to the power supply VDD, and the drain of the seventh PMOS tube Mp7 is connected to the drain of the seventh NMOS tube Mn7, the source of the third NMOS tube Mn3 and the source of the fourth NMOS tube Mn4; The gate of the seventh PMOS transistor Mp7 and the gate of the seventh NMOS transistor Mn7 are both connected to the clock signal EN, and the source of the seventh NMOS transistor Mn7 is grounded.

6. The open-loop residual amplifier circuit for pipelined successive approximation ADC according to claim 1, characterized in that: The source of the third PMOS transistor Mp3 and the source of the fourth PMOS transistor Mp4 are both connected to the power source VDD.

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