Non-polar dual-bus communication system structure

Abstract

The invention relates to a non-polar dual-bus communication system structure. The structure has polarity judgment and polarity selection functions. The structure comprises a polarity judgment part and a decoding part. The decoding part is connected with the BUSA bus and the BUSB bus and decodes the two buses, and meanwhile, the decoding part further comprises a counting circuit part which is used for controlling polarity judgment time; the polarity judgment part firstly generates a polarity judgment signal according to two input bus signals, and then outputs a decoding bus after polarity judgment. And the decoding judgment is not influenced even if the bus polarity switching is carried out at any moment in the communication process, namely, a complete blind insertion effect can be realized, and complete communication can be realized.

Description

Technical Field

[0001] The invention relates to a non-polarity dual-bus communication system architecture, and in particular to a bus decoding function for polarity judgment and selection. Background Art

[0002] Compared with other bus systems, dual bus combines the signal line and the power supply line into one, realizing a technology that transmits data and provides voltage on the same bus.

[0003] During the signal transmission process, the correct data transmission and the robustness of the communication system are improved by changing the signal level polarity. Polarity switching is based on the application of differential signal transmission technology and is widely used in communication systems in long-distance, high-speed, low-power and noisy environments.

[0004] Bus polarity switching usually occurs in differential signal systems, and data is transmitted through two buses. When using a general communication system, the user needs to manually distinguish the positive and negative polarity lines to prevent the module from being inserted in the wrong direction, causing decoding errors or chip damage. Before actual use, the bus polarity should be determined first. If the polarity is switched during the communication process, the bus polarity cannot be determined, which will cause communication interruption.

[0005] Therefore, the present invention designs a dual bus communication system architecture and proposes to perform polarity judgment and reselect the bus when the polarity is switched during the communication process. This not only improves the security and reliability of the system, but also solves the problem that the chip cannot judge the polarity of the dual bus. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a non-polarity dual-bus communication system architecture to solve the problem that the decoding circuit cannot recognize and decode forward and reverse blind insertion during the communication process.

[0007] The dual-bus communication system architecture proposed by the present invention has its own polarity judgment function and decoding function, and the structure is connected to two buses: BUSA and BUSB.

[0008] The structure includes a polarity judgment part and a decoding part. The decoding part connects the BUSA bus and the BUSB bus, decodes the two buses, and outputs the bus decoding to the polarity judgment part; the polarity judgment part first generates a polarity judgment signal according to the two decoded buses input, and then outputs the decoded buses.

[0009] Specifically, the decoding part includes voltage-dividing resistors (R1, R2, R3, R4, R5, R6), two MOS tubes (M1, M2), an inverter I1, voltage comparators (U1, U2) and a counting circuit (a NAND gate, three RS flip-flops);

[0010] One end of the voltage-dividing resistor R1 is connected to the bus BUSA, and the other end is connected to the voltage-dividing resistor R2; one end of the voltage-dividing resistor R2 is connected to the drain of the MOS tube M1, and the other end is grounded; one end of the voltage-dividing resistor R3 is connected to the bus BUSB, and the other end is connected to the voltage-dividing resistor R4; one end of the voltage-dividing resistor R4 is connected to the drain of the MOS tube M2, and the other end is grounded; the resistance values ​​of the voltage-dividing resistors R5 and R6 are equal, one end of the voltage-dividing resistor R5 is connected to the bus BUSA, and the other end is the negative electrode of the comparator U1, and one end of the voltage-dividing resistor R6 is connected to the negative electrode of the comparator U1, and the other end is grounded;

[0011] The inverter I1 has an input end connected to one end of R5, namely, the BUSREF end, and an output end connected to the positive input end of the voltage comparator U2;

[0012] The MOS tube M1 has a drain connected to the common end of R1 and R2, a source connected to the positive electrode of the comparator U1, and a gate connected to a 3.3v voltage; the MOS tube M2 has a drain connected to the common end of R3 and R4, a source connected to the negative electrode of the comparator U2, and a gate connected to a 3.3v voltage;

[0013] The voltage comparator U1 has a positive input connected to the source of the MOS tube M1 and a negative input connected to BUSREF. The comparator outputs a voltage judgment result signal U out1 , that is, bus_a line;

[0014] The voltage comparator U2 has a positive electrode connected to the output of the inverter I1 and a negative electrode connected to the source of the MOS tube M2. The comparator outputs a voltage judgment result signal U out2 , that is, bus_b line.

[0015] The counting circuit includes two inverters (I2, I3), a NAND gate D2, and three RS flip-flops.

[0016] The inverter I2 has an input end connected to the output bus_b of the voltage comparator U2, and an output end connected to the input end of the inverter I3; the output end of the inverter I3 is connected to the RESET ends of the three RS triggers;

[0017] Specifically, three flip-flops are cascaded to form a counter circuit; at the same time, an external clock input CLK and a NAND gate D2 are also required to be connected, one input of the NAND gate D2 is connected to the external clock, the other input is connected to the output of the last flip-flop, and the output of D2 is connected to the clock input of the first flip-flop; through the last flip-flop, a polarity judgment signal ENABLE is output;

[0018] The circuit for polarity determination includes a two-input AND gate D1 and a two-to-one selector MUX;

[0019] One end of the two-input AND gate D1 is connected to the bus_a line, and the other end is connected to the output end of the third trigger;

[0020] The two input terminals of the two-to-one selector MUX are connected to the bus_a line and the bus_b line respectively, the selection control signal is ENABLE, and the final output signal of MUX is Data_in, which is the bus output after the polarity is determined.

[0021] The beneficial effects brought about by the technical solution provided in the example of the present application include at least: the structure can automatically determine which bus to decode after switching the polarity before power-on and during communication, realize adaptive polarity judgment and selection, and decode the bus in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to clearly illustrate the technical solution in the example of the present invention, the following briefly introduces the drawings required for describing this example. In the drawings:

[0023] Figure 1 This is a circuit with self-contained polarity switching and judgment provided in the example of this application;

[0024] Figure 2 This is the timing diagram of ENABLE changing with bus BUSA and BUSB;

[0025] Figure 3 It is the timing diagram of the bus, polarity judgment signal and decoding output signal. DETAILED DESCRIPTION

[0026] In order to make the purpose and technical solution of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figure 1 This is a circuit diagram with self-contained polarity switching and judgment provided by the example of this application. The circuit diagram includes two parts: a decoding part and a polarity judgment part. In this decoding part, two bus lines BUSA and BUSB are first connected, bus_a line and bus_b line are generated by decoding, and the decoding output result is transmitted to the polarity judgment part, a polarity judgment signal ENABLE is generated, and finally a decoded bus after polarity selection is output.

[0028] The voltage comparator U1 has a positive input connected to the source of the MOS tube M1 and a negative input connected to BUSREF. The comparator outputs a voltage judgment result signal U out1 , that is, bus_a line; because the voltage divider resistor is very large, the voltage value of BUSREF terminal is controlled within one-fourth of the bus voltage; the gate of M1 is connected to a 3.3v voltage, the purpose is to control the positive voltage reaching the comparator U1 within 0 to one-fourth of the bus voltage;

[0029] The voltage comparator U2 has a positive electrode connected to the output end of the inverter I1 and a negative electrode connected to the source of the MOS tube M2. The comparator outputs a voltage judgment result signal U out2 , i.e. bus_b line; since the voltage divider resistor is very large, the voltage value of BUSREF terminal is controlled within one-fourth of the bus voltage; the gate of M2 is connected to a 3.3v voltage, the purpose is to control the negative voltage reaching the comparator U2 within 0 to one-fourth of the bus voltage;

[0030] Specifically, by comparing the positive electrode U IN+ and negative electrode U IN- If the voltage at the end is IN+ The terminal voltage is higher than U IN- terminal, that is, the voltage of BUSA is higher than the voltage of BUSREF, then the comparator output result U out1 is high, that is, bus_a is high, at this time the positive terminal U IN+ The terminal voltage is lower than the negative terminal U IN- The voltage at the end, the comparator U2 outputs the result U out2 is low, that is, bus_b is low; if U IN+ The terminal voltage is lower than U IN- terminal, that is, the voltage of BUSA is lower than the voltage of BUSREF, then the comparator output result U out1 is low, that is, bus_a is low, at this time the positive terminal U IN+ The terminal voltage is higher than the negative terminal U IN- The voltage at the end, the comparator U2 outputs the result U out2 is high, that is, bus_b is high;

[0031] The bus_b line passes through two inverters and is connected to the RESET terminal of the trigger. Bus_b is connected to two inverters I2 and I3. Once bus_b is low, the signal passes through the output of the two inverters, and the low-level signal reaches the RESET terminal of the trigger. The trigger will start counting again, and the previous state of the ENABLE signal will still be latched. When the counting is completed, the ENABLE signal will be updated to the current value.

[0032] Figure 2 This is the timing diagram of ENABLE changing with bus BUSA and BUSB; after switching polarity, bus BUSA and BUSB need to remain unchanged for a fixed time to store the current ENABLE signal value; when ENABLE is high, decode the BUSA bus, otherwise, decode the BUSB bus. After the polarity judgment is completed, as long as the pulse width of the communication signal is less than the polarity judgment time, it will not affect the ENABLE value.

[0033] Figure 3The timing diagram of two buses, polarity judgment enable signal and decoded output bus signal is given. When the device is initially powered on, the BUSA line is high, the BUSB line is low, and the ENABLE signal is powered on high, that is, the current decoded BUSA bus; then in the communication process, the polarity starts to switch for the first time. When the clock rising edge arrives, the polarity of the two buses is switched in an instant, but ENABLE will not change immediately. It needs to go through a polarity judgment time, wait for the counting circuit to complete the count, and then the ENABLE signal is completed. That is, the current BUSA bus is low, the BUSB bus is high, and ENABLE should respond to become a low-level signal, that is, the current decoded BUSB bus; then in the communication process, the polarity starts to switch for the second time. When the clock rising edge arrives, the polarity of the two buses is switched in an instant, but ENABLE will not change immediately. It needs to go through a polarity judgment time, wait for the counting circuit to complete the count, and then the ENABLE signal is completed. That is, the current BUSA bus is high, the BUSB bus is low, and ENABLE should respond to become a high-level signal, that is, the current decoded BUSA bus;

[0034] It can be seen from this that switching the bus polarity at any time during the communication process will not affect the decoding judgment, that is, a complete blind plug-in effect can be achieved and communication can be intact.

[0035] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A non-polarity dual-bus communication system architecture, characterized in that: The decoding module includes a decoding part and a counting circuit part. The decoding part connects two buses BUSA and BUSB and decodes the two buses. The decoding part also includes a counting circuit part for controlling the time of polarity judgment. The decoding part includes voltage-dividing resistors R1, R2, R3, R4, R5, R6, two MOS tubes M1, M2, an inverter I1, voltage comparators U1 and U2, and a counting circuit, wherein the counting circuit includes a NAND gate and three RS flip-flops; One end of the voltage-dividing resistor R1 is connected to the bus BUSA, and the other end is connected to the voltage-dividing resistor R2; one end of the voltage-dividing resistor R2 is connected to the drain of the MOS tube M1, and the other end is grounded; one end of the voltage-dividing resistor R3 is connected to the bus BUSB, and the other end is connected to the voltage-dividing resistor R4; one end of the voltage-dividing resistor R4 is connected to the drain of the MOS tube M2, and the other end is grounded; the resistance values ​​of the voltage-dividing resistors R5 and R6 are equal, one end of the voltage-dividing resistor R5 is connected to the bus BUSA, and the other end is the negative electrode of the comparator U1, and one end of the voltage-dividing resistor R6 is connected to the negative electrode of the comparator U1, and the other end is grounded; The inverter I1 has an input end connected to one end of R5, namely, the BUSREF end, and an output end connected to the positive input end of the voltage comparator U2; The MOS tube M1 has a drain connected to the common end of R1 and R2, a source connected to the positive electrode of the comparator U1, and a gate connected to a 3.3v voltage; the MOS tube M2 has a drain connected to the common end of R3 and R4, a source connected to the negative electrode of the comparator U2, and a gate connected to a 3.3v voltage; The voltage comparator U1 has a positive input connected to the source of the MOS tube M1 and a negative input connected to BUSREF. The comparator outputs a voltage judgment result signal U out1 , that is, bus_a line; the voltage comparator U2, the positive electrode is connected to the output of the inverter I1, and the negative electrode input is connected to the source of the MOS tube M2; the comparator output voltage judgment result signal is U out2 , namely bus_b line; the counting circuit includes two inverters, namely I2 and I3, a NAND gate D2, and three RS flip-flops; The inverter I2 has an input end connected to the output bus_b of the voltage comparator U2, and an output end connected to the input end of the inverter I3; the output end of the inverter I3 is connected to the RESET ends of the three RS triggers; Three RS flip-flops are cascaded to form a counter circuit. At the same time, an external clock input CLK and a NAND gate D2 are also required. One input of the NAND gate D2 is connected to the external clock, and the other input is connected to the output of the last flip-flop. The output of D2 is connected to the clock input of the first flip-flop. Through the last flip-flop, the polarity judgment signal ENABLE is output. The circuit in polarity judgment includes a two-input AND gate D1 and a two-to-one selector MUX; one end of the two-input AND gate D1 is connected to the bus_a line, and the other end is connected to the output end of the third trigger; the two input ends of the two-to-one selector MUX are respectively connected to the bus_a line and the bus_b line, the selection control signal is ENABLE, and the final output signal of MUX is Data_in, which is the bus output after the polarity is determined.

2. The non-polarity dual bus communication system architecture according to claim 1, characterized in that: The polarity judgment signal ENABLE is connected to the selector MUX selection port. When the ENABLE signal is high, the BUSA bus is currently decoded; when the ENABLE signal is low, the BUSB bus is currently decoded.

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