Filtering architecture with minimized transients

Abstract

The invention relates to a filtering architecture with minimized transients. A digital microphone includes: a logarithmic amplifier; an analog-to-digital converter (ADC) coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; and a digital filter coupled to the digital decompression component, wherein the digital filter includes a controlled up-sampling component coupled to an input of the digital filter, and a controlled down-sampling component coupled to an output of the digital filter.

Description

Technical Field

[0001] The present disclosure generally relates to filtering architectures with minimized transients and corresponding methods. Background Art

[0002] Digital microphones are known in the art. In digital microphones, there is an increasing demand from consumers for new features such as dynamic acoustic overload point (AOP) switching or for increased signal-to-noise ratio (SNR) and for reduced power consumption. In existing solutions, there is a trade-off between decompression performance (SNR / classified noise, total harmonic distortion (THD)) and audible transients. These transients occur in particular during switching between operating modes of the digital microphone. Some existing solutions employ stronger low-pass filters (with lower cut-off frequencies), which results in better signal reconstruction, but at the expense of longer audible transients. Summary of the invention

[0003] According to an embodiment, a digital microphone includes: a logarithmic amplifier; an analog-to-digital converter (ADC) coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; and a digital filter coupled to the digital decompression component, wherein the digital filter includes a controlled upsampling component coupled to an input of the digital filter, and a controlled downsampling component coupled to an output of the digital filter.

[0004] According to an embodiment, a digital filter system includes: a controlled upsampling component coupled to an input of a digital filter; a digital filter having an input coupled to an output of the controlled upsampling component; a controlled downsampling component coupled to the output of the digital filter; and a controller having a trigger signal input and a first output, the first output being coupled to a first control input of the controlled upsampling component and coupled to a first control input of the controlled downsampling component.

[0005] According to an embodiment, a method includes: in a first operating mode, upsampling a digital input signal to provide an interpolated digital signal, filtering the interpolated digital signal, and downsampling the interpolated digital signal to provide a digital output signal; and in a second operating mode, filtering the digital input signal to provide a digital output signal without upsampling or downsampling the digital input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0007] Figure 1A and Figure 1B is a block diagram of a logarithmic amplifier architecture according to the prior art;

[0008] Figure 2 is a block diagram of an exemplary digital microphone including compression and decompression;

[0009] Figure 3 According to the embodiment, suitable for Figure 2 A high-level block diagram of a digital filter with transient reduction for a digital microphone;

[0010] Figure 4 , Figure 5 and Figure 6 is a more detailed block diagram of a digital filter according to an embodiment, the digital filter being suitable for Figure 2 A digital microphone having a transient reduction circuit device;

[0011] Figure 7 is a simulated step response of a digital low pass filter using a transient reduction circuit arrangement according to an embodiment;

[0012] Figure 8 is a block diagram of a digital filter having transient reduction circuitry, showing additional details with respect to showing clock signals and labeling internal circuit nodes;

[0013] Fig. 9 is with Figure 8 a timing diagram associated with the block diagram; and

[0014] Fig.10 is a flow chart of a digital filtering method for reducing transients in a digital microphone according to an embodiment;

[0015] Fig.11 is a schematic diagram of a standard filter topology for upsampling using a digital finite impulse response (FIR) filter (L=2);

[0016] Fig.12 is a schematic diagram of a polyphase filter topology for upsampling using a digital finite impulse response (FIR) filter (L=2);

[0017] Fig.13 is a schematic diagram of a polyphase filter topology operating at a high sampling rate;

[0018] Fig.14 is a schematic diagram of a switchable polyphase architecture for a finite impulse response (FIR) filter with minimized transients according to an embodiment (L=2);

[0019] Fig.15 is a schematic diagram of a standard filter topology for upsampling using a digital finite impulse response (FIR) filter (L=3);

[0020] Fig.16is a schematic diagram of a polyphase filter topology operating at a high sampling rate (L=3); and

[0021] Fig.17 is a schematic diagram of a switchable polyphase architecture for a finite impulse response (FIR) filter with minimized transients according to an embodiment (L=3). DETAILED DESCRIPTION

[0022] The manufacture and use of the preferred embodiment are discussed in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts that can be implemented in various specific situations. The specific embodiments discussed only illustrate specific methods for making and using the present invention and do not limit the scope of the present invention.

[0023] In the following detailed description, reference is made to the accompanying drawings, which form part of the present invention and in which specific embodiments are illustrated in the accompanying drawings, in which the present invention can be practiced. It should be understood that other embodiments can be used, and that the structure and logic can be changed without exceeding the scope of the present invention. For example, the features illustrated and described for one embodiment can be used in other embodiments or combined with other embodiments to produce another embodiment. The present invention is intended to include such modifications and variations. The examples described using specific language should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not to scale and are for illustrative purposes only. For clarity, if not otherwise specified, the same or similar elements are designated by corresponding reference numerals in different drawings.

[0024] More demanding specifications for digital microphones have led to the introduction of architectures using logarithmic amplifiers, such as Figure 1A The logarithmic amplifier architecture 100A is shown in FIG. Figure 1A In the embodiment of the present invention, the logarithmic amplifier 102 receives an analog input signal of a digital microphone. The output signal of the logarithmic amplifier 102 is converted into a digital signal by an analog-to-digital converter (ADC) 104. The digital signal provided by the ADC 104 is then processed by a digital de-logarithmic component 106. Figure 1B Another logarithmic amplifier architecture 100B is shown in FIG. 1, wherein the logarithmic amplifier 102 is replaced by a plurality of linear amplifiers 108 and a summing circuit. The logarithmic amplifier architecture 100B is shown and described in further detail in co-pending U.S. Patent Application No. 17 / 660,120, entitled “Logarithmic Amplifiers in Silicon Microphones,” which is hereby incorporated by reference in its entirety.

[0025] In some embodiments described herein, ADC 104 may include a ΣΔ ADC (ΣΔ converter). According to embodiments described in further detail below, Figure 2 As depicted in the digital microphone 200 shown in block diagram format in FIG. 1 , the digital output of the ADC 104 is reconstructed as “fast” as possible in the digital domain (eg, by low pass filtering with minimized transients).

[0026] The digital microphone 200 includes a micro-electromechanical system (MEMS) device 202 for converting sound waves into analog output signals. In some embodiments, the MEMS device 202 includes a capacitive silicon MEMS device. The analog output signal of the MEMS device 202 is converted into a digital signal and digitally processed in an application specific integrated circuit (ASIC) 204. The ASIC 204 includes a logarithmic amplifier 208, which may be a Figure 1A or Figure 1B . The output of the logarithmic amplifier 208 is coupled to the input of the ADC 210, which in an embodiment may be a ΣΔ ADC. The output of the ADC 210 is coupled to the input of the digital low-pass filter 212. Several embodiments of the digital low-pass filter 212 are shown and described in detail below, which are specifically designed to minimize audible transients, especially during the switching of the operating mode of the digital microphone 200. The output of the digital low-pass filter 212 is coupled to the input of the digital compression component 214. The output of the digital compression component 214 is coupled to the input of the digital filter 216. In an embodiment, the digital filter 216 may be any suitable filter (e.g., an offset compensation filter). In operation, the digital filter 216 is used to compensate for the offset. The output of the digital filter 216 is coupled to the input of an optional digital modulator 218, which converts the digital signal provided by the digital filter 216 into a one-bit output signal on the output digital bus 220. Finally, the ASIC 204 receives a clock signal at the node 206, which is distributed to one or more of the above components.

[0027] In the case of dynamic AOP switching, the digital microphone 200 can switch operating modes. If the switching is not performed during the zero crossing, a "step" may occur in the signal chain during the switching. This "step" generates a transient in the digital filter chain that degrades performance (e.g., audible artifacts). The digital low-pass filter 212 is designed to address and reduce the impact of these audible artifacts in the various embodiments described below.

[0028] Figure 3 According to the embodiment, suitable for Figure 2Schematic diagram of a high-level block diagram of a digital filter system 300 with transient reduction for a digital microphone 200. The digital filter system 300 includes an input x(k) at a node 310, a controlled upsampling component 302, a digital filter 304, a controlled downsampling component 306, and an output y(k) at a node 321, wherein the digital filter 304 may include a digital low-pass filter. The digital filter system 300 also includes a control unit 308 for receiving a trigger signal at a node 314 and for generating a control signal ("ctr") at a node 316. When the trigger signal at the node 314 is switched, interpolated samples are fed from the controlled upsampling component 302 to the digital filter system 300, and the cutoff frequency of the digital filter 304 is implicitly changed. Synchronously with the interpolation, the controlled downsampling component 306 extracts the output signal of the digital filter 304. In general, the length of the transient is defined by the impulse response of the digital filter 304. For example, if the length of the digital filter is "N" samples, the length of the transient is also the maximum length of "N" samples. According to an embodiment, since the digital filter 304 is filled with interpolated samples "faster", the digital microphone 200 exhibits reduced audible transients. After the filter is "filled", the control unit 308 is switched back to the "normal" operating mode, in which the digital filter 304 is filled with non-interpolated samples at the normal sampling rate. In other words, according to an embodiment, interpolation (and decimation) of the digital filter system 300 is enabled until "N" samples are applied to the digital filter 304, and then switched back to the normal operating mode (in which interpolation (and decimation) is disabled).

[0029] In an embodiment, the digital filter system 300 includes a topology in which the input of a controlled upsampling component 302 is a node 310 for receiving a digital input signal x(k). The output of the controlled upsampling component 302 is coupled to the input of a digital filter 304. The output of the digital filter 304 is coupled to the input of a controlled downsampling component 306. The output of the controlled downsampling component 306 is a node 312 for providing a digital output signal y(k). The input of a control unit 308 is a node 314 for receiving a trigger signal, and the output of the control unit 308 is used to provide a control signal ("ctr") for controlling the selective interpolation and decimation of the input signal samples. Figure 3 An example topology is shown in . Other topologies may be used to provide selective interpolation and decimation associated with digital filter 304 .

[0030] exist Figure 4 An efficient implementation of a digital filter system is shown in . Interpolation is performed using repeaters and multiplexers, and the output signal of the digital filter 304 is then downsampled (without additional filters).

[0031] exist Figure 4 In , the controlled upsampling component 302 includes a repeater 318A having an output coupled to a first input of a multiplexer 320. The multiplexer 320 includes a control input for receiving a "ctr" control signal. A second input of the multiplexer 320 is coupled to an input of the controlled upsampling component 302. The repeater 318A has a constant upsampling rate set by an integer "L", which specifies the number of additional samples that are appended in the interpolation. For example, L=2 means that each input sample is repeated once, and L=3 means that each input sample is repeated twice. In Figure 4 In an embodiment of the present invention, the integer "L" is constant during the operating mode using interpolation and decimation.

[0032] exist Figure 4 , the controlled downsampling component 306 includes a decimation component 322A having an output coupled to a first input of a multiplexer 324. The multiplexer 324 includes a control input for receiving a "ctr" control signal. A second input of the multiplexer 320 is coupled to the input of the controlled downsampling component 306. In this case, the decimation 322A has a constant downsampling rate that is also set by an integer "L" that specifies the number of additional samples removed in the decimation. For example, L=2 means that one of two repeated samples is removed during decimation, and L=3 means that two of three repeated samples are removed during decimation.

[0033] exist Figure 5 An alternative embodiment of variable interpolation / decimation is shown for a digital filter system 500 in FIG. The digital filter system 500 includes a control unit 308 having a first output at a node 316 for providing a "ctr" control signal as discussed above, and the control unit 308 having a second output at a node 326 for providing a "ctr_L" control signal for controlling an integer "L" of a variable repeater 318B and a variable decimation component 322B. For example, when the "ctr_L" signal is in a first state, "L" may assume a first value, and when the "ctr_L" signal is in a second state, "L" may assume a second value, wherein the first value and the second value are different values. In an embodiment, the first value of "L" may be higher than the second value, which means that the digital filter 304 is filled faster during the initial stage of interpolation than in subsequent segments of interpolation.

[0034] Figure 6A digital filter system 600 is shown in which the interpolation component 318C is configured to provide a general interpolation component (higher order interpolation). Higher order interpolation can include polynomial interpolation, piecewise interpolation, "sinc" interpolation, and many other known interpolation techniques. The decimation component 322 is also configured to provide a general decimation component.

[0035] exist Figure 4 , Figure 5 and Figure 6 In the embodiment shown in , when switching between operating modes, information of the input signal x(k) at node 310 is interpolated to fill the digital filter 304 with "N" samples during the switching transient, and then the control unit 308 switches back to the "normal" operating mode after the switching transient, where interpolation is no longer used.

[0036] Figure 7 700 is a simulated step response of a digital low pass filter using a transient reduction circuit device according to an embodiment, and a simulated step response of a digital low pass filter not using a transient reduction circuit device ("reference"). Interpolation of L=2 was used in the simulation. According to an embodiment, chart 700 shows trace 704 associated with a digital low pass filter not using a transient reduction circuit device, and trace 702 associated with a digital low pass filter using a transient reduction circuit device. The x-axis units are sample numbers, and the y-axis units are arbitrary size units. It should be noted that in chart 700, trace 702 stabilizes to a final value before trace 704. In other words, the use of transient reduction circuit devices (controlled interpolation and controlled decimation) improves the transient response to the step function of the digital low pass filter when compared to a digital low pass filter not using a transient reduction circuit device.

[0037] Figure 8 8 is a block diagram of a digital filter system 800 having transient reduction circuitry, showing further details regarding clock signals and labeled internal circuit nodes. Except for the further details and labeled internal circuit nodes described below, the digital filter system 800 is substantially the same as Figure 5 The digital filter system 500 is the same as that shown in FIG. Figure 8 , ADC 210 is shown as having an input at node 328 and an output x(k) at node 310. ADC 210 receives the CLK clock signal at node 206, variable repeater 318B receives the CLK-INT clock signal at node 206A, and variable decimation element 32B receives the CLK-DEC clock signal at node 206. Figure 8 , the output of digital filter 304 is labeled “z(t)” at node 330. In addition, Figure 8The alternative decimation element 306A shown in FIG. 1 is a unit delay element shown in Z-transform notation, where a delay of one sample (L=2) is used. The alternative decimation element 306A may be used in some embodiments in place of the variable decimation element 322B. The operation of the digital filter system 800 is simulated using all clock signals and labeled internal circuit nodes, and in FIG. Fig. 9 The corresponding timing diagram is shown in and described below.

[0038] Fig. 9 is with Figure 8 The block diagram of FIG. 900 is associated with a timing diagram of FIG. 901 . Various clock signals and internal node voltages are shown during three operating modes of the digital microphone according to an embodiment. The three optional modes include a first operating mode, which may be at time t 1 The second operating mode is a transition mode in which controlled interpolation and controlled decimation occur in response to a trigger signal. The transition mode begins at time t 1 , and lasts for a period of time t 2 , and ends at time t 3 The first sub-transition mode starts at time t 1 and ends at time t 2 In a variable interpolation embodiment, the first sub-transition mode is associated with interpolation performed at a first rate. The second sub-transition mode begins at time t 2 and ends at time t 3 In a variable interpolation embodiment, the second sub-transition mode is associated with interpolation performed at a second rate less than the first rate. The third operating mode may be a low power mode (low SNR mode) or a high power mode (high SNR mode) which is at time t 3 happened before.

[0039] Fig. 9 310 'associated with node 330 ; and Y(t) 312 'associated with node 312 .

[0040] CLK-INT 206A' is shown at a relatively low clock rate in the first and third modes of operation. During the first sub-transition mode, CLK-INT 206A' is shown at a first relatively high clock rate, and during the second sub-transition mode, CLK-INT 206A' is shown at a second relatively high clock rate that is lower than the first relatively high clock rate. CTR-MUX 316' is shown as low in the first and third modes of operation and high in the transition mode. CLK 206' and CLK-DEC 206B' are shown at relatively low clock rates in all modes of operation. (In an embodiment, the output y[k] is always at a relatively low clock rate, and extraction is achieved by the clock of register 306A.) In the first mode of operation, the TRIGGER 314' signal is shown as low, but it gradually rises during the first mode of operation, remains low in the transition mode of operation, and gradually decreases during the third mode of operation. X(t) 310', Z(t) 330', and Y(t) 312' are complex digital signals that illustrate the effects of interpolation and decimation on digital data.

[0041] Fig.10 1 is a flow chart of a digital filtering method 1000 for transient reduction in a digital microphone according to an embodiment. The method includes: at step 1002, in a first operating mode, upsampling a digital input signal to provide an interpolated digital signal, filtering the interpolated digital signal, and downsampling the interpolated digital signal to provide a digital output signal; and at step 1004, in a second operating mode, filtering the digital input signal to provide a digital output signal without upsampling or downsampling the digital input signal. In the digital filtering method 1000, the second operating mode includes a low power operating mode or a high power operating mode, and the first operating mode is a transition mode between the low power operating mode and the high power operating mode. In the digital filtering method 1000, upsampling the digital input signal includes constant upsampling or variable upsampling, and downsampling the interpolated digital signal includes constant upsampling or variable upsampling.

[0042] In another embodiment, Fig.14 and Fig.17 A digital filter architecture including a switchable FIR filter is shown and described in further detail below, which avoids the need for an increased sampling frequency. Fig.14 and Fig.17 The filter embodiment shown in FIG. 1 replaces the filter embodiment shown in FIG. Fig.10 The digital filter system shown and described may be with respect to FIG1- Fig.10An alternative to the digital filter system shown and described. In a transient operating mode, the switchable FIR filter is switched to a polyphase FIR filter architecture, and in a low power operating mode or a high power operating mode, the switchable FIR filter is switched to a standard FIR filter architecture. In an embodiment, the switchable polyphase FIR filter uses a modified polyphase architecture to minimize the number of registers used in the filter.

[0043] To minimize transients, Figure 4 The digital filter system 400 operates at a sampling frequency that is L times higher for a limited time (based on the "ctr" control signal). The output signal of the digital filter system is decimated by L, and based on the control signal, the sampling frequency is changed back to the standard sampling frequency.

[0044] In an embodiment, an efficient switchable topology is implemented based on a fifth-order FIR filter, which implements Figure 4 The functions shown, and Fig.14 and Fig.17 The effective switchable topology is shown in FIG. 4 and will be described in detail below. Fig.14 and Fig.17 Embodiments of the invention advantageously do not require a high sampling frequency.

[0045] Fig.11 1 shows an exemplary implementation of the interpolation (upsampling by a factor of L=2) depicted in a standard FIR filter system 1100. The standard FIR filter system 1100 includes a repeater 1108 coupled to an input x[k], a plurality of unit delay elements 1102A, 1102B, 1102C, 1102D shown in Z-transform notation. The plurality of unit delay elements are coupled to a plurality of multipliers 1104A (h 0 )、1104B(h 1 )、1104C(h 2 )、1104D(h 3 )、1104E(h 4 ) and 1104F(h 5 ). The output of each multiplier is the product of the input and the coefficient written inside the multiplier. The multipliers are coupled to adder 1106, and the output y[k] of adder 1106 is the sum of all its inputs.

[0046] However, to avoid the higher sampling frequencies of digital FIR filters, a Fig.12 The polyphase topology of the digital FIR filter system 1200 is shown in FIG. The digital FIR filter system 1200 includes a first filter section, which includes a unit delay element 1202A and a unit delay element 1202B, and a multiplier 1204A (h 0)、Multiplier 1204B(h 2 ) and multiplier 1204C (h 4 ), and adder 1206A. The digital FIR filter system 1200 includes a second filter section, which includes a unit delay element 1202C and a unit delay element 1202D, and a multiplier 1204D (h 1 )、Multiplier 1204E(h 3 ) and multiplier 1204F(h 5 ), and adder 1206B. The output of adder 1206A is coupled to repeater 1208A, and the output of adder 1206B is coupled to repeater 1208B. The output of repeater 1208A is coupled to adder 1210, and the output of repeater 1208B is coupled to adder 1210 through unit delay element 1202E. The output of adder 1210 is the output y[k] of digital FIR filter system 1200.

[0047] exist Fig.13 In FIG. 1 , a polyphase topology operating at a high sampling rate is shown in a digital FIR filter system 1300. The digital FIR filter system 1300 uses a method for Fig.12 The same unit delay elements, multipliers and adders are shown in the digital FIR filter system 1200 shown in FIG. However, repeaters 1208A and 1208B are not used. Instead, repeater 1302 is inserted between the input x[k] and the inputs of the first filter part and the second filter part.

[0048] One potential disadvantage of the digital FIR filter system 1300 is that it requires twice the number of registers compared to the standard FIR filter system 1100 and is therefore relatively inefficient.

[0049] Fig.14 An efficient switchable architecture of a switchable FIR filter 1400 is shown, which implements Figure 4 The function avoids high sampling frequency with minimal registers. Figure 4 With respect to the implementation of the functionality shown in FIG. 1 , according to an embodiment, the switchable FIR filter 1400 advantageously and efficiently switches between a polyphase topology and a standard FIR filter implementation, thereby avoiding the use of a higher clock frequency.

[0050] Switchable FIR filter 1400 includes delay and multiplexer circuit, it includes unit delay component (or register) 1402A, unit delay component 1402B, unit delay component 1402C and unit delay component 1402D, and multiplexer 1408A, multiplexer 1408B, multiplexer 1408C and multiplexer 1408D. The input of multiplexer 1408A is coupled between the input and output of unit delay component 1402A. The input of multiplexer 1408B is coupled between the input and output of unit delay component 1402B. The input of multiplexer 1408C is coupled to the output of unit delay component 1402A and unit delay component 1402C. The input of multiplexer 1408D is coupled to the output of unit delay component 1402B and unit delay component 1402D.

[0051] The first filter portion of the switchable FIR filter 1400 includes a multiplier 1404A (h 0 )、Multiplier 1404B(h 2 ), and multiplier 1404C (h 4 ), and adder 1406A. Multiplier 1404A is coupled between unit delay element 1402A and adder 1406A, multiplier 1404B is coupled between unit delay element 1402B and adder 1406A, and multiplier 1404C is coupled between multiplexer 1408D and adder 1406A. The second filter portion of switchable FIR filter 1400 includes multiplier 1404D (h 1 )、Multiplier 1404E(h 3 ) and multiplier 1404F(h 5 ), and adder 1406B. Multiplier 1404D is coupled between unit delay element 1402A and adder 1406B, multiplier 1404E is coupled between unit delay element 1402B and adder 1406B, and multiplier 1404F is coupled between multiplexer 1408D and adder 1406B.

[0052] The switchable FIR filter 1400 also includes a unit delay element 1402E, a multiplexer 1408E, an adder 1410, and a control unit 1412. The input of the control unit 1412 receives a trigger signal at a node 1414 and provides a "ctr" control signal at a node 1416. The control inputs of multiplexers 1408A, 1408B, 1408C, 1408D, and 1408E are coupled to a node 1416 for receiving the trigger signal. The output of the adder 1406A is coupled to a first input of the adder 1410, and the output of the multiplexer 1408E is coupled to a second input of the adder 1410. The output of the adder 1410 is the output y[k] of the switchable FIR filter 1400. The output of adder 1406B is directly coupled to a first input of multiplexer 1408E and is indirectly coupled to a second input of multiplexer 1408E through unit delay element 1402E.

[0053] In fast transient mode (L=2), half of the registers of the switchable FIR filter 1400 are bypassed, but are preloaded accordingly. In fast transient mode, multiplexer 1408C takes the output of register 1402A (thereby bypassing register 1402C), and multiplexer 1408A takes the input signal [x] and preloads register 1402C. This is also valid for registers 1402D and 1402E. In normal operating mode (low power mode or high power mode), the preloaded registers are switched in, and this configuration then represents the function of the FIR filter. In other words, in fast transient mode, the following components are bypassed: register 1402C, register 1402D and register 1402E. In this way, a polyphase FIR filter architecture is provided. In normal operating mode, none of these registers is bypassed. In this way, a standard FIR filter architecture is provided.

[0054] The switchable FIR filter 1400 advantageously provides a topology that can reduce transients of the digital FIR filter and avoid higher sampling frequencies. Accordingly, because the clock tree of the corresponding digital microphone can be designed based on a single reduced frequency clock signal, this advantageously leads to relatively low power consumption.

[0055] exist Fig.14 In the embodiment of the present invention, the switchable FIR filter architecture is described for an interpolation factor L = 2. The switchable FIR filter architecture can be generalized to include other interpolation factors, such as an interpolation factor of L = 3. Other higher interpolation factors, such as L = 4 or L = 5, or even larger interpolation factors can also be used if necessary.

[0056] Fig.15 1 is a schematic diagram of a standard filter topology for upsampling using a general digital finite impulse response (FIR) filter system 1500 (L=3). The general digital FIR filter system 1500 is Figure 4 1500 is a standard implementation of the functions shown in . The general digital FIR filter system 1500 includes an interpolation component 1508 having an interpolation factor L=3 for receiving a digital input signal x[k]. The interpolation component 1508 is coupled to a standard topology digital filter, which includes a unit delay component 1502A, a unit delay component 1502B, ..., a unit delay component 1502C and a unit delay component 1502D, and a multiplier 1504A (h 0 )、Multiplier 1504B(h 1 )、Multiplier 1504C(h 2 )、Multiplier 1504D(h N-2 )、Multiplier 1504E(h N-1 ) and multiplier 1504F(h N ), and an adder 1506 for providing a digital output signal y[k].

[0057] Fig.16 1 is a schematic diagram of a polyphase FIR filter 1600 having a polyphase FIR filter topology (L=3) operating at a high sampling rate. The polyphase FIR filter 1600 is an intermediate implementation method operating at a high sampling frequency, and Fig.17 The switchable FIR filter topology is shown in FIG. The polyphase FIR filter 1600 includes three branches and three inter-coefficient delays. These two parameters (the number of branches and the number of inter-coefficient delays) are generally defined by the interpolation factor L=3. The first branch includes unit delays 1602A, ..., unit delays 1602B, multipliers 1604A (h 0 )、Multiplier 1604B(h 3 ) and multiplier 1604A (h N-2 ), and adder 1606A. The second branch includes unit delay 1602C, ..., unit delay 1602D, multiplier 1604D (h 1 )、Multiplier 1604E(h 4 ) and multiplier 1604F(h N-1 ), and adder 1606B. The third branch includes unit delay 1602E, ..., unit delay 1602F, multiplier 1604G (h 2 )、Multiplier 1604H(h 5 ) and multiplier 1604I(h N), and adder 1606C. The output of adder 1606A is coupled to adder 1610A, which in turn provides a digital output signal y[k]. The output of adder 1606B is coupled to adder 1610B, which in turn is coupled to adder 1610A via unit delay element 1602G. The output of adder 1606C is coupled to unit delay element 1602H, which in turn is coupled to adder 1610B.

[0058] Fig.17 is a schematic diagram of a switchable polyphase architecture for a finite impulse response (FIR) filter with minimized transients according to an embodiment (L=3). Fig.17 The switchable FIR filter 1700 shown in comprises a delay circuit and a multiplexer coupled to three filter branches. In the transient operation mode, the switchable FIR filter 1700 simulates a polyphase FIR filter topology when a relatively high clock frequency is not necessary. In the normal operation mode, the switchable FIR filter 1700 simulates a standard FIR filter topology. In response to the trigger signal at node 1714, a control unit 1712 is used to generate a "ctr" control signal, which changes the state of the multiplexer in the multiplexer and the delay circuit. The state of the multiplexer then determines the specific topology of the switchable FIR filter 1700.

[0059] The multiplexer and delay circuit includes a unit delay component (or register) 1702A, a unit delay component 1702B, and a unit delay component 1702C coupled to multiplexers 1708A, multiplexers 1708B, and multiplexers 1708C. Each multiplexer receives a "ctr" control signal at the control input of the multiplexer. The subcircuits of unit delay component 1702A, unit delay component 1702B, and unit delay component 1702C and multiplexers 1708A, multiplexers 1708B, and multiplexers 1708C are repeated as required by the interpolation factor of the filter. For example, in switchable FIR filter 1700, the multiplexer and delay subcircuit is repeated once and includes unit delay element 1702D, unit delay element 1702E, and unit delay element 1702F coupled to multiplexer 1708D, multiplexer 1708E, and multiplexer 1708F.

[0060] The switchable FIR filter 1700 includes a first filter branch including a multiplier 1704A (h 0 )、Multiplier 1704B(h 3 ) and multiplier 1704C (h N-2), and adder 1706A. Adder 1706A is coupled to adder 1710A. The second filter branch includes multiplier 1704D (h 1 )、Multiplier 1704E(h 4 ) and multiplier 1704F(h N-1 ), and adder 1706B. Adder 1706B is coupled to adder 1710B. The third filter branch includes multiplier 1704G (h 2 )、Multiplier 1704H(h 5 ) and multiplier 1704I(h N ), and adder 1706C. Adder 1706B is coupled to multiplexer 1708H and unit delay unit 1702H. In an embodiment, the output of adder 1710A provides y[k] digital output signal. Adder 1710A and adder 1710B are coupled together through multiplexer 1708G and unit delay unit 1702G. Adder 1710B and adder 1706C are coupled together through multiplexer 1708H and unit delay unit 1702H.

[0061] In transient operation mode, switchable FIR filter 1700 emulates standard FIR filter topology and no registers are bypassed. In normal operation mode (low power mode or high power mode), switchable FIR filter 1700 emulates polyphase FIR filter topology and bypasses the following registers: 1702B, 1702C, 1702E, 1702F, 1702G and 1702H.

[0062] in short, Fig.14 and Fig.17 An embodiment of a switchable FIR filter topology is shown which advantageously does not require a high clock frequency during transient operating modes and provides Figure 4 All transient reduction functions of the audible transient reduction circuit shown in . In addition, the number of registers can be reduced when compared to a full polyphase filter topology, so that power can also be reduced. The clock tree of a digital microphone incorporating a switchable FIR filter topology can also be simplified.

[0063] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the entirety of the specification and appended claims filed herein.

[0064] Example 1. According to an embodiment, a digital microphone includes: a logarithmic amplifier; an analog-to-digital converter (ADC) coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; and a digital filter coupled to the digital decompression component, wherein the digital filter includes a controlled upsampling component coupled to an input of the digital filter and a controlled downsampling component coupled to an output of the digital filter.

[0065] Example 2. The digital microphone of Example 1, further comprising a controller having an input configured to receive a trigger signal and having a first output.

[0066] Example 3. The digital microphone of any of the preceding examples, wherein the upsampling component comprises a multiplexer having a control input coupled to the first output of the controller.

[0067] Example 4. The digital microphone of any of the preceding examples, wherein the downsampling component comprises a multiplexer having a control input coupled to the first output of the controller.

[0068] Example 5. The digital microphone of any of the preceding examples, wherein the controller further comprises a second output.

[0069] Example 6. The digital microphone of any of the preceding examples, wherein the upsampling component comprises a repeater having a control input coupled to the second output of the controller.

[0070] Example 7. The digital microphone of any of the preceding examples, wherein the downsampling component comprises a decimation component having a control input coupled to the second output of the controller.

[0071] Example 8. The digital microphone of any of the preceding examples, wherein the upsampling component comprises a constant interpolation repeater, a variable interpolation repeater, or a general interpolation component.

[0072] Example 9. The digital microphone of any of the preceding examples, wherein the downsampling component comprises a constant decimation component, a variable decimation component, or a general decimation component.

[0073] Example 10. The digital microphone of any of the preceding examples, wherein the ADC comprises a ΣΔ converter.

[0074] Example 11. According to an embodiment, a digital filter system includes: a controlled upsampling component coupled to an input of a digital filter; a digital filter having an input coupled to an output of the controlled upsampling component; a controlled downsampling component coupled to the output of the digital filter; and a controller having a trigger signal input and a first output, the first output being coupled to a first control input of the controlled upsampling component and coupled to a first control input of the controlled downsampling component.

[0075] Example 12. The digital filter system of Example 11, wherein the controller further comprises a second output coupled to the second control input of the controlled upsampling component and coupled to the second control input of the controlled downsampling component.

[0076] Example 13. The digital filter system of any of the preceding examples, wherein the upsampling component comprises a constant interpolation repeater, a variable interpolation repeater, or a general interpolation component.

[0077] Example 14. The digital microphone of any of the preceding examples, wherein the downsampling component comprises a constant decimation component, a variable decimation component, or a general decimation component.

[0078] Example 15. The digital microphone of any of the preceding examples, wherein at least one of the upsampling component and the downsampling component comprises a multiplexer.

[0079] Example 16. According to an embodiment, the method includes: in a first operating mode, upsampling a digital input signal to provide an interpolated digital signal, filtering the interpolated digital signal, and downsampling the interpolated digital signal to provide a digital output signal; and in a second operating mode, filtering the digital input signal to provide a digital output signal without upsampling or downsampling the digital input signal.

[0080] Example 17. The method of Example 16, wherein the second operating mode comprises a low power operating mode or a high power operating mode.

[0081] Example 18. The method of any of the preceding examples, wherein the first operating mode is a transition mode between a low power operating mode and a high power operating mode.

[0082] Example 19. The method of any of the preceding examples, wherein upsampling the digital input signal comprises constant upsampling or variable upsampling.

[0083] Example 20. The method of any of the preceding examples, wherein downsampling the interpolated digital signal comprises constant upsampling or variable upsampling.

[0084] Example 21. According to an embodiment, a digital filter system includes a switchable FIR filter configured to switch between a standard FIR filter architecture and a polyphase FIR filter architecture.

[0085] Example 22. The digital filter system of Example 21, wherein the FIR filter comprises a multiplexer switching circuit.

[0086] Example 23. A digital filtering method for a digital microphone, the method comprising: switching between a standard FIR filter architecture in a first operating mode of the digital microphone and a polyphase FIR filter architecture in a second operating mode of the digital microphone.

[0087] Example 24. The digital filtering method of Example 23, wherein the FIR filter includes a multiplexer switching circuit for switching between the first operating mode and the second operating mode.

[0088] Example 25. The digital filtering method of any of the preceding examples, wherein the multiplexer switching circuit comprises a plurality of multiplexers, and wherein each of the plurality of multiplexers comprises a control input for receiving a control signal.

[0089] Although the present invention is described with reference to illustrative embodiments, this description is not intended to be interpreted as limiting. The technician will understand various modifications and combinations of the illustrated embodiments, as well as other embodiments of the present invention, after referring to this specification. Therefore, the attached claims are intended to cover any such modifications or embodiments.

Claims

1. A digital microphone, comprising: Logarithmic amplifier; an analog-to-digital converter ADC coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; as well as A digital filter is coupled to the digital decompression component, wherein the digital filter includes a controlled up-sampling component coupled to an input of the digital filter and a controlled down-sampling component coupled to an output of the digital filter. 2 . The digital microphone of claim 1 , further comprising a controller having an input configured to receive a trigger signal and having a first output.

3. The digital microphone of claim 2, wherein the upsampling component comprises a multiplexer having a control input coupled to the first output of the controller.

4. The digital microphone of claim 2, wherein the downsampling component comprises a multiplexer having a control input coupled to the first output of the controller.

5. The digital microphone of claim 2, wherein the controller further comprises a second output.

6. The digital microphone of claim 5, wherein the upsampling component comprises a repeater having a control input coupled to the second output of the controller.

7. The digital microphone of claim 5, wherein the downsampling component comprises a decimation component having a control input coupled to the second output of the controller. 8 . The digital microphone according to claim 1 , wherein the up-sampling component comprises a constant interpolation repeater, a variable interpolation repeater, or a general interpolation component. 9 . The digital microphone of claim 1 , wherein the down-sampling component comprises a constant decimation component, a variable decimation component, or a general decimation component.

10. The digital microphone of claim 1, wherein the ADC comprises a ΣΔ converter.

11. A digital filter system, comprising: a controlled upsampling component coupled to an input of the digital filter; a digital filter having an input coupled to the output of the controlled upsampling component; a controlled downsampling component coupled to an output of the digital filter; as well as A controller has a trigger signal input and a first output coupled to a first control input of the controlled up-sampling component and to a first control input of the controlled down-sampling component.

12. The digital filter system of claim 11, wherein the controller further comprises a second output coupled to a second control input of the controlled upsampling component and to a second control input of the controlled downsampling component.

13. The digital filter system according to claim 11, wherein the up-sampling component comprises a constant interpolation repeater, a variable interpolation repeater or a general interpolation component.

14. The digital microphone of claim 1, wherein the down-sampling component comprises a constant interpolation component, a variable interpolation component, or a general interpolation component.

15. The digital microphone of claim 1, wherein at least one of the upsampling component and the downsampling component comprises a multiplexer.

16. A method comprising: In a first operating mode, upsampling a digital input signal to provide an interpolated digital signal, filtering the interpolated digital signal, and downsampling the interpolated digital signal to provide a digital output signal; as well as In a second mode of operation, the digital input signal is filtered to provide the digital output signal without upsampling or downsampling the digital input signal. The method of claim 16 , wherein the second operating mode comprises a low power operating mode or a high power operating mode.

18. The method of claim 17, wherein the first operation mode is a transition mode between the low power operation mode and the high power operation mode.

19. The method of claim 16, wherein upsampling the digital input signal comprises constant upsampling or variable upsampling.

20. The method of claim 16, wherein downsampling the interpolated digital signal comprises constant upsampling or variable upsampling.

21. A digital filter system comprising a switchable FIR filter configured to switch between a standard FIR filter architecture and a polyphase FIR filter architecture.

22. The digital filter system of claim 21, wherein the FIR filter comprises a multiplexer switching circuit.

23. A digital filtering method for a digital microphone, the method comprising: Switching is performed between a standard FIR filter architecture in a first operating mode of the digital microphone and a polyphase FIR filter architecture in a second operating mode of the digital microphone.

24. The digital filtering method of claim 23, wherein the FIR filter comprises a multiplexer switching circuit for switching between the first operation mode and the second operation mode.

25. The digital filtering method of claim 24, wherein the multiplexer switching circuit comprises a plurality of multiplexers, and wherein each of the plurality of multiplexers comprises a control input for receiving a control signal.

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