Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel includes: a substrate; the active layer and the conductive layers are stacked on one side of the substrate; the active layer and the plurality of conductive layers form at least one gate driving circuit; the gate drive circuit comprises a plurality of transistors, and the plurality of transistors comprise at least one switch transistor and at least one output transistor; the plurality of conductive layers comprise a first conductive layer, a second conductive layer and a third conductive layer which are sequentially stacked in the direction away from the substrate; the active layer is arranged between the first conductive layer and the second conductive layer; the third conductive layer comprises a first power line; the bottom gate of each transistor is located on the first conductive layer, the top gate of each transistor is located on the second conductive layer, the top and bottom gates of the switch transistor are connected, and the bottom gate of the output transistor is electrically connected with a first power line. According to the embodiment of the invention, the output effect of the gate drive circuit can be improved, and the occupied area of the gate drive circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the display performance of display panels. The display panel includes a gate drive circuit for generating a gate drive signal, and the output effect and layout of the gate drive circuit affect the display effect and border width of the display panel. Summary of the invention

[0003] The present invention provides a display panel and a display device to improve the output effect of a gate driving circuit and reduce the occupied area of ​​the gate driving circuit, which is beneficial to improving the display effect of the display panel and realizing a narrow frame.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] substrate;

[0006] An active layer and a plurality of conductive layers are stacked on one side of the substrate;

[0007] The active layer and the plurality of conductive layers are used to form a gate drive circuit, the gate drive circuit includes a plurality of transistors, the plurality of transistors include at least one switch transistor and at least one output transistor, each of the switch transistors and each of the output transistors is a double-gate transistor having a top gate and a bottom gate;

[0008] The multiple conductive layers include: a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence in a direction away from the substrate; the active layer is arranged between the first conductive layer and the second conductive layer; the third conductive layer includes a first power line; the bottom gate of each of the transistors is located in the first conductive layer, the top gate of each of the transistors is located in the second conductive layer, the top gate of any of the switching transistors is connected to the bottom gate of the same switching transistor, and the bottom gate of the output transistor is electrically connected to the first power line.

[0009] Optionally, the top gate and the bottom gate of the same switching transistor are connected via a gate connection line located in the third conductive layer;

[0010] Preferably, the third conductive layer further comprises a plurality of transmission lines, at least some of which connect different transistors; the first electrode and the second electrode of each transistor are both located in the third conductive layer; wherein each transistor comprises an active region located in the active layer, and the active region comprises: a channel region, a source region and a drain region; the orthographic projection of the top gate and the bottom gate of any transistor on the substrate at least partially overlaps with the orthographic projection of the channel region of the transistor on the substrate, and the first electrode and the second electrode of the transistor extend from the active layer to the third conductive layer;

[0011] Preferably, the material of the third conductive layer includes titanium aluminum titanium;

[0012] The materials of the first conductive layer and the second conductive layer both include molybdenum;

[0013] Preferably, each of the transistors is an N-type transistor;

[0014] Preferably, the material of the active layer includes indium gallium zinc oxide.

[0015] Optionally, the channel region of each of the transistors is located in the active layer; the orthographic projection of the first conductive layer on the substrate covers the orthographic projections of the channel regions of all the transistors on the substrate;

[0016] Preferably, the orthographic projection of the bottom gate of any of the transistors on the substrate covers the orthographic projection of the top gate of the same transistor on the substrate;

[0017] Preferably, the orthographic projection area of ​​the bottom gate of any of the transistors on the substrate is larger than the orthographic projection area of ​​the top gate of the same transistor on the substrate;

[0018] Preferably, the orthographic projection of the bottom gate of any of the transistors on the substrate has a first contour edge, and the orthographic projection of the top gate of the same transistor on the substrate has a second contour edge, and the first contour edge is outside the second contour edge;

[0019] Preferably, the material of the first conductive layer includes a light-proof conductive material;

[0020] Preferably, the material of the first conductive layer includes molybdenum.

[0021] Optionally, the active layer includes a switch tube active region and an output tube active region, and the area of ​​the output tube active region is at least three times that of the switch tube active region;

[0022] The output tube active region comprises a first output tube active region and a second output tube active region connected to each other, and an orthographic projection area of ​​the first output tube active region on the substrate is smaller than an orthographic projection area of ​​the second output tube active region on the substrate;

[0023] The switch tube active area includes a plurality of switch tube active sub-areas spaced apart from each other;

[0024] Preferably, the first output tube active area includes a plurality of first active segments arranged at intervals, the plurality of first active segments are sequentially arranged along the second direction, the second output tube active area includes a plurality of second active segments arranged at intervals, the plurality of second active segments are sequentially arranged along the second direction, the first active segments and the second active segments are arranged along the first direction, and in the first direction, the second active segments are connected to the first active segments;

[0025] Some of the second active segments are connected to two adjacent first active segments;

[0026] Preferably, the display panel further comprises a light shielding portion located on a side of the third conductive layer away from the substrate, and an orthographic projection of the light shielding portion on the substrate covers the active area of ​​the switch tube and the active area of ​​the output tube;

[0027] Preferably, the at least one output transistor comprises a first transistor and a second transistor, the first conductive layer comprises a first transistor bottom gate and at least one second transistor bottom gate extending along the second direction, the second conductive layer comprises a first transistor top gate and at least one second transistor top gate extending along the second direction, the orthographic projections of the first transistor bottom gate and the first transistor top gate on the substrate overlap with the orthographic projections of all the first active segments on the substrate, and the orthographic projections of the second transistor bottom gate and the second transistor top gate on the substrate overlap with the orthographic projections of all the second active segments on the substrate;

[0028] Preferably, the display panel further comprises a light shielding portion located on a side of the third conductive layer away from the substrate, and an orthographic projection of the light shielding portion on the substrate covers an orthographic projection of the gate driving circuit on the substrate;

[0029] Preferably, the plurality of conductive layers further include: a fourth conductive layer and a fifth conductive layer sequentially stacked on a side of the third conductive layer away from the substrate;

[0030] The light shielding portion is located on the fourth conductive layer and the fifth conductive layer;

[0031] The orthographic projection of the light shielding portion located in the fourth conductive layer on the substrate and the orthographic projection of the light shielding portion located in the fifth conductive layer on the substrate jointly cover the orthographic projections of the active regions of all the transistors on the substrate;

[0032] Preferably, the orthographic projection of the light shielding portion located on the fourth conductive layer on the substrate and the orthographic projection of the light shielding portion located on the fifth conductive layer on the substrate jointly cover the orthographic projection of all the gate driving circuits on the substrate;

[0033] Preferably, the light shielding portion located on the fourth conductive layer and the light shielding portion located on the fifth conductive layer are both electrically connected to the DC signal;

[0034] Preferably, the display panel further includes:

[0035] A first interlayer insulating layer, located between the third conductive layer and the fourth conductive layer;

[0036] a planarization layer, located between the fourth conductive layer and the fifth conductive layer;

[0037] The materials of the first interlayer insulating layer and the planarization layer both include organic materials;

[0038] The fourth conductive layer includes at least one first gas release hole, the fifth conductive layer includes at least one second gas release hole, and the orthographic projection of the first gas release hole on the substrate does not overlap with the orthographic projection of the second gas release hole on the substrate;

[0039] Preferably, the materials of the fourth conductive layer and the fifth conductive layer both include opaque conductive layer materials;

[0040] Preferably, the material of the fourth conductive layer includes titanium aluminum titanium; the material of the fifth conductive layer includes silver;

[0041] Preferably, the display panel includes: a display area and a frame area, the frame area is arranged around the display area; all the gate driving circuits are located in the frame area; the display area is provided with a light-emitting device, a data line and a DC signal line; the anode of the light-emitting device is located in the fifth conductive layer, and the data line and / or the DC signal line are located in the fourth conductive layer.

[0042] Optionally, the third conductive layer further includes: a clock signal line for providing a clock signal to the gate drive circuit; the clock signal line extends along a first direction; along a second direction, a plurality of the gate drive circuits are located on the same side of the clock signal line; the first direction is perpendicular to the second direction;

[0043] Preferably, the number of the clock signal lines is four, and each of the clock signal lines is arranged along the second direction; the number of the gate drive circuits is multiple, and the layout areas of each of the gate drive circuits are arranged in sequence along the first direction;

[0044] Two of the clock signal lines are connected to each odd-numbered gate drive circuit, and the other two of the clock signal lines are connected to each even-numbered gate drive circuit;

[0045] Preferably, the first power line extends along the first direction; along the second direction, the first power line is arranged on a side of the second layout area away from the first layout area;

[0046] Preferably, the display panel includes: a display area and a border area, the border area is arranged around the display area; the layout area of ​​the clock signal line and the gate drive circuit are both located in the border area, and along the second direction, the clock signal line is arranged on the side of the layout area of ​​the gate drive circuit away from the display area.

[0047] Optionally, the plurality of conductive layers further include: a sixth conductive layer located between the substrate and the first conductive layer; the gate drive circuit further includes at least one capacitor;

[0048] For any of the capacitors, one electrode plate of the capacitor is located on the sixth conductive layer, the other electrode plate of the capacitor is located on the first conductive layer, and the orthographic projections of the two electrodes of the capacitor on the substrate at least partially overlap.

[0049] Optionally, the third conductive layer includes a second power line extending along the first direction, at least two clock signal lines extending along the first direction, and output signal lines of each of the gate drive circuits; the at least one output transistor includes a first transistor and a second transistor, the at least one switch transistor includes a third transistor and a fourth transistor, and the at least one capacitor includes a first capacitor;

[0050] The bottom gate of the first transistor is connected to the first power line through a first connection line, the first electrode of the first transistor is connected to the second power line through a second connection line, and the second electrode of the first transistor is connected to the output signal line; the first electrode of the second transistor is connected to a clock signal line for providing a second clock signal to the gate driving circuit through a third connection line, and the second electrode of the second transistor is connected to the output signal line; the bottom gate of the second transistor is connected to the first plate of the first capacitor through a fourth connection line, the first electrode of the third transistor is connected to the fourth connection line through a fifth connection line, the second electrode of the third transistor is connected to the bottom gate of the first transistor through a sixth connection line, and the top gate of the third transistor is connected to the top gate of the first transistor through a seventh connection line; the second plate of the first capacitor is connected to the first electrode of the fourth transistor through an eighth connection line, the second electrode of the fourth transistor is connected to the third connection line through a ninth connection line, and the top gate of the fourth transistor is connected to the top gate of the second transistor;

[0051] Preferably, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor all extend along the second direction, and the orthographic projections of the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor on the substrate cover the orthographic projections of the active areas of the first transistor and the second transistor on the substrate; the first electrode of the second transistor includes at least two first electrode plates extending along the second direction and arranged along the first direction, and the second conductive layer includes at least two second transistor top gates extending along the second direction and arranged along the first direction; the orthographic projections of the first electrode plates on the substrate and the orthographic projections of the second transistor top gates on the substrate are alternately arranged;

[0052] Preferably, the first connecting line, the second connecting line, the fourth connecting line and the first electrode plate of the first capacitor are located in the first conductive layer; the seventh connecting line is located in the second conductive layer; at least part of the third connecting line, the fifth connecting line, the sixth connecting line, the eighth connecting line and the ninth connecting line are located in the third conductive layer; the second electrode plate of the first capacitor is located in the sixth conductive layer;

[0053] Preferably, the third connection line includes a first sub-connection line, a second sub-connection line, a third sub-connection line and a fourth sub-connection line sequentially connected between the first electrode of the second transistor and a clock connection line for providing a second clock signal to the gate drive circuit; the first sub-connection line and the third sub-connection line are located in the third conductive layer, the second sub-connection line is located in the sixth conductive layer, and the fourth sub-connection line is located in the first conductive layer;

[0054] Preferably, the capacitance of the first capacitor is greater than the parasitic capacitance at the bottom gate of the second transistor.

[0055] Optionally, the at least one capacitor further includes: a second capacitor and a third capacitor;

[0056] The bottom gate of the third transistor is connected to the first plate of the second capacitor through a tenth connecting line, and the first electrode of the first transistor is connected to the second plate of the second capacitor through an eleventh connecting line;

[0057] The top gate of the second transistor is connected to the first plate of the third capacitor through a twelfth connecting line, and the second gate of the first transistor is connected to the second plate of the third capacitor through a thirteenth connecting line;

[0058] Preferably, the tenth connecting line, the first electrode plate of the second capacitor and the first electrode plate of the third capacitor are all located in the first conductive layer; the twelfth connecting line is located in the second conductive layer; the eleventh connecting line and the thirteenth connecting line are both located in the third conductive layer; the second electrode plate of the second capacitor and the second electrode plate of the third capacitor are both located in the sixth conductive layer;

[0059] Preferably, the capacitance of the second capacitor is greater than the parasitic capacitance at the top gate of the first transistor;

[0060] Preferably, the capacitance of the third capacitor is greater than the parasitic capacitance at the top gate of the second transistor.

[0061] Optionally, the third conductive layer further includes a third power supply line and an input signal line of each gate drive circuit; the at least one switch transistor further includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;

[0062] The first electrode of the fifth transistor is connected to the input signal line, the bottom gate of the fifth transistor is connected to the clock signal line for providing the first clock signal to the gate driving circuit through a fourteenth connecting line, and the second electrode of the fifth transistor is connected to the top gate of the sixth transistor through a fifteenth connecting line; the first electrode of the sixth transistor is connected to the top gate of the fifth transistor through a sixteenth connecting line, and the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor through a seventeenth connecting line; the first electrode of the seventh transistor is connected to the third power line, the top gate of the seventh transistor is connected to the top gate of the fifth transistor, and the bottom gate of the seventh transistor is connected to the bottom gate of the fifth transistor;

[0063] The first electrode of the eighth transistor is connected to the second electrode plate of the second capacitor through an eighteenth connecting line, the top gate of the eighth transistor is connected to the seventeenth connecting line, and the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor through a nineteenth connecting line; the top gate of the ninth transistor is connected to the third connecting line, and the second electrode of the ninth transistor is connected to the top gate of the sixth transistor through a twentieth connecting line; the first electrode of the tenth transistor and the top gate of the fourth transistor are both connected to the twentieth connecting line, the top gate of the tenth transistor is connected to the third power supply line through a twenty-first connecting line, and the second electrode of the tenth transistor is connected to the first electrode plate of the third capacitor through a twenty-second connecting line;

[0064] Preferably, the fourteenth connecting line is located in the first conductive layer; the fifteenth connecting line, the sixteenth connecting line, the seventeenth connecting line, the eighteenth connecting line, the nineteenth connecting line, at least a portion of the twentieth connecting line, the twenty-first connecting line, and at least a portion of the twenty-second connecting line are located in the third conductive layer;

[0065] Preferably, the 20th connection line includes: a fifth sub-connection line, a sixth sub-connection line and a seventh sub-connection line sequentially connected between the second electrode of the ninth transistor and the top gate of the sixth transistor, wherein the sixth sub-connection line is connected between the first electrode of the tenth transistor and the top gate of the fourth transistor; the fifth sub-connection line and the sixth sub-connection line are located in the third conductive layer, and the seventh sub-connection line is located in the first conductive layer;

[0066] Preferably, the 22nd connecting line includes an eighth sub-connecting line and a ninth sub-connecting line sequentially connected between the second electrode of the tenth transistor and the first electrode plate of the third capacitor; the eighth sub-connecting line is located in the third conductive layer, and the ninth sub-connecting line is located in the first conductive layer;

[0067] Preferably, each of the clock signal lines extends along the first direction; along the second direction, each of the clock signal lines is arranged on one side of the layout area of ​​the gate drive circuit; the layout area of ​​the gate drive circuit includes a first sub-layout area, a second sub-layout area and a second layout area which are sequentially away from any of the clock signal lines along the second direction; the first sub-layout area is provided with the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor, the second sub-layout area is provided with the first capacitor, the second capacitor, the third capacitor, the third transistor and the fourth transistor, and the second layout area is provided with the first transistor and the second transistor; the first direction is perpendicular to the second direction;

[0068] Preferably, the width-to-length ratios of the fifth transistor and the tenth transistor are both greater than the width-to-length ratios of the other switch transistors;

[0069] Preferably, the second conductive layer and the third conductive layer are connected via a first type via; the third conductive layer and the active layer are connected via a second type via, and the first type via and the second type via are prepared in the same mask process;

[0070] The third conductive layer is connected to the first conductive layer through a third type via, and the third conductive layer is connected to the sixth conductive layer through a fourth type via. The third type via and the fourth type via are prepared in the same mask process.

[0071] In a second aspect, an embodiment of the present invention further provides a display device, comprising: a display panel provided by any embodiment of the present invention.

[0072] In the display panel provided by the embodiment of the present invention, at least one gate drive circuit is formed by stacking an active layer and a plurality of conductive layers, and a first power line is set in the third conductive layer. By setting each transistor in the gate drive circuit to be a dual-gate transistor with a top gate and a bottom gate, compared with the use of a single-gate transistor, the size of the transistor can be effectively reduced, thereby reducing the occupied area of ​​the gate drive circuit, which is conducive to achieving a narrow frame. By setting the top gate and the bottom gate of the switching transistor to be connected, it is conducive to quickly realizing the on-off control of the switching transistor, reducing the voltage jump time of the internal node of the gate drive circuit, avoiding the distortion of the output signal of the gate drive circuit due to the delay of the internal node voltage change, and is conducive to achieving high-frequency drive. And, by setting the bottom gate of the output transistor to be electrically connected to the first power line, the threshold voltage of the output transistor can be adjusted by adjusting the bottom gate voltage of the output transistor to improve the driving ability of the output transistor and improve the problem of waveform distortion of the output signal of the gate drive circuit. In summary, the embodiment of the present invention can improve the output effect of the gate drive circuit and reduce the occupied area of ​​the gate drive circuit, which is conducive to improving the display effect of the display panel and achieving a narrow frame.

[0073] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0075] Figure 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0076] Figure 2 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0077] Figure 3 is a schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention;

[0078] Figure 4 is a schematic structural diagram of an active layer provided by an embodiment of the present invention;

[0079] Figure 5 is a schematic structural diagram of a first conductive layer provided by an embodiment of the present invention;

[0080] Figure 6 is a schematic structural diagram of a second conductive layer provided by an embodiment of the present invention;

[0081] Figure 7 is a schematic diagram of a stacked structure of a first conductive layer, an active layer, and a second conductive layer provided by an embodiment of the present invention;

[0082] Figure 8 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0083] Fig. 9 is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0084] Fig.10 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0085] Fig.11 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0086] Fig.12 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0087] Fig.13 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0088] Fig.14is a timing diagram of multiple gate drive circuits provided by an embodiment of the present invention;

[0089] Fig.15 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0090] Fig.16 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0091] Fig.17 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0092] Fig.18 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0093] Fig.19 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0094] Fig. 20 yes Fig.19 Schematic diagram of the enlarged structure of area F in the middle. DETAILED DESCRIPTION

[0095] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0096] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0097] An embodiment of the present invention provides a display panel. Figure 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention. Figure 1 The display panel includes: a substrate 100, and an active layer 70 and a plurality of conductive layers stacked on one side of the substrate 100.

[0098] Among them, the active layer 70 and the plurality of conductive layers are used to form at least one gate drive circuit (Gatein Panel, GIP). The output signal of the gate drive circuit is a gate drive signal provided to the gate of the transistor in the pixel circuit, such as a scan signal, which is used to control the on and off of the transistor in the pixel circuit. The gate drive circuit can be arranged in the frame area of ​​the display panel, such as the left and right frames; the pixel circuit can be arranged in the display area of ​​the display panel. The gate drive circuit includes a plurality of transistors, and the plurality of transistors include at least one switching transistor STFT and at least one output transistor OTFT; each switching transistor STFT and each output transistor OTFT are double-gate transistors with top gate and bottom gate. The plurality of conductive layers include: a first conductive layer 10, a second conductive layer 20 and a third conductive layer 30 stacked in sequence in a direction away from the substrate 100. The active layer 70 is arranged between the first conductive layer 10 and the second conductive layer 20; the third conductive layer 30 includes a first power line LVGLL. The bottom gate of each transistor is located in the first conductive layer 10, the top gate of each transistor is located in the second conductive layer 20, the top gate of any switch transistor STFT is connected to the bottom gate of the same switch transistor STFT, and the bottom gate of the output transistor OTFT is electrically connected to the first power line LVGLL.

[0099] Figure 1 In the embodiment, a switching transistor STFT and an output transistor OTFT are exemplarily given, and a top gate and a bottom gate of the switching transistor STFT are connected through a connecting line located in the third conductive layer 30, and a structure in which the bottom gate of the output transistor OTFT is directly connected to the first power line LVGLL is exemplarily given, but it is not intended to limit the present invention. In other embodiments, the top gate and the bottom gate of the switching transistor STFT may be directly connected through a via, and the bottom gate of the output transistor OTFT may be indirectly connected to the first power line LVGLL through the switching transistor STFT or other components. The specific configuration may be based on the actual process, circuit function requirements, and layout space, and is not limited here.

[0100] The active layer 70 may include the channel region of each transistor, the positive projection of the top gate of any transistor on the substrate 100 at least partially overlaps with the positive projection of the channel region of the transistor on the substrate 100, and the positive projection of the bottom gate of any transistor on the substrate 100 at least partially overlaps with the positive projection of the channel region of the transistor on the substrate 100. It can be understood that Figure 1 In the figure, only the top gate, channel region and bottom gate of each transistor are shown as examples, but the source-drain related structures of the transistor are not shown. For example, the source-related structures and the drain-related structures are arranged in a direction perpendicular to the paper surface. Figure 1 Both sides of the position shown.

[0101] By setting the switching transistor STFT to a dual-gate structure with a top gate and a bottom gate, and directly connecting the top gate and the bottom gate of the switching transistor STFT, current can flow through the upper and lower surfaces of the channel of the switching transistor STFT, thereby increasing the driving current, which is conducive to quickly realizing the on-off control of the switching transistor STFT, thereby realizing a rapid jump in the voltage of the node connected to the switching transistor STFT, that is, reducing the voltage jump time of the internal node of the gate drive circuit, which is conducive to realizing high-frequency drive; on the other hand, on the basis of realizing the same function, the dual-gate structure can effectively reduce the size of the transistor compared to the single-gate structure.

[0102] By electrically connecting the bottom gate of the output transistor OTFT to the first power line LVGLL, the output transistor OTFT can be made into a top gate drive device, and the bottom gate voltage can be used to adjust the threshold voltage of the output transistor OTFT, so as to shorten the turn-on delay of the output transistor OTFT when the output transistor OTFT needs to be turned on, thereby reducing the delay of the output signal of the gate drive circuit, and / or, when the output transistor OTFT is turned off, reduce the cut-off current of the output transistor OTFT, thereby reducing the distortion of the output signal and ensuring the normal output of the output signal. The voltage on the first power line LVGLL can be adjusted according to actual needs, for example, a DC voltage can be transmitted. Exemplarily, the adjustment direction of the threshold voltage of the output transistor OTFT by the voltage transmitted by the first power line LVGLL can be set according to actual needs, for example, the threshold voltage can be controlled to be positive or negative, so as to realize the adjustment function in one of the above-mentioned turn-on and turn-off states. Among them, the voltage transmitted by the first power line LVGLL can be set according to the state in which the output transistor OTFT is kept for a longer time / higher importance during the operation process, so as to ensure that the first power line LVGLL provides the threshold adjustment function for the output transistor OTFT in most periods / important periods. In the case where the bottom gate of the output transistor OTFT is indirectly connected to the first power line LVGLL, other components in the gate driving circuit can be used to control the voltage transmitted by the first power line LVGLL to be provided to the bottom gate of the output transistor OTFT in the above-mentioned most of the time periods / important time periods, and prevent the voltage transmitted by the first power line LVGLL from being provided to the bottom gate of the output transistor OTFT in other time periods, so as to avoid the voltage transmitted by the first power line LVGLL from having an adverse effect on the working state in other time periods.

[0103] Exemplarily, the substrate 100 is used to provide protection and support for other film layers of the display panel. The substrate 100 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. Each conductive layer can be composed of any conductive material, such as a metal, alloy, metal oxide or non-metallic conductive material, and specific materials may include silver, molybdenum, titanium, aluminum and copper. It can be understood that at least one insulating layer is provided between each two adjacent conductive layers, and at least one insulating layer is also provided between the active layer 70 and the conductive layer adjacent thereto; the material of the insulating layer can be set to an inorganic material or an organic material according to requirements, and is not specifically limited here. Two structures located in two different film layers can be directly connected through vias, or can be bridged through connecting wires located in other conductive layers (that is, both structures are connected to the same connecting wire through vias to achieve electrical connection).

[0104] In the display panel provided by the embodiment of the present invention, at least one gate drive circuit is formed by stacking an active layer 70 and a plurality of conductive layers, and a first power line LVGLL is set on the third conductive layer 30. By setting each transistor in the gate drive circuit to be a dual-gate transistor with a top gate and a bottom gate, compared with the use of a single-gate transistor, the size of the transistor can be effectively reduced, thereby reducing the occupied area of ​​the gate drive circuit, which is conducive to achieving a narrow frame. By setting the top gate and the bottom gate of the switching transistor STFT to be connected, it is conducive to quickly realizing the on-off control of the switching transistor STFT, reducing the voltage jump time of the internal node of the gate drive circuit, avoiding the distortion of the output signal of the gate drive circuit due to the delay of the internal node voltage change, and is conducive to achieving high-frequency drive. And, by setting the bottom gate of the output transistor OTFT to be electrically connected to the first power line, the threshold voltage of the output transistor OTFT can be adjusted by adjusting the bottom gate voltage of the output transistor OTFT to improve the driving ability of the output transistor OTFT and improve the problem of output signal waveform distortion of the gate drive circuit. In summary, the embodiment of the present invention can improve the output effect of the gate drive circuit and reduce the occupied area of ​​the gate drive circuit, which is conducive to improving the display effect of the display panel and achieving a narrow frame.

[0105] On the basis of the above-mentioned embodiments, optionally, each transistor in the gate drive circuit is an N-type transistor. Exemplarily, the material of the active layer 70 includes an oxide material, such as indium gallium zinc oxide (IGZO). In this way, it is equivalent to providing a GIP circuit based on a full oxide TFT process. The N-type IGZO transistor has the advantages of low leakage current and low process cost, which is beneficial to improving the display effect and reducing the panel cost, and is beneficial to the preparation of medium and large-sized screens. And through the relevant settings of the above-mentioned dual-gate transistors, the problem that the threshold voltage of the N-type IGZO transistor is discrete and easily negative, as well as the problem of large borders can be effectively solved.

[0106] Continue to see Figure 1 On the basis of the above embodiments, optionally, the top gate and the bottom gate of the same switch transistor STFT are connected by a gate connection line located in the third conductive layer 30. Exemplarily, the third conductive layer 30 is made of a material with a smaller square resistance than the first conductive layer 10 and the second conductive layer 20, so that the impedance of the connection structure between the top gate and the bottom gate of the switch transistor STFT can be effectively reduced. Exemplarily, the material of the third conductive layer 30 includes titanium aluminum titanium, for example, a stacked structure in which a titanium layer, an aluminum layer and a titanium layer are stacked in sequence. The materials of the first conductive layer 10 and the second conductive layer 20 may both include molybdenum.

[0107] Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present invention. Figure 2 On the basis of the above embodiments, the third conductive layer 30 may further include a plurality of transmission lines LL, at least some of which connect different transistors. Specifically, the first electrode and the second electrode of each transistor TFT are both located in the third conductive layer 30; at least some of the connection lines between the top gate, the first electrode or the second electrode of each transistor TFT and the top gate, the first electrode or the second electrode of other transistors TFT may be realized by the transmission lines LL located in the third conductive layer 30. It is understandable that Figure 2 The transistor TFT shown can be a switch transistor STFT or an output transistor OTFT, and any two transistors TFT that are in a connection relationship can be connected through corresponding connection lines. Figure 2 As shown, the left transistor TFT has a first electrode on the left and a second electrode on the right, and its second electrode is connected to the top gate of the right transistor TFT through a transmission line LL located in the third conductive layer 30 .

[0108] Exemplarily, the connection lines between different transistors TFT can be mainly realized by using the transmission lines LL located in the third conductive layer 30; in some locations where routing is inconvenient, such as locations where the routing of the transmission lines LL set in the same layer will cross or there is insufficient routing space, a jumper connection line located in other conductive layers can be set; if the top gates of two transistors need to be connected, they can also be directly connected using the connection lines on the second conductive layer 20, and if the bottom gates of two transistors need to be connected, they can also be directly connected using the connection lines on the first conductive layer 10 to reduce the number of vias. Among them, the third conductive layer 30 is made of a material with a smaller square resistance than the first conductive layer 10 and the second conductive layer 20, which can improve the signal transmission speed between different transistors TFT, reduce the voltage jump time of the internal node of the gate drive circuit, and is conducive to high-frequency driving.

[0109] Among them, each transistor TFT includes an active area located in the active layer 70, and the active area includes: a channel area, a source area and a drain area. Specifically, for any transistor TFT, the positive projection of the top gate of the transistor TFT on the substrate 100 overlaps with the positive projection of the active area of ​​the transistor TFT on the substrate 100 at least partially, and the overlap forms a channel area, and the active areas located at both ends of the channel area form a source area and a drain area; the positive projection of the bottom gate of the transistor TFT on the substrate 100 overlaps with the positive projection of the channel area of ​​the transistor TFT on the substrate 100 at least partially. The positive projections of the top gate and the bottom gate of any transistor TFT on the substrate 100 overlap with the positive projection of the channel area of ​​the transistor TFT on the substrate 100 at least partially. The first and second electrodes of the transistor TFT extend from the active layer 70 to the third conductive layer 30. For example, one of the first and second electrodes of the transistor TFT is connected to the source area of ​​the transistor TFT through a via hole, and the other of the first and second electrodes of the transistor TFT is connected to the drain area of ​​the transistor TFT through a via hole. Since the transistor TFT has a symmetrical structure, the source and drain of the transistor TFT are not distinguished here. According to actual needs, the first electrode of the transistor TFT can be the source (or drain), and the second electrode can be the drain (or source).

[0110] Figure 3 is a schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention, Figure 2 It can be considered as Figure 3 Schematic diagram of the cross-sectional structure along the line E-E'. Figure 2 and Figure 3On the basis of the above-mentioned embodiments, optionally, the orthographic projection of the first conductive layer 10 on the substrate 100 covers the orthographic projection of the channel region of all transistors TFT on the substrate 100. Such a setting is equivalent to using the first conductive layer 10 as a light shielding layer, and the bottom light shielding of the channel region of each transistor TFT can be performed by the first conductive layer 10, which is beneficial to improve the adverse effects of light on the transistor TFT, improve the light stability of the screen, and thus improve the display effect. Among them, the channel region of the transistor TFT is, for example, the area covered by the orthographic projection of the top gate of the transistor TFT on the active layer 70. Exemplarily, the material of the first conductive layer 10 includes an opaque conductive material, such as an opaque metal, and the material of the first conductive layer 10 can specifically be molybdenum.

[0111] For details, see Figure 2 and Figure 3 The orthographic projection of the bottom gate of any transistor TFT on the substrate 100 can be set to cover the orthographic projection of the top gate of the same transistor TFT on the substrate 100 to ensure that the bottom gate of the transistor TFT can shield the bottom of its channel region from light.

[0112] Furthermore, the orthographic projection area of ​​the bottom gate of any transistor TFT on the substrate 100 can be set larger than the orthographic projection area of ​​the top gate of the same transistor TFT on the substrate 100 to ensure good light shielding effect of the bottom gate on the bottom of the channel region.

[0113] Specifically, the orthographic projection of the bottom gate of any transistor TFT on the substrate 100 has a first contour edge, and the orthographic projection of the top gate of the same transistor TFT on the substrate 100 has a second contour edge, and the first contour edge is outside the second contour edge. Figure 2 and Figure 3 As shown in , it can be set in a direction parallel to the connection line between the first electrode and the second electrode of the transistor TFT, the width D1 of the top gate of the transistor TFT is smaller than the width D2 of the bottom gate of the transistor TFT, and the projection of the top gate of the transistor TFT on the bottom gate of the transistor TFT is located in the middle part of the bottom gate, that is, there is a certain distance between the contour edge of the top gate and the contour edge of the bottom gate to ensure the good shading effect of the bottom gate on the bottom of the channel region.

[0114] Furthermore, the orthographic projection of the first conductive layer 10 on the substrate 100 can be set to completely cover the orthographic projection of the second conductive layer 20 on the substrate 100; the area of ​​the first conductive layer 10 can be larger than the area of ​​the second conductive layer 20, so as to achieve complete wrapping of the second conductive layer 20 by the first conductive layer 10, thereby ensuring the bottom shading effect of each transistor TFT.

[0115] Figure 4 is a schematic diagram of the structure of an active layer provided by an embodiment of the present invention. Figure 4, the active layer 70 may include a switch tube active region 71 and an output tube active region 72. The switch tube active region 71 is used to set the active region of each switch transistor STFT, and the output tube active region 72 is used to set the active region of each output transistor OTFT. Exemplarily, the area of ​​the output tube active region 72 is at least three times that of the switch tube active region 71, so that each output transistor OTFT has sufficient load capacity.

[0116] Specifically, the switch tube active area 71 may include a plurality of switch tube active sub-areas 711 spaced apart from each other, and each switch tube active sub-area 711 serves as an active area of ​​each switch transistor STFT. The output tube active area 72 includes a first output tube active area 721 and a second output tube active area 722 connected to each other. At least one output transistor OTFT may include a first transistor and a second transistor, the first output tube active area 721 being, for example, an active area of ​​the first transistor, and the second output tube active area 722 being, for example, an active area of ​​the second transistor. In practical applications, the areas of the first output tube active area 721 and the second output tube active area 722 may be set according to the driving requirements of the output transistor OTFT. For example, the active area area of ​​the output transistor with higher functional requirements is set to be larger than the active area area of ​​another output transistor. Exemplarily. The orthographic projection area of ​​the first output tube active area 721 on the substrate 100 may be set to be smaller than the orthographic projection area of ​​the second output tube active area 722 on the substrate 100.

[0117] Exemplarily, the first output tube active area 721 includes a plurality of first active sections 7211 arranged at intervals, and the plurality of first active sections 7211 are arranged in sequence along the second direction X2. The second output tube active area 722 includes a plurality of second active sections 7221 arranged at intervals, and the plurality of second active sections 7221 are arranged in sequence along the second direction X2. The first active section 7211 and the second active section 7221 are arranged along the first direction X1. In the first direction X1, the second active section 7221 is connected to the first active section 7211; part of the second active section 7221 is connected to two adjacent first active sections 7211. The first direction X1 is perpendicular to the second direction X2. Exemplarily, in the first direction X1, the length of the second active section 7221 is greater than the length of the first active section 7211.

[0118] Based on the above embodiments, optionally, at least one output transistor includes a first transistor and a second transistor. Figure 5 , the first conductive layer 10 includes a first transistor bottom gate 101 and at least one second transistor bottom gate 102 extending along the second direction X2. The first transistor bottom gate 101 and the second transistor bottom gate 102 are arranged along the first direction X1; when there are multiple second transistor bottom gates 102, the multiple second transistor bottom gates 102 are arranged along the first direction X1; Figure 5exemplarily shows three second transistor bottom gates 102. Figure 6 , the second conductive layer 20 includes a first transistor top gate 201 and at least one second transistor top gate 202 extending along the second direction X2; wherein the first transistor top gate 201 and the second transistor top gate 202 are arranged along the first direction X1; when there are multiple second transistor top gates 202, the multiple second transistor top gates 202 are arranged along the first direction X1; Figure 6 exemplarily shows three second transistor top gates 202. Figure 7 In the stacked structure, the orthographic projections of the first transistor bottom gate 101 and the first transistor top gate 201 on the substrate overlap with the orthographic projections of all the first active segments 7211 on the substrate to form a first transistor; the orthographic projections of the second transistor bottom gate 102 and the second transistor top gate 202 on the substrate overlap with the orthographic projections of all the second active segments 7211 on the substrate to form a second transistor.

[0119] In the above embodiment, the bottom light shielding scheme of the transistor TFT is exemplified. On this basis, a light shielding portion may be provided to achieve the top light shielding of the transistor TFT, which is described in detail below.

[0120] In one embodiment, optionally, the display panel further includes a shading portion located on a side of the third conductive layer 30 away from the substrate 100, and the orthographic projection of the shading portion on the substrate 100 covers the switch tube active area 71 and the output tube active area 72, so as to achieve top shading of the active area of ​​each transistor TFT in the gate drive circuit.

[0121] Furthermore, the orthographic projection of the light shielding portion on the substrate 100 covers the orthographic projection of the gate driving circuit on the substrate 100, so as to ensure the light shielding effect on the top of each transistor TFT in the gate driving circuit.

[0122] Figure 8 FIG. 1 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present invention. Figure 8 On the basis of the above embodiments, optionally, the multiple conductive layers further include: a fourth conductive layer 40 and a fifth conductive layer 50 stacked in sequence on a side of the third conductive layer 30 away from the substrate 100, and the light shielding portion is located in the fourth conductive layer 40 and the fifth conductive layer 50. In other words, the portions of the fourth conductive layer 40 and the fifth conductive layer 50 located above the gate driving circuit together constitute the light shielding portion to achieve light shielding of the top of each transistor TFT.

[0123] Figure 9-11 The stacked structure of the active layer 70 and the fourth conductive layer 40, the stacked structure of the active layer 70 and the fifth conductive layer 50, and the stacked structure of the active layer 70 and the fourth conductive layer 40 and the fifth conductive layer 50 are shown in sequence. Figure 8-Figure 11The orthographic projection of the light-shielding portion located in the fourth conductive layer 40 (or the light-shielding portion is located in the light-shielding structure in the fourth conductive layer 40) on the substrate 100, and the orthographic projection of the light-shielding portion located in the fifth conductive layer 50 (or the light-shielding portion is located in the light-shielding structure in the fifth conductive layer 50) on the substrate 100, together cover the orthographic projections of the active areas of all transistors TFT on the substrate 100, that is, cover the active areas 71 of each switch tube and the active areas 72 of each output tube. In other words, the orthographic projection of the fourth conductive layer 40 on the substrate 100 overlaps at least partially with the orthographic projection of the active area of ​​all transistors TFT on the substrate 100, and the orthographic projection of the fifth conductive layer 50 on the substrate 100 overlaps at least partially with the orthographic projection of the active area of ​​all transistors TFT on the substrate 100; if there is a non-overlapping portion between the orthographic projection of one of the fourth conductive layer 40 and the fifth conductive layer 50 on the substrate 100 and the orthographic projection of the active area of ​​all transistors TFT on the substrate 100, the non-overlapping portion is covered by the orthographic projection of the other of the fourth conductive layer 40 and the fifth conductive layer 50 on the substrate 100. This embodiment is set up in this way, which is equivalent to using the fourth conductive layer 40 and the fifth conductive layer 50 to jointly form a shading portion, which is used to achieve shading of the top of the active area of ​​each transistor TFT, which is conducive to improving the adverse effects of light on the transistor TFT, improving the light stability of the screen, and improving the display effect. Exemplarily, the materials of the fourth conductive layer 40 and the fifth conductive layer 50 both include opaque conductive layer materials to ensure their shading effect.

[0124] Furthermore, an orthographic projection of a light-shielding portion located in the fourth conductive layer 40 on the substrate 100 and an orthographic projection of a light-shielding portion located in the fifth conductive layer 50 on the substrate 100 may be set to jointly cover the orthographic projections of all gate drive circuits on the substrate 100, that is, to cover the layout areas of all gate drive circuits, so as to ensure a top shading effect on each transistor TFT in the gate drive circuit.

[0125] On the basis of the above embodiments, optionally, the light shielding portion located in the fourth conductive layer 40 and the light shielding portion located in the fifth conductive layer 50 are both electrically connected to the DC signal to avoid the parasitic capacitance formed by the light shielding portion affecting the performance and working stability of the gate drive circuit. Exemplarily, the light shielding portion located in the fourth conductive layer 40 and the light shielding portion located in the fifth conductive layer 50 can be connected to the same DC signal, which can be a DC signal required for the gate drive circuit or the pixel circuit to work, or an additionally introduced DC signal, which is not specifically limited here.

[0126] Continue to see Figure 8On the basis of the above embodiments, optionally, the display panel further includes: a first interlayer insulating layer 91 and a planarizing layer 92. The first interlayer insulating layer 91 is located between the third conductive layer 30 and the fourth conductive layer 40; the planarizing layer 92 is located between the fourth conductive layer 40 and the fifth conductive layer 50; the materials of the first interlayer insulating layer 91 and the planarizing layer 92 both include organic materials. Accordingly, the fourth conductive layer 40 includes at least one first gas release hole K4, and the fifth conductive layer 50 includes at least one second gas release hole K5. Since the organic layer releases gas (out gas) during the preparation process, by providing gas release holes in both the fourth conductive layer 40 and the fifth conductive layer 50, gas release can be effectively performed, thereby avoiding bulging or even peeling of the conductive layer. Among them, the orthographic projection of the first gas release hole K4 on the substrate 100 can be set not to overlap with the orthographic projection of the second gas release hole K5 on the substrate 100, that is, the fourth conductive layer 40 and the fifth conductive layer 50 are staggered to ensure that the upper surfaces of the active areas of all transistors TFT are blocked by at least one conductive layer, thereby improving the lighting stability of the screen.

[0127] On the basis of the above embodiments, optionally, the display panel includes: a display area and a frame area, and the frame area is arranged around the display area. All gate drive circuits are arranged in the frame area, for example, on the left and / or right side of the display area; the display area is used to arrange pixel circuits and light-emitting devices, and at least part of the active layer 70 and the multi-layer conductive layer can also be used to form various pixel circuits and light-emitting devices, as well as various signal lines for driving the pixel circuits to work.

[0128] Exemplarily, the display area is provided with a light-emitting device, a data line and a DC signal line; the light-emitting device can emit light under the drive of the pixel circuit, the data line can be used to provide a data signal to the pixel circuit, and the DC signal line can be used to provide the pixel circuit with various DC signals required by it, such as a power signal and an initialization signal, etc. The power signal includes a first DC power signal and a second DC power signal with different voltages. Among them, the anode of the light-emitting device is located in the fifth conductive layer 50; the data line and / or the DC signal line is located in the fourth conductive layer 40. Exemplarily, the material of the fourth conductive layer 40 includes titanium aluminum titanium to reliably reduce the voltage drop (IR drop) on the signal line arranged thereon. The material of the fifth conductive layer 50 may include silver, such as a laminated structure of indium tin oxide (ITO) and silver. In this way, it is equivalent to using the conductive layer required for arranging the pixel circuit and the light-emitting device to realize the top shading of each transistor TFT in the gate drive circuit, without adding a separate shading layer in the display panel for top shading, which can simplify the panel structure. At the same time, the first gas release holes K4 (second gas release holes K5) can be prepared in the same process of preparing the graphic structure of the fourth conductive layer 40 (fifth conductive layer 50) in the display area, thereby simplifying the panel preparation process.

[0129] Fig.12 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention; Fig.13 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig.12 and Fig.13 On the basis of the above embodiments, optionally, the third conductive layer further includes: a clock signal line for providing a clock signal to the gate drive circuit. The clock signal line extends along the first direction X1; along the second direction X2, multiple gate drive circuits are located on the same side of the clock signal line; the first direction X1 is perpendicular to the second direction X2. Wherein, in the case of multiple clock signal lines, along the second direction X2, multiple clock signal lines can be arranged in sequence on the same side of the layout area A of the gate drive circuit. Fig.12 and Fig.13 , four clock signal lines are exemplarily shown, namely LCK1, LCK2, LCK3 and LCK4, which are sequentially arranged on the left side of the layout area A of the gate drive circuit.

[0130] On this basis, the layout area A of the gate drive circuit (such as Fig.12 The portion framed by the thick black solid line in the figure includes a first layout area A1 and a second layout area A2 arranged along the second direction X2. Along the second direction X2, the second layout area A2 is located on the side of the first layout area A1 away from the clock signal line. Among them, the first layout area A1 is used to layout each switching transistor STFT in the gate drive circuit, and the first layout area A1 includes a switch tube active area 71; the second layout area A2 is used to layout each output transistor OTFT in the gate drive circuit, and the second layout area A2 includes an output tube active area 72. This arrangement of the present embodiment is equivalent to arranging the clock signal line as far away from the output transistor OTFT as possible, which can effectively reduce the parasitic capacitance between the clock signal line and the output transistor OTFT, and avoid the clock signal provided by the clock signal line coupling to the node connected to the top gate of the output transistor OTFT, resulting in an unstable output signal, which in turn causes flickering problems or uneven display (such as mura in the first direction).

[0131] See also Fig.13On the basis of the above-mentioned embodiments, optionally, the display panel includes: a display area AA and a frame area NAA, and the frame area NAA is arranged around the display area AA. The layout area A of the clock signal line and the gate drive circuit are both located in the frame area NAA. Moreover, along the second direction X2, the clock signal line is arranged on the side of the layout area A of the gate drive circuit away from the display area AA. This embodiment is equivalent to setting the clock signal line away from the display area AA, and the second layout area A2 for arranging the output transistor OTFT is close to the display area AA; since the output transistor OTFT is used to output the output signal SOUT of the gate drive circuit, and the output signal SOUT needs to be provided to the pixel circuit in the display area AA through the gate drive signal line, such a setting is conducive to realizing the connection between the output transistor OTFT and the gate drive signal line.

[0132] Exemplarily, there are multiple gate drive circuits, and the layout areas A of the gate drive circuits are arranged in sequence along the first direction X1. Each gate drive circuit needs to be connected to two clock signal lines, which are respectively used to provide the first clock signal SCK1 and the second clock signal SCK2 to the gate drive circuit. Then, at least two clock signal lines can be arranged in the display panel to provide the clock signals required by each gate drive circuit.

[0133] In a specific embodiment, optionally, see Fig.13 , the number of clock signal lines is four, and each clock signal line is arranged along the second direction X2. Two of the clock signal lines are connected to each odd-numbered gate drive circuit, and the other two clock signal lines are connected to each even-numbered gate drive circuit. Each odd-numbered gate drive circuit is cascaded, each even-numbered gate drive circuit is cascaded, and there is no connection relationship between the odd-numbered gate drive circuit and the even-numbered gate drive circuit.

[0134] Specifically, the four clock signal lines include: a first clock signal line LCK1, a second clock signal line LCK2, a third clock signal line LCK3 and a fourth clock signal line LCK4. Fig.13For example, from top to bottom, they are the 1st to 5th gate drive circuits. Then, the first clock signal line LCK1 can be used to provide the first clock signal SCK1 to the 4n-3th gate drive circuit, and provide the second clock signal SCK2 to the 4n-1th gate drive circuit; the third clock signal line LCK3 can be used to provide the second clock signal SCK2 to the 4n-3th gate drive circuit, and provide the first clock signal SCK1 to the 4n-1th gate drive circuit; the second clock signal line LCK2 can be used to provide the first clock signal SCK1 to the 4n-2th gate drive circuit, and provide the second clock signal SCK2 to the 4nth gate drive circuit; the fourth clock signal line LCK4 can be used to provide the second clock signal SCK2 to the 4n-2th gate drive circuit, and provide the first clock signal SCK1 to the 4nth gate drive circuit; n is a positive integer.

[0135] Based on the above embodiments, optionally, the third conductive layer 30 further includes an input signal line LIN and an output signal line LOUT of each gate drive circuit. The input signal line LIN is used to provide an input signal SIN to the gate drive circuit; the output signal line LOUT is used to receive an output signal SOUT of the gate drive circuit and connect to the corresponding gate drive signal line. Fig.13 , exemplarily, the output signal line of the 4n-3th gate driving circuit is connected to the input signal line of the 4n-1th gate driving circuit, and the output signal line of the 4n-2th gate driving circuit is connected to the input signal line of the 4nth gate driving circuit.

[0136] Fig.14 is a timing diagram of multiple gate drive circuits provided by an embodiment of the present invention. Fig.14, exemplarily, the input signal of the first gate drive circuit is SIN1, the input signal of the second gate drive circuit is SIN2, and the clock signal lines LCK1, LCK2, LCK3 and LCK4 are used to provide clock signals CK1, CK2, CK3 and CK4 respectively. The output signal SOUT1 of the first gate drive circuit is used as the input signal SIN3 of the third gate drive circuit, the output signal SOUT3 of the third gate drive circuit is used as the input signal SIN5 of the fifth gate drive circuit, the output signal SOUT5 of the fifth gate drive circuit is used as the input signal SIN7 of the seventh gate drive circuit, and so on, to achieve signal level transmission between each odd-numbered gate drive circuit; the output signal SOUT2 of the second gate drive circuit is used as the input signal SIN4 of the fourth gate drive circuit, the output signal SOUT4 of the fourth gate drive circuit is used as the input signal SIN6 of the sixth gate drive circuit, and so on, to achieve signal level transmission between each even-numbered gate drive circuit. By staggering the timing of the odd and even gate drive circuits, a multi-level output signal is formed that is transmitted step by step as a whole.

[0137] On the basis of the above embodiments, optionally, the first power line LVGLL extends along the first direction X1; along the second direction X2, the first power line LVGLL is arranged on a side of the second layout area A2 away from the first layout area A1.

[0138] On the basis of the above embodiments, optionally, the third conductive layer 30 further includes a second power line LVGL and a third power line LVGH. The second power line LVGL and the third power line LVGH both extend along the first direction X1; along the second direction X2, the second power line LVGL and the third power line LVGH can be arranged on both sides of the layout area A of the gate drive circuit. Exemplarily, the first power line LVGLL, the second power line LVGL and the third power line LVGH are all used to transmit DC voltage, and the voltage values ​​transmitted by the three are different. Among the second power line LVGL and the third power line LVGH, the one whose voltage value is closer to the voltage of the first power line LVGLL can be arranged close to the first power line LVGLL to avoid coupling caused by too large a voltage difference between adjacent power lines. Exemplarily, the voltages transmitted on the first power line LVGLL, the second power line LVGL and the third power line LVGH increase in sequence, and the second power line LVGL can be arranged on the side of the layout area A of the gate drive circuit close to the first power line LVGLL, and the third power line LVGH can be arranged on the side of the layout area A of the gate drive circuit close to the clock signal line.

[0139] Continue to see Figure 8, based on the above embodiments, optionally, the multiple conductive layers also include: a sixth conductive layer 60, and the sixth conductive layer 60 is located between the substrate 100 and the first conductive layer 10. The gate drive circuit also includes at least one capacitor C. Among them, for any capacitor C, one plate of the capacitor C is located in the sixth conductive layer 60, and the other plate of the capacitor C is located in the first conductive layer 10, and the orthographic projections of the two plates of the capacitor C on the substrate 100 at least partially overlap. By setting the capacitor C, the coupling and / or storage of the potential of the key nodes inside the gate drive circuit can be achieved, thereby improving the output effect of the gate drive circuit. The material of the sixth conductive layer 60 includes, for example, molybdenum.

[0140] On the basis of the above embodiments, optionally, a capacitor insulating layer 96 may be provided between the sixth conductive layer 60 and the first conductive layer 10, a first gate insulating layer 93 may be provided between the first conductive layer 10 and the active layer 70, a second gate insulating layer 94 may be provided between the active layer 70 and the second conductive layer 20, and a second interlayer insulating layer 95 may be provided between the second conductive layer 20 and the third conductive layer 30. The materials of the capacitor insulating layer 96, the first gate insulating layer 93, the second gate insulating layer 94 and the second interlayer insulating layer 95 may all include inorganic materials, and any of the above insulating layers may be a single-layer structure or a stacked structure consisting of a plurality of sub-insulating layers.

[0141] Fig.15 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, Fig.15 The main figure shows the various types of vias required in the gate drive circuit. Fig.15 On the basis of the above embodiments, optionally, the second conductive layer 20 and the third conductive layer 30 are connected via a first type via K11; the third conductive layer 30 and the active layer 70 are connected via a second type via K22. The first type via K11 penetrates the second interlayer insulating layer 95, and the second type via K22 penetrates the second interlayer insulating layer 95 and the second gate insulating layer 94.

[0142] Exemplarily, the first type via K11 and the second type via K22 are prepared in the same mask process. Exemplarily, the second interlayer insulating layer 95 may include a first insulating sublayer; a mask process may be used to prepare the first insulating sublayer on the side of the second conductive layer 20 away from the substrate 100 to form each first type via K11 and each second type via K22. The formed structure can be seen in Fig.16 , Fig.16 The positions of the first type vias K11 and the second type vias K22 are given in FIG.

[0143] The third conductive layer 30 is connected to the first conductive layer 10 via the third type via K33, and the third conductive layer 30 is connected to the sixth conductive layer 60 via the fourth type via K44. The third type via K33 penetrates the second interlayer insulating layer 95, the second gate insulating layer 94 and the first gate insulating layer 93, and the fourth type via K44 penetrates the second interlayer insulating layer 95, the second gate insulating layer 94, the first gate insulating layer 93 and the capacitor insulating layer 96.

[0144] Exemplarily, the third type via K33 and the fourth type via K44 are prepared in the same mask process. Exemplarily, the second interlayer insulating layer 95 further includes a second insulating sublayer; a mask process can be used to prepare the second insulating sublayer on the side of the first insulating sublayer away from the substrate 100 to form each third type via K33 and each fourth type via K44. The formed structure can be seen in Fig.17 , Fig.17 The positions of the third type vias K33 and the fourth type vias K44 are given in FIG. It can be understood that the second insulating sublayer also exposes the first type vias K11 and the second type vias K22, so that when the third conductive layer 30 is subsequently prepared, the material of the third conductive layer 30 is connected to the corresponding film layer through the first type vias K11, the second type vias K22, the third type vias K33 and the fourth type vias K44.

[0145] The layout structure of the gate driving circuit is exemplarily described below in combination with the specific circuit structure of the gate driving circuit.

[0146] Fig.18 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present invention. Fig.18, the gate drive circuit is, for example, a 1OT3C structure, at least one output transistor includes a first transistor M1 and a second transistor M2; at least one switch transistor includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10, and at least one capacitor includes a first capacitor C1, a second capacitor C2 and a third capacitor C3. The signals required for the gate drive circuit to work include an input signal SIN, a first power signal VGLL, a second power signal VGL, a third power signal VGH, a first clock signal SCK1 and a second clock signal SCK2. The key nodes inside the gate drive circuit include a first node N1, a second node N2, a third node N3 and a fifth node N5, wherein the first node N1 is connected to the top gate of the second transistor M2, the tenth transistor M10 is connected between the second node N2 and the first node N1, the third node N3 is connected to the top gate of the first transistor M1, and the fifth node N5 is connected to the bottom gate of the second transistor M2. Each transistor is, for example, an N-type IGZO transistor with a dual-gate structure.

[0147] Based on the above embodiments, optionally, see Fig.12 In the layout area of ​​the gate driving circuit, the first layout area A1 can be divided into a first sub-layout area A11 and a second sub-layout area A12 sequentially arranged along the second direction X2. That is, the layout area A of the gate driving circuit includes the first sub-layout area A11, the second sub-layout area A12 and the second layout area A2 sequentially away from the third power line LVGH (or sequentially away from the clock signal line) along the second direction X2. Figure 3 For example, it is an enlarged view of the upper half of the first sub-layout area A11. Fig.19 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention, Fig.19 and Fig.12 The layout structure is consistent with that in the figure. For the convenience of display, Fig.12 The main markings are the division of the layout area. Fig.19 The transistors, capacitors and key nodes are mainly marked; and, Fig.19 In order to facilitate the labeling of transistors and capacitors, the via structures are not shown. Fig.12 and Fig.19, the first sub-layout area A11 is used to lay out the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10; the second sub-layout area A12 is used to lay out the first capacitor C1, the second capacitor C2, the third capacitor C3, the third transistor M3 and the fourth transistor M4; the second layout area A2 is used to lay out the first transistor M1 and the second transistor M2. Among them, the nodes connected to the top gate and the bottom gate of the two output transistors include the first node N1, the third node N3 and the fifth node N5. The layout of the gate drive circuit in this embodiment according to the above-mentioned area distribution is equivalent to setting the clock signal lines used to provide the first clock signal SCK1 and the second clock signal SCK2 required by the gate drive circuit away from the first node N1, the third node N3 and the fifth node N5, which can reduce the parasitic capacitance between the clock signal line and the above-mentioned key nodes, avoid the clock signal coupling to the above-mentioned nodes to cause the output signal to be unstable, and thus improve the flicker problem or the first direction mura.

[0148] The following Fig.18 The layout structure of the gate driving circuit shown is provided for illustrative purposes only and is not intended to be a limitation of the present invention.

[0149] Fig. 20 yes Fig.19 Schematic diagram of the enlarged structure of the middle area F. Fig.19 and Fig. 20 Based on the above embodiments, optionally, at least one output transistor includes a first transistor M1 and a second transistor M2, at least one switch transistor includes a third transistor M3 and a fourth transistor M4, and at least one capacitor includes a first capacitor C1.

[0150] The bottom gate of the first transistor M1 (including Figure 5 The bottom gate 101 of the first transistor shown in FIG. 101 is connected to the first power line LVGLL through the first connection line L1, the first electrode 311 of the first transistor M1 is connected to the second power line LVGL through the second connection line L2, and the second electrode 312 of the first transistor M1 is connected to the output signal line LOUT. The first electrode 321 of the second transistor M2 is connected to the clock signal line (here, the third clock signal line LCK3) for providing the second clock signal to the gate drive circuit through the third connection line; the second electrode 322 of the second transistor M2 is connected to the output signal line LOUT; the bottom gate of the second transistor M2 (including Figure 5The plurality of second transistor bottom gates 102 shown in FIG. 1 are connected to the first plate of the first capacitor C1 through the fourth connection line L4. The first electrode of the third transistor M3 is connected to the fourth connection line L4 through the fifth connection line L5, the second electrode of the third transistor M3 is connected to the bottom gate of the first transistor M1 through the sixth connection line L6, and the top gate of the third transistor M3 is connected to the top gate of the first transistor M1 through the seventh connection line L7. The second plate of the first capacitor C1 is connected to the first electrode of the fourth transistor M4 through the eighth connection line L8, the second electrode of the fourth transistor M4 is connected to the third connection line through the ninth connection line L9, and the top gate of the fourth transistor M4 is connected to the second node N2, and then connected to the top gate of the second transistor M2 through the tenth transistor M10.

[0151] The bottom gate of the first transistor M1 is directly connected to the first power line LVGLL, and the bottom gate of the second transistor M2 is indirectly connected to the first power line LVGLL. Specifically, the first power signal VGLL is directly transmitted to the bottom gate of the first transistor M1, and the voltage of the first power signal VGLL is less than the voltage of the second power signal VGL, which can ensure that the first transistor M1 is effectively turned off, reduce the cut-off current of the first transistor M1, and ensure the normal output of the gate drive circuit. The bottom gate of the second transistor M2 can be connected to the first power signal VGLL or the second clock signal SCK2 through the control of the third transistor M3 and the fourth transistor M4; when the second transistor M2 needs to output the second clock signal SCK2, the fourth transistor M4 is turned on, and at the same time, through the coupling of the first capacitor C1, the relevant voltage of the second clock signal SCK2 is transmitted to the bottom gate of the second transistor M2, so that the threshold voltage of the second transistor M2 can be adjusted to make the threshold voltage negative, which is beneficial to increase the output current of the second transistor M2, reduce the output signal delay, and improve the screen refresh rate, and can reduce the size of the second transistor M2, which is beneficial to a narrow frame; when the second transistor M2 does not need to output the second clock signal SCK2 (that is, when the second transistor M2 is turned off), the third transistor M3 is turned on, and the first power signal VGLL is transmitted to the bottom gate of the second transistor M2, wherein the voltage of the first power signal VGLL is less than the voltage of the second power signal VGL, which can make the threshold voltage of the second transistor M2 positive, ensure that the second transistor M2 is effectively turned off, reduce the off current of the second transistor M2, and ensure the normal output of the gate drive circuit.

[0152] Exemplarily, the first electrode 311 of the first transistor M1, the second electrode 312 of the first transistor M1, the first electrode 321 of the second transistor M2, and the second electrode 322 of the second transistor M2 all extend along the second direction X2; the orthographic projections of the first electrode 311 of the first transistor M1, the second electrode 312 of the first transistor M1, the first electrode 321 of the second transistor M2, and the second electrode 322 of the second transistor M2 on the substrate cover the active area of ​​the first transistor M1 (see Figure 4The first output tube active area 721) and the active area of ​​the second transistor M2 (see Figure 4 The orthographic projection of the second output tube active area 722 in the substrate. Exemplarily, the first electrode 321 of the second transistor M2 includes at least two first electrode plates 3211 extending along the second direction X2 and arranged along the first direction X1, and the second conductive layer 20 includes at least two second transistor top gates 202 extending along the second direction X2 and arranged along the first direction X1; the orthographic projection of each first electrode plate 3211 on the substrate and the orthographic projection of each second transistor top gate 202 on the substrate are alternately arranged; for example, each first electrode plate 3211, each second transistor top gate 202 and the second electrode 322 of the second transistor M2 are alternately arranged in the first direction X1.

[0153] Among them, the first connection line L1, the second connection line L2, the fourth connection line L4 and the first electrode plate of the first capacitor C1 are located in the first conductive layer 10; the seventh connection line L7 is located in the second conductive layer 20; at least part of the third connection line, the fifth connection line L5, the sixth connection line L6, the eighth connection line L8 and the ninth connection line L9 are located in the third conductive layer 30; the second electrode plate of the first capacitor C1 is located in the sixth conductive layer 60. Specifically, the third connection line includes a first sub-connection line L31, a second sub-connection line L32, a third sub-connection line L33 and a fourth sub-connection line L34 connected in sequence between the first electrode of the second transistor M2 and the clock connection line for providing the second clock signal to the gate drive circuit; the ninth connection line L9 is connected to the connection portion between the first sub-connection line L31 and the second sub-connection line L32, for example; the first sub-connection line L31 and the third sub-connection line L33 are located in the third conductive layer 30, the second sub-connection line L32 is located in the sixth conductive layer 60, and the fourth sub-connection line L34 is located in the first conductive layer 10.

[0154] The at least one capacitor further includes: a second capacitor C2 and a third capacitor C3. The bottom gate of the third transistor M3 is connected to the first plate of the second capacitor C2 through the tenth connection line L10, and the first electrode of the first transistor M1 is connected to the second plate of the second capacitor C2 through the eleventh connection line L11. The top gate of the second transistor M2 is connected to the first plate of the third capacitor C3 through the twelfth connection line L12, and the second electrode of the first transistor M1 is connected to the second plate of the third capacitor C3 through the thirteenth connection line L13.

[0155] Among them, the tenth connecting line L10, the first plate of the second capacitor C2 and the first plate of the third capacitor C3 are all located in the first conductive layer 10; the twelfth connecting line L12 is located in the second conductive layer 20; the eleventh connecting line L11 and the thirteenth connecting line L13 are both located in the third conductive layer 30; the second plate of the second capacitor C2 and the second plate of the third capacitor C3 are both located in the sixth conductive layer 60.

[0156] The at least one switch transistor further includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10. A first electrode of the fifth transistor M5 is connected to the input signal line LIN, a bottom gate of the fifth transistor M5 is connected to a clock signal line (here, the first clock signal line LCK1) for providing a first clock signal to the gate drive circuit through a fourteenth connection line L14, a second electrode of the fifth transistor M5 is connected to a top gate of the sixth transistor M6 through a fifteenth connection line L15; a first electrode of the sixth transistor M6 is connected to a top gate of the fifth transistor M5 through a sixteenth connection line L16, a second electrode of the sixth transistor M6 is connected to a second electrode of the seventh transistor M7 through a seventeenth connection line L17, and is also connected to a first electrode plate of the second capacitor C2 through a twenty-fourth connection line L24; a first electrode of the seventh transistor M7 is connected to a third power line LVGH, for example, connected to the third power line LVGH through a twenty-third connection line L23; a top gate of the seventh transistor M7 is connected to a top gate of the fifth transistor M5, and a bottom gate of the seventh transistor M7 is connected to a bottom gate of the fifth transistor M5. The first electrode of the eighth transistor M8 is connected to the second electrode plate of the second capacitor C2 through the eighteenth connection line L18, the top gate of the eighth transistor M8 is connected to the seventeenth connection line L17, and the second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9 through the nineteenth connection line L19; the top gate of the ninth transistor M9 is connected to the third connection line L3, specifically, the bottom gate of the ninth transistor M9 is connected to the fourth sub-connection line L34, and the top gate of the ninth transistor M9 is connected to the bottom gate of the ninth transistor M9 and the third sub-connection line L33; the second electrode of the ninth transistor M9 is connected to the top gate of the sixth transistor M6 through the twentieth connection line; the first electrode of the tenth transistor M10 and the top gate of the fourth transistor M4 are both connected to the twentieth connection line, the top gate of the tenth transistor M10 is connected to the third power supply line LVGH through the twenty-first connection line L21, and the second electrode of the tenth transistor M10 is connected to the first electrode plate of the third capacitor C3 through the twenty-second connection line L22.

[0157] Among them, the fourteenth connecting line L14 is located in the first conductive layer 10; the fifteenth connecting line L15, the sixteenth connecting line L16, the seventeenth connecting line, the eighteenth connecting line L18, the nineteenth connecting line L19, at least part of the twentieth connecting line, the twenty-first connecting line L21, and at least part of the twenty-second connecting line L22 are located in the third conductive layer 30.

[0158] Specifically, the seventeenth connection line L17 includes a tenth sub-connection line L171 and an eleventh sub-connection line L172 connected in sequence between the second electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7, and the top gate of the eighth transistor M8 is connected to the connection portion between the tenth sub-connection line L171 and the eleventh sub-connection line L172.

[0159] The twentieth connection line includes a fifth sub-connection line L201, a sixth sub-connection line L202, and a seventh sub-connection line L203 which are sequentially connected between the second electrode of the ninth transistor M9 and the top gate of the sixth transistor M6. Among them, the fifth sub-connection line L201 is connected between the second electrode of the ninth transistor M9 and the first electrode of the tenth transistor M10, the sixth sub-connection line L201 is connected between the first electrode of the tenth transistor M10 and the top gate of the fourth transistor M4, the top gate of the fourth transistor M4 is connected to its bottom gate, the seventh sub-connection line L203 is connected between the bottom gate of the fourth transistor M4 and the bottom gate of the sixth transistor M6, the top gate of the sixth transistor M6 is connected to its bottom gate. The fifth sub-connection line L201 and the sixth sub-connection line L202 are located in the third conductive layer 30, and the seventh sub-connection line L203 is located in the first conductive layer 10.

[0160] The twenty-second connection line includes an eighth sub-connection line L221 and a ninth sub-connection line L222 connected in sequence between the second electrode of the tenth transistor M10 and the first electrode plate of the third capacitor C3; the eighth sub-connection line L221 is located in the third conductive layer 30, and the ninth sub-connection line L222 is located in the first conductive layer 10.

[0161] In summary, the embodiment of the present invention provides a specific layout scheme of the gate drive circuit. Among them, the first power line LVGLL, the second power line LVGL, the third power line LVGH and each clock signal line extend along the first direction X1; along the second direction X2, each clock signal line, the third power line LVGH, the layout area A of the gate drive circuit, the second power line LVGL and the first power line LVGLL are arranged in sequence; the first direction X1 is perpendicular to the second direction X2.

[0162] On the basis of the above embodiments, the layout area of ​​the first transistor M1 can be set to be smaller than the layout area of ​​the second transistor M2. Since the main function of the gate drive circuit is to control the output period of the second clock signal SCK2, in order to reduce the delay of the output signal SOUT, the second transistor M2 for outputting the second clock signal SCK2 can be made larger, and the size of the first transistor M1 can be reduced accordingly, so as to optimize the output effect without increasing the circuit wiring area.

[0163] Specifically, in the same gate drive circuit, the layout area of ​​the first transistor M1 is adjacent to the layout area of ​​the second transistor M2 and is arranged along the first direction X1; the layout area of ​​the first transistor M1 and the layout area of ​​the second transistor M2 can be set to be equal in length in the second direction X2, and the length of the layout area of ​​the first transistor M1 in the first direction X1 is set to be smaller than the length of the layout area of ​​the second transistor M2 in the first direction X1, so that the layout area of ​​the first transistor M1 is smaller than the layout area of ​​the second transistor M2.

[0164] On the basis of the above embodiments, optionally, the capacitance of the first capacitor C1 can be set to be greater than the parasitic capacitance at the bottom gate of the second transistor M2. Since the function of the first capacitor C1 is to adjust the bottom gate voltage of the second transistor M2 through coupling, the capacitance of the first capacitor C1 needs to be greater than the sum of the parasitic capacitances between the bottom gate of the second transistor M2 and all other signals (or wiring). If the layout space allows, the capacitance of the first capacitor C1 can be increased as much as possible.

[0165] On the basis of the above embodiments, optionally, the capacitance of the third capacitor C3 can be set to be greater than the parasitic capacitance at the top gate of the second transistor M2. Since the function of the third capacitor C3 is to adjust the top gate voltage of the second transistor M2 through coupling, the capacitance of the third capacitor C3 needs to be greater than the sum of the parasitic capacitances between the top gate of the second transistor M2 and all other signals (or wiring). If the layout space allows, the capacitance of the third capacitor C3 can be increased as much as possible.

[0166] On the basis of the above embodiments, optionally, since the second capacitor C2 is used to maintain the top gate voltage of the first transistor M1, there is no need to perform coupling control on the top gate voltage of the first transistor M1, and the capacitance of the second capacitor C2 can be appropriately reduced. Exemplarily, on the basis of ensuring that the capacitance of the second capacitor C2 is greater than the parasitic capacitance at the top gate of the first transistor M1, the area of ​​the second capacitor C2 can be appropriately reduced.

[0167] On the basis of the above-mentioned embodiments, optionally, the width-to-length ratio of the fifth transistor M5 and the tenth transistor M10 can be set to be greater than the width-to-length ratio of other switch transistors. In this way, the delay of the voltage jump of the first node N1 can be effectively reduced, which is conducive to achieving high-frequency output. Specifically, the frequency of the output signal SOUT is the frequency of the second clock signal SCK2 output by the gate drive circuit, and the second clock signal SCK2 is output by the second transistor M2. The higher the top gate voltage of the second transistor M2, the faster the voltage jump, the smaller the output delay of the second transistor M2, and the more conducive to achieving high-frequency output, the width-to-length ratio of the fifth transistor M5 and the tenth transistor M10 is set larger, so that the voltage of the first node N1 can rise faster when it needs to jump to high.

[0168] In summary, the embodiment of the present invention provides a layout design of a 10T3C structure gate drive circuit based on a full oxide TFT process, all transistors are four-terminal devices with top gates and bottom gates, and most of the connecting lines between the first and second poles of each transistor are connected by jumper punching located in the third conductive layer, which is conducive to reducing the voltage jump time of the internal node of the gate drive circuit and is conducive to high-frequency drive. The switching transistor adopts a device structure in which the top and bottom gates are connected, and the output transistor adopts a device structure in which the top and bottom gates are separately controlled. With the optimization design of the relevant device size and capacitor size, the gate drive circuit can be guaranteed to work normally and is conducive to achieving a narrow frame. By setting the clock signal line away from the gate node of the output transistor, the flicker problem or the first direction mura can be eliminated. In addition, all transistors are designed to be shaded at the top and bottom, which is conducive to improving the light stability. Therefore, based on the device structure design, size design, wiring design and shading design of the embodiment of the present invention, the screen refresh rate can be improved, which is conducive to achieving a narrow frame, eliminating flicker problems or G-direction mura, and improving the light stability of the screen.

[0169] The embodiment of the present invention further provides a display device, including the display panel provided by any embodiment of the present invention, having corresponding beneficial effects. Exemplarily, the display device can be a mobile phone, a television, a laptop computer, a desktop computer, etc.

[0170] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0171] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; An active layer and a plurality of conductive layers are stacked on one side of the substrate; The active layer and the plurality of conductive layers are used to form a gate drive circuit, the gate drive circuit includes a plurality of transistors, the plurality of transistors include at least one switch transistor and at least one output transistor, each of the switch transistors and each of the output transistors is a double-gate transistor having a top gate and a bottom gate; The multiple conductive layers include: a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence in a direction away from the substrate; the active layer is arranged between the first conductive layer and the second conductive layer; the third conductive layer includes a first power line; the bottom gate of each of the transistors is located in the first conductive layer, the top gate of each of the transistors is located in the second conductive layer, the top gate of any of the switching transistors is connected to the bottom gate of the same switching transistor, and the bottom gate of the output transistor is electrically connected to the first power line.

2. The display panel according to claim 1, characterized in that: The top gate and the bottom gate of the same switching transistor are connected via a gate connection line located in the third conductive layer; Preferably, the third conductive layer further comprises a plurality of transmission lines, at least some of which connect different transistors; the first electrode and the second electrode of each transistor are both located in the third conductive layer; wherein each transistor comprises an active region located in the active layer, and the active region comprises: a channel region, a source region and a drain region; the orthographic projection of the top gate and the bottom gate of any transistor on the substrate at least partially overlaps with the orthographic projection of the channel region of the transistor on the substrate, and the first electrode and the second electrode of the transistor extend from the active layer to the third conductive layer; Preferably, the material of the third conductive layer includes titanium aluminum titanium; The materials of the first conductive layer and the second conductive layer both include molybdenum; Preferably, each of the transistors is an N-type transistor; Preferably, the material of the active layer includes indium gallium zinc oxide.

3. The display panel according to claim 1, characterized in that: The channel region of each transistor is located in the active layer; the orthographic projection of the first conductive layer on the substrate covers the orthographic projections of the channel regions of all transistors on the substrate; Preferably, the orthographic projection of the bottom gate of any of the transistors on the substrate covers the orthographic projection of the top gate of the same transistor on the substrate; Preferably, the orthographic projection area of ​​the bottom gate of any of the transistors on the substrate is larger than the orthographic projection area of ​​the top gate of the same transistor on the substrate; Preferably, the orthographic projection of the bottom gate of any of the transistors on the substrate has a first contour edge, and the orthographic projection of the top gate of the same transistor on the substrate has a second contour edge, and the first contour edge is outside the second contour edge; Preferably, the material of the first conductive layer includes a light-proof conductive material; Preferably, the material of the first conductive layer includes molybdenum.

4. The display panel according to claim 1, characterized in that: The active layer includes a switch tube active region and an output tube active region, and the area of ​​the output tube active region is at least three times that of the switch tube active region; The output tube active region comprises a first output tube active region and a second output tube active region connected to each other, and an orthographic projection area of ​​the first output tube active region on the substrate is smaller than an orthographic projection area of ​​the second output tube active region on the substrate; The switch tube active area includes a plurality of switch tube active sub-areas spaced apart from each other; Preferably, the first output tube active area includes a plurality of first active segments arranged at intervals, the plurality of first active segments are sequentially arranged along the second direction, the second output tube active area includes a plurality of second active segments arranged at intervals, the plurality of second active segments are sequentially arranged along the second direction, the first active segments and the second active segments are arranged along the first direction, and in the first direction, the second active segments are connected to the first active segments; Some of the second active segments are connected to two adjacent first active segments; Preferably, the display panel further comprises a light shielding portion located on a side of the third conductive layer away from the substrate, and an orthographic projection of the light shielding portion on the substrate covers the active area of ​​the switch tube and the active area of ​​the output tube; Preferably, the at least one output transistor comprises a first transistor and a second transistor, the first conductive layer comprises a first transistor bottom gate and at least one second transistor bottom gate extending along the second direction, the second conductive layer comprises a first transistor top gate and at least one second transistor top gate extending along the second direction, the orthographic projections of the first transistor bottom gate and the first transistor top gate on the substrate overlap with the orthographic projections of all the first active segments on the substrate, and the orthographic projections of the second transistor bottom gate and the second transistor top gate on the substrate overlap with the orthographic projections of all the second active segments on the substrate; Preferably, the display panel further comprises a light shielding portion located on a side of the third conductive layer away from the substrate, and an orthographic projection of the light shielding portion on the substrate covers an orthographic projection of the gate driving circuit on the substrate; Preferably, the plurality of conductive layers further include: a fourth conductive layer and a fifth conductive layer sequentially stacked on a side of the third conductive layer away from the substrate; The light shielding portion is located on the fourth conductive layer and the fifth conductive layer; The orthographic projection of the light shielding portion located in the fourth conductive layer on the substrate and the orthographic projection of the light shielding portion located in the fifth conductive layer on the substrate jointly cover the orthographic projections of the active regions of all the transistors on the substrate; Preferably, the orthographic projection of the light shielding portion located on the fourth conductive layer on the substrate and the orthographic projection of the light shielding portion located on the fifth conductive layer on the substrate jointly cover the orthographic projection of all the gate driving circuits on the substrate; Preferably, the light shielding portion located on the fourth conductive layer and the light shielding portion located on the fifth conductive layer are both electrically connected to the DC signal; Preferably, the display panel further includes: A first interlayer insulating layer, located between the third conductive layer and the fourth conductive layer; a planarization layer, located between the fourth conductive layer and the fifth conductive layer; The materials of the first interlayer insulating layer and the planarization layer both include organic materials; The fourth conductive layer includes at least one first gas release hole, the fifth conductive layer includes at least one second gas release hole, and the orthographic projection of the first gas release hole on the substrate does not overlap with the orthographic projection of the second gas release hole on the substrate; Preferably, the materials of the fourth conductive layer and the fifth conductive layer both include opaque conductive layer materials; Preferably, the material of the fourth conductive layer includes titanium aluminum titanium; the material of the fifth conductive layer includes silver; Preferably, the display panel includes: a display area and a frame area, the frame area is arranged around the display area; all the gate driving circuits are located in the frame area; the display area is provided with a light-emitting device, a data line and a DC signal line; the anode of the light-emitting device is located in the fifth conductive layer, and the data line and / or the DC signal line are located in the fourth conductive layer.

5. The display panel according to claim 1, characterized in that: The third conductive layer further includes: a clock signal line for providing a clock signal to the gate drive circuit; the clock signal line extends along a first direction; along a second direction, a plurality of the gate drive circuits are located on the same side of the clock signal line; the first direction is perpendicular to the second direction; Preferably, the number of the clock signal lines is four, and each of the clock signal lines is arranged along the second direction; the number of the gate drive circuits is multiple, and the layout areas of each of the gate drive circuits are arranged in sequence along the first direction; Two of the clock signal lines are connected to each odd-numbered gate drive circuit, and the other two of the clock signal lines are connected to each even-numbered gate drive circuit; Preferably, the first power line extends along the first direction; along the second direction, the first power line is arranged on a side of the second layout area away from the first layout area; Preferably, the display panel includes: a display area and a border area, the border area is arranged around the display area; the layout area of ​​the clock signal line and the gate drive circuit are both located in the border area, and along the second direction, the clock signal line is arranged on the side of the layout area of ​​the gate drive circuit away from the display area.

6. The display panel according to any one of claims 1 to 5, characterized in that: The plurality of conductive layers further include: a sixth conductive layer located between the substrate and the first conductive layer; the gate drive circuit further includes at least one capacitor; For any of the capacitors, one electrode plate of the capacitor is located on the sixth conductive layer, the other electrode plate of the capacitor is located on the first conductive layer, and the orthographic projections of the two electrodes of the capacitor on the substrate at least partially overlap.

7. The display panel according to claim 6, characterized in that: The third conductive layer includes a second power supply line extending along the first direction, at least two clock signal lines extending along the first direction, and output signal lines of each of the gate drive circuits; the at least one output transistor includes a first transistor and a second transistor, the at least one switch transistor includes a third transistor and a fourth transistor, and the at least one capacitor includes a first capacitor; The bottom gate of the first transistor is connected to the first power line through a first connection line, the first electrode of the first transistor is connected to the second power line through a second connection line, and the second electrode of the first transistor is connected to the output signal line; the first electrode of the second transistor is connected to a clock signal line for providing a second clock signal to the gate driving circuit through a third connection line, and the second electrode of the second transistor is connected to the output signal line; the bottom gate of the second transistor is connected to the first plate of the first capacitor through a fourth connection line, the first electrode of the third transistor is connected to the fourth connection line through a fifth connection line, the second electrode of the third transistor is connected to the bottom gate of the first transistor through a sixth connection line, and the top gate of the third transistor is connected to the top gate of the first transistor through a seventh connection line; the second plate of the first capacitor is connected to the first electrode of the fourth transistor through an eighth connection line, the second electrode of the fourth transistor is connected to the third connection line through a ninth connection line, and the top gate of the fourth transistor is connected to the top gate of the second transistor; Preferably, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor all extend along the second direction, and the orthographic projections of the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor on the substrate cover the orthographic projections of the active areas of the first transistor and the second transistor on the substrate; The first electrode of the second transistor includes at least two first electrode plates extending along the second direction and arranged along the first direction, and the second conductive layer includes at least two second transistor top gates extending along the second direction and arranged along the first direction; The orthographic projections of the first electrode plates on the substrate and the orthographic projections of the second transistor top gates on the substrate are arranged alternately; Preferably, the first connecting line, the second connecting line, the fourth connecting line and the first electrode plate of the first capacitor are located in the first conductive layer; the seventh connecting line is located in the second conductive layer; at least part of the third connecting line, the fifth connecting line, the sixth connecting line, the eighth connecting line and the ninth connecting line are located in the third conductive layer; the second electrode plate of the first capacitor is located in the sixth conductive layer; Preferably, the third connection line includes a first sub-connection line, a second sub-connection line, a third sub-connection line and a fourth sub-connection line sequentially connected between the first electrode of the second transistor and a clock connection line for providing a second clock signal to the gate drive circuit; the first sub-connection line and the third sub-connection line are located in the third conductive layer, the second sub-connection line is located in the sixth conductive layer, and the fourth sub-connection line is located in the first conductive layer; Preferably, the capacitance of the first capacitor is greater than the parasitic capacitance at the bottom gate of the second transistor.

8. The display panel according to claim 7, characterized in that: The at least one capacitor further comprises: a second capacitor and a third capacitor; The bottom gate of the third transistor is connected to the first plate of the second capacitor through a tenth connecting line, and the first electrode of the first transistor is connected to the second plate of the second capacitor through an eleventh connecting line; The top gate of the second transistor is connected to the first plate of the third capacitor through a twelfth connecting line, and the second gate of the first transistor is connected to the second plate of the third capacitor through a thirteenth connecting line; Preferably, the tenth connecting line, the first electrode plate of the second capacitor and the first electrode plate of the third capacitor are all located in the first conductive layer; the twelfth connecting line is located in the second conductive layer; the eleventh connecting line and the thirteenth connecting line are both located in the third conductive layer; the second electrode plate of the second capacitor and the second electrode plate of the third capacitor are both located in the sixth conductive layer; Preferably, the capacitance of the second capacitor is greater than the parasitic capacitance at the top gate of the first transistor; Preferably, the capacitance of the third capacitor is greater than the parasitic capacitance at the top gate of the second transistor.

9. The display panel according to claim 8, characterized in that: The third conductive layer further includes a third power supply line and an input signal line of each gate drive circuit; the at least one switch transistor further includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The first electrode of the fifth transistor is connected to the input signal line, the bottom gate of the fifth transistor is connected to the clock signal line for providing the first clock signal to the gate driving circuit through a fourteenth connecting line, and the second electrode of the fifth transistor is connected to the top gate of the sixth transistor through a fifteenth connecting line; the first electrode of the sixth transistor is connected to the top gate of the fifth transistor through a sixteenth connecting line, and the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor through a seventeenth connecting line; the first electrode of the seventh transistor is connected to the third power line, the top gate of the seventh transistor is connected to the top gate of the fifth transistor, and the bottom gate of the seventh transistor is connected to the bottom gate of the fifth transistor; The first electrode of the eighth transistor is connected to the second electrode plate of the second capacitor through an eighteenth connecting line, the top gate of the eighth transistor is connected to the seventeenth connecting line, and the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor through a nineteenth connecting line; the top gate of the ninth transistor is connected to the third connecting line, and the second electrode of the ninth transistor is connected to the top gate of the sixth transistor through a twentieth connecting line; the first electrode of the tenth transistor and the top gate of the fourth transistor are both connected to the twentieth connecting line, the top gate of the tenth transistor is connected to the third power supply line through a twenty-first connecting line, and the second electrode of the tenth transistor is connected to the first electrode plate of the third capacitor through a twenty-second connecting line; Preferably, the fourteenth connecting line is located in the first conductive layer; the fifteenth connecting line, the sixteenth connecting line, the seventeenth connecting line, the eighteenth connecting line, the nineteenth connecting line, at least a portion of the twentieth connecting line, the twenty-first connecting line, and at least a portion of the twenty-second connecting line are located in the third conductive layer; Preferably, the 20th connection line includes: a fifth sub-connection line, a sixth sub-connection line and a seventh sub-connection line sequentially connected between the second electrode of the ninth transistor and the top gate of the sixth transistor, wherein the sixth sub-connection line is connected between the first electrode of the tenth transistor and the top gate of the fourth transistor; the fifth sub-connection line and the sixth sub-connection line are located in the third conductive layer, and the seventh sub-connection line is located in the first conductive layer; Preferably, the 22nd connecting line includes an eighth sub-connecting line and a ninth sub-connecting line sequentially connected between the second electrode of the tenth transistor and the first electrode plate of the third capacitor; the eighth sub-connecting line is located in the third conductive layer, and the ninth sub-connecting line is located in the first conductive layer; Preferably, each of the clock signal lines extends along the first direction; along the second direction, each of the clock signal lines is arranged on one side of the layout area of ​​the gate drive circuit; the layout area of ​​the gate drive circuit includes a first sub-layout area, a second sub-layout area and a second layout area which are sequentially away from any of the clock signal lines along the second direction; the first sub-layout area is provided with the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor, the second sub-layout area is provided with the first capacitor, the second capacitor, the third capacitor, the third transistor and the fourth transistor, and the second layout area is provided with the first transistor and the second transistor; the first direction is perpendicular to the second direction; Preferably, the width-to-length ratios of the fifth transistor and the tenth transistor are both greater than the width-to-length ratios of the other switch transistors; Preferably, the second conductive layer and the third conductive layer are connected via a first type via; the third conductive layer and the active layer are connected via a second type via, and the first type via and the second type via are prepared in the same mask process; The third conductive layer is connected to the first conductive layer through a third type via, and the third conductive layer is connected to the sixth conductive layer through a fourth type via. The third type via and the fourth type via are prepared in the same mask process.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9.

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