Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a data signal line connected with the pixel driving circuit, the pixel driving circuit at least comprises a storage capacitor and a first transistor, the storage capacitor at least comprises a first pole plate and a second pole plate, and the first transistor is connected with the data signal line; in the direction perpendicular to the display substrate, the display substrate comprises a first conductive layer arranged on the substrate and a semiconductor layer arranged on the side, away from the substrate, of the first conductive layer, the first conductive layer at least comprises a data signal line, and the semiconductor layer at least comprises a first active layer of a first transistor; in at least one sub-pixel, the first active layer is connected with a data signal line through a via hole. According to the invention, the number of patterning processes is reduced, the production efficiency is effectively improved, the production cost is effectively reduced, and the product yield is improved to the greatest extent.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, existing display substrates have problems such as complex production processes and high production costs. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a preparation method thereof, and a display device, so as to solve the problems of complex production process and high production cost of existing display substrates.

[0006] On the one hand, the present disclosure provides a display substrate, including multiple repeating units, at least one repeating unit including multiple sub-pixels, at least one sub-pixel including a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a first transistor, the storage capacitor including at least a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the plane of the display substrate and the orthographic projection of the second electrode plate on the plane of the display substrate at least partially overlap; in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer arranged on a base and a semiconductor layer arranged on a side of the first conductive layer away from the base, the first conductive layer including at least the data signal line, and the semiconductor layer including at least the second electrode plate and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via.

[0007] In an exemplary embodiment, in at least one sub-pixel, the first active layer and the second electrode plate are interconnected as an integral structure.

[0008] In an exemplary embodiment, the pixel driving circuit also includes a second transistor, which is connected to the first power line through a power connection line; the first conductive layer also includes the first power line, and the semiconductor layer also includes the power connection line and a second active layer of the second transistor; in at least one sub-pixel, the second active layer is connected to the power connection line, and the power connection line is connected to the first power line through a via.

[0009] In an exemplary embodiment, in at least one sub-pixel, the second active layer and the power connection line are an integrated structure connected to each other.

[0010] In an exemplary embodiment, the first power line is in the shape of a straight line or a zigzag line extending along the second direction, the power connection line is in the shape of a straight line or a zigzag line extending along the first direction, and the first direction and the second direction intersect; two adjacent first power lines in the first direction are connected to the same power connection line to form a mesh structure.

[0011] In an exemplary embodiment, the first power line is in the shape of a straight line or a zigzag line extending along the second direction, the power connection line is in the shape of a straight line or a zigzag line extending along the first direction, the first direction and the second direction intersect; two adjacent first power lines in the first direction are connected to different power connection lines.

[0012] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on a side of the semiconductor layer away from the base, the second conductive layer at least includes a second gate electrode of the second transistor, and the second gate electrode is connected to the second electrode plate via a gate connecting electrode.

[0013] In an exemplary embodiment, the display substrate further includes a third conductive layer disposed on a side of the second conductive layer away from the base, the third conductive layer at least including the gate connecting electrode; the gate connecting electrode is respectively connected to the second gate electrode and the second electrode plate through the same via hole, or the gate connecting electrode is connected to the second gate electrode through one via hole and to the second electrode plate through another via hole.

[0014] In an exemplary embodiment, the third conductive layer further includes a first electrode and an active connection electrode, the first electrode and the active connection electrode are an integrated structure connected to each other, and the active connection electrode is connected to the second active layer through an active via.

[0015] In an exemplary embodiment, the second active layer is connected to the first electrode plate through a board-level via, or the second active layer is connected to a transparent connection electrode through a board-level via, and the transparent connection electrode and the first electrode plate are an integrated structure connected to each other.

[0016] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the active via on the substrate at least partially overlaps an orthographic projection of the board-level via on the substrate.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a third transistor, the third transistor includes at least a third active layer, the first conductive layer further includes a compensation signal line, and the compensation signal line is connected to the third active layer of multiple sub-pixels in the repeating unit through the semiconductor layer.

[0018] In an exemplary embodiment, the semiconductor layer further includes a compensation connection line, the compensation signal line is connected to the compensation connection line through a via hole, and the compensation connection line is connected to the third active layer of a plurality of sub-pixels in a repeating unit.

[0019] In an exemplary embodiment, in at least one repeating unit, the compensation connection line and the third active layers of a plurality of sub-pixels are an integral structure connected to each other.

[0020] In an exemplary embodiment, in at least one repeating unit, the compensation signal line is in a straight line or a folded line shape extending along the second direction, and the compensation signal line is arranged in the middle position of the repeating unit in the first direction, and the first direction and the second direction intersect.

[0021] In an exemplary embodiment, in at least one repeating unit, the plurality of sub-pixels include at least a red sub-pixel, a white sub-pixel, a green sub-pixel, and a blue sub-pixel sequentially arranged along the first direction, the red sub-pixel includes a red data signal line, the green sub-pixel includes a green data signal line, the blue sub-pixel includes a blue data signal line, the red data signal line is arranged on one side of the compensation signal line in the first direction, and the green data signal line and the blue data signal line are arranged on the other side of the compensation signal line in the first direction.

[0022] In an exemplary embodiment, in at least one repeating unit, a first gap is provided between the pixel driving circuit of the red sub-pixel and the pixel driving circuit of the white sub-pixel, a second gap is provided between the pixel driving circuit of the green sub-pixel and the pixel driving circuit of the blue sub-pixel, the red data signal line is provided in the first gap, and the green data signal line and the blue data signal line are provided in the second gap.

[0023] In an exemplary embodiment, the first electrode plate is disposed in the first conductive layer.

[0024] In an exemplary embodiment, the display substrate further includes a transparent conductive layer disposed between the base and the first conductive layer, and the first electrode plate is disposed in the transparent conductive layer.

[0025] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0026] In another aspect, the present disclosure further provides a preparation method, wherein the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit includes at least a storage capacitor and a first transistor, the storage capacitor includes at least a first electrode plate and a second electrode plate, and an orthographic projection of the first electrode plate on a plane of the display substrate at least partially overlaps with an orthographic projection of the second electrode plate on the plane of the display substrate; the preparation method includes:

[0027] forming a first conductive layer on a substrate, wherein the first conductive layer at least includes the data signal line;

[0028] A semiconductor layer is formed on the first conductive layer, wherein the semiconductor layer at least includes the second electrode and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

[0029] The embodiments of the present disclosure provide a display substrate and a method for preparing the same, and a display device. By disposing a data signal line in a first conductive layer, and connecting a first active layer in a semiconductor layer to the data signal line through a via hole, the number of patterning processes is reduced, production efficiency is effectively improved, production costs are effectively reduced, and product yield is maximized.

[0030] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0032] Figure 1 is a structural schematic diagram of a display device;

[0033] Figure 2 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 3 An equivalent circuit diagram of a pixel driving circuit in a repeating unit of an exemplary embodiment of the present disclosure;

[0035] Figure 4 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 5A for Figure 4 Sectional view along AA direction;

[0037] Figure 5B for Figure 4 Cross-sectional view along the BB direction;

[0038] Figure 6 This is a schematic diagram of a display substrate after a first conductive layer pattern is formed on the display substrate of the present disclosure;

[0039] Figure 7 This is a schematic diagram of a display substrate after a first insulating layer pattern is formed in the present disclosure;

[0040] Fig. 8A and Figure 8B This is a schematic diagram of a display substrate after a semiconductor layer pattern is formed on the display substrate of the present disclosure;

[0041] Fig. 9A and Fig. 9B This is a schematic diagram of a display substrate after a second conductive layer pattern is formed on the display substrate of the present disclosure;

[0042] Fig.10 This is a schematic diagram of a display substrate disclosed in the present invention after a third insulating layer and a planar layer pattern are formed;

[0043] Fig.11A and Fig. 11B This is a schematic diagram of a display substrate after a third conductive layer pattern is formed on the display substrate of the present disclosure;

[0044] Fig.12 It is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0045] Fig.13 It is a schematic structural diagram of another display substrate of an exemplary embodiment of the present disclosure;

[0046] Fig.14 It is a schematic diagram of another display substrate of the present disclosure after forming a transparent conductive layer and a first conductive layer pattern;

[0047] Fig.15 It is a schematic diagram of another display substrate of the present disclosure after a first insulating layer pattern is formed;

[0048] Fig.16A and Fig. 16BIt is a schematic diagram of another display substrate disclosed in the present invention after a semiconductor layer pattern is formed;

[0049] Fig.17A and Fig. 17B It is a schematic diagram of another display substrate of the present disclosure after a second conductive layer pattern is formed;

[0050] Fig.18 It is a schematic diagram of another display substrate of the present disclosure after forming a third insulating layer and a planar layer pattern;

[0051] Fig.19A and Fig.19B It is a schematic diagram of another display substrate of the present disclosure after a third conductive layer pattern is formed;

[0052] Fig. 20 The figure is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.

[0053] Description of reference numerals:

[0054] 10—substrate; 11—first electrode plate; 12—second electrode plate;

[0055] 13—transparent connecting electrode; 14—shielding electrode; 21—first power line;

[0056] 22—data signal line; 23—compensation signal line; 31—first active layer;

[0057] 32—second active layer; 33—third active layer; 34—power connection line;

[0058] 35—compensation connection line; 40—scanning signal line; 41—first gate electrode;

[0059] 42—second gate electrode; 43—third gate electrode; 50—first electrode;

[0060] 51—eleventh connecting electrode; 52—twelfth connecting electrode; 61—first insulating layer;

[0061] 62—second insulating layer; 63—third insulating layer; 64—planar layer. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0063] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0064] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0065] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0066] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0067] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0068] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0069] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0070] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0071] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0072] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0073] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0074] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data driver, a scan driver and a pixel array, the timing controller is respectively connected to the data driver and the scan driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), and the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a light-emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line and the data signal line, the light-emitting unit may include at least a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel PXij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and to the j-th data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal having a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of a conduction level pulse to a next level circuit under the control of a clock signal, where m may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0075] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor and a first transistor, the storage capacitor comprising at least a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the plane of the display substrate at least partially overlapping the orthographic projection of the second electrode plate on the plane of the display substrate; in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer disposed on a base and a semiconductor layer disposed on a side of the first conductive layer away from the base, the first conductive layer comprising at least the data signal line, the semiconductor layer comprising at least the second electrode plate and a first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via.

[0076] In an exemplary embodiment, the pixel driving circuit also includes a second transistor, which is connected to the first power line through a power connection line; the first conductive layer also includes the first power line, and the semiconductor layer also includes the power connection line and a second active layer of the second transistor; in at least one sub-pixel, the second active layer is connected to the power connection line, and the power connection line is connected to the first power line through a via.

[0077] In an exemplary embodiment, the pixel driving circuit further includes a third transistor, the third transistor includes at least a third active layer, the first conductive layer further includes a compensation signal line, and the compensation signal line is connected to the third active layer of multiple sub-pixels in the repeating unit through the semiconductor layer.

[0078] In an exemplary embodiment, the semiconductor layer further includes a compensation connection line, the compensation signal line is connected to the compensation connection line through a via hole, and the compensation connection line is connected to the third active layer of a plurality of sub-pixels in a repeating unit.

[0079] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0080] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 2 As shown, in an exemplary embodiment, in a direction parallel to the display substrate, the display substrate may include a plurality of repeating units 100, and at least one repeating unit 100 may include a plurality of sub-pixels sequentially arranged along a first direction X. In an exemplary embodiment, the repeating unit is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging along at least one direction, that is, the display substrate is spliced ​​by a plurality of repeating units.

[0081] In an exemplary embodiment, one repeating unit 100 may include four sub-pixels, and the four sub-pixels may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light.

[0082] In an exemplary embodiment, in at least one repeating unit 100, the second subpixel P2 may be disposed on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be disposed on one side of the second subpixel P2 in the first direction X, and the fourth subpixel P4 may be disposed on one side of the third subpixel P3 in the first direction X. A plurality of subpixels sequentially disposed along the first direction X may be referred to as pixel rows, and a plurality of subpixels sequentially disposed along the second direction Y may be referred to as pixel columns. A plurality of pixel rows and a plurality of pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0083] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a white sub-pixel (W) emitting white light, the third sub-pixel P3 may be a green sub-pixel (G) emitting green light, and the fourth sub-pixel P4 may be a blue sub-pixel (B) emitting blue light. In some possible embodiments, the arrangement of RWGB may be adjusted according to actual needs, and the present disclosure does not specifically limit this.

[0084] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. In at least one repeating unit, the driving circuit layer may include a plurality of circuit units, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to a scanning signal line and a data signal line, etc., the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line, and output a corresponding current to the light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, the light-emitting unit may include at least a light-emitting device, the light-emitting device is connected to a pixel driving circuit of a circuit unit of a sub-pixel in which it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to a current output by the pixel driving circuit of the sub-pixel in which it is located.

[0085] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a substrate, a color filter structure layer disposed on a side of the driving circuit layer away from the substrate, and a light emitting structure layer disposed on a side of the color filter structure layer away from the substrate. In at least one repeating unit, the color filter structure layer may include a plurality of color filter units, and the color filter unit may include at least a color filter layer, and the color filter layer is configured to enable the corresponding sub-pixel to emit light of a desired color.

[0086] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit. The color filter unit mentioned in the present disclosure refers to an area divided according to a color filter layer. The light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. The positions of the orthographic projection of the circuit unit on the substrate, the orthographic projection of the color filter layer on the substrate, and the orthographic projection of the light-emitting unit on the substrate may correspond, or may not correspond.

[0087] In the exemplary embodiment of the present disclosure, the positions of the circuit unit's orthographic projection on the substrate, the color filter layer's orthographic projection on the substrate, and the light-emitting unit's orthographic projection on the substrate are one-to-one corresponding, and the circuit unit, the color filter unit, and the light-emitting unit constitute sub-pixels. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0088] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged along a first direction X may be referred to as pixel rows, a plurality of sub-pixels sequentially arranged along a second direction Y may be referred to as pixel columns, a plurality of pixel rows and a plurality of pixel columns constitute an array-arranged pixel array, and the first direction X and the second direction Y intersect.

[0089] In an exemplary embodiment, the first direction X may be a horizontal direction, the second direction Y may be a vertical direction, and the first direction X and the second direction Y may be perpendicular to each other.

[0090] Figure 3 The equivalent circuit diagram of the pixel driving circuit in one repeating unit of the exemplary embodiment of the present disclosure. Figure 3 As shown, at least one repeating unit may include four pixel driving circuits, the four pixel driving circuits may be arranged in a square manner, and the pixel driving circuit may be a 3T1C structure.

[0091] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2 and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 40, the first power line 21, the data signal line 22 and the compensation signal line 23.

[0092] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is respectively connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, and the second node N2 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C.

[0093] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0094] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0095] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 40, a first electrode of the first transistor T1 is connected to the data signal line 22, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 40, the first transistor T1 inputs a data signal of the data signal line 22 to the gate electrode of the second transistor T2.

[0096] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 21, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received by its gate electrode.

[0097] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 40, a first electrode of the third transistor T3 is connected to the compensation signal line 23, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 40, the third transistor T3 extracts the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0098] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 40 .

[0099] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one pixel row, gate electrodes of the plurality of first transistors T1 and gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 40 .

[0100] In an exemplary embodiment, in the four pixel driving circuits of at least one repeating unit, the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3 are connected to the same scan signal line 40 .

[0101] In an exemplary embodiment, the light emitting device EL may be an OLED, including a stacked first electrode, an organic light emitting layer, and a second electrode, or may be a QLED, including a stacked first electrode, a quantum dot light emitting layer, and a second electrode. The first electrode of the light emitting device EL is connected to the second node N2, the second electrode of the light emitting device EL is connected to the second power line VSS, and the light emitting device EL emits light of corresponding brightness in response to the current of the second electrode of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; or the first electrode may be a cathode, and the second electrode may be an anode.

[0102] In an exemplary embodiment, the signal of the first power line 21 is a high level signal that is continuously provided, and the signal of the second power line VSS is a low level signal that is continuously provided.

[0103] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the third transistor T3 may include a P-type transistor and an N-type transistor.

[0104] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and an oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide transistor is oxide semiconductor (Oxide). Low-temperature polysilicon transistors have the advantages of high mobility and fast charging, and oxide transistors have the advantages of low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate, i.e., an LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0105] Figure 4 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a structure of a repeating unit (four sub-pixels) of a bottom emission display substrate. Figure 4As shown, in a direction parallel to the display substrate, at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3 and a fourth subpixel P4 arranged along a first direction X, and each subpixel includes a pixel driving circuit.

[0106] In an exemplary embodiment, the first subpixel P1 may be a red subpixel, the second subpixel P2 may be a white subpixel, the third subpixel P3 may be a green subpixel, and the fourth subpixel P4 may be a blue subpixel.

[0107] In an exemplary embodiment, at least one repeating unit may include two first power lines 21, four data signal lines 22, one compensation signal line 23, and one scan signal line 40, all of which are connected to pixel driving circuits in four sub-pixels.

[0108] In an exemplary embodiment, the shape of the scan signal line 40 can be a straight line or a folded line extending along the first direction X, the shape of the first power line 21, the data signal line 22 and the compensation signal line 23 can be a straight line or a folded line extending along the second direction Y, the compensation signal line 23 can be arranged in the middle position of the repeating unit in the first direction X, the two first power lines 21 can be arranged on both sides of the repeating unit in the first direction X, four data signal lines 22 and one compensation signal line 23 can be arranged between the two first power lines 21, two of the four data signal lines 22 can be located between the compensation signal line 23 and one first power line 21, and the other two of the four data signal lines 22 can be located between the compensation signal line 23 and another first power line 21.

[0109] In an exemplary embodiment, the four data signal lines 22 may include at least a red data signal line located at a red sub-pixel, a green data signal line located at a green sub-pixel, and a blue data signal line located at a blue sub-pixel, the red data signal line may be arranged on one side of the first direction X of the compensation signal line 23, and the green data signal line and the blue data signal line may be arranged on the other side of the first direction X of the compensation signal line 23.

[0110] In an exemplary embodiment, a first sub-pixel P1 is formed between a first power line 21 and a data signal line 22 adjacent to the first direction X, a second sub-pixel P2 is formed between the compensation signal line 23 and a data signal line 22 adjacent to the opposite direction of the first direction X, a third sub-pixel P3 is formed between the compensation signal line 23 and a data signal line 22 adjacent to the first direction X, and a fourth sub-pixel P4 is formed between another first power line 21 and a data signal line 22 adjacent to the opposite direction of the first direction X.

[0111] In an exemplary embodiment, in at least one repeating unit, a first gap is provided between the pixel driving circuit of the red sub-pixel and the pixel driving circuit of the white sub-pixel, a second gap is provided between the pixel driving circuit of the green sub-pixel and the pixel driving circuit of the blue sub-pixel, a red data signal line is provided in the first gap, and a green data signal line and a blue data signal line are provided in the second gap.

[0112] In an exemplary embodiment, among the four sub-pixels of the repeating unit, the pixel driving circuit of at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The first transistor T1, the second transistor T2, and the third transistor T3 may each include an active layer, a gate electrode, a first electrode, and a second electrode, and the storage capacitor may include at least a first electrode plate 11 and a second electrode plate 12, and the orthographic projection of the first electrode plate 11 on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate 12 on the display substrate plane.

[0113] In an exemplary embodiment, in at least one repeating unit, the scan signal line 40 is respectively connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in each sub-pixel, the data signal line 22 is connected to the first electrode of the first transistor T1 in each sub-pixel, the compensation signal line 23 is connected to the first electrode of the third transistor T3 in each sub-pixel, the first power line 21 is connected to the first electrode of the second transistor T2 in each sub-pixel, the second electrode of the first transistor T1 in each sub-pixel, the gate electrode of the second transistor T2 and the second electrode plate 12 of the storage capacitor are interconnected, and the second electrode of the second transistor T2 in each sub-pixel, the second electrode of the third transistor T3 and the first electrode plate 11 of the storage capacitor are interconnected.

[0114] In an exemplary embodiment, at least one repeating unit may further include a power connection line 34, and the first power line 21 is connected to the first electrode of the second transistor T2 in each sub-pixel through the power connection line 34. The power connection line 34 may be in the shape of a straight line or a folded line extending along the first direction X, and the power connection line 34 is connected to two adjacent first power lines 21 in the first direction X, so that the power connection line 34 extending along the first direction X and the first power line 21 extending along the second direction Y form a mesh structure in the repeating unit.

[0115] In an exemplary embodiment, the power connection line 34 may be arranged across the first sub-pixel P1 to the fourth sub-pixel P4, the first end of the power connection line 34 is connected to the first power line 21 in the first sub-pixel P1, the second end of the power connection line 34 is connected to the first power line 21 in the fourth sub-pixel P4, and the area between the first end and the second end is respectively connected to the first electrode of the second transistor T2 in the four sub-pixels. In this way, one first power line 21 can provide power signals to the pixel driving circuits of the four sub-pixels through one power connection line 34, forming a two-to-four structure of the first power line.

[0116] In an exemplary embodiment, at least one repeating unit may further include a compensation connection line 35, and the compensation signal line 23 is connected to the first electrode of the third transistor T3 in each sub-pixel through the compensation connection line 35. The shape of the compensation connection line 35 may be a straight line or a folded line extending along the first direction X. The compensation connection line 35 is connected to the compensation signal line 23 on one hand, and is respectively connected to the first electrodes of the third transistors T3 in the four sub-pixels on the other hand.

[0117] In an exemplary embodiment, the compensation connection line 35 may be arranged across the first sub-pixel P1 to the fourth sub-pixel P4, the middle of the compensation connection line 35 in the first direction X is connected to the compensation signal line 23, and both sides of the compensation connection line 35 in the first direction X are respectively connected to the first electrodes of the third transistors T3 in the four sub-pixels. In this way, one compensation signal line 23 can provide compensation signals to the pixel driving circuits of the four sub-pixels, forming a one-to-four structure of compensation signal lines.

[0118] Figure 5A for Figure 4 Sectional view along AA direction, Figure 5B for Figure 4 The cross-sectional view along the BB axis. Figure 4 , Figure 5A and Figure 5B As shown, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate 10 and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate. In an exemplary embodiment,

[0119] The driving circuit layer may include a first conductive layer arranged on the substrate 10, a first insulating layer 61 arranged on the side of the first conductive layer away from the substrate, a semiconductor layer arranged on the side of the first insulating layer 61 away from the substrate, a second insulating layer 62 arranged on the side of the semiconductor layer away from the substrate, a second conductive layer arranged on the side of the second insulating layer 62 away from the substrate, and a third insulating layer 63 and a flat layer 64 arranged on the side of the second conductive layer away from the substrate. The light-emitting structure layer may include at least a third conductive layer arranged on the side of the driving circuit layer away from the substrate.

[0120] In an exemplary embodiment, the first conductive layer may include at least a first electrode 11 and a data signal line 22, and the semiconductor layer may include at least a second electrode 12 and a first active layer 31 of the first transistor T1. In at least one sub-pixel, the first region of the first active layer 31 is connected to the data signal line 22 through a via hole.

[0121] In an exemplary embodiment, in at least one sub-pixel, the first active layer 31 and the second electrode plate 12 may be an integral structure connected to each other.

[0122] In an exemplary embodiment, the first conductive layer may further include a first power line 21, and the semiconductor layer may further include a power connection line 34 and a second active layer 32 of the second transistor T2. In at least one sub-pixel, the first region of the second active layer 32 is connected to the power connection line 34, and the power connection line 34 is connected to the first power line 21 through a via.

[0123] In an exemplary embodiment, in at least one sub-pixel, the second active layer 32 and the power connection line 34 may be an integral structure connected to each other.

[0124] In an exemplary embodiment, the first conductive layer may further include a compensation connection line 35, the semiconductor layer may further include a third active layer 33 of the third transistor T3, and the compensation signal line 35 is connected to the third active layer 33 of a plurality of sub-pixels in the repeating unit through the semiconductor layer.

[0125] In an exemplary embodiment, the semiconductor layer may further include a compensation connection line 35. In at least one repeating unit, the compensation connection line 35 is connected to the first region of the third active layer 33 of the plurality of sub-pixels in the repeating unit on one hand, and is connected to the compensation signal line 23 through a via hole on the other hand.

[0126] In an exemplary embodiment, in at least one repeating unit, the compensation connection line 35 and the third active layers 33 of the plurality of sub-pixels may be an integral structure connected to each other.

[0127] In an exemplary embodiment, the second conductive layer may include at least a second gate electrode 42 of the second transistor, and the second gate electrode 42 is connected to the second electrode plate 12 through a twelfth connection electrode 52 , and the twelfth connection electrode 52 may serve as a gate connection electrode of the present disclosure.

[0128] In an exemplary embodiment, the third conductive layer may include at least a twelfth connecting electrode 52. In one embodiment, the twelfth connecting electrode 52 may be connected to the second gate electrode 42 in the second conductive layer through a via hole, and connected to the second electrode plate 12 in the semiconductor layer through another via hole. In another embodiment, the twelfth connecting electrode 52 may be connected to the second gate electrode 42 in the second conductive layer and the second electrode plate 12 in the semiconductor layer through the same via hole.

[0129] In an exemplary embodiment, the third conductive layer may further include a first electrode 50 and an eleventh connecting electrode 51. The first electrode 50 and the eleventh connecting electrode 51 may be an integral structure connected to each other. The eleventh connecting electrode 51 is connected to the second region of the second active layer 32 through the eleventh via V11. The eleventh connecting electrode 51 may serve as an active connecting electrode of the present disclosure, and the eleventh via V11 may serve as an active via of the present disclosure.

[0130] In an exemplary embodiment, the second region of the second active layer 32 is connected to the first electrode plate 11 through a second via hole V2 , and the second via hole V2 may serve as a board-level via hole of the present disclosure.

[0131] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the eleventh via hole V11 (active via hole) on the substrate at least partially overlaps with an orthographic projection of the second via hole V2 (board-level via hole) on the substrate.

[0132] In an exemplary embodiment, the area of ​​the orthographic projection of the eleventh via hole V11 on the substrate may be larger than the area of ​​the orthographic projection of the second via hole V2 on the substrate, which may improve connection reliability.

[0133] In exemplary embodiments, the first electrode may be an anode of the light emitting structure layer, or the first electrode may be a cathode of the light emitting structure layer.

[0134] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0135] In an exemplary embodiment, taking an example in which a repeating unit includes four sub-pixels (a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4), the preparation process of the display substrate in this exemplary embodiment may include the following operations.

[0136] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate. Figure 6 In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0137] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel in the repeating unit may include at least a first electrode plate 11 of a storage capacitor.

[0138] In an exemplary embodiment, the shape of the first electrode plate 11 can be rectangular, the corners of the rectangle can be chamfered, the edges of the rectangle can be fold lines, the first electrode plate 11 can be set in the middle area of ​​the sub-pixel in the second direction Y, the first electrode plate 11 can serve as a electrode plate of the storage capacitor, and the first electrode plate 11 is configured to form a storage capacitor with a second electrode plate formed subsequently.

[0139] In an exemplary embodiment, the areas of the first plates 11 in the respective sub-pixels in the repeating unit may be substantially the same, so that the capacities of the storage capacitors in the respective sub-pixels are substantially the same.

[0140] In an exemplary embodiment, the first conductive layer of the repeating unit may further include two first power lines 21 , four data signal lines 22 , and one compensation signal line 23 .

[0141] In an exemplary embodiment, the shapes of the first power line 21, the data signal line 22 and the compensation signal line 23 may be straight lines or folded lines with the main part extending along the second direction Y. The compensation signal line 23 may be located in the middle of the repeating unit in the first direction X, and may be arranged between the second sub-pixel P2 and the third sub-pixel P3. Two first power lines 21 may be located on both sides of the compensation signal line 23 in the first direction X, and are respectively arranged in the first sub-pixel P1 and the fourth sub-pixel P4. Four data signal lines 22 may be respectively arranged in each sub-pixel, two of the four data signal lines 22 may be located between one first power line 21 and the compensation signal line 23, and the other two of the four data signal lines 22 may be located between another first power line 21 and the compensation signal line 23.

[0142] In an exemplary embodiment, the two first power lines 21 may include a first first power line 21-1 and a second first power line 21-2 sequentially disposed along the first direction X, and the four data signal lines 22 may include a first data signal line 22-1, a third data signal line 22-3, and a fourth data signal line 22-4 sequentially disposed along the first direction X. The first first power line 21-1 and the first data signal line 22-1 may define a first pixel column, the second data signal line 22-2 and the compensation signal line 23 may define a second pixel column, the compensation signal line 23 and the third data signal line 22-3 may define a third pixel column, and the fourth data signal line 22-4 and the second first power line 21-2 may define a fourth pixel column.

[0143] In an exemplary embodiment, the first power line 21 , the data signal line 22 and the compensation signal line 23 may be folded lines of unequal widths. Using folded lines of variable widths can not only facilitate the layout of the pixel structure but also reduce parasitic capacitance.

[0144] In an exemplary embodiment, the orthographic projection of the compensation signal line 23 on the substrate at least partially overlaps with the orthographic projection of the vertical reference line on the substrate, the positions and shapes of the two first power lines 21 can be substantially mirror-symmetrical with respect to the vertical reference line, the positions and shapes of the two data signal lines 22 located on the opposite side of the first direction X of the compensation signal line 23 and the positions and shapes of the two data signal lines 22 located on the side of the first direction X of the compensation signal line 23 can be substantially mirror-symmetrical with respect to the vertical reference line, the positions and shapes of the four first electrodes 11 in the repeating unit can be substantially mirror-symmetrical with respect to the vertical reference line, and the vertical reference line can be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0145] (12) Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include: depositing a first insulating film on the substrate on which the aforementioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer pattern covering the first conductive layer, wherein a plurality of via holes are provided on the first insulating layer, such as Figure 7 shown.

[0146] In an exemplary embodiment, the plurality of via holes of each sub-pixel in the repeating unit includes at least a first via hole V1 , a second via hole V2 , and a third via hole V3 .

[0147] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the data signal line 22 on the substrate, the first insulating layer in the first via hole V1 is etched away to expose the surface of the data signal line 22, and the first via hole V1 is configured to connect the first region of the first active layer formed subsequently to the data signal line 22 through the via hole. In an exemplary embodiment, the second via hole V2 can be used as a board-level via hole of the present disclosure.

[0148] In an exemplary embodiment, the orthographic projections of the second via V2 and the third via V3 on the substrate at least partially overlap with the orthographic projections of the first electrode plate 11 on the substrate, the first insulating layer in the second via V2 and the third via V3 is etched away to expose the surface of the first electrode plate 11, the second via V2 is configured to connect the second area of ​​the second active layer formed subsequently to the first electrode plate 11 through the via, and the third via V3 is configured to connect the second area of ​​the third active layer formed subsequently to the first electrode plate 11 through the via.

[0149] In an exemplary embodiment, the first insulating layer in the repeating unit may further include a fourth via hole V4 and a fifth via hole V5 .

[0150] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the first power line 21 on the substrate, the first insulating layer in the fourth via hole V4 is etched away to expose the surface of the first power line 21, and the fourth via hole V4 is configured to connect a subsequently formed power connection line to the first power line 21 through the via hole. In an exemplary embodiment, the fourth via hole V4 may be respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4.

[0151] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate, the first insulating layer in the fifth via hole V5 is etched away to expose the surface of the compensation signal line 23, and the fifth via hole V5 is configured to connect a subsequently formed compensation connection line to the compensation signal line 23 through the via hole. In an exemplary embodiment, the fifth via hole V5 may be disposed between the second sub-pixel P2 and the third sub-pixel P3.

[0152] In an exemplary embodiment, the plurality of via holes on the first insulating layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0153] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process, and forming a semiconductor layer pattern disposed on the first insulating layer, such as Fig. 8A and Figure 8B As shown, Figure 8B for Fig. 8A Schematic diagram of the semiconductor layer in the figure.

[0154] In an exemplary embodiment, the semiconductor layer pattern in each sub-pixel in the repeating unit may include at least a first active layer 31 , a second active layer 32 , a third active layer 33 , a power connection line 34 , a compensation connection line 35 , and a second plate 12 .

[0155] In an exemplary embodiment, the shape of the second electrode plate 12 can be rectangular, and the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 is configured to form another electrode plate of the storage capacitor, and the first electrode plate 11 and the second electrode plate 12 constitute the storage capacitor of the pixel driving circuit.

[0156] In an exemplary embodiment, in one repeating unit, the overlapping area of ​​the orthographic projection of the second electrode plate 12 on the substrate and the orthographic projection of the first electrode plate 11 on the substrate in each sub-pixel may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0157] In an exemplary embodiment, the shape of the power connection line 34 can be a straight line or a broken line with the main part extending along the first direction X. The power connection line 34 can be arranged on the side of the second electrode plate 12 in the opposite direction of the second direction Y. The power connection line 34 is connected to the first power line 21 through the fourth via V4.

[0158] In an exemplary embodiment, in one repeating unit, the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate.

[0159] In an exemplary embodiment, the power connection line 34 can be used as a horizontal connection line, and the two first power lines 21 in a repeating unit are both connected to the power connection line 34, so that the power connection line 34 extending along the first direction X and the first power line 21 extending along the second direction Y form a mesh structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0160] In an exemplary embodiment, the shape of the compensation connection line 35 can be a straight line or a broken line with the main part extending along the first direction X. The compensation connection line 35 can be arranged on one side of the second electrode plate 12 in the second direction Y, and the compensation connection line 35 is connected to the compensation signal line 23 through the fifth via V5.

[0161] In an exemplary embodiment, in one repeating unit, the orthographic projection of the compensation connection line 35 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the compensation connection line 35 on the substrate does not overlap with the orthographic projection of the first power line 21 on the substrate.

[0162] In an exemplary embodiment, the first active layer 31 can serve as an active layer of the first transistor T1, the second active layer 32 can serve as an active layer of the second transistor T2, the third active layer 33 can serve as an active layer of the third transistor T3, the first active layer 31 and the third active layer 33 can be disposed between the compensation connection line 35 and the second electrode plate 12, and the second active layer 32 can be disposed between the power connection line 34 and the second electrode plate 12.

[0163] In example embodiments, the first active layer 31 , the second active layer 32 , and the third active layer 33 may each include a channel region and first and second regions located at both sides of the channel region.

[0164] In an exemplary embodiment, the first active layer 31 may be in a strip shape extending along the second direction Y, and may be disposed on one side of the second electrode plate 12 in the second direction Y. The first region of the first active layer 31 is connected to the data signal line 22 through the first via hole V1, and the second region of the first active layer 31 is connected to the second electrode plate 12, thereby enabling the data signal line 22 to write the data signal into the first electrode of the first transistor T1. In an exemplary embodiment, the first region of the first active layer 31 in each sub-pixel may be connected to one data signal line 22 through the first via hole V1, thereby enabling four data signal lines 22 to write the data signals into the first electrodes of four first transistors T1 in one repeating unit, respectively.

[0165] In an exemplary embodiment, the four data signal lines 22 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line sequentially arranged along the first direction X. The first data signal line may be located at one side of the first pixel column in the first direction X, and connected to the first region of the first active layer in the first sub-pixel P1. The second data signal line may be located at one side of the second pixel column in the opposite direction of the first direction X, and located at one side of the first data signal line in the first direction X, and connected to the first region of the first active layer in the second sub-pixel P2. The third data signal line may be located at one side of the third pixel column in the first direction X, and connected to the first region of the first active layer in the third sub-pixel P3. The fourth data signal line may be located at one side of the fourth pixel column in the opposite direction of the first direction X, and located at one side of the first direction X of the third data signal line, and connected to the first region of the first active layer in the fourth sub-pixel P4.

[0166] In an exemplary embodiment, in one sub-pixel, the first active layer 31 and the second electrode plate 12 may be an integral structure connected to each other.

[0167] In an exemplary embodiment, the second active layer 32 may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The orthographic projection of the channel region of the second active layer 32 on the substrate may be located within the range of the orthographic projection of the first electrode plate 11 on the substrate, and the first electrode plate 11 may shield the channel region of the second active layer 32 to prevent light from affecting the channel, reduce leakage current, and thus prevent the influence of light on transistor characteristics, thereby ensuring the electrical performance of the second transistor T2.

[0168] In the exemplary embodiment, the first region of the second active layer 32 is connected to the power connection line 34, and the second region of the second active layer 32 is connected to the first electrode plate 11 through the second via hole V2. Since the power connection line 34 is connected to the first power line, the first power line 21 writes the first power signal to the first electrode of the second transistor T2, and the second electrode of the second transistor T2 and the first electrode plate 11 have the same potential.

[0169] In an exemplary embodiment, the two first power lines 21 may include a first first power line and a second first power line, the first first power line may be located on the side of the first pixel column in the opposite direction of the first direction X, and the second first power line may be located on the side of the fourth pixel column in the first direction X. Since the first first power line of the first pixel column can simultaneously provide the first power signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4 through the power connection line 34, and the second first power line of the fourth pixel column can simultaneously provide the first power signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4 through the power connection line 34, the first power lines 21 in one repeating unit are a two-to-four structure. The display substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is conducive to improving the resolution.

[0170] In an exemplary embodiment, two first power lines 21 in a repeating unit are substantially mirror-symmetrical with respect to a vertical reference line, and four second transistors T2 in a repeating unit are substantially mirror-symmetrical with respect to the vertical reference line. This symmetrical structure disclosed in the present invention can ensure that the voltage drop of the first power line written into the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0171] In an exemplary embodiment, in one repeating unit, the power connection line 34 and the second active layers 32 in four sub-pixels may be an integral structure connected to each other.

[0172] In an exemplary embodiment, the shape of the third active layer 33 can be a strip shape extending along the second direction Y, the first area of ​​the third active layer 33 is connected to the compensation connection line 35, and the second area of ​​the third active layer 33 is connected to the first electrode 11 through the third via V3, thereby realizing that the compensation signal line 23 writes the compensation signal into the first electrode of the third transistor T3, and at the same time realizes that the second electrode of the third transistor T3 has the same potential as the first electrode 11.

[0173] In an exemplary embodiment, the compensation signal line 23 may be located between the second pixel column and the third pixel column, and the compensation signal line 23 may provide compensation signals to the pixel driving circuits in the four sub-pixels at the same time through the compensation connection line 35, so that the four pixel driving circuits in one repeating unit may share one compensation signal line 23, that is, the compensation signal line 23 in one repeating unit is a one-to-four structure. The display substrate disclosed herein saves the number of signal lines and reduces the occupied space by designing the compensation signal line as a one-to-four structure, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is conducive to improving the resolution.

[0174] In an exemplary embodiment, the compensation connection line 35 may be mirror-symmetrical with respect to the compensation signal line 23. Such a symmetrical structure of the present disclosure can ensure that the RC delay of the third transistors T3 in the four sub-pixels when the compensation signal is written is substantially the same, thereby ensuring display uniformity.

[0175] In an exemplary embodiment, in one repeating unit, the compensation connection line 35 and the third active layers 33 in four sub-pixels may be an integral structure connected to each other.

[0176] In example embodiments, positions of respective patterns in the semiconductor layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0177] In an exemplary embodiment, the positions of the various patterns of the semiconductor layer in the first subpixel P1 and the second subpixel P2 can be substantially mirror-symmetrical with respect to a pixel reference line, the positions of the various patterns of the semiconductor layer in the third subpixel P3 and the fourth subpixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the various patterns of the semiconductor layer in the first subpixel P1 and the fourth subpixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the various patterns of the semiconductor layer in the second subpixel P2 and the third subpixel P3 can be substantially mirror-symmetrical with respect to the pixel reference line, and the pixel reference line can be a straight line located between adjacent subpixels and extending along the second direction Y.

[0178] In an exemplary embodiment, the semiconductor layer may use a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0179] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the second conductive film by a patterning process to form a second insulating layer disposed on the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, such as Fig. 9A and Fig. 9B As shown, Fig. 9B for Fig. 9A In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GT) layer.

[0180] In an exemplary embodiment, the second conductive layer pattern of each sub-pixel in a repeating unit may include at least a scan signal line 40 and a second gate electrode 42 .

[0181] In an exemplary embodiment, the shape of the scanning signal line 40 can be a straight line or a broken line with the main part extending along the first direction X. The scanning signal line 40 can be located on one side of the second direction Y of the second electrode plate 12. The scanning signal line 40 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0182] In an exemplary embodiment, the orthographic projection of the scan signal line 40 on the substrate at least partially overlaps with the orthographic projection of the first active layer in each subpixel on the substrate, and the scan signal line 40 in the overlapping area may serve as the gate electrode of the first transistor T1.

[0183] In an exemplary embodiment, the orthographic projection of the scan signal line 40 on the substrate at least partially overlaps with the orthographic projection of the third active layer in each subpixel on the substrate, and the scan signal line 40 in the overlapping area can serve as the gate electrode of the third transistor T3.

[0184] In an exemplary embodiment, in one sub-pixel, one scan signal line 40 may serve as both the first gate electrode and the third gate electrode, so that the scan signal line 40 may control the on or off of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0185] In an exemplary embodiment, in one repeating unit, one scan signal line 40 simultaneously serves as four first gate electrodes and four third transistors in four sub-pixels, so that the scan signal line 40 can control the on or off of four first transistors T1 and four third transistors T3 in one repeating unit.

[0186] In an exemplary embodiment, in one pixel row, one scan signal line 40 simultaneously serves as all first gate electrodes and all third transistors in a plurality of sub-pixels, so that the scan signal line 40 can control the on or off of all first transistors T1 and all third transistors T3 in one pixel row.

[0187] In an exemplary embodiment, the second gate electrode 42 may be in the shape of a strip having a main portion extending along the first direction X, and the second gate electrode 42 may serve as a gate electrode of the second transistor T2. On one hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and on the other hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate.

[0188] In exemplary embodiments, positions of respective patterns in the second conductive layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0189] In an exemplary embodiment, the positions of the various patterns of the second conductive layer in the first subpixel P1 and the second subpixel P2 can be substantially mirror-symmetrical with respect to a pixel reference line, the positions of the various patterns of the second conductive layer in the third subpixel P3 and the fourth subpixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the various patterns of the second conductive layer in the first subpixel P1 and the fourth subpixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, and the positions of the various patterns of the second conductive layer in the second subpixel P2 and the third subpixel P3 can be substantially mirror-symmetrical with respect to the pixel reference line.

[0190] In an exemplary embodiment, after the second insulating film and the second conductive film are patterned, the second insulating layer pattern and the second conductive layer pattern are substantially the same, and the second insulating layer is disposed on a side of the second conductive layer close to the substrate.

[0191] In an exemplary embodiment, this process also includes a conductorization treatment. The conductorization treatment is to perform plasma treatment using the second conductive layer as a shield after forming the second conductive layer pattern, and the semiconductor layer shielded by the second conductive layer is used as the channel region of the transistor, and the semiconductor layer not shielded by the second conductive layer is processed into a conductorization layer to form a conductorized second electrode plate and a conductorized source and drain region.

[0192] (15) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: first depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process, forming a third insulating layer covering the second conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, such as Fig.10 shown.

[0193] In an exemplary embodiment, the plurality of via holes in each sub-pixel in the repeating unit includes at least an eleventh via hole V11 and a twelfth via hole V12 .

[0194] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the second region of the second active layer on the substrate, the flat layer and the third insulating layer in the eleventh via hole V11 are etched away, exposing the surface of the second region of the second active layer, and the eleventh via hole V11 is configured to connect the second connection electrode formed subsequently to the second region of the second active layer through the via hole. In an exemplary embodiment, the eleventh via hole V11 can serve as an active via hole of the present disclosure.

[0195] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the eleventh via hole V11 on the substrate at least partially overlaps with an orthographic projection of the second via hole V2 on the substrate.

[0196] In an exemplary embodiment, the area of ​​the orthographic projection of the eleventh via hole V11 on the substrate may be larger than the area of ​​the orthographic projection of the second via hole V2 on the substrate, which may improve connection reliability.

[0197] In an exemplary embodiment, the twelfth via hole V12 may include two sub-holes, the orthographic projection of one sub-hole on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 42 on the substrate, and exposes the surface of the second gate electrode 42, and the orthographic projection of the other sub-hole on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate, and exposes the surface of the second electrode plate 12. The twelfth via hole V12 is configured to allow the first connection electrode formed subsequently to be connected to the second gate electrode 42 and the second electrode plate 12 at the same time through the via hole.

[0198] In some possible embodiments, the twelfth via V12 can be a via of a transition structure, including two half holes, one half hole exposing the surface of the second gate electrode 42, and the other half hole exposing the surface of the second electrode plate 12, so that the twelfth via V12 of the transition structure composed of the two half holes simultaneously exposes the second gate electrode 42 and the second electrode plate 12.

[0199] In an exemplary embodiment, this process can use a patterning process to form vias on the third insulating layer and the flat layer at the same time. The third insulating layer and the flat layer share a halftone or gray tone mask (MASK) process, which effectively reduces the number of patterning processes.

[0200] In an exemplary embodiment, the plurality of via holes on the third insulating layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0201] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the flat layer, such as Fig.11A and Fig. 11B As shown, Fig. 11B for Fig.11A Schematic plan view of the third conductive layer in FIG.

[0202] In an exemplary embodiment, the third conductive layer of each sub-pixel in the repeating unit may include at least the first connection electrode 51 , the second connection electrode 52 , and the first electrode 50 .

[0203] In an exemplary embodiment, the first connection electrode 51 may be in a strip shape with a main portion extending along the second direction Y, a first end of the first connection electrode 51 is connected to the second region of the second active layer through an eleventh via hole V11, and a second end of the first connection electrode 51 is connected to the first electrode 50. In an exemplary embodiment, the first connection electrode 51 may serve as an active connection electrode of the present disclosure.

[0204] In an exemplary embodiment, the second connection electrode 52 may be in a block shape (such as a rectangle), and the second connection electrode 52 is connected to the second gate electrode 42 and the second electrode plate 12 through the twelfth via hole V12. In an exemplary embodiment, since the second electrode plate 12 is connected to the second region of the first active layer, the second connection electrode 52 enables the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 12 of the storage capacitor to have the same potential, forming a first node N1 in the pixel driving circuit. In an exemplary embodiment, the second connection electrode 52 may serve as a gate connection electrode of the present disclosure.

[0205] In an exemplary embodiment, the shape of the first electrode 50 may be rectangular, and the corners of the rectangle may be provided with chamfers, grooves or protrusions, and the edge of the first electrode 50 on one side close to the second electrode plate 12 is connected to the second end of the first connection electrode 51. Since the second region of the second active layer is connected to the first electrode plate 11 through a via hole, and the second region of the third active layer is connected to the first electrode plate 11 through a via hole, the first connection electrode 51 enables the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential, thereby forming a second node N2 in the pixel driving circuit.

[0206] In an exemplary embodiment, the first plate 11 has a potential of the second node N2 in the pixel driving circuit, the second plate 12 has a potential of the first node N1 in the pixel driving circuit, and the first plate 11 and the second plate 12 constitute a storage capacitor of the pixel driving circuit.

[0207] In an exemplary embodiment, the first connection electrode 51 and the first electrode 50 may be an integral structure connected to each other.

[0208] In exemplary embodiments, the first electrode 50 may be an anode of the light emitting device, or the first electrode 50 may be a cathode of the light emitting device.

[0209] In an exemplary embodiment, at least one sub-pixel may include a circuit area and a light-transmitting area, the first transistor T1, the second transistor T2, the third transistor T3 and the storage capacitor may be arranged in the circuit area, the first electrode 50 may be arranged in the light-transmitting area, and the orthographic projection of the first electrode 50 on the substrate does not overlap with the orthographic projection of the second electrode plate 12 on the substrate.

[0210] In an exemplary embodiment, the four first electrodes 50 in one repeating unit may be sequentially arranged along the first direction X, and respectively connected to the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4. In some possible implementations, the arrangement of the anodes may be adjusted according to actual needs, and the present disclosure does not specifically limit this.

[0211] In an exemplary embodiment, the third conductive layer may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0212] In an exemplary embodiment, positions of respective patterns in the third conductive layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0213] (17) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate formed with the aforementioned pattern, patterning the pixel definition film through a patterning process, and forming a pixel definition layer covering the fourth conductive layer, such as Fig.12 shown.

[0214] In an exemplary embodiment, a pixel opening K is opened on the pixel definition layer of each sub-pixel in the repeating unit, the pixel definition film in the pixel opening K is removed to expose the surface of the first electrode 50, and the orthographic projection of the pixel opening K on the substrate is within the range of the orthographic projection of the first electrode 50 on the substrate.

[0215] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the pixel opening K may be similar to that of the first electrode 50 , and in a plane perpendicular to the substrate, the cross-sectional shape of the pixel opening K may be a rectangle or a trapezoid, etc.

[0216] In an exemplary embodiment, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a five-frame shape, a six-frame shape, a circle, and an ellipse.

[0217] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels may be the same or may be different. The areas of the pixel openings of the four sub-pixels may be the same or may be different.

[0218] In an exemplary embodiment, the shapes and areas of the pixel openings of the four sub-pixels may be different to accommodate the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0219] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0220] (18) Forming an organic light emitting layer and a cathode pattern. In an exemplary embodiment, forming an organic light emitting layer and a cathode pattern may include: first forming an organic light emitting layer pattern, wherein the organic light emitting layer is connected to the first electrode 50 through the pixel opening K. Then forming a second electrode, wherein the second electrode is connected to the organic light emitting layer.

[0221] In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or by inkjet process.

[0222] (19) Forming a packaging structure layer pattern. In an exemplary embodiment, forming a packaging structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first packaging layer. Subsequently, an organic material is inkjet printed on the first packaging layer using an inkjet printing process, and after curing into a film, a second packaging layer is formed. Subsequently, a second inorganic thin film is deposited using an open mask to form a third packaging layer, and the first packaging layer, the second packaging layer and the third packaging layer constitute a packaging structure layer. The first packaging layer and the third packaging layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The second packaging layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0223] At this point, a driving circuit layer, a light-emitting structure layer disposed on the driving circuit layer, and an encapsulation structure layer disposed on the light-emitting structure layer are prepared on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a flat layer stacked in sequence on the substrate. The light-emitting structure layer may include at least a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, and the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked.

[0224] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0225] In an exemplary embodiment, the first conductive layer and the second conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo. The third conductive layer may be made of a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO. The first insulating layer, the second insulating layer and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The planar layer may be made of an organic material, such as a resin.

[0226] In an exemplary embodiment, the display substrate of this embodiment may include a color filter structure layer, and the color filter structure layer may be arranged between the third insulating layer and the flat layer. In at least one repeating unit, the color filter structure layer may include a plurality of color filter units, and at least one color filter unit may include a color filter layer, and the color filter layer is configured to make the corresponding sub-pixel emit light of a desired color. In an exemplary embodiment, the preparation process of the display substrate may include: first depositing a third insulating layer on the substrate formed with the aforementioned pattern, then coating a first color filter layer on the third insulating layer, and patterning the first color filter layer using a patterning process to form a first color filter unit. Then coating a second color filter layer, and patterning the second color filter layer using a patterning process to form a second color filter unit. Then coating a third color filter layer, and patterning the third color filter layer using a patterning process to form a third color filter unit. Then coating a flat film, and using a patterning process to form an eleventh via and a twelfth via, the flat layer, the color filter structure layer and the third insulating layer in the via are removed.

[0227] At present, existing display substrates have problems such as complex production processes and high production costs. For example, the preparation process of the driving circuit layer in a display substrate requires 7 patterning (MASK) processes, which not only has low production efficiency and high production costs, but also affects the product yield.

[0228] The disclosed embodiment provides a display substrate with a bottom emission structure, in which structures such as a first power line, a data signal line and a compensation signal line are arranged in a first conductive layer, and the first active layer, the second active layer and the third active layer in the semiconductor layer are respectively connected to the first power line, the data signal line and the compensation signal line through vias, thereby not only reducing the number of conductive layers, but also reducing the patterning process of switching vias and the patterning process of switching conductive layers, so that the preparation process of the driving circuit layer only requires five patterning processes, reducing the number of patterning processes, effectively improving production efficiency, effectively reducing production costs, and maximizing product yield.

[0229] In a display substrate, in order to reduce the number of patterning processes, the gate metal layer and the semiconductor layer are connected by a transfer via structure including a deep half hole and a shallow half hole, and the semiconductor layer needs to be conductorized twice, which not only causes damage to the semiconductor layer, but also complicates the process and reduces the process yield. The display substrate disclosed in the present invention does not need to use a transfer via structure, nor does it need to conduct the semiconductor layer twice, which not only reduces the damage to the semiconductor layer caused by etching, but also reduces the number of vias, reduces the size of the vias, reduces the process complexity, and improves the process yield.

[0230] The display substrate disclosed in the present invention arranges power connection lines on the semiconductor layer. The power connection lines and the first power lines form a mesh structure for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0231] The disclosed display substrate is a 3T1C one gate structure, using a scanning signal line to drive the pixel driving circuit, and the scanning signal line is connected to the first transistor and the third transistor in the pixel driving circuit. By reducing the number of scanning signal lines, not only can the structure of the pixel driving circuit be simplified, the occupied area of ​​the pixel driving circuit be reduced, which is conducive to achieving high-resolution display, but also the light-transmitting area of ​​the light-transmitting area can be effectively increased, and the space ratio of the light-transmitting area can be increased, which is conducive to achieving high-transparency display. In addition, since a repeating unit only needs one scanning signal line to drive, the number of its corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced by multiples, which effectively reduces the occupied area of ​​the gate driving circuit and the clock signal line, which is conducive to achieving a narrow frame and improving product advantages.

[0232] The preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0233] Fig.13 FIG. 1 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in a repeating unit (four sub-pixels) in a bottom emission display substrate. Fig.13 As shown, the main structure of the display substrate of this embodiment is basically the same as that shown in FIG. 5 , except that the storage capacitor of the display substrate of this embodiment is a transparent storage capacitor.

[0234] In an exemplary embodiment, the display substrate of this embodiment may further include a transparent conductive layer disposed between the base and the first conductive layer, the first electrode plate of the storage capacitor may be disposed in the transparent conductive layer, and the second electrode plate may be disposed in the semiconductor layer.

[0235] In an exemplary embodiment, the transparent conductive layer may further include a transparent connecting electrode, and the transparent connecting electrode and the first electrode plate may be an integral structure connected to each other.

[0236] In an exemplary embodiment, the second region of the second active layer is connected to the transparent connection electrode through a via hole.

[0237] In an exemplary embodiment, the preparation process of the display substrate of the exemplary embodiment may include the following operations.

[0238] (21) Forming a transparent conductive layer and a first conductive layer pattern. In an exemplary embodiment, forming the transparent conductive layer and the first conductive layer pattern may include: sequentially depositing a first conductive film and a second conductive film on a substrate, patterning the first conductive film and the second conductive film through a patterning process, and forming the transparent conductive layer and the first conductive layer pattern on the substrate, such as Fig.14 In an exemplary embodiment, the transparent conductive layer may be referred to as a first transparent (1ITO) layer, and the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0239] In an exemplary embodiment, the transparent conductive layer pattern in each sub-pixel in the repeating unit may include at least a first plate 11 of a storage capacitor and a transparent connecting electrode 13 , and the first conductive layer of each sub-pixel in the repeating unit may include at least a shielding electrode 14 .

[0240] In an exemplary embodiment, the shape of the first electrode 11 can be rectangular, the corners of the rectangle can be chamfered, the edges of the rectangle can be fold lines, the first electrode 11 can be set in the middle area of ​​the sub-pixel in the second direction Y, the first electrode 11 can serve as a transparent electrode of a transparent storage capacitor, and the first electrode 11 is configured to form a transparent storage capacitor with a second electrode formed subsequently.

[0241] In an exemplary embodiment, the transparent connecting electrode 13 may be in the shape of a strip having a main portion extending along the second direction Y, and may be disposed on one side of the first electrode plate 11 in the opposite direction of the second direction Y, wherein a first end of the transparent connecting electrode 13 is connected to the first electrode plate 11, and a second end of the transparent connecting electrode 13 extends in a direction away from the first electrode plate 11, and the second end of the transparent connecting electrode 13 is configured to be connected to a second region of a third active layer formed subsequently.

[0242] In an exemplary embodiment, the first electrode plate 11 and the transparent connecting electrode 13 of each sub-pixel may be an integral structure connected to each other.

[0243] In an exemplary embodiment, the shape of the shielding electrode 14 can be a strip shape with the main part extending along the second direction Y, and can be arranged on the side of the first electrode plate 11 in the opposite direction of the second direction Y. The shielding electrode 14 overlaps the extended section of the first electrode plate 11. On the one hand, the shielding electrode 14 is configured to be connected to the second area of ​​the second active layer formed subsequently, and on the other hand, it is configured to shield the second transistor, reduce the intensity of light irradiating the second transistor, reduce the leakage current of the second transistor, and thus reduce the influence of light on the characteristics of the second transistor.

[0244] In an exemplary embodiment, the first conductive layer of the repeating unit may further include two first power lines 21, four data signal lines 22 and one compensation signal line 23, and the shapes and positions of the first power lines 21, the data signal lines 22 and the compensation signal lines 23 are substantially the same as those in the previous embodiment.

[0245] In an exemplary embodiment, patterning the first conductive film and the second conductive film by a patterning process may include: after sequentially depositing the first conductive film and the second conductive film, coating a layer of photoresist on the second conductive film, exposing the photoresist using a half-tone mask, and after development, the photoresist forms a fully exposed area, a partially exposed area, and an unexposed area, the photoresist in the fully exposed area is removed, the fully exposed area exposes the surface of the second conductive film, the photoresist in the partially exposed area is partially removed, the photoresist in the partially exposed area has a first thickness, the photoresist in the unexposed area does not change, the photoresist in the unexposed area has a second thickness, and the first thickness is less than the second thickness. The unexposed area is the area where the shielding electrode 14, the first power line 21, the data signal line 22, and the compensation signal line 23 are located, and the partially exposed area is the area of ​​the first electrode plate 11 and the transparent connecting electrode 13. Subsequently, by a first etching process, the first conductive film and the second conductive film in the fully exposed area are etched away to form patterns of the first power line 21, the data signal line 22, and the compensation signal line 23. Subsequently, the photoresist in the partially exposed area is removed by an ashing process, so that the partially exposed area exposes the surface of the second conductive film, and the unexposed area is still covered with photoresist. Subsequently, the second conductive film in the partially exposed area is etched away by a second etching process to expose the first conductive film, forming the patterns of the first electrode 11, the transparent connecting electrode 13 and the shielding electrode 14. Finally, the remaining photoresist is stripped off.

[0246] In an exemplary embodiment, the shielding electrode 14, the first power line 21, the data signal line 22 and the compensation signal line 23 are all double-layer structures of a first conductive film and a second conductive film, and a first transparent layer is arranged between the shielding metal layer and the substrate. The first transparent layer and the first electrode plate 11 are an integral structure interconnected, thereby achieving electrical connection between the shielding electrode 14 and the first electrode plate 11.

[0247] In an exemplary embodiment, the double-layer structure of the first power line 21 , the data signal line 22 , and the compensation signal line 23 can effectively reduce the resistance of the signal line, lower the voltage drop of the signal, and improve the display performance.

[0248] In an exemplary embodiment, the material of the transparent conductive layer may be a transparent conductive material such as indium tin oxide ITO or indium zinc oxide IZO.

[0249] (22) Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include: depositing a first insulating film on the substrate on which the aforementioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer pattern covering the transparent conductive layer and the first conductive layer, wherein a plurality of via holes are provided on the first insulating layer, such as Fig.15 shown.

[0250] In an exemplary embodiment, the plurality of via holes of each sub-pixel in the repeating unit includes at least a first via hole V1 , a second via hole V2 , and a third via hole V3 .

[0251] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the data signal line 22 on the substrate, the first insulating layer in the first via hole V1 is etched away to expose the surface of the data signal line 22, and the first via hole V1 is configured to connect the first region of the first active layer formed subsequently to the data signal line 22 through the via hole.

[0252] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate at least partially overlaps with the orthographic projection of the blocking electrode 14 on the substrate, the first insulating layer in the second via hole V2 is etched away to expose the surface of the blocking electrode 14, and the second via hole V2 is configured to connect the second region of the second active layer formed subsequently to the first electrode plate 11 through the via hole.

[0253] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate at least partially overlaps with the orthographic projection of the second end of the transparent connecting electrode 13 on the substrate, the first insulating layer in the third via hole V3 is etched away to expose the surface of the second end of the transparent connecting electrode 13, and the third via hole V3 is configured to connect the second area of ​​the subsequently formed third active layer to the second end of the transparent connecting electrode 13 through the via hole.

[0254] In an exemplary embodiment, the first insulating layer in the repeating unit may further include a fourth via hole V4 and a fifth via hole V5 .

[0255] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the first power line 21 on the substrate, the first insulating layer in the fourth via hole V4 is etched away to expose the surface of the first power line 21, and the fourth via hole V4 is configured to connect a subsequently formed power connection line to the first power line 21 through the via hole. In an exemplary embodiment, the fourth via hole V4 may be respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4.

[0256] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate, the first insulating layer in the fifth via hole V5 is etched away to expose the surface of the compensation signal line 23, and the fifth via hole V5 is configured to connect a subsequently formed compensation connection line to the compensation signal line 23 through the via hole. In an exemplary embodiment, the fifth via hole V5 may be disposed between the second sub-pixel P2 and the third sub-pixel P3.

[0257] (23) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process, and forming a semiconductor layer pattern disposed on the first insulating layer, such as Fig.16A and Fig. 16B As shown, Fig. 16B for Fig.16A Schematic diagram of the semiconductor layer in the figure.

[0258] In an exemplary embodiment, the semiconductor layer pattern in each sub-pixel in the repeating unit may include at least a first active layer 31 , a second active layer 32 , a third active layer 33 , a power connection line 34 , a compensation connection line 35 , and a second plate 12 .

[0259] In an exemplary embodiment, the shape of the second electrode plate 12 can be rectangular, and the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as another transparent electrode plate of a transparent storage capacitor, and the first electrode plate 11 and the second electrode plate 12 constitute a transparent storage capacitor of the pixel driving circuit.

[0260] In an exemplary embodiment, in one repeating unit, the overlapping area of ​​the orthographic projection of the second electrode plate 12 on the substrate and the orthographic projection of the first electrode plate 11 on the substrate in each sub-pixel may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0261] In an exemplary embodiment, a plate connection block 12-1 may be provided on the second electrode plate 12. The plate connection block 12-1 may be in a block shape and may be provided on one side of the second electrode plate 12 in the second direction Y. A first end of the plate connection block 12-1 is connected to the second electrode plate 12, and a second end of the plate connection block 12-1 extends in a direction away from the second electrode plate 12. The second end of the plate connection block 12-1 is configured to be connected to a twelfth connection electrode formed subsequently.

[0262] In an exemplary embodiment, the shape of the power connection line 34 can be a straight line or a broken line with the main part extending along the first direction X. The power connection line 34 can be arranged on one side of the second electrode plate 12 in the second direction Y, and the power connection line 34 is connected to the first power line 21 through the fourth via V4.

[0263] In an exemplary embodiment, in one repeating unit, the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate.

[0264] In an exemplary embodiment, the power connection line 34 can be used as a horizontal connection line, and the two first power lines 21 in a repeating unit are both connected to the power connection line 34, so that the power connection line 34 extending along the first direction X and the first power line 21 extending along the second direction Y form a mesh structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0265] In an exemplary embodiment, the shape of the compensation connection line 35 can be a straight line or a broken line with the main part extending along the first direction X. The compensation connection line 35 can be arranged on the side of the second electrode plate 12 in the opposite direction of the second direction Y. The compensation connection line 35 is connected to the compensation signal line 23 through the fifth via V5.

[0266] In an exemplary embodiment, in one repeating unit, the orthographic projection of the compensation connection line 35 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the compensation connection line 35 on the substrate does not overlap with the orthographic projection of the first power line 21 on the substrate.

[0267] In an exemplary embodiment, the first active layer 31 can serve as an active layer of the first transistor T1, the second active layer 32 can serve as an active layer of the second transistor T2, the third active layer 33 can serve as an active layer of the third transistor T3, the first active layer 31 and the third active layer 33 can be disposed between the compensation connection line 35 and the second electrode plate 12, and the second active layer 32 can be disposed between the power connection line 34 and the second electrode plate 12.

[0268] In example embodiments, the first active layer 31 , the second active layer 32 , and the third active layer 33 may each include a channel region and first and second regions located at both sides of the channel region.

[0269] In an exemplary embodiment, the first active layer 31 may be in an "L" shape and may be disposed on one side of the second electrode plate 12 in the opposite direction of the second direction Y. The first region of the first active layer 31 is connected to the data signal line 22 through the first via hole V1, and the second region of the first active layer 31 is connected to the second electrode plate 12, thereby enabling the data signal line 22 to write the data signal into the first electrode of the first transistor T1. In an exemplary embodiment, the first region of the first active layer 31 in each sub-pixel may be connected to one data signal line 22 through the first via hole V1, thereby enabling four data signal lines 22 to write the data signals into the first electrodes of four first transistors T1 in one repeating unit.

[0270] In an exemplary embodiment, in one sub-pixel, the first active layer 31 and the second electrode plate 12 may be an integral structure connected to each other.

[0271] In an exemplary embodiment, the second active layer 32 may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 14 on the substrate. The orthographic projection of the channel region of the second active layer 32 on the substrate may be located within the range of the orthographic projection of the shielding electrode 14 on the substrate, and the shielding electrode 14 may shield the channel region of the second active layer 32 to prevent light from affecting the channel, reduce leakage current, and thereby prevent the influence of light on transistor characteristics, thereby ensuring the electrical performance of the second transistor T2.

[0272] In the exemplary embodiment, the first area of ​​the second active layer 32 is connected to the power connection line 34, and the second area of ​​the second active layer 32 is connected to the shielding electrode 14 through the second via V2. Since the power connection line 34 is connected to the first power line, the first power line 21 writes the first power signal to the first electrode of the second transistor T2. Since the shielding electrode 14 is connected to the first electrode plate 11, the second electrode of the second transistor T2 and the first electrode plate 11 have the same potential.

[0273] In an exemplary embodiment, the two first power lines 21 may include a first first power line and a second first power line, the first first power line may be located on the side of the first pixel column in the opposite direction of the first direction X, and the second first power line may be located on the side of the fourth pixel column in the first direction X. Since the first first power line of the first pixel column can simultaneously provide the first power signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4 through the power connection line 34, and the second first power line of the fourth pixel column can simultaneously provide the first power signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4 through the power connection line 34, the first power lines 21 in one repeating unit are a two-to-four structure. The display substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is conducive to improving the resolution.

[0274] In an exemplary embodiment, two first power lines 21 in a repeating unit are substantially mirror-symmetrical with respect to a vertical reference line, and four second transistors T2 in a repeating unit are substantially mirror-symmetrical with respect to the vertical reference line. This symmetrical structure disclosed in the present invention can ensure that the voltage drop of the first power line written into the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0275] In an exemplary embodiment, in one repeating unit, the power connection line 34 and the second active layers 32 in four sub-pixels may be an integral structure connected to each other.

[0276] In an exemplary embodiment, the third active layer 33 may be in a strip shape extending along the first direction X, the first region of the third active layer 33 is connected to the compensation connection line 35, and the second region of the third active layer 33 is connected to the second end of the transparent connection electrode 13 through the third via hole V3, thereby enabling the compensation signal line 23 to write the compensation signal into the first electrode of the third transistor T3. Since the transparent connection electrode 13 is connected to the first electrode plate 11, the second electrode of the third transistor T3 and the first electrode plate 11 have the same potential.

[0277] In an exemplary embodiment, the compensation signal line 23 may be located between the second pixel column and the third pixel column, and the compensation signal line 23 may provide compensation signals to the pixel driving circuits in the four sub-pixels at the same time through the compensation connection line 35, so that the four pixel driving circuits in one repeating unit may share one compensation signal line 23, that is, the compensation signal line 23 in one repeating unit is a one-to-four structure. The display substrate disclosed herein saves the number of signal lines and reduces the occupied space by designing the compensation signal line as a one-to-four structure, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is conducive to improving the resolution.

[0278] In an exemplary embodiment, the compensation connection line 35 may be mirror-symmetrical with respect to the compensation signal line 23. Such a symmetrical structure of the present disclosure can ensure that the RC delay of the third transistors T3 in the four sub-pixels when the compensation signal is written is substantially the same, thereby ensuring display uniformity.

[0279] In an exemplary embodiment, in one repeating unit, the compensation connection line 35 and the third active layers 33 in four sub-pixels may be an integral structure connected to each other.

[0280] In an exemplary embodiment, the semiconductor layer may use a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0281] (24) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the second conductive film by a patterning process to form a second insulating layer disposed on the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, such as Fig.17A and Fig. 17B As shown, Fig. 17B for Fig.17A Schematic plan view of the first conductive layer in FIG.

[0282] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel in a repeating unit may include at least a scan signal line 40 , a first gate electrode 41 , a second gate electrode 42 , and a third gate electrode 43 .

[0283] In an exemplary embodiment, the shape of the scanning signal line 40 can be a straight line or a broken line with the main part extending along the first direction X. The scanning signal line 40 can be located on the side of the second electrode plate 12 in the opposite direction of the second direction Y. The scanning signal line 40 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0284] In an exemplary embodiment, the first gate electrode 31 may be in the shape of a strip extending along the second direction Y, and may be disposed on a side of the scan signal line 40 close to the first active layer 21, a first end of the first gate electrode 31 is connected to the scan signal line 40, a second end of the first gate electrode 31 extends toward the first active layer 21, and an orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with an orthographic projection of the first active layer 21 on the substrate. In an exemplary embodiment, the first gate electrode 31 may serve as a gate electrode of the first transistor T1, and may control the on or off state of the first transistor T1.

[0285] In an exemplary embodiment, the first gate electrode 31 and the scan signal line 40 may be an integral structure connected to each other.

[0286] In an exemplary embodiment, the third gate electrode 33 may be in a strip shape extending along the second direction Y, and may be disposed on a side of the scan signal line 40 close to the third active layer 23, a first end of the third gate electrode 33 is connected to the scan signal line 40, a second end of the third gate electrode 33 extends toward the third active layer 23, and an orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps an orthographic projection of the third active layer 23 on the substrate. In an exemplary embodiment, the third gate electrode 33 may serve as a gate electrode of the third transistor T3, and may control the on or off state of the third transistor T3.

[0287] In an exemplary embodiment, the third gate electrode 33 and the scan signal line 40 may be an integral structure connected to each other.

[0288] In an exemplary embodiment, in one repeating unit, the scan signal line 40 and the first gate electrode 31 and the third gate electrode 33 in four sub-pixels may be an integral structure connected to each other.

[0289] In an exemplary embodiment, the first gate electrode 31 and the third gate electrode 33 in one sub-pixel are connected to the same scan signal line 40 , and one scan signal line 40 can simultaneously control the turning on or off of the first transistor T1 and the third transistor T3 .

[0290] In an exemplary embodiment, the first gate electrode 31 and the third gate electrode 33 in four sub-pixels in one repeating unit are connected to the same scan signal line 40 , and one scan signal line 40 simultaneously controls the on or off of four first transistors T1 and four third transistors T3 in one repeating unit.

[0291] In an exemplary embodiment, the first gate electrodes 31 and the third gate electrodes 33 in a plurality of sub-pixels in one pixel row are connected to the same scan signal line 40 , and one scan signal line 40 simultaneously controls the on or off of all first transistors T1 and all third transistors T3 in one pixel row.

[0292] In an exemplary embodiment, the second gate electrode 42 may be in an "L" shape, and the second gate electrode 42 may serve as the gate electrode of the second transistor T2. On one hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and on the other hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the electrode plate connecting block 12-1 of the second electrode plate 12 on the substrate.

[0293] In an exemplary embodiment, after the second insulating film and the second conductive film are patterned, the second insulating layer pattern is substantially the same as the first conductive layer pattern, and the second insulating layer is disposed on a side of the first conductive layer close to the substrate.

[0294] In an exemplary embodiment, this process also includes a conductorization treatment. The conductorization treatment is to perform plasma treatment using the first conductive layer as a shield after forming the first conductive layer pattern, and the semiconductor layer shielded by the first conductive layer is used as the channel region of the transistor, and the semiconductor layer not shielded by the first conductive layer is processed into a conductorization layer to form a conductorized second electrode plate and a conductorized source and drain region.

[0295] (25) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: first depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process, forming a third insulating layer covering the first conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, such as Fig.18 shown.

[0296] In an exemplary embodiment, the plurality of via holes in each sub-pixel in the repeating unit includes at least an eleventh via hole V11 and a twelfth via hole V12 .

[0297] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the flat layer and the third insulating layer within the eleventh via hole V11 are etched away to expose the surface of the second region of the second active layer, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0298] In an exemplary embodiment, the twelfth via hole V12 may include two sub-holes, the orthographic projection of one sub-hole on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 42 on the substrate, and exposes the surface of the second gate electrode 42, and the orthographic projection of the other sub-hole on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate, and exposes the surface of the second electrode plate 12. The twelfth via hole V12 is configured to allow the first connection electrode formed subsequently to be connected to the second gate electrode 42 and the second electrode plate 12 at the same time through the via hole.

[0299] In some possible embodiments, the twelfth via V12 can be a via of a transition structure, including two half holes, one half hole exposing the surface of the second gate electrode 42, and the other half hole exposing the surface of the second electrode plate 12, so that the twelfth via V12 of the transition structure composed of the two half holes simultaneously exposes the second gate electrode 42 and the second electrode plate 12.

[0300] In an exemplary embodiment, this process can use a patterning process to form vias on the third insulating layer and the flat layer at the same time. The third insulating layer and the flat layer share a halftone or gray tone mask (MASK) process, which effectively reduces the number of patterning processes.

[0301] (26) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the flat layer, such as Fig.19A and Fig.19B As shown, Fig.19B for Fig.19A In an exemplary embodiment, the third conductive layer may be referred to as a second transparent (2ITO) layer.

[0302] In an exemplary embodiment, the third conductive layer of each sub-pixel in the repeating unit may include at least the first connection electrode 51 , the second connection electrode 52 , and the first electrode 50 .

[0303] In an exemplary embodiment, the first connection electrode 51 may be shaped like a strip having a main portion extending along the second direction Y, a first end of the first connection electrode 51 being connected to the second region of the second active layer through the eleventh via hole V11, and a second end of the first connection electrode 51 being connected to the first electrode 50.

[0304] In an exemplary embodiment, the second connection electrode 52 may be in a block shape (e.g., a rectangle), and the second connection electrode 52 is connected to the second gate electrode 42 and the plate connection block 12-1 through the twelfth via hole V12. In an exemplary embodiment, since the plate connection block 12-1 is connected to the second plate 12, and the second plate 12 is connected to the second region of the first active layer, the second connection electrode 52 enables the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 12 of the storage capacitor to have the same potential, thereby forming a first node N1 in the pixel driving circuit.

[0305] In an exemplary embodiment, the shape of the first electrode 50 may be rectangular, and the corners of the rectangle may be provided with chamfers, grooves or protrusions, and one side of the first electrode 50 is connected to the second end of the first connection electrode 51. Since the second region of the second active layer is connected to the shielding electrode 14 through a via hole, the shielding electrode 14 is connected to the first electrode plate 11, and the second region of the third active layer is connected to the transparent connection electrode 13 through a via hole, and the transparent connection electrode 13 is connected to the first electrode plate 11, the first connection electrode 51 enables the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential, forming a second node N2 in the pixel driving circuit.

[0306] In an exemplary embodiment, the first plate 11 has a potential of the second node N2 in the pixel driving circuit, the second plate 12 has a potential of the first node N1 in the pixel driving circuit, and the first plate 11 and the second plate 12 constitute a storage capacitor of the pixel driving circuit.

[0307] In an exemplary embodiment, the first connection electrode 51 and the first electrode 50 may be an integral structure connected to each other.

[0308] In exemplary embodiments, the first electrode 50 may be an anode of the light emitting device, or the first electrode 50 may be a cathode of the light emitting device.

[0309] In an exemplary embodiment, the first electrode 50 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 50 is connected to the first connection electrode 51, the first connection electrode 51 has the potential of the second node N2 in the pixel driving circuit, so that the first electrode 50 having the potential of the second node N2 and the second electrode plate 12 having the potential of the first node N1 form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure uses the first electrode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. On the one hand, the capacitance value of the storage capacitor can be effectively increased, and on the other hand, the plate area can be reduced while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0310] In an exemplary embodiment, the four first electrodes 50 in one repeating unit may be sequentially arranged along the first direction X, and respectively connected to the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4. In some possible implementations, the arrangement of the anodes may be adjusted according to actual needs, and the present disclosure does not specifically limit this.

[0311] In an exemplary embodiment, the third conductive layer may be made of a transparent conductive material such as indium tin oxide ITO or indium zinc oxide IZO.

[0312] (27) The pixel definition layer, the organic light-emitting layer, the cathode and the encapsulation structure layer patterns are formed. The preparation process is basically the same as that of the above-mentioned embodiment and will not be repeated here.

[0313] At this point, a driving circuit layer, a light-emitting structure layer disposed on the driving circuit layer, and an encapsulation structure layer disposed on the light-emitting structure layer are prepared on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a flat layer stacked in sequence on the substrate. The light-emitting structure layer may include at least a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, and the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked.

[0314] In an exemplary embodiment, the display substrate of this embodiment may include a color filter structure layer, and the color filter structure layer may be disposed between the third insulating layer and the planar layer, which will not be described in detail herein.

[0315] The display substrate of the embodiment of the present disclosure can not only achieve the technical effect of the display substrate shown in Figure 5, but also through the transparent storage capacitor composed of a transparent conductive layer and a transparent semiconductor layer, light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be set in the pixel opening, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel opening ratio.

[0316] Fig. 20 FIG. 5 is a schematic diagram of the structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in a repeating unit (four sub-pixels) in a bottom emission display substrate. The main structure of the display substrate of this embodiment is substantially the same as that shown in FIG. 5 , except that the display substrate of this embodiment adopts a first power line structure of a non-mesh structure, and two adjacent first power lines 21 in the first direction X are connected to different power connection lines 34.

[0317] The structures of the first electrode plate 11, the second electrode plate 12, the first power line 21, the data signal line 22, the compensation signal line 23, the compensation connection line 35, the first transistor T1, the second transistor T2, the third transistor T3 and the first anode 60 of the display substrate of this embodiment are basically the same as those shown in Figure 5 and are not repeated here.

[0318] like Fig. 20 As shown, the shape of the two power connection lines 34 in this embodiment can be a straight line or a broken line with the main part extending along the first direction X. The first power connection line 34 can be arranged in the first pixel column and the second pixel column, one end of the first power connection line 34 is connected to the first first power line 21 through the fourth via hole V4, and the other end of the first power connection line 34 is respectively connected to the first area of ​​the second active layer 32 in the first pixel column and the second pixel column. The second power connection line 34 can be arranged in the third pixel column and the fourth pixel column, one end of the second power connection line 34 is connected to the second first power line 21 through the fourth via hole V4, and the other end of the second power connection line 34 is respectively connected to the first area of ​​the second active layer 32 in the third pixel column and the fourth pixel column.

[0319] In an exemplary embodiment, in one repeating unit, the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the power connection line 34 on the substrate does not overlap with the orthographic projection of the compensation signal line 23 on the substrate.

[0320] In an exemplary embodiment, the first first power line of the first pixel column can provide the first power signal to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2 simultaneously through the power connection line 34, and the second first power line of the fourth pixel column can provide the first power signal to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4 simultaneously through the power connection line 34, so that the first power line 21 in a repeating unit is a one-to-two structure. The display substrate of the present disclosure saves the number of signal lines and reduces the occupied space by designing the first power line as a one-to-two structure, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is conducive to improving the resolution.

[0321] The display substrate of the embodiment of the present disclosure can not only achieve the technical effect of the display substrate shown in FIG. 5 , but also effectively increase the pixel aperture ratio and improve the display effect by adopting a first power line structure with a non-mesh structure, making it more suitable for display types.

[0322] The structure and preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0323] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0324] The exemplary embodiment of the present disclosure also provides a method for preparing a display substrate to prepare the display substrate of the aforementioned embodiment. In the exemplary embodiment, the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit includes at least a storage capacitor and a first transistor, the storage capacitor includes at least a first electrode plate and a second electrode plate, and the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane; the preparation method may include:

[0325] forming a first conductive layer on a substrate, wherein the first conductive layer at least includes the data signal line;

[0326] A semiconductor layer is formed on the first conductive layer, wherein the semiconductor layer at least includes the second electrode and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

[0327] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0328] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The device comprises a plurality of repeating units, at least one of which comprises a plurality of sub-pixels, at least one of which comprises a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit comprises at least a storage capacitor and a first transistor, the storage capacitor comprises at least a first electrode plate and a second electrode plate, and an orthographic projection of the first electrode plate on a display substrate plane at least partially overlaps with an orthographic projection of the second electrode plate on the display substrate plane; In a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer disposed on a base and a semiconductor layer disposed on a side of the first conductive layer away from the base, the first conductive layer at least comprises the data signal line, and the semiconductor layer at least comprises the second electrode plate and a first active layer of the first transistor; In at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

2. The display substrate according to claim 1, characterized in that: In at least one sub-pixel, the first active layer and the second electrode plate are interconnected as an integral structure.

3. The display substrate according to claim 1, characterized in that: The pixel driving circuit also includes a second transistor, which is connected to the first power line through a power connection line; the first conductive layer also includes the first power line, and the semiconductor layer also includes the power connection line and a second active layer of the second transistor; in at least one sub-pixel, the second active layer is connected to the power connection line, and the power connection line is connected to the first power line through a via.

4. The display substrate according to claim 3, characterized in that: In at least one sub-pixel, the second active layer and the power connection line are interconnected as an integrated structure.

5. The display substrate according to claim 3, characterized in that: The shape of the first power line is a straight line or a broken line extending along the second direction, and the shape of the power connection line is a straight line or a broken line extending along the first direction, and the first direction and the second direction intersect; two adjacent first power lines in the first direction are connected to the same power connection line to form a mesh structure.

6. The display substrate according to claim 3, characterized in that: The shape of the first power line is a straight line or a broken line extending along the second direction, the shape of the power connection line is a straight line or a broken line extending along the first direction, the first direction and the second direction intersect; two adjacent first power lines in the first direction are connected to different power connection lines.

7. The display substrate according to claim 3, characterized in that: The display substrate further includes a second conductive layer disposed on a side of the semiconductor layer away from the base, the second conductive layer at least includes a second gate electrode of the second transistor, and the second gate electrode is connected to the second electrode plate via a gate connecting electrode.

8. The display substrate according to claim 7, characterized in that: The display substrate also includes a third conductive layer arranged on a side of the second conductive layer away from the base, and the third conductive layer at least includes the gate connecting electrode; the gate connecting electrode is respectively connected to the second gate electrode and the second electrode plate through the same via hole, or the gate connecting electrode is connected to the second gate electrode through one via hole and connected to the second electrode plate through another via hole.

9. The display substrate according to claim 8, characterized in that: The third conductive layer further includes a first electrode and an active connection electrode. The first electrode and the active connection electrode are an integrated structure connected to each other. The active connection electrode is connected to the second active layer through an active via.

10. The display substrate according to claim 9, characterized in that: The second active layer is connected to the first electrode plate through a plate-level via, or the second active layer is connected to a transparent connecting electrode through a plate-level via, and the transparent connecting electrode and the first electrode plate are an integrated structure connected to each other.

11. The display substrate according to claim 10, characterized in that: In at least one sub-pixel, an orthographic projection of the active via on the substrate at least partially overlaps with an orthographic projection of the board-level via on the substrate.

12. The display substrate according to claim 1, characterized in that: The pixel driving circuit further includes a third transistor, which includes at least a third active layer. The first conductive layer further includes a compensation signal line, which is connected to the third active layer of multiple sub-pixels in the repeating unit through the semiconductor layer.

13. The display substrate according to claim 12, characterized in that: The semiconductor layer further includes a compensation connection line, the compensation signal line is connected to the compensation connection line through a via hole, and the compensation connection line is connected to the third active layer of a plurality of sub-pixels in a repeating unit.

14. The display substrate according to claim 13, characterized in that: In at least one repeating unit, the compensation connection line and the third active layers of a plurality of sub-pixels are interconnected as an integral structure.

15. The display substrate according to claim 12, characterized in that: In at least one repeating unit, the compensation signal line is in a straight line or a broken line shape extending along the second direction, and the compensation signal line is arranged in the middle position of the repeating unit in the first direction, and the first direction intersects with the second direction.

16. The display substrate according to claim 15, characterized in that: In at least one repeating unit, a plurality of sub-pixels include at least a red sub-pixel, a white sub-pixel, a green sub-pixel and a blue sub-pixel arranged in sequence along the first direction, the red sub-pixel includes a red data signal line, the green sub-pixel includes a green data signal line, the blue sub-pixel includes a blue data signal line, the red data signal line is arranged on one side of the compensation signal line in the first direction, and the green data signal line and the blue data signal line are arranged on the other side of the compensation signal line in the first direction.

17. The display substrate according to claim 16, characterized in that: In at least one repeating unit, a first gap is arranged between the pixel driving circuit of the red sub-pixel and the pixel driving circuit of the white sub-pixel, a second gap is arranged between the pixel driving circuit of the green sub-pixel and the pixel driving circuit of the blue sub-pixel, the red data signal line is arranged in the first gap, and the green data signal line and the blue data signal line are arranged in the second gap.

18. The display substrate according to any one of claims 1 to 17, characterized in that: The first electrode plate is disposed in the first conductive layer.

19. The display substrate according to any one of claims 1 to 17, characterized in that: The display substrate further includes a transparent conductive layer disposed between the base and the first conductive layer, and the first electrode plate is disposed in the transparent conductive layer.

20. A display device, characterized in that: Comprising the display substrate as claimed in any one of claims 1 to 19.

21. A method for preparing a display substrate, characterized in that: The display substrate comprises a plurality of repeating units, at least one of the repeating units comprises a plurality of sub-pixels, at least one of the sub-pixels comprises a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit comprises at least a storage capacitor and a first transistor, the storage capacitor comprises at least a first electrode plate and a second electrode plate, and an orthographic projection of the first electrode plate on a plane of the display substrate at least partially overlaps with an orthographic projection of the second electrode plate on a plane of the display substrate; the preparation method comprises: forming a first conductive layer on a substrate, wherein the first conductive layer at least includes the data signal line; A semiconductor layer is formed on the first conductive layer, wherein the semiconductor layer at least includes the second electrode and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

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