Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate, a pixel driving circuit, a conductive structure and a fixed voltage signal line, the pixel driving circuit, the conductive structure and the fixed voltage signal line are located on one side of the substrate, the pixel driving circuit comprises a driving transistor and a voltage adjusting transistor, and the driving transistor is connected between a first power signal line and a light-emitting element in series; the voltage regulation transistor is electrically connected with the grid electrode of the driving transistor, the conductive structure and the active layer of the voltage regulation transistor are at least partially overlapped in the direction perpendicular to the plane where the substrate is located, and the conductive structure is electrically connected with the fixed voltage signal line. According to the display panel and the display device provided by the embodiment of the invention, the leakage current of the voltage regulation transistor is reduced, the stability of the voltage of the grid electrode of the driving transistor is improved, the stability of the light emitting brightness of the light emitting element is ensured, and the screen shaking phenomenon of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display panels have the advantages of high visibility, high brightness, and being lighter and thinner. Therefore, the application of OLED display panels is becoming more and more widespread.

[0003] However, the current OLED display panels have the problem of screen jitter. Summary of the invention

[0004] The present invention provides a display panel and a display device to solve the problem of screen shaking.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising a base substrate and a pixel driving circuit, a conductive structure and a fixed voltage signal line located on one side of the base substrate;

[0006] The pixel driving circuit comprises a driving transistor and a voltage regulating transistor, wherein the driving transistor is connected in series between the first power signal line and the light emitting element;

[0007] The voltage regulating transistor is electrically connected to the gate of the driving transistor;

[0008] Along a direction perpendicular to the plane of the substrate, the conductive structure and the active layer of the voltage regulating transistor at least partially overlap;

[0009] The conductive structure is electrically connected to the fixed voltage signal line.

[0010] According to another aspect of the present invention, a display device is provided, comprising the display panel according to the first aspect.

[0011] The display panel and display device provided by the embodiments of the present invention are provided with an overlap between a conductive structure and an active layer of a voltage regulating transistor, and a coupling capacitor is formed between the conductive structure and the active layer of the voltage regulating transistor to stabilize the voltage of the active layer and the gate of the voltage regulating transistor, reduce the leakage current of the voltage regulating transistor, and further stabilize the voltage of the gate of the driving transistor, and reduce the voltage fluctuation of the gate of the driving transistor; at the same time, the conductive structure and the fixed voltage signal line are electrically connected to apply a constant voltage to the conductive structure through the fixed voltage signal line, so that the conductive structure shields the active layer of the voltage regulating transistor, reduces the interference of the signals transmitted on each signal line in the display panel to the voltage regulating transistor, and keeps the conductive structure at a stable potential, so that through the effect of the coupling capacitor, the leakage current of the voltage regulating transistor is further reduced, the voltage fluctuation of the gate of the driving transistor is reduced, the stability of the voltage of the gate of the driving transistor is improved, the stability of the luminous brightness of the light-emitting element is ensured, and the screen shaking phenomenon of the display panel is improved.

[0012] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the A-A' direction;

[0016] Figure 3 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 4 A schematic diagram of a film layer structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention;

[0018] Figure 5 for Figure 4 A schematic structural diagram of a semiconductor layer in a pixel driving circuit shown;

[0019] Figure 6 for Figure 4A schematic structural diagram of a first metal layer in a pixel driving circuit shown;

[0020] Figure 7 for Figure 4 A schematic structural diagram of a second metal layer in a pixel driving circuit shown;

[0021] Figure 8 for Figure 4 A schematic structural diagram of a third metal layer in a pixel driving circuit shown;

[0022] Fig. 9 for Figure 4 A schematic structural diagram of a conductive structure in a pixel driving circuit shown;

[0023] Fig.10 for Figure 4 A schematic diagram of a laminated structure of a partial film layer in a pixel driving circuit shown;

[0024] Fig.11 for Figure 4 A schematic diagram of another partial film layer stacking structure in a pixel driving circuit shown;

[0025] Fig.12 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in a pixel driving circuit shown;

[0026] Fig.13 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in a pixel driving circuit shown;

[0027] Fig.14 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in a pixel driving circuit shown;

[0028] Fig.15 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in a pixel driving circuit shown;

[0029] Fig.16 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in a pixel driving circuit shown;

[0030] Fig.17 A schematic diagram of a laminated structure of a film layer of a pixel driving circuit provided by an embodiment of the present invention;

[0031] Fig.18 A schematic diagram of a partial cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0032] Fig.19A schematic diagram of a partial cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0033] Fig. 20 A schematic diagram of a laminated structure of a film layer of another pixel driving circuit provided by an embodiment of the present invention;

[0034] Fig.21 for Fig. 20 A schematic diagram of a laminated structure of a partial film layer in a pixel driving circuit shown;

[0035] Fig. 22 A schematic diagram of a laminated structure of a film layer of another pixel driving circuit provided by an embodiment of the present invention;

[0036] Fig.23 A schematic diagram of a laminated structure of a film layer of another pixel driving circuit provided by an embodiment of the present invention;

[0037] Fig.24 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the A-A' direction, Figure 3 A schematic diagram of a pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 1-Figure 3 As shown, the display panel provided by the embodiment of the present invention includes a base substrate 10 and a pixel driving circuit 20, a conductive structure 21 and a fixed voltage signal line 22 located on one side of the base substrate 10. The pixel driving circuit 20 includes a driving transistor T3 and a voltage regulating transistor 30. The driving transistor T3 is connected in series between the first power signal line PVDD and the light-emitting element 23. The voltage regulating transistor 30 is electrically connected to the gate G3 of the driving transistor T3. In a direction perpendicular to the plane where the base substrate 10 is located, the conductive structure 21 and the active layer 301 of the voltage regulating transistor 30 at least partially overlap. The conductive structure 21 is electrically connected to the fixed voltage signal line 22.

[0041] Specifically, the display panel provided in this embodiment may be an organic light emitting diode (OLED) display panel, but is not limited thereto.

[0042] Among them, Figure 1-Figure 3 As shown, the display panel includes a display area AA and a peripheral area NAA located at least on one side of the display area AA. A plurality of array-arranged sub-pixels PX are arranged in the display area AA, and the plurality of sub-pixels PX are arranged on the same side of the base substrate 10. Figure 1 In the above description, only a plurality of sub-pixels PX are arranged in a standard RGB manner on the display panel. In other embodiments, the plurality of sub-pixels PX may be arranged in other manners. In addition, the shape of the light emitting area of ​​the sub-pixel PX includes but is not limited to: Figure 1 In other embodiments, the shape of the light emitting area of ​​the sub-pixel PX may also be designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0043] Furthermore, the sub-pixel PX includes a pixel driving circuit 20 and a light emitting element 23, such as Figure 2 As shown, the light emitting element 23 is an organic light emitting diode for example. The light emitting element 23 may include a stacked anode 231, a light emitting layer 232 and a cathode 233. When electrons and holes are injected from the cathode 233 and the anode 231 into the light emitting layer 232, excitons are formed in the light emitting layer 232 to excite the light emitting molecules, so that the light emitting layer 232 emits visible light. By setting the light emitting layer 232 to have different materials, different colors of visible light can be emitted.

[0044] It should be noted that the light emitting element 23 is not limited to an organic light emitting diode. In other embodiments, the light emitting element 23 may also be other types of light emitting devices, which is not specifically limited in the embodiment of the present invention.

[0045] Continue to refer Figure 2Optionally, the light-emitting layers 232 of each light-emitting element 23 are separated by a pixel definition layer 11, wherein the pixel definition layer 11 includes a plurality of openings, at least part of the light-emitting layer 232 is located in the opening, and the area where the opening of the pixel definition layer 11 is located is the light-emitting area of ​​the sub-pixel PX.

[0046] Further, the light emitting element 23 may include at least two light emitting elements of different colors. For example, the light emitting element 23 may include a red light emitting element, a green light emitting element and a blue light emitting element, so that the sub-pixel PX may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, thereby realizing color image display.

[0047] Continue to refer Figure 2 and Figure 3 The pixel driving circuit 20 is electrically connected to the light-emitting element 23. The pixel driving circuit 20 is used to transmit the driving current to the light-emitting element 23 under the action of the signal of the driving signal line (such as a scanning signal line, a data signal line, a power signal line and a reference signal line, etc.) on the display panel, thereby providing the driving current for the light-emitting element 23 to drive the light-emitting element 23 to emit light.

[0048] The pixel driving circuit 20 may include at least one thin film transistor T, and the thin film transistor T may include an active layer 1 , a gate 2 , and a source-drain electrode 3 stacked on one side of the base substrate 10 .

[0049] Specifically, Figure 3 As shown, the pixel driving circuit 20 includes a driving transistor T3, and the driving transistor T3 and the light-emitting element 23 are connected in series between a first power signal line PVDD and a second power signal line PVEE. The first power signal line PVDD is used to transmit a first power signal, and the second power signal line PVEE is used to transmit a second power signal, and the voltage of the first power signal is greater than the voltage of the second power signal.

[0050] The driving transistor T3 can be turned on according to the voltage of its gate, and the driving current formed by the turning on of the driving transistor T3 is used to drive the light-emitting element 23 to emit light. It can be understood that the driving transistor T3 is used as a driving tube, and its gate voltage will determine the size of the driving current formed by the turning on of the driving transistor T3, so that the light-emitting brightness of the light-emitting element 23 can be adjusted by controlling the gate voltage of the driving transistor T3, thereby controlling the grayscale.

[0051] Furthermore, if Figure 2 and Figure 3As shown, in addition to the driving transistor T3, the pixel driving circuit 20 also includes a voltage regulating transistor 30, and the voltage regulating transistor 30 is electrically connected to the gate G3 of the driving transistor T3. When the voltage regulating transistor 30 is turned on, a specific voltage signal can be allowed to be written into the gate G3 of the driving transistor T3 to change the voltage of the gate G3 of the driving transistor T3, which is beneficial to improving the driving performance of the pixel driving circuit 20 and improving the display effect.

[0052] For example, Figure 3 Taking the pixel driving circuit 20 shown in the figure as an example, the pixel driving circuit 20 may include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a first reset transistor T5, a second light emitting control transistor T6, a second reset transistor T7 and a storage capacitor Cst.

[0053] The data writing transistor T2 is connected in series between the second end (ie, the N2 node) of the driving transistor T3 and the data signal line data, and the gate of the data writing transistor T2 is electrically connected to the data scanning signal line ScanP.

[0054] The compensation transistor T4 is connected in series between the gate G3 of the driving transistor T3 and the first end (ie, the N3 node), and the gate of the compensation transistor T4 is electrically connected to the second scanning signal line Scan2.

[0055] The reset transistor T5 is connected in series between the gate G3 of the driving transistor T3 and the first reset signal line vref, and the gate of the first reset transistor T5 is electrically connected to the first scan signal line Scan1.

[0056] The first light emission control transistor T1 is connected between the second end (ie, the N2 node) of the driving transistor T3 and the first power signal line PVDD, and a gate of the first light emission control transistor T1 is electrically connected to the light emission control signal line EMIT.

[0057] The second light emission control transistor T6 is connected between the first end (ie, the N3 node) of the driving transistor T3 and the light emitting element 23 , and the gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line EMIT.

[0058] The second reset transistor T7 is connected in series between the first reset signal line vref and the anode of the light emitting element 23, and the gate of the second reset transistor T7 is electrically connected to the data scanning signal line ScanP.

[0059] The first plate C11 of the storage capacitor Cst is electrically connected to the gate G3 of the driving transistor T3 , and the second plate C12 of the storage capacitor Cst is electrically connected to the first power signal line PVDD . The storage capacitor Cst can ensure the voltage stability of the gate G3 of the driving transistor T3 .

[0060] Optionally, the working process of the pixel driving circuit 20 may include but is not limited to the following stages:

[0061] Initialization stage: the first scanning signal provided by the first scanning signal line Scan1 is a valid signal to control the conduction of the reset transistor T5. The first reset signal provided by the first reset signal line vref is transmitted to the gate G3 of the driving transistor T3 through the reset transistor T5, thereby resetting the gate G3 of the driving transistor T3. At this time, the gate G3 voltage of the driving transistor T3 is consistent with the voltage of the first reset signal to avoid the data signal of the previous frame carried on the gate G3 of the driving transistor T3 affecting the writing of the data signal of the next frame.

[0062] Data writing stage: the data scanning signal provided by the data scanning signal line ScanP is a valid pulse, and the second scanning signal provided by the second scanning signal line Scan2 is a valid pulse to control the data writing transistor T2 and the compensation transistor T4 to be turned on. At the same time, the gate G3 voltage of the driving transistor T3 is consistent with the voltage of the first reset signal, and the driving transistor T3 is also turned on. The data signal provided by the data signal line data passes through the data writing transistor T2, the driving transistor T3 and the compensation transistor T4, and is applied to the gate G3 of the driving transistor T3. The potential of the gate G3 of the driving transistor T3 is gradually increased until the driving transistor T3 is turned off. When the driving transistor T3 is turned off, the potential of the gate G3 of the driving transistor T3 is Vdata-|Vth|, where Vdata is the voltage of the data signal and |Vth| is the threshold voltage of the driving transistor T3.

[0063] Optionally, in the data writing stage, the data scanning signal transmitted by the data scanning signal line ScanP is a valid pulse to control the conduction of the second reset transistor T7, and the first reset signal transmitted by the first reset signal line vref is transmitted to the anode of the light-emitting element 23 via the second reset transistor T7 to initialize the anode of the light-emitting element 23 to prevent the driving current provided to the anode of the light-emitting element 23 in the previous frame from affecting the luminous brightness of the light-emitting element 23 in the next frame.

[0064] Light-emitting stage: the light-emitting control signal provided by the light-emitting control signal line EMIT is a valid pulse to control the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to be turned on, and the first power signal provided by the first power signal line PVDD is transmitted to the second end (i.e., the N2 node) of the driving transistor T3, then the voltage difference between the second end (i.e., the N2 node) of the driving transistor T3 and its gate G3 is Vpvdd-(Vdata-|Vth|), so that the driving current generated by the driving transistor T3 is K*(Vdata-Vpvdd) 2, where K is a coefficient related to the size and material of the driving transistor T3, and Vpvdd is the voltage of the first power signal provided by the first power signal line PVDD. In this way, the driving current generated by the driving transistor T3 is independent of its own threshold voltage |Vth|, and the driving current is transmitted to the anode of the light-emitting element 23 through the turned-on second light-emitting control transistor T6 to drive the light-emitting element 23 to emit light.

[0065] It should be noted that Figure 3 The structure of the pixel driving circuit 20 is only provided as an example, but not all. Those skilled in the art may set the structure of the pixel driving circuit 20 according to actual needs. For example, the pixel driving circuit 20 may be a 1T1C circuit, a 2T1C circuit, a 7T1C circuit, an 8T1C circuit or other types of pixel circuits known to those skilled in the art, and the embodiments of the present invention are not limited to this.

[0066] Furthermore, the inventor has found through research that as the resolution of the display panel continues to increase, the pixel density also increases accordingly, making the distribution of the pixel driving circuit 20 more compact. In the design of the high-density pixel driving circuit 20, the number of driving signal lines (such as scanning signal lines, data signal lines, power signal lines, and reference signal lines, etc.) on the display panel increases, and more space is required. The dense wiring and limited space will make it difficult to effectively block the active layer 301 of the voltage regulating transistor 30. Among them, the active layer 301 of the voltage regulating transistor 30 is usually made of semiconductor materials, which will generate additional carriers under light irradiation to form a photogenerated leakage current. Since the voltage regulating transistor 30 is electrically connected to the gate G3 of the driving transistor T3, the leakage current will affect the voltage of the gate G3 of the driving transistor T3, making the voltage of the gate G3 of the driving transistor T3 unstable. Especially in the low-frequency working mode, due to the long frame period, the photogenerated leakage current will accumulate over a long period of time, thereby having a greater impact on the voltage of the gate G3 of the driving transistor T3. As mentioned above, the driving transistor T3 is used as a driving tube, and its gate voltage will determine the size of the driving current formed by its conduction, which will affect the brightness of the light-emitting element 23. Therefore, if the voltage of the gate G3 of the driving transistor T3 is unstable, the brightness of the light-emitting element 23 will be unstable, causing the display panel to experience screen jitter.

[0067] Based on the above technical issues, such as Figure 2As shown, in the present embodiment, a conductive structure 21 is provided, and there is an overlap between the conductive structure 21 and the active layer 301 of the voltage regulating transistor 30 along a direction perpendicular to the plane where the substrate 10 is located, and a coupling capacitor can be formed between the conductive structure 21 and the active layer 301 of the voltage regulating transistor 30, and the coupling capacitor can stabilize the voltage of the active layer 301 and the gate of the voltage regulating transistor 30 to a certain extent, reduce the leakage current of the voltage regulating transistor 30, and further stabilize the voltage of the gate G3 of the driving transistor T3, reduce the voltage fluctuation of the gate G3 of the driving transistor T3, improve the stability of the voltage of the gate G3 of the driving transistor T3, improve the stability of the luminous brightness of the light-emitting element 23, and improve the screen shaking phenomenon of the display panel.

[0068] Furthermore, if Figure 2 and Figure 3 As shown, the display panel further includes a fixed voltage signal line 22, and the fixed voltage signal line 22 is used to transmit a fixed voltage signal, wherein the voltage of the fixed voltage signal is a constant voltage.

[0069] In this embodiment, the conductive structure 21 is electrically connected to the fixed voltage signal line 22 so that a constant voltage is applied to the conductive structure 21 through the fixed voltage signal line 22, so that the conductive structure 21 can shield the active layer 301 of the voltage regulating transistor 30, thereby helping to reduce the interference of signals transmitted on each signal line in the display panel to the voltage regulating transistor 30; at the same time, by applying a constant voltage to the conductive structure 21 through the fixed voltage signal line 22, the conductive structure 21 can be kept at a stable potential. The constant voltage, as a potential reference, helps to reduce the leakage current of the voltage regulating transistor 30 through the action of the coupling capacitor, thereby reducing the voltage fluctuation of the gate G3 of the driving transistor T3, and further improving the stability of the voltage of the gate G3 of the driving transistor T3, ensuring the stability of the luminous brightness of the light-emitting element 23, and improving the screen jitter phenomenon of the display panel.

[0070] In summary, the display panel provided by the embodiment of the present invention is provided with an overlap between the conductive structure and the active layer of the voltage regulating transistor, and a coupling capacitor is formed between the conductive structure and the active layer of the voltage regulating transistor to stabilize the voltage of the active layer and the gate of the voltage regulating transistor, reduce the leakage current of the voltage regulating transistor, and further stabilize the voltage of the gate of the driving transistor, and reduce the voltage fluctuation of the gate of the driving transistor; at the same time, the conductive structure and the fixed voltage signal line are electrically connected to apply a constant voltage to the conductive structure through the fixed voltage signal line, so that the conductive structure shields the active layer of the voltage regulating transistor, reduces the interference of the signals transmitted on the signal lines in the display panel to the voltage regulating transistor, and keeps the conductive structure at a stable potential, thereby further reducing the leakage current of the voltage regulating transistor through the effect of the coupling capacitor, reducing the voltage fluctuation of the gate of the driving transistor, improving the stability of the voltage of the gate of the driving transistor, ensuring the stability of the luminous brightness of the light-emitting element, and improving the screen jitter phenomenon of the display panel.

[0071] Continue to refer Figure 2 and Figure 3 Optionally, the pixel driving circuit 20 includes a first reset transistor T5, the fixed voltage signal line 22 includes a first reset signal line vref, and the first reset transistor T5 is connected in series between the gate of the driving transistor T3 and the first reset signal line vref.

[0072] The connection relationship and function between the first reset transistor T5 and the first reset signal line vref may refer to the above embodiment and will not be described in detail here.

[0073] In this embodiment, the voltage of the first reset signal provided by the first reset signal line vref is a constant voltage. Figure 2 and Figure 3 As shown, the first reset signal line vref is set to a fixed voltage signal line 22, that is, the conductive structure 21 and the first reset signal line vref are electrically connected to apply a constant voltage to the conductive structure 21 through the first reset signal line vref. In this way, the existing signal line resources of the display panel can be fully utilized without setting up new signal lines. This can simplify circuit design, reduce wiring complexity, save space, and reduce manufacturing costs.

[0074] Continue to refer Figure 3 Optionally, the fixed voltage signal line 22 includes a first power signal line PVDD.

[0075] The first power signal transmitted on the first power signal line PVDD is a direct current signal, not an alternating current (AC) signal. Therefore, the first power signal line PVDD can also provide a constant voltage for the conductive structure 21 .

[0076] In this embodiment, if Figure 3 As shown, the first power signal line PVDD is set as a fixed voltage signal line 22, that is, the conductive structure 21 and the first power signal line PVDD are electrically connected to apply a constant voltage to the conductive structure 21 through the first power signal line PVDD. In this way, the existing signal line resources of the display panel can be fully utilized without setting up new signal lines. This can simplify circuit design, reduce wiring complexity, save space, and reduce manufacturing costs.

[0077] Figure 4 A schematic diagram of a film layer structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention; Figure 5 for Figure 4 A schematic structural diagram of a first metal layer in a pixel driving circuit shown;

[0078] Figure 6 for Figure 4 A schematic structural diagram of a first metal layer in a pixel driving circuit shown; Figure 7 for Figure 4 A schematic structural diagram of a second metal layer in a pixel driving circuit shown; Figure 8 for Figure 4 A schematic structural diagram of a third metal layer in a pixel driving circuit shown; Fig. 9 for Figure 4 A schematic structural diagram of a conductive structure in a pixel driving circuit shown; Fig.10 for Figure 4 A schematic diagram of a laminated structure of a portion of film layers in the pixel driving circuit shown, specifically a schematic diagram of a laminated structure of a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a conductive structure; Fig.11 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in the pixel driving circuit shown, specifically a schematic diagram of a stacked structure of a semiconductor layer and a first metal layer; Fig.12 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in the pixel driving circuit shown, specifically a schematic diagram of a stacked structure of a semiconductor layer, a first metal layer and a conductive structure; Fig.13 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in the pixel driving circuit shown, specifically a schematic diagram of a stacked structure of a second metal layer and a conductive structure, wherein a punched connection position between the second metal layer and the conductive structure is shown; Fig.14 for Figure 4 A schematic diagram of a stacked structure of another partial film layer in the pixel driving circuit shown, specifically a schematic diagram of a stacked structure of a semiconductor layer and a third metal layer, wherein a punching connection position between the semiconductor layer and the third metal layer is shown; Fig.15 for Figure 4A schematic diagram of a stacked structure of another partial film layer in the pixel driving circuit shown, specifically a schematic diagram of a stacked structure of a second metal layer and a third metal layer, wherein a punching connection position between the second metal layer and the third metal layer is shown; Fig.16 for Figure 4 The schematic diagram of the stacked structure of another partial film layer in the pixel driving circuit shown is specifically a schematic diagram of the stacked structure of the first metal layer and the third metal layer, wherein the punching connection position between the first metal layer and the third metal layer is shown.

[0079] like Figure 2 , Figure 4-Figure 16 As shown, optionally, a semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a third metal layer M2 and an anode layer RE are sequentially stacked on one side of the base substrate 10. The active layer of the voltage regulating transistor 30 is located in the semiconductor layer POLY, and the gate of the voltage regulating transistor 30 is located in the first metal layer M1. The pixel driving circuit 20 also includes a storage capacitor Cst, which is connected in series between the gate G3 of the driving transistor T3 and the first power signal line PVDD, the first plate C11 of the storage capacitor Cst is located in the first metal layer M1, and the second plate C12 of the storage capacitor Cst is located in the second metal layer MC. The conductive structure 21 includes a first conductive layer 211, and the first conductive layer 211 and the semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the third metal layer M2 and the anode layer RE are located in different film layers.

[0080] Specifically, Figure 4 As shown, taking the LTPS display panel as an example, a semiconductor layer POLY, a first metal layer M1 , a second metal layer MC, a third metal layer M2 and an anode layer RE are stacked on one side of the base substrate 10 .

[0081] Among them, Figure 2 and Figure 4 As shown, an insulating layer 12 may be provided between any two adjacent conductive film layers to avoid a short circuit between the two adjacent conductive film layers.

[0082] It should be noted that Figure 5-Figure 16 The film structure shown can correspond to Figure 3 In the pixel driving circuit 20 shown in the figure, the first light emission control transistor T1, the data writing transistor T2, the driving transistor T3, the compensation transistor T4, the first reset transistor T5, the second light emission control transistor T6 and the second reset transistor T7 can all be low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) transistors, and the LTPS transistor has the advantages of small size and good stability.

[0083] For example, Figure 5-Figure 16As shown, active layers of the first light emission control transistor T1 , the data writing transistor T2 , the driving transistor T3 , the compensation transistor T4 , the first reset transistor T5 , the second light emission control transistor T6 , and the second reset transistor T7 may be located in the semiconductor layer POLY.

[0084] The gates of the first light emission control transistor T1 , the data writing transistor T2 , the driving transistor T3 , the compensation transistor T4 , the first reset transistor T5 , the second light emission control transistor T6 , and the second reset transistor T7 and the first electrode C11 of the storage capacitor Cst may be located in the first metal layer M1 .

[0085] The first metal layer M1 may further include a first scan signal line Scan1, a second scan signal line Scan2, a data scan signal line ScanP and a light emitting control signal line EMIT extending along the row direction. The connection relationship and functions of the above signal lines can be referred to the above embodiments and will not be repeated here.

[0086] The second metal layer MC may include a second electrode C12 of the storage capacitor Cst and a first reset signal line vref extending along the row direction. The connection relationship and functions thereof may refer to the above embodiments and will not be described in detail herein.

[0087] The third metal layer M2 may include a first power signal line PVDD and a data signal line data extending along the column direction. The connection relationship and functions of the above signal lines may refer to the above embodiments and will not be described again.

[0088] Optionally, the second metal layer MC may also include a first power signal line PVDD extending along the row direction. The first power signal line PVDD extending along the row direction is electrically connected to the first power signal line PVDD extending along the column direction in the third metal layer M2, and can form a grid routing structure, which is beneficial to reducing line resistance, and further reducing the voltage drop of the first power signal on the first power signal line PVDD, which is beneficial to ensuring the stability of the first power signal.

[0089] The anode layer RE may include the anode 231 of the light emitting element 23 .

[0090] It should be noted that the specific film layer settings of the display panel can be adaptively adjusted according to actual needs, such as adding or removing some film layers, and the embodiments of the present invention do not specifically limit this.

[0091] In this embodiment, if Figure 2 , Figure 4-Figure 16As shown, the conductive structure 21 includes a first conductive layer 211, wherein the first conductive layer 211 and the semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the third metal layer M2 and the anode layer RE are all located in different film layers. By adding an additional film layer to set the first conductive layer 211, the distance between the first conductive layer 211 and other signal lines (such as scanning signal lines, data signal lines, etc.) can be increased in a direction perpendicular to the plane where the substrate 10 is located, which helps to reduce the coupling capacitance effect between the first conductive layer 211 and the other signal lines, thereby reducing the influence of voltage fluctuations between the first conductive layer 211 and the other signal lines, ensuring that the voltage on the first conductive layer 211 is more stable, which is beneficial to reduce the leakage current of the voltage regulating transistor 30, reduce the voltage fluctuation of the gate G3 of the driving transistor T3, and improve the screen jitter phenomenon of the display panel.

[0092] At the same time, by adding an additional film layer to set the first conductive layer 211, an independent arrangement space can be provided for the first conductive layer 211, so that the first conductive layer 211 is no longer restricted by the layout and routing arrangement of the original film layer, so that the first conductive layer 211 can be more flexibly designed according to actual needs. For example, its coverage range can be expanded to shield the mutual interference between signal lines of different layers over a larger range, which helps to improve the screen jitter phenomenon of the display panel.

[0093] It should be noted that the first conductive layer 211 can be located between any two adjacent original film layers (for example, including the semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the third metal layer M2 and the anode layer RE), and the first conductive layer 211 can also be located between the semiconductor layer POLY and the base substrate 10. The specific film layer position can be set according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0094] In addition, the specific shape of the first conductive layer 211 can be set according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0095] Continue to refer Figure 6-Figure 16 Optionally, the fixed voltage signal line 22 extends along a first direction X, the first conductive layer 211 extends along a second direction Y, and the first direction X and the second direction Y intersect.

[0096] Among them, the first conductive layer 211 is set as a routing structure extending along the second direction Y, so that multiple first conductive layers 211 and multiple fixed voltage signal lines 22 can be cross-set to form a grid routing structure, which can effectively reduce the line resistance and reduce the voltage drop of the signal transmitted on the fixed voltage signal line 22, which helps to improve the signal transmission efficiency and ensure that each pixel driving circuit 20 obtains a more stable voltage supply, thereby reducing the brightness difference caused by uneven voltage supply, which is beneficial to improving display uniformity.

[0097] Optional, such as Figure 6-Figure 16 As shown, the first direction X may be a row direction, and the second direction Y may be a column direction, but it is not limited thereto.

[0098] Optionally, the material of the first conductive layer 211 includes metal or indium gallium zinc oxide.

[0099] Among them, the metal material has a relatively high electrical conductivity. The use of metal material for the first conductive layer 211 can significantly reduce the resistance of the first conductive layer 211, thereby enhancing the effect of forming a coupling capacitor between the conductive structure 21 and the active layer 301 of the voltage regulating transistor 30, reducing the leakage current of the voltage regulating transistor 30, and stabilizing the voltage of the gate G3 of the driving transistor T3, improving the stability of the voltage of the gate G3 of the driving transistor T3, and improving the screen jitter phenomenon of the display panel.

[0100] At the same time, when the first conductive layer 211 crosses the fixed voltage signal line 22 to form a grid routing structure, the smaller resistance of the first conductive layer 211 can effectively reduce the line resistance, thereby reducing the voltage drop, helping to improve signal transmission efficiency, and ensuring that each pixel driving circuit 20 obtains a more stable voltage supply, thereby reducing the brightness difference caused by uneven voltage supply, which is beneficial to improving display uniformity.

[0101] Furthermore, the metal material also has a high reflectivity and light absorption rate. The first conductive layer 211 is made of metal material, and the first conductive layer 211 can form a shield for the active layer 301 of the voltage regulating transistor 30, thereby blocking the ambient light from irradiating the active layer 301 of the voltage regulating transistor 30, reducing the generation of photogenerated carriers, thereby reducing the photogenerated leakage current of the voltage regulating transistor 30, and further helping to stabilize the voltage of the gate G3 of the driving transistor T3, improve the stability of the voltage of the gate G3 of the driving transistor T3, and improve the screen jitter phenomenon of the display panel.

[0102] Optionally, the material of the first conductive layer 211 may include aluminum (Al), copper (Cu), molybdenum (Mo) or titanium (Ti), etc., to provide good conductive properties, but is not limited thereto.

[0103] Fig.17 A schematic diagram of a laminated structure of a film layer of a pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Fig.17 As shown, optionally, the material of the first conductive layer 211 can also be indium gallium zinc oxide (IGZO), wherein the IGZO material has good transparency. The first conductive layer 211 is made of IGZO material and can be suitable for application scenarios requiring high light transmittance, such as transparent display panels.

[0104] In addition, IGZO material can be deposited and processed at a lower temperature, which helps to avoid damage to the substrate and other film layers caused by high-temperature processes. The first conductive layer 211 is made of IGZO material and can be suitable for the manufacture of flexible display panels or large-area display panels.

[0105] Continue to refer Figure 2 , Figure 4-Figure 17 Optionally, the first conductive layer 211 is located on a side of the second metal layer MC away from the base substrate 10 , or the first conductive layer 211 is located on a side of the semiconductor layer POLY close to the base substrate 10 .

[0106] Specifically, Figure 2 , Figure 4-Figure 17 As shown, in a direction perpendicular to the plane where the base substrate 10 is located, the first conductive layer 211 is arranged on the side of the second metal layer MC away from the base substrate 10, so as to increase the distance between the first conductive layer 211 and the signal lines (such as scanning signal lines, reset signal lines, etc.) in the first metal layer M1 and the second metal layer MC in a direction perpendicular to the plane where the base substrate 10 is located, which helps to reduce the coupling capacitance effect between the first conductive layer 211 and the other signal lines, thereby reducing the influence of voltage fluctuations between the first conductive layer 211 and the other signal lines, ensuring that the voltage on the first conductive layer 211 is more stable, and further helps to reduce the leakage current of the voltage regulating transistor 30, helps to reduce the voltage fluctuation of the gate G3 of the driving transistor T3, and improves the screen jitter phenomenon of the display panel.

[0107] Fig.18 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present invention, such as Fig.18 As shown, optionally, in a direction perpendicular to the plane where the base substrate 10 is located, the first conductive layer 211 can also be arranged on a side of the semiconductor layer close to the base substrate 10, so as to increase the distance between the first conductive layer 211 and the signal lines (such as scanning signal lines, reset signal lines, etc.) in the first metal layer M1 and the second metal layer MC in a direction perpendicular to the plane where the base substrate 10 is located, which helps to reduce the coupling capacitance effect between the first conductive layer 211 and the other signal lines, thereby reducing the influence of voltage fluctuations between the first conductive layer 211 and the other signal lines, ensuring that the voltage on the first conductive layer 211 is more stable, which is beneficial to reduce the leakage current of the voltage regulating transistor 30, reduce the voltage fluctuation of the gate G3 of the driving transistor T3, and improve the screen jitter phenomenon of the display panel.

[0108] Continue to refer Figure 2 , Figure 4-Figure 16Optionally, the pixel driving circuit 20 includes a first reset transistor T5, and the fixed voltage signal line 22 includes a first reset signal line vref. The first reset transistor T5 is connected in series between the gate G3 of the driving transistor T3 and the first reset signal line vref. In a direction perpendicular to the plane where the substrate 10 is located, the first conductive layer 211 at least partially overlaps the first reset signal line vref, and the first conductive layer 211 is electrically connected to the first reset signal line vref through the first via H1.

[0109] The connection relationship and function between the first reset transistor T5 and the first reset signal line vref may refer to the above embodiment and will not be described in detail here.

[0110] In this embodiment, if Figure 2 , Figure 4-Figure 17 As shown, along a direction perpendicular to the plane where the base substrate 10 is located, there is an overlapping area between the first conductive layer 211 and the first reset signal line vref, so that the first conductive layer 211 can be electrically connected to the first reset signal line vref through the first via hole H1.

[0111] The first via hole H1 is a conductive channel vertically penetrating the insulating layer between the first conductive layer 211 and the first reset signal line vref. The first conductive layer 211 and the first reset signal line vref can be reliably electrically connected through the first via hole H1.

[0112] Optionally, the first via hole H1 and other via holes between the third metal layer M2 and the semiconductor layer POLY may be prepared in the same process, thereby reducing one mask process, and reducing process time and cost.

[0113] Continue to refer Figure 5-Figure 16 Optionally, the display panel provided by the embodiment of the present invention further includes a data signal line data. The first reset signal line vref extends along a first direction X, the data signal line data extends along a second direction Y, and the first direction X intersects the second direction Y. Along the first direction X, the first via H1 is located between the first reset transistor T5 and the data signal line data.

[0114] The connection relationship and function of the data signal line data and the first reset signal line vref may refer to the above embodiment and will not be described in detail here.

[0115] In this embodiment, if Figure 5-Figure 16As shown, at the position of the first reset signal line vref in the same pixel driving circuit 20, along the first direction X, the number of signal lines between the first reset transistor T5 and the data signal line data is small, which can provide sufficient arrangement space for the first via H1. Therefore, along the first direction X, the first via H1 is arranged between the first reset transistor T5 and the data signal line data, which helps to reduce the overlapping area between the first via H1 and other signal lines in the thickness direction of the display panel, thereby reducing the coupling capacitance between the first via H1 and other signal lines, and further reducing the signal interference between the first via H1 and other signal lines, which is beneficial to improving the display uniformity of the display panel.

[0116] It should be noted that the location of the first via hole H1 is not limited to the above embodiment. In other embodiments, the first via hole H1 may also be located at other locations, which is not specifically limited in the embodiment of the present invention.

[0117] Fig.19 A partial cross-sectional structure diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Fig.19 As shown, optionally, the fixed voltage signal line 22 includes a first power signal line PVDD, and the first conductive layer 211 is electrically connected to the first power signal line PVDD.

[0118] Among them, Fig.19 As shown, the first conductive layer 211 and the first power signal line PVDD are electrically connected so that the first power signal line PVDD is used as the fixed voltage signal line 22. A constant voltage is applied to the first conductive layer 211 through the first power signal line PVDD. In this way, the existing signal line resources of the display panel can be fully utilized without setting up new signal lines. This can simplify circuit design, reduce wiring complexity, save space, and reduce manufacturing costs.

[0119] Fig. 20 A schematic diagram of a laminated structure of a film layer of another pixel driving circuit provided by an embodiment of the present invention, Fig.21 for Fig. 20 The schematic diagram of the stacked structure of a partial film layer in the pixel driving circuit shown is specifically a schematic diagram of the stacked structure of the second metal layer and the first conductive layer, wherein the punched connection position between the second metal layer and the first conductive layer is shown.

[0120] like Fig. 20 and Fig.21As shown, optionally, the pixel driving circuit 20 further includes a storage capacitor Cst, which is connected in series between the gate G3 of the driving transistor T3 and the first power signal line PVDD. The second plate C12 of the storage capacitor Cst is electrically connected to the first power signal line PVDD. In a direction perpendicular to the plane where the substrate 10 is located, the first conductive layer 211 at least partially overlaps the second plate C12 of the storage capacitor Cst, and the first conductive layer 211 is electrically connected to the second plate C12 of the storage capacitor Cst through the second via H2.

[0121] The specific structure, connection relationship and function of the storage capacitor Cst may refer to the above embodiments and will not be described in detail here.

[0122] In this embodiment, if Fig. 20 and Fig.21 As shown, if the first conductive layer 211 is directly connected to the first power signal line PVDD extending along the second direction Y through a via hole, coupling interference may be formed between the via hole and the signal line, increasing the process difficulty and reducing the reliability.

[0123] Since the second electrode plate C12 of the storage capacitor Cst is electrically connected to the first power signal line PVDD, in this embodiment, Fig. 20 and Fig.21 As shown, the first conductive layer 211 is electrically connected to the second electrode C12 of the storage capacitor Cst through the second via H2, so as to indirectly realize the electrical connection between the first conductive layer 211 and the first power signal line PVDD, which helps to reduce the coupling interference between the second via H2 and other signal lines, and can reduce the process difficulty and improve reliability.

[0124] The second via H2 is a conductive channel vertically penetrating the insulating layer between the first conductive layer 211 and the second electrode C12 of the storage capacitor Cst. The first conductive layer 211 and the second electrode C12 of the storage capacitor Cst can be reliably electrically connected through the second via H2.

[0125] Optionally, the second via hole H2 and other via holes between the third metal layer M2 and the semiconductor layer POLY may be prepared in the same process, thereby reducing a mask process, and reducing process time and cost.

[0126] It should be noted that the location of the second via hole H2 is not limited to the above embodiment. In other embodiments, the second via hole H2 may also be located at other locations, which is not specifically limited in the embodiment of the present invention.

[0127] Continue to refer Figure 2 , Figure 5-Figure 21Optionally, along a direction perpendicular to the plane where the substrate 10 is located, the first conductive layer 211 and the gate of the voltage regulating transistor 30 at least partially overlap.

[0128] Specifically, Figure 2 , Figure 5-Figure 21 As shown, in a direction perpendicular to the plane of the substrate 10, an overlap is set between the first conductive layer 211 and the gate of the voltage regulating transistor 30, and a coupling capacitor can be formed between the conductive structure 21 and the gate of the voltage regulating transistor 30. The coupling capacitor can stabilize the gate voltage of the voltage regulating transistor 30 to a certain extent, reduce the leakage current of the voltage regulating transistor 30, and further improve the stability of the voltage of the gate G3 of the driving transistor T3, thereby improving the screen jitter phenomenon of the display panel.

[0129] It should be noted that the coverage range of the first conductive layer 211 can be set according to actual needs. Since the first conductive layer 211 is set in the newly added film layer, the first conductive layer 211 has an independent layout space. Therefore, the coverage range of the first conductive layer 211 can be further expanded so that it can cover other transistors (for example, covering the gate and / or active layer of the transistor) or signal lines in a direction perpendicular to the plane of the base substrate 10, so as to shield the mutual interference between signal lines and signal nodes of different layers in a larger range, which helps to improve the display effect of the display panel.

[0130] It is understandable that when setting the coverage of the first conductive layer 211 , it is only necessary to ensure that the first conductive layer 211 does not affect the via connections between the layers, and the embodiment of the present invention does not specifically limit this.

[0131] Continue to refer Figure 4-Figure 17 , Fig. 20 and Fig.21 Optionally, a semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a third metal layer M2 and an anode layer RE are sequentially stacked on one side of the base substrate 10. The active layer of the voltage regulating transistor 30 is located in the semiconductor layer POLY, and the gate of the voltage regulating transistor 30 is located in the first metal layer M1. The pixel driving circuit 20 also includes a storage capacitor Cst, which is connected in series between the gate G3 of the driving transistor T3 and the first power signal line PVDD, the first electrode C11 of the storage capacitor Cst is located in the first metal layer M1, and the second electrode C12 of the storage capacitor Cst is located in the second metal layer MC. The conductive structure 21 includes a second conductive layer 212, and the second conductive layer 212 is located in the same film layer as the first metal layer M1, the second metal layer MC, the third metal layer M2 or the anode layer RE.

[0132] The structure and function of the pixel driving circuit 20 and the film layer arrangement of the display panel may refer to the above-mentioned embodiment and will not be described in detail here.

[0133] In this embodiment, if Figure 4-Figure 17 , Fig. 20 and Fig.21 As shown, the conductive structure 21 includes a second conductive layer 212, wherein the second conductive layer 212 is located in the same film layer as at least one of the first metal layer M1, the second metal layer MC, the third metal layer M2 and the anode layer RE, so that the second conductive layer 212 is set by using the original film layer in the display panel, so that the number of film layers can be reduced, thereby achieving the purpose of reducing production costs and reducing the thickness of the display panel. At the same time, the second conductive layer 212 can be prepared in the same process as other film layer structures, thereby shortening the process time.

[0134] It should be noted that the second conductive layer 212 can be located in the same film layer as any film layer among the first metal layer M1, the second metal layer MC, the third metal layer M2 and the anode layer RE, and its specific film layer position can be set according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0135] Fig. 22 A schematic diagram of a laminated structure of a film layer of another pixel driving circuit provided in an embodiment of the present invention is shown in FIG. Fig. 22 As shown, optionally, the pixel driving circuit 20 includes a first reset transistor T5, the fixed voltage signal line 22 includes a first reset signal line vref, and the first reset transistor T5 is connected in series between the gate G3 of the driving transistor T3 and the first reset signal line vref. The second conductive layer 212 and the first reset signal line vref are both located in the second metal layer MC, and the second conductive layer 212 and the first reset signal line vref are electrically connected.

[0136] The connection relationship and function between the first reset transistor T5 and the first reset signal line vref may refer to the above embodiment and will not be described in detail here.

[0137] In this embodiment, if Fig. 22 As shown, the second conductive layer 212 and the first reset signal line vref can be set in the same film layer to reduce the number of film layers, thereby reducing production costs and reducing the thickness of the display panel. At the same time, the second conductive layer 212 and the first reset signal line vref can be prepared in the same process, thereby shortening the process time.

[0138] Among them, since the second conductive layer 212 and the first reset signal line vref are located in the same film layer, the second conductive layer 212 and the first reset signal line vref can be electrically connected through a simple graphical process without the need for additional vias or other complex connection structures, which helps to reduce the process difficulty, reduce the contact resistance, and improve the signal transmission efficiency.

[0139] It should be noted that the shape of the second conductive layer 212 can be set according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0140] Continue to refer Figure 4-Figure 17 , Fig. 20 and Fig.21 The fixed voltage signal line 22 includes a first power signal line PVDD. In a direction perpendicular to the plane of the substrate 10, the second conductive layer 212 at least partially overlaps the first power signal line PVDD, and the second conductive layer 212 is electrically connected to the first power signal line PVDD through a third via H3.

[0141] Among them, Figure 4-Figure 17 , Fig. 20 and Fig.21 As shown, the second conductive layer 212 and the first power signal line PVDD are electrically connected so that the first power signal line PVDD is used as the fixed voltage signal line 22. A constant voltage is applied to the second conductive layer 212 through the first power signal line PVDD. In this way, the existing signal line resources of the display panel can be fully utilized without setting up new signal lines. This can simplify circuit design, reduce wiring complexity, save space, and reduce manufacturing costs.

[0142] Furthermore, if Figure 4-Figure 17 , Fig. 20 and Fig.21 As shown, along the direction perpendicular to the plane where the base substrate 10 is located, there is an overlapping area between the second conductive layer 212 and the first power signal line PVDD, so that the second conductive layer 212 can be electrically connected to the first power signal line PVDD through the third via H3.

[0143] The third via hole H3 is a conductive channel vertically penetrating the insulating layer between the second conductive layer 212 and the first power signal line PVDD. The second conductive layer 212 and the first power signal line PVDD can be reliably electrically connected through the third via hole H3.

[0144] Optionally, the third via hole H3 and other via holes between the third metal layer M2 and the semiconductor layer POLY may be prepared in the same process, thereby reducing a mask process, and reducing process time and cost.

[0145] Continue to refer Figure 4-Figure 17, Fig. 20 and Fig.21 Optionally, there is a gap between a vertical projection of the second conductive layer 212 on the base substrate 10 and a vertical projection of the second metal layer MC on the base substrate 10 .

[0146] Among them, Figure 4-Figure 17 , Fig. 20 and Fig.21 As shown, in a direction perpendicular to the plane where the base substrate 10 is located, there is no overlap between the second conductive layer 212 and the second metal layer MC, which can reduce the coupling capacitance effect between the signal lines in the second conductive layer 212 and the second metal layer MC, thereby reducing the influence of voltage fluctuations between the second conductive layer 212 and the signal lines in the second metal layer MC, ensuring that the voltage on the second conductive layer 212 is more stable, which is beneficial to reducing the leakage current of the voltage regulating transistor 30, reducing the voltage fluctuation of the gate G3 of the driving transistor T3, and improving the screen jitter phenomenon of the display panel.

[0147] Continue to refer Figure 4-Figure 17 , Fig. 20 and Fig.21 Optionally, there is a gap between a vertical projection of the second conductive layer 212 on the base substrate 10 and a vertical projection of the first metal layer M1 on the base substrate 10 .

[0148] Among them, Figure 4-Figure 17 , Fig. 20 and Fig.21 As shown, in a direction perpendicular to the plane where the base substrate 10 is located, there is no overlap between the second conductive layer 212 and the first metal layer M1, which can reduce the coupling capacitance effect between the second conductive layer 212 and the signal line in the first metal layer M1, thereby reducing the influence of voltage fluctuations between the second conductive layer 212 and the signal line in the first metal layer M1, ensuring that the voltage on the second conductive layer 212 is more stable, which is beneficial to reduce the leakage current of the voltage regulating transistor 30, reduce the voltage fluctuation of the gate G3 of the driving transistor T3, and improve the screen jitter phenomenon of the display panel.

[0149] It should be noted that, in other embodiments, the second conductive layer 212 may also be located in a different film layer from the semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the third metal layer M2 and the anode layer RE, so that the second conductive layer 212 can be set by adding an additional film layer. In this way, the distance between the second conductive layer 212 and other signal lines (such as scanning signal lines, data signal lines, etc.) can be increased in a direction perpendicular to the plane of the substrate 10, which helps to reduce the coupling capacitance effect between the second conductive layer 212 and the other signal lines, thereby reducing the influence of voltage fluctuations between the second conductive layer 212 and the other signal lines, ensuring that the voltage on the second conductive layer 212 is more stable, which is beneficial to reduce the leakage current of the voltage regulating transistor 30, reduce the voltage fluctuation of the gate G3 of the driving transistor T3, and improve the screen jitter phenomenon of the display panel.

[0150] Fig.23 A schematic diagram of a laminated structure of a film layer of another pixel driving circuit provided in an embodiment of the present invention is shown in FIG. Fig. 22 and Fig.23 As shown, along the direction perpendicular to the plane where the base substrate 10 is located, there is an overlapping area between the first conductive layer 211, the second conductive layer 212 and the active layer 301 of the voltage regulating transistor 30. This arrangement allows the first conductive layer 211 and the second conductive layer 212 to form a coupling capacitor with the active layer 301 of the voltage regulating transistor 30, which is beneficial to stabilizing the voltage of the active layer and the gate of the voltage regulating transistor, reducing the leakage current of the voltage regulating transistor, and further stabilizing the voltage of the gate of the driving transistor, ensuring the stability of the light emitting brightness of the light emitting element, and improving the screen shaking phenomenon of the display panel.

[0151] Continue to refer Figure 2 , Figure 5-Figure 22 Optionally, the voltage regulating transistor 30 is a dual-gate transistor. Along a direction perpendicular to the plane where the substrate 10 is located, the conductive structure 21 and the active layer between the two gates in the voltage regulating transistor 30 at least partially overlap.

[0152] Among them, the dual-gate transistor has two independent gates, which can control the channel region of the transistor separately to form two independent electric field regions. By rationally designing the voltage of the two gates, the charge distribution in the channel region can be more accurately controlled, reducing subthreshold leakage current and photogenerated leakage current.

[0153] In this embodiment, the voltage regulating transistor 30 adopts a dual-gate transistor, which can reduce the leakage current of the voltage regulating transistor 30, thereby stabilizing the voltage of the gate G3 of the driving transistor T3, improving the stability of the luminous brightness of the light-emitting element 23, and improving the screen jitter phenomenon of the display panel.

[0154] For example, Figure 2 , Figure 5-Figure 22 As shown, the voltage regulating transistor 30 may adopt a top gate structure. In this case, the two gates of the voltage regulating transistor 30 are both located on the side of its active layer away from the substrate 10, but it is not limited to this. In some embodiments, the voltage regulating transistor 30 may also adopt a top-bottom double gate structure, that is, the two gates of the voltage regulating transistor 30 are respectively located on both sides of its active layer. The embodiment of the present invention does not make specific limitations on this.

[0155] Furthermore, if Figure 2 , Figure 5-Figure 22 As shown, in the direction perpendicular to the plane where the substrate 10 is located, the conductive structure 21 and the active layer between the two gates in the voltage regulating transistor 30 at least partially overlap, and the electric fields generated by the two gates will be superimposed in the overlapping area to form a strong electric field effect. The superposition of electric fields is conducive to controlling the charge distribution in the channel region, so that the gate voltage can be controlled more accurately, the drift of the threshold voltage can be reduced, and the characteristics of the voltage regulating transistor 30 can be kept stable, which helps to further reduce the leakage current of the voltage regulating transistor 30, thereby stabilizing the voltage of the gate G3 of the driving transistor T3, improving the stability of the light emitting brightness of the light emitting element 23, and improving the screen shaking phenomenon of the display panel.

[0156] Optionally, in a direction perpendicular to the plane of the substrate 10, the conductive structure 21 may further cover the active layer between the two gates in the voltage regulating transistor 30 to further reduce the leakage current of the voltage regulating transistor 30, stabilize the voltage of the gate G3 of the driving transistor T3, improve the stability of the luminous brightness of the light-emitting element 23, and improve the screen jitter phenomenon of the display panel.

[0157] It is understandable that the coverage of the conductive structure 21 can be set according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0158] Continue to refer Figure 2 , Figure 5-Figure 22 Optionally, the voltage regulating transistor 30 includes a first reset transistor T5, the display panel further includes a first reset signal line vref, and the first reset transistor T5 is connected in series between the first reset signal line vref and the anode of the light emitting element.

[0159] and / or,

[0160] The voltage regulating transistor 30 includes a compensation transistor T4 connected between the gate G3 of the driving transistor T3 and the first terminal (ie, the N3 node) of the driving transistor T3 .

[0161] The connection relationship and functions of the first reset transistor T5 , the compensation transistor T4 and the first reset signal line vref may refer to the above embodiments, which will not be described in detail here.

[0162] In this embodiment, the first reset transistor T5 and the compensation transistor T4 are both connected to the gate G3 of the driving transistor T3. If the first reset transistor T5 and the compensation transistor T4 generate leakage current, the leakage current will affect the voltage of the gate G3 of the driving transistor T3, making the voltage of the gate G3 of the driving transistor T3 unstable. Especially in the low-frequency working mode, due to the long frame period, the light-generated leakage current will accumulate over a long period of time, thereby having a greater impact on the voltage of the gate G3 of the driving transistor T3, making the light emitting brightness of the light-emitting element 23 unstable, and causing the display panel to have a screen shaking phenomenon.

[0163] Based on the above technical problems, the first reset transistor T5 and / or the compensation transistor T4 can be set as a voltage regulating transistor 30. By setting an overlap between the conductive structure 21 and the active layer of the first reset transistor T5 and / or the compensation transistor T4, a coupling capacitor is formed between the conductive structure 21 and the active layer of the first reset transistor T5 and / or the compensation transistor T4 to stabilize the voltage of the active layer and the gate of the first reset transistor T5 and / or the compensation transistor T4, reduce the leakage current of the first reset transistor T5 and / or the compensation transistor T4, and then stabilize the voltage of the gate G3 of the driving transistor T3, ensure the stability of the light emitting brightness of the light emitting element 23, and improve the screen jitter phenomenon of the display panel.

[0164] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.24 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.24 As shown, the display device 40 includes the display panel 41 described in any embodiment of the present invention. Therefore, the display device 40 provided in the embodiment of the present invention has the technical effect of the technical solution in any of the above embodiments, and the structures that are the same or corresponding to the above embodiments and the explanation of terms are no longer repeated here.

[0165] The display device 40 provided in the embodiment of the present invention can be Fig.24 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0166] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0167] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: It includes a base substrate and a pixel driving circuit, a conductive structure and a fixed voltage signal line located on one side of the base substrate; The pixel driving circuit comprises a driving transistor and a voltage regulating transistor, wherein the driving transistor is connected in series between the first power signal line and the light emitting element; The voltage regulating transistor is electrically connected to the gate of the driving transistor; Along a direction perpendicular to the plane of the substrate, the conductive structure and the active layer of the voltage regulating transistor at least partially overlap; The conductive structure is electrically connected to the fixed voltage signal line.

2. The display panel according to claim 1, characterized in that: The pixel driving circuit includes a first reset transistor, and the fixed voltage signal line includes a first reset signal line; The first reset transistor is connected in series between the gate of the driving transistor and the first reset signal line.

3. The display panel according to claim 1, characterized in that: The fixed voltage signal line includes the first power signal line.

4. The display panel according to claim 1, characterized in that: A semiconductor layer, a first metal layer, a second metal layer, a third metal layer and an anode layer are sequentially stacked on one side of the substrate; The active layer of the voltage regulating transistor is located in the semiconductor layer; The gate of the voltage regulating transistor is located at the first metal layer; The pixel driving circuit further includes a storage capacitor, which is connected in series between the gate of the driving transistor and the first power signal line; a first plate of the storage capacitor is located on the first metal layer, and a second plate of the storage capacitor is located on the second metal layer; The conductive structure includes a first conductive layer, and the first conductive layer, the semiconductor layer, the first metal layer, the second metal layer, the third metal layer and the anode layer are located in a different film layer.

5. The display panel according to claim 4, characterized in that: The fixed voltage signal line extends along a first direction, and the first conductive layer extends along a second direction; The first direction intersects the second direction.

6. The display panel according to claim 4, characterized in that: The material of the first conductive layer includes metal or indium gallium zinc oxide.

7. The display panel according to claim 4, characterized in that: The first conductive layer is located on a side of the second metal layer away from the substrate; or, The first conductive layer is located on a side of the semiconductor layer close to the substrate.

8. The display panel according to claim 4, characterized in that: The pixel driving circuit includes a first reset transistor, and the fixed voltage signal line includes a first reset signal line; The first reset transistor is connected in series between the gate of the driving transistor and the first reset signal line; Along a direction perpendicular to the plane where the substrate is located, the first conductive layer at least partially overlaps with the first reset signal line, and the first conductive layer is electrically connected to the first reset signal line through a first via hole.

9. The display panel according to claim 8, characterized in that: The display panel also includes a data signal line; The first reset signal line extends along a first direction, the data signal line extends along a second direction, and the first direction intersects the second direction; Along the first direction, the first via hole is located between the first reset transistor and the data signal line.

10. The display panel according to claim 4, characterized in that: The fixed voltage signal line includes the first power signal line; The first conductive layer is electrically connected to the first power signal line.

11. The display panel according to claim 10, characterized in that: The pixel driving circuit further comprises a storage capacitor, wherein the storage capacitor is connected in series between the gate of the driving transistor and the first power signal line; The second electrode plate of the storage capacitor is electrically connected to the first power signal line; Along a direction perpendicular to the plane where the substrate is located, the first conductive layer at least partially overlaps with the second electrode plate of the storage capacitor, and the first conductive layer is electrically connected to the second electrode plate of the storage capacitor through a second via hole.

12. The display panel according to claim 4, characterized in that: Along a direction perpendicular to a plane where the substrate is located, the first conductive layer and the gate of the voltage regulating transistor at least partially overlap.

13. The display panel according to claim 1, characterized in that: A semiconductor layer, a first metal layer, a second metal layer, a third metal layer and an anode layer are sequentially stacked on one side of the substrate; The active layer of the voltage regulating transistor is located in the semiconductor layer; The gate of the voltage regulating transistor is located at the first metal layer; The pixel driving circuit further includes a storage capacitor, which is connected in series between the gate of the driving transistor and the first power signal line; a first plate of the storage capacitor is located on the first metal layer, and a second plate of the storage capacitor is located on the second metal layer; The conductive structure includes a second conductive layer, and the second conductive layer is located in the same film layer as the first metal layer, the second metal layer, the third metal layer or the anode layer.

14. The display panel according to claim 13, characterized in that: The pixel driving circuit comprises a first reset transistor, the fixed voltage signal line comprises a first reset signal line, and the first reset transistor is connected in series between the gate of the driving transistor and the first reset signal line; The second conductive layer and the first reset signal line are both located in the second metal layer, and the second conductive layer and the first reset signal line are electrically connected.

15. The display panel according to claim 13, characterized in that: The fixed voltage signal line includes the first power signal line; Along a direction perpendicular to the plane where the substrate is located, the second conductive layer at least partially overlaps with the first power signal line, and the second conductive layer is electrically connected to the first power signal line through a third via hole.

16. The display panel according to claim 15, characterized in that: There is a gap between a vertical projection of the second conductive layer on the base substrate and a vertical projection of the second metal layer on the base substrate.

17. The display panel according to claim 13, characterized in that: There is a gap between a vertical projection of the second conductive layer on the base substrate and a vertical projection of the first metal layer on the base substrate.

18. The display panel according to claim 1, characterized in that: The voltage regulating transistor is a dual-gate transistor; Along a direction perpendicular to a plane where the substrate is located, the conductive structure and an active layer between two gates in the voltage regulating transistor at least partially overlap.

19. The display panel according to claim 1, characterized in that: The voltage regulating transistor includes a first reset transistor, and the display panel further includes a first reset signal line, wherein the first reset transistor is connected in series between the gate of the driving transistor and the first reset signal line; and / or, The voltage regulating transistor includes a compensation transistor connected between a gate of the driving transistor and a first terminal of the driving transistor.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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