Routing circuit for computer resource topology

Abstract

A routing circuit for an integrated circuit is configured to access a set of resources organized according to a topology having multiple dimensions. The routing receives a request for a particular resource in the set of resources, the request including an address that includes a first set of bits and a second set of bits, the topology having a first dimension with n routing options (where n is not a power of two) and a second dimension with m routing options. The routing circuit determines a first routing choice and a second routing choice for the first dimension and the second dimension by performing respective modulo-n and div-n operations on a value formed by the address including the first set of bits and the second set of bits. The routing circuit then activates one or more selection signals according to the first routing choice and the second routing choice, the one or more selection signals usable to cause the particular resource to be selected in response to the request.

Description

Technical Field

[0001] This disclosure relates generally to computer systems, and more generally to routing requests for computer resources in a topology having a number of options that is not a power of two. Background Technology

[0002] Related technical descriptions

[0003] Modern computer systems have become extremely complex. Such systems contain many different types of resources, and a given type of resource is often duplicated to achieve performance benefits. A memory system is one such example of a hierarchical collection of resources within a computer system. Requests for these resources typically involve addresses that must be interpreted to determine the route to the appropriate resource. Summary of the Invention

[0004] According to one aspect of this disclosure, an apparatus is provided, the apparatus comprising: an integrated circuit including: a set of storage locations arranged according to a hierarchical structure having multiple levels, the multiple levels including a first level having n hash options and a second level having m hash options, wherein n is an integer not a power of two; a hash circuit configured to: receive a request to access a specific storage location in the set of storage locations, the request including an address having a first bit set and a non-overlapping second bit set; and form a first value by masking the address with a first mask value, the first mask value including the first bit set and the second bit set. The set of bits, and a first intermediate set of bits separating the first set of bits and the second set of bits; forming a second value by masking the address with a second mask value, the second mask value including the first set of bits, the second set of bits, and a second intermediate set of bits separating the first set of bits and the second set of bits; determining a first hash value for the first level by performing a modulo-n operation on the first value; determining a second hash value for the second level by performing a div-n operation on the second value; and generating a plurality of selection signals based on the first hash value and the second hash value that can be used to select the specific storage location.

[0005] According to another aspect of this disclosure, a method is provided, the method comprising: receiving, at a routing circuit of a computer system including a resource set organized according to a topology having multiple dimensions, a request for a specific resource within the resource set, the request including an address having a first set and a non-overlapping second set, the topology having a first dimension with n routing options and a second dimension with m routing options, wherein n and m are both integers greater than two, and wherein n is not a power of two; determining, by the routing circuit, a first route selection for the first dimension by performing a modulo-n operation on a first value formed from the address, the first value including the first set and the second set; and determining, by the routing circuit, a route selection for the first dimension by performing a div-n operation on a second value formed from the address. A second routing selection with two dimensions, the second value including the first bit set and the second bit set; and one or more selection signals activated by the routing circuit based on the first routing selection and the second routing selection, the one or more selection signals being able to cause the specific resource to be selected in response to the request, wherein the first bit set and the second bit set are separated within the address by a set of intermediate bits, wherein the first value is formed by masking the address with a first mask value, the first mask value including the first bit set and the second bit set separated by a first set of intermediate bits, and wherein the second value is formed by masking the address with a different second mask value, the second mask value including the first bit set and the second bit set separated by a second set of intermediate bits.

[0006] According to another aspect of this disclosure, an apparatus is provided, the apparatus comprising: an integrated circuit, the integrated circuit comprising: a memory system arranged according to a hierarchical structure having multiple dimensions, the multiple dimensions including a first dimension having n hash options and a second dimension having m hash options, wherein n and m are integers greater than two, and wherein n is not a power of two; a hash circuit configured to: receive a request to access a specific memory location of the memory system, the request including a memory address having a first bit set and a second bit set separated by a middle bit set, the first bit set and the second bit set together encoding the first dimension and the second dimension; determine a first hash value for the first dimension by performing a modulo-n operation on a first value formed by the memory address using a first mask value, the first mask value including the first bit set, the second bit set and a first middle bit set; determine a second hash value for the second dimension by performing a div-n operation on a second value formed by the memory address using a second mask value, the second mask value including the first bit set, the second bit set and the second middle bit set; and generate a plurality of selection signals based on the first hash value and the second hash value capable of causing the specific memory location to be selected. Attached Figure Description

[0007] The following detailed embodiments are described with reference to the accompanying drawings, which will now be briefly described.

[0008] Figure 1 It is a block diagram of a routing circuit in a computer system, which is configured to determine a route to a resource in a set of resources having a topology with multiple dimensions, at least one of which has a number of options that is not a power of two.

[0009] Figure 2 It is an example of a storage system that is a collection of resources with multiple dimensions.

[0010] Figures 3A to 3B An example of routing in a multidimensional topology is provided, where one dimension has the number of options n, where n is not a power of two.

[0011] Figures 3C to 3D Examples of aliasing problems that may occur when addressing multidimensional topologies are provided.

[0012] Figure 4A An example of a lookup table that can be used to implement a mod-3 circuit is shown.

[0013] Figures 4B to 4C A method is described for performing a mod-3 operation on a number by means of a series of mod-3 operations on the components of the logarithm.

[0014] Figure 4D An implementation of a circuit that can be used to calculate mod-3 on an ad hoc number is illustrated.

[0015] Figure 5A A lookup table is shown as an example of an implementation scheme for div-3 circuits.

[0016] Figures 5B to 5C The method for performing the div-3 operation is described.

[0017] Figure 5D An implementation of a circuit that can be used to perform div-3 operations is illustrated.

[0018] Figure 6A Examples of lookup tables, functions, and circuits that can be used to implement mod-15 functionality are shown.

[0019] Figures 6B to 6C An implementation scheme for performing the mod-15 operation is described.

[0020] Figure 6D An implementation of a circuit that can be used to perform mod-15 operations is illustrated.

[0021] Figure 7A A lookup table is shown as an example of an implementation scheme for a div-15 circuit.

[0022] Figures 7B to 7C An implementation scheme for performing the div-15 operation is described.

[0023] Figure 7D An implementation of a circuit that can be used to compute the div-15 operation is illustrated.

[0024] Figure 8 This is a flowchart illustrating an implementation of a method for performing routing on a set of resources organized according to a topology with multiple dimensions.

[0025] Figure 9 This is a block diagram illustrating an example computing device used to implement the disclosed technology.

[0026] Figure 10 These are illustrations of example applications of systems and devices employing the disclosed technologies.

[0027] Figure 11 This is a block diagram illustrating an example computer-readable medium for storing circuit design information for implementing a device employing the disclosed technology. Detailed Implementation

[0028] A collection of computer resources can be arranged in a topology such that each "dimension" in the topology has multiple possible options. The number of options in a given dimension is typically equal to a power of two, as binary arithmetic has long been a building block of computer architecture. However, the inventors have recognized the need to accommodate a number of routing options that are not powers of two in one or more dimensions of the resource topology. Therefore, when faced with a scenario where a number n of routing (or hashing) options for a first dimension is desired, and n is not a power of two, a first value and a second value can be generated from request addresses for the first dimension and different second dimensions in the topology. A series of mod-n operations can be performed on the first value to determine the routing choice for the first dimension, while a series of div-n operations (also utilizing the mod-n result) can be performed on the second value to determine the routing choice for the second dimension. In this way, efficient routing without leaving "holes" in the address space can be achieved. This method may be particularly useful in settings where a dimension of a previous topology (e.g., in a previous product release) has changed from a power of two value to a non-power of two value in a new topology (e.g., for a new product release).

[0029] Overview

[0030] exist Figure 1 In the context of this application, this application begins with a general discussion of using mod-n and div-n operations to perform routing on a hierarchical structure having at least one dimension of routing options with a number that is not a power of two. Figure 2 It describes specific use cases for resources within a memory system, and Figures 3A to 3B An example of routing within this use case is illustrated. About Figures 3C to 3D An example of aliasing is described. This application then turns to mod 3 ( Figures 4A to 4D ); div 3 ( Figures 5A to 5D ); mod 15 ( Figures 6A to 6D ); div 15 ( Figures 7A to 7D The specific possible implementations of mod-n and div-n. Regarding Figure 8 A flowchart describing the methods used for routing is provided. About Figure 9 Exemplary devices are described in which the disclosed techniques (e.g., in computer circuitry) can be employed. Regarding Figure 10 Exemplary applications and platforms for such devices are described, while regarding Figure 11 A computer-readable medium is described that stores design information that can be used to manufacture computer circuits configured to implement the disclosed techniques.

[0031] Hashes that are not powers of two

[0032] This example is in Figure 1Example in Figure 1 A computer system 100 comprising a resource set 110 is depicted. Various entities (not depicted) within the computer system 100 will need to access one or more resources in the set 110. Therefore, a requesting entity will generate a request for the resource including a request address 104. A routing circuit 120 within the computer system 100 is configured to receive the request address 104 and generate a selection signal 150 that causes the requested resource to be selected for access.

[0033] like Figure 1 As shown, resource set 110 is organized according to a topological structure with multiple dimensions. For the sake of different terminology, resource set 110 can also be considered as a hierarchical structure with different levels. The following section discusses... Figure 2 An example organization of resource 110 is provided. Resource set 110 has at least two dimensions. Dimension a has n routing options (i.e., routing circuit 120 needs to choose one of n distinct possibilities for dimension a), where n is not a power of two. Therefore, n can be 3, 5, or 6, but not 2, 4, 8, 16, etc. Dimension b is a distinct dimension with m routing options.

[0034] One possible option for routing dimension a is to use extra bits. For example, if n=3, then 2 bits could be used for routing in this dimension. However, the inventors recognize that this would be inefficient from a hashing perspective, and it would mean that a portion of the memory space addressed by request address 104 would not be mapped to a resource in resource 110. That is, while address bits 00, 01, and 10 could be mapped to routing options 0, 1, and 2, address bit 11 would not be mapped to a feasible option.

[0035] Instead, the inventors propose determining routing for dimensions a and b by utilizing a portion of the request address 104 corresponding to both dimensions a and b. As shown, address 104 has a first set of one or more bits 106f and a second set of one or more bits 106s, corresponding to the number of options in dimensions a and b (i.e., n and m, respectively). Bit 106f may correspond to dimension a, and bit 106s to dimension b, or vice versa. As shown, in some cases, there is an intermediate bit 106i between bits 106f and bits 106s, because the inventors have found that hash balance is better for dimension a (which has a number of options that is not a power of two) when more bits are used. Address 104 may also contain bits more significant than bit 106f and bits less significant than bit 106s.

[0036] Address 104 is supplied to blocks 128 and 138, which generate a first value 129 and a second value 139, respectively. (As will be described with respect to Figure 3, blocks 128 and 138 may apply a mask value to address 104 to generate the first value 129 and the second value 139. The masks used by blocks 128 and 138 may be the same or different.) In various embodiments, the first value 129 and the second value 139 may be generated such that they include bits 106f and 106s. Values ​​129 and 139 are then supplied to arithmetic circuit 126, which includes mod-n circuit 130 and div-n circuit 140.

[0037] The mod-n circuit 130 is configured to perform a mod-n operation on the first value 129 to determine a route 132 for dimension a. Similarly, the div-n circuit 140 is configured to perform a div-n operation on the second value 139 to determine a route 142 for dimension b. As will be described below, in some specific implementations of the arithmetic circuit 126, routes 132 and 142 can be determined together; for example, the div-n operation performed by circuit 140 can use the result of the mod-n operation performed by circuit 130 (e.g., ...). Figure 1 (As shown by the arrows from circuits 130 to 140). For the example where n=3 and m=2, route 132 can be 0, 1, or 2, while route 142 can be 0 or 1. This arrangement provides a more efficient distribution (i.e., better hashing) of routing decisions for dimensions a and b compared to simply routing dimension a by itself using extra address bits.

[0038] In short, Figure 1Therefore, an apparatus is illustrated, comprising an integrated circuit including a set of storage locations (e.g., resource set 110) arranged according to a hierarchical structure having multiple levels, including a first dimension (or level) (e.g., dimension a) with n hash (or routing) options (n ​​being an integer not a power of two) and a second dimension (level) (dimension b) with m hash options. The apparatus also includes routing circuitry (or hashing circuitry) (e.g., routing circuitry 120). This circuitry is configured to receive a request to access a specific storage location in the set of storage locations, the request including an address (e.g., request address 104) having a first bit set (106f) and a second non-overlapping bit set (106s). The routing circuitry is also configured to determine a first hash value for the first level by performing a modulo-n operation on the first value formed from the address (e.g., using mod-n circuitry 130). The routing circuitry is further configured to determine a second hash value for the second level by performing a div-n operation on the second value formed from the address (e.g., using div-n circuitry 130 and potential information from mod-n circuitry 130). In addition, the routing circuit is configured to generate multiple selection signals (e.g., selection signal 150) based on a first hash value and a second hash value that can be used to select a particular storage location.

[0039] Consider an example where the requested address is a 10-bit value 01 0101 1110 (in the form [9:0]). Assume only bits [8:2] are of interest, and bits [8:7] are bits 106f, bits [4:2] are bits 106s, and bits [6:5] are bits 106i. In some implementations, this can be achieved using mask values ​​and combinational logic including AND functions (or their equivalents). Figure 1 Blocks 128 and 138 are shown. In this example, the binary mask value 01 1001 1100 can be ANDed with a 10-bit address, where the most significant bit [9] and the two least significant bits [1:0] are discarded. (Alternatively, only bits [8:2] can be ANDed with the 7-bit mask 1100111.)

[0040] The following text is about Figures 4A to 4D (When n=3) and Figures 6A to 6D (In the case of n=15) the potential structure and exemplary operation of the mod-n circuit 130 are further described. Similarly, the following section discusses... Figures 5A to 5D (When n=3) and Figures 7A to 7D (In the case of n=15) the potential structure and exemplary operation of the div-n circuit 140 are further described. However, Figure 1 Not limited to the cases of n=3 and n=15, these cases are provided as examples of values ​​of n that are not powers of two in the specific implementation.

[0041] Figure 2 An exemplary resource set 110 is illustrated. Here, resource set 110 corresponds to the memory system of computer system 100. The memory system has a topology 200, which includes five dimensions: memory controller dimension 212A, memory plane dimension 212B, memory bank dimension 212C, memory row dimension 212D, and memory column dimension 212E. Any type and number of dimensions are possible; the memory system is simply shown for illustrative purposes. In this hierarchical structure, a "memory plane" is a combination of the memory banks and the associated caches for those memory banks. This arrangement can produce a more scalable memory than a single cache for all memory banks. Each memory plane may also have its own independent memory pipeline.

[0042] Consider a request for memory location 220 based on address 104. To select memory location 220, five routes must be made, one for each dimension. First, routing is performed for dimension 212A. In this example, dimension 212A includes two memory controllers 214A-214B. Second, routing is performed for dimension 212B. In this example, dimension 212B includes three memory planes: 0, 1, and 2. Next, routing is performed for dimension 212C. Dimension 212C includes multiple memory banks ranging from 0 to z. Once the memory banks are selected, routing is performed for dimensions 212D (rows) and 212E (columns).

[0043] The portions of address 104 can be used to make various routing decisions for topology 200. For example, a single bit of address 104 can be used to select memory controller 0 or 1. In some computer systems, the number of options for routing decisions for each dimension of topology 200 can all be powers of 2 (e.g., 2 options in one dimension, 4 options in another, and 16 options in yet another). However, different versions of computer systems may have different configurations. Therefore, while computer topologies are typically organized around powers of two, there may be desirable configurations where the topology has dimensions with a number of options that are not powers of two. For example, as... Figure 2 Dimension 212B, as shown, has three options. The expectation of expanding the memory hierarchy by adding another plane to an existing topology with only two planes can inspire this topology.

[0044] One possible solution is to use two bits to select the memory plane. Two bits can encode four possibilities (00, 01, 10, 11). However, the inventors have recognized that this method will create "holes" in the memory space, as one of the four possibilities will never be selected. Another approach could be a complete redesign of the routing logic. However, since topology 200 could be a revision of a previous topology (e.g., the only change might be the addition of a third memory plane), it is advantageous to retain a portion of the existing routing logic rather than completely redesigning it from scratch. Therefore, the techniques disclosed herein are particularly useful for modifying existing designs that are configured to select resources from topologies in which all levels have options that are powers of two. These techniques can thus be used to change one or more levels to have options with a number that is not a power of two, without affecting those parts of the design that process levels unaffected by topology changes.

[0045] Figure 3A Example 300 provides routing in a topology comprising three memory planes, four memory banks per plane, and four columns and two rows per memory bank. Therefore, there will be 3 × 4 × 4 × 2 = 96 possible routes, which can be represented as 0 to 95d. Example 300 illustrates how a route can be routed for the value 95.

[0046] In Example 300, address 104 (which in one implementation may be a physical address) has 7 bits, which are arranged as follows: Figure 3A The format shown is [6:0]. Bits 6 and 5 correspond to... Figure 1 The set of bits in y1 is 106f (denoted as y2 here), while bit 0 corresponds to the set of bits 106s (denoted as y1 here). The presence of a single bit in y1 indicates that a "set" can have one or more bits. Bits 4, 3, 2, and 1 correspond to... Figure 1 The bit set in the middle is 106i.

[0047] Bits 3 and 4 are used for routing the bank dimension with 4 options, while bits 1 and 2 are used for routing the column dimension, which also has 4 options. An XOR hash can be applied to bits 3 and 4 to determine their values ​​(e.g., address 104 can be masked consecutively with 0001000b and 0010000b to determine the values ​​of bits 3 and 4). This technique results in routing for bank 3. Similarly, an XOR hash can be applied to bits 1 and 2, resulting in routing for column 3 of bank 3.

[0048] The memory plane dimension and row dimension are calculated in different ways. Block 128 applies a mask value M to address 104 to generate a first value 129. In example 300, M is 1100001b, which has the effect of producing a 7-bit value, where bits 1 to 4 will necessarily be 0. Therefore, the mask M in this example has the effect of clearing bit 106i from address 104. If a corresponding 1 exists in address 104, bits 0, 5, and 6 will be 1. Since address 104 equals 1011111, 1 exists at bits 0 and 6, but not at bit 5. Therefore, applying the mask value M to address 104 produces 1000001 for the first value 129, which is equivalent to 65d. Then, mod-3 circuit 130 can estimate mod 3 (65), which produces the value 2.

[0049] In Example 300, the routing determination for the row dimension is computed in a slightly similar manner. Block 129 applies the mask value M to address 104 to generate a second value 139 that is the same as the first value 129 (65d). The bit extraction function can then be performed to obtain bits 6, 5, and 0 of the second value 139 (101b or 5d). The div-3 circuit 140 can then estimate div 3 (5), which produces a value of 1 for the row dimension.

[0050] Therefore, 95d in Example 300 is routed to memory plane 2, memory bank 3, row 1, and column 3.

[0051] In Example 300, the same mask value is used to generate the first value 129 and the second value 139. However, the inventors have recognized that in some cases it may be desirable to use a larger number of bits for one dimension. The inventors have found that this method adds entropy to the hash.

[0052] Figure 3B Provides usage and Figure 3A Example 310 uses the same topology and address value (95d) as Example 300. However, in Example 310, two different mask values ​​are used to generate the first value 129 and the second value 139. The mask value M2 used for the row dimension is the same as the mask value M (1100001) in Example 300. However, the mask value M1 used for the plane dimension includes more bits. M1 = 1100 11 1, where the underlined part is relative to M / M2.

[0053] Therefore, given the form as <y1iiiiy2>The address of y1 (106f) and y2 (106s) represents the bits that are not masked in the original mask, and iiii (106i) represents the middle bit. Additional middle bits i can be added to the mask to increase the hash entropy.

[0054] Therefore, the first value 129 in Example 310 is 71d, which also leads to the selection of plane 2. The second value 139 is calculated in the same way as in Example 300, and thus also leads to the selection of row 1. Therefore, 95d in Example 310 is also routed to memory plane 2, memory bank 3, row 1, and column 3.

[0055] Blending

[0056] Another design problem is aliasing, where two different addresses hash to the same set of routing decisions. For example, aliasing occurs when two different addresses hash to the same plane, memory bank, row, and column. The inventors have determined that certain constraints can be applied to the selection of the bits in the address used for routing decisions and to the selection of the mask used.

[0057] These constraints can vary in different applications. Consider... Figures 3A to 3B Continuing the example of a hierarchical memory structure, addresses are encoded for memory planes (determined by mod-n operations), memory rows (determined by div-n operations), memory volumes (determined by XOR hashes), and memory columns (determined by XOR hashes). A set of possible constraints on the hashes includes four separate constraints. First, the mask (M...) for the plane dimension... p ) equals row dimension (M) r ), or in M r The bit set in M ​​is p A subset of the bits set in M. For example, M r It can be 110 0001b, and M p It can be 110 0111b. Second, relative to M r In M p Any additional bits set in the address should belong to the memory column dimension. Consider a 7-bit address of the form [6:0], where bits [6:5] correspond to y2, bits [4:3] correspond to the bank dimension, bits [2:1] correspond to the column dimension, and bit [0] corresponds to y1, where y2+y1 jointly encodes the plane dimension and the row dimension. In this scenario, 110 0001b and 110 0111b are M r and M p The effective value. Third, although in M r and M p In M, any number of groups are allowed (a "group" is a continuous set of bits set to 1), but in M... p Between any two groups, there must be an even number of zeros. Therefore, under this constraint, 110 0001b and 110 0111b are also M respectively. r and M p The effective value, because in M p In =110 0111b, there are two zeros between two groups. Fourth, M r and M p The highest and lowest bits in M ​​are the same, and in M r Between the highest and lowest groups, M p There must be an even number of extra ones in M. Again, M r =110 0001b and M p =110 0111b satisfies this constraint. M r The highest and lowest groups are shown below: 11 0 000 1 b. Among these groups, M p There are two extra ones: 110 0 11 1b.

[0058] Figure 3C Example 320 is provided, where M r and M p This violates the constraints listed above. In particular, constraint 3 is not followed because there is an odd number of zeros between y2 and y1. For example... Figure 3C As can be seen from this, for M r and M p These values, 2 and 32 (in decimal), will be hashed to the same plane (2), storage (0), row (0) and column (0).

[0059] Various other constraints can be applied to other settings. For example, for an intermediate bit set 106i that separates the more valid first bit set 106f (which may also be referred to as y2) from the less valid second bit set 106s (y1), the anti-aliasing constraint may require an even number of zeros and ones between y2 and y1.

[0060] Figure 3D An example illustrating how aliasing can occur is provided. Example 330 addresses a simple scenario with three memory planes, each with four banks, each bank with four rows and each row with four columns. Eight-bit addresses (in this case, the physical address (PA)) are used to encode the memory rows (bits [7:6]; labeled y2), banks (bits [5:4]; b), planes (bits [3:2]; p), and columns (bits [1:0]; c). Note that two bits are used to encode the plane dimensions. Also note that constraint 1 is violated because M... r =1100 0000b and M p =000 1100b. In M r The bit set in M p The bits set in it are completely different. In fact, it is different from... Figures 3A to 3B In contrast to the illustrated example, the hash in the planar dimension has been decoupled from the hash in the row dimension. For example, in Figure 3D As can be seen, this leads to aliasing: for M r and M p These values, 0 and 12 (in decimal), will be hashed to the same plane (0), storage (0), row (0), and column (0).

[0061] therefore, Figure 3D This illustrates the problem when attempting to hash a single dimension of options having a number that is not a power of two from a group of address bits. For the case n=3, using one bit is insufficient to generate 3 possible options. For example... Figure 3D As illustrated, using two (or more) bits for the mod-3 algorithm is problematic. Figure 3D This demonstrates that performing a two-dimensional hash independently on two distinct bit groups with a number of options that are not powers of two in one dimension can result in aliasing.

[0062] This problem is particularly problematic for physical memory. Consider, for example... Figure 3D A set of 8-bit values ​​that address rows, banks, planes, and columns, where each 8-bit value is distinct. Each 8-bit value should address different combinations of rows, banks, planes, and columns. If not... Figure 3D In cases like these, aliasing caused by conflicting mappings (rewrites, incorrect data, etc.) can lead to data problems. This aliasing can also result in certain portions of physical memory being unused.

[0063] However, the method disclosed herein avoids these problems by encoding the first and second dimensions using bit sets (e.g., <106f>, <106i>, <106s>), where the first dimension has n options (where n is not a power of two) and is determined by a mod-n operation, and where the second dimension is determined by a div-n operation. This method avoids aliasing because for sets of dissimilar address values ​​(e.g., 8-bit values), the combination of mod-n and div-n will produce dissimilar values.<mod-n, div-n> In other words, given two distinct address values ​​a1 and a2, and n is an integer greater than two, the result will not be mod n(a1) = mod n(a2) AND div n(a1) = div n(a2). In short, given distinct inputs, the combination of mod-n and div-n will produce a unique combination of mod-n / div-n (and...). Figure 3D different).

[0064] Therefore, address aliasing should not occur if a suitable set of constraints specified at design time is followed. In some embodiments, routing circuitry 120 may also include checking circuitry that verifies at runtime whether constraints are being violated or whether conditions that could lead to aliasing exist. Such circuitry may have constraints / conditions stored in memory and may execute a program to verify that each constraint / condition is satisfied at different points in time (e.g., before routing operations are allowed to occur).

[0065] Specific implementation of mod 3 and div 3

[0066] There are various ways to achieve this. Figure 1 The arithmetic circuit 126 shown contains a mod-n circuit 130 and a div-n circuit 140. A possible specific implementation for n=3 (meaning circuit 130 calculates the mod-3 operation and circuit 140 calculates the div-3 operation) relies on the understanding that mod-3 and div-3 operations on numbers with a first bit width can be performed by performing mod-3 and div-3 operations on sub-parts of numbers with a second smaller bit width. This method can be implemented using combinational and / or sequential logic, and in some cases, using lookup tables (LUTs). LUTs eliminate the need for full modulo and division circuitry, which can be expensive in terms of effective chip area.

[0067] Consider a bit width of 2 k+1 binary number z ,in z The highest effective half of the digits is determined by x It means, and z The least significant half of the bits are determined by y This indicates that for a 16-bit bit width, k=3; for an 8-bit bit width, k=2. In either case, The inventors have recognized that mod 3 can be found using the following formula ( z ) and div 3( z ):

[0068] (1) ;as well as

[0069] (2) .

[0070] It can be seen that equation (1) depends on the constituent parts. x and y The mod-3 value, while equation (2) depends on x and y Both mod-3 and div-3 values.

[0071] As an example of mod-3 and div-3 calculations for 8-bit numbers, consider z =19d(0001 0011b), where x =1d=0001b and y =3d=0011b. The mod 3 can be determined by querying the LUT. x =1, div 3( x )=0, mod 3( y )=0 and div3( y =1.

[0072] Equation (1) can be estimated as follows to determine mod 3 ( z =19d):

[0073] .

[0074] On the other hand, equation (2) can be decomposed into multiple components:

[0075] ;

[0076]

[0077]

[0078] ;as well as

[0079] .

[0080] therefore, div 3 (z=19d) can be estimated as follows:

[0081]

[0082] As mentioned earlier, LUTs facilitate the calculation of mod-n and div-n values. Figure 4A An implementation of LUT 410 is shown, which includes a mod 3 value for each possible 4-bit binary number and can be used for mod-3 and div-3 operations. LUT 410 is also referred to as LUT3-M to indicate that it stores mod-3 values, distinguishing this LUT from other LUTs discussed later. LUT 410 can be used by adopting... z The equation (1) of the constituent parts is used to address the z The maximum value is calculated modulo 3. LUT 410 is relatively small and can advantageously provide fast lookup time.

[0083] Figure 4B Method 420 is illustrated, where a LUT 410 can be used for 16-bit values ​​(referred to as LUT 410). z Calculate mod 3. At position 422, z Divided into four 4-bit vectors z 1 ( z [15:12]), z 2 ( z [11:8]), z 3 ( z [7:4]) and z 4 ( z [3:0]). At position 424, use LUT 410 to target... z 1 to z 4. Calculate mod 3; store these values ​​as m1 to m4, such that m1 = mod 3. z 1) m2 = mod3 ( z 2) etc. In 426, equation (1) is used to combine m1 and m2 for { z 1, z 2} Calculate mod 3, and combine m3 and m4 to target { z 3, z 4) Calculate mod 3. The value m5 is calculated by performing a lookup in LUT 410 to calculate mod 3 for the sum of m1 and m2. Similarly, the value m6 is calculated by performing a lookup in LUT 410 to calculate mod 3 for the sum of m3 and m4. (Since m1 to m4 have a maximum value of 2, the sum of m1+m2 and m3+m4 will not exceed 15, and therefore the mod-3 of these sums can be found in LUT 410.) This process is repeated in 428, which includes performing a lookup in LUT 410 to calculate mod 3 for the sum of m5 and m6. The result is mod 3( z ).

[0084] This method can be applied to any width of z Implementation. Specifically, given input... z Leading zeros can be used for padding. z To obtain a width of The vector. Next, z The block can be divided into four consecutive bits. Then, for each of the four consecutive bits, a LUT can be used to compute div 3 and mod 3. Consecutive 4-bit block pairs can be combined to compute div 3 and mod 3 for an 8-bit block according to equations (1) and (2). Subsequently, consecutive 8-bit block pairs can be combined to compute div 3 and mod 3 again for a 16-bit block according to equations (1) and (2). The process of combining adjacent block pairs is repeated until the result is of length . z Until the value is reached.

[0085] Method 420 thus exemplifies the modulo-n operation where n=3. Method 420 includes determining the equality sub-part for the first value at 422 ( z 1 to z 4) The modulo-n value of each of the following yields the current set (m1 to m4) of modulo-n results. Method 420 then includes combining pairs of the current set of modulo-n results at 424 (e.g., combining m1 / m2 and combining m3 / m4) to obtain a new set (m5, m6) of modulo-n results with a larger number of bits than the previous modulo-n results, wherein the new set of modulo-n results becomes the current set of modulo-n results. Furthermore, method 420 includes repeating the combination of the current set of modulo-n results at 426 until the new set of modulo-n results has a single modulo-n result (m6) at the output of 428, which is the final result of the modulo-n operation on the first value. In some embodiments, the combination at 424 includes combining with the first sub-part of the address (denoted as...). x ) and the immediately following lower significant sub-part of the address (represented as y Given a pair of the current set of results corresponding to modulo-n, and combined by computing the expression mod n(mod n( x )+mod n( y To generate a new set of corresponding results modulo-n.

[0086] Figure 4C This example demonstrates how to use method 420 to calculate mod 3 of a specific number, in which case, z =55,618d, which can also be written as 1101 1001 0100 0010b. z The value can be divided by three 18,539 times, leaving a remainder of 1. The same result can also be calculated using method 420. In 422, the 16-bit value is divided into four parts, and in 424, LUT 410 is used to calculate the mod-3 values ​​m1 to m4 (1, 0, 1, and 2 respectively) using equation (1). This process is repeated in 426 because m1 is added to m2, and then LUT 410 is used to calculate mod 3 over the sum, resulting in m5=1. Similarly, m3 is added to m4, and then LUT 410 is used to calculate mod 3 over the sum, resulting in m6=0. Finally, in 428, m5 is added to m6, and LUT 410 is used again to calculate mod 3 over the sum, resulting in mod 3( z =55,618)=1.

[0087] Method 420 can be used to calculate mod 3 for any 16-bit binary number. Furthermore, method 420 can be extended to calculate mod 3 for even larger values.

[0088] Figure 4D An implementation of the mod-3 circuit 130-3 is illustrated. This mod-3 circuit takes a first value 129 (which is a 16-bit value) as input and computes a 4-bit version of the mod-3 of the first value 129 as a route selection 132 for dimension a. As shown, the mod-3 circuit 130-3 can use an adder and a LUT3-M (in... Figure 4D This is achieved using the reference numerals 410A to 410G.

[0089] The mod-3 circuit 130-3 stores the first value in register 430A, and this first value is represented as a variable. z .Then, z It is divided into four 4-bit vectors, 432A to 432D, representing respectively z [15:12]), z [11:8]), ( z [7:4]) and ( z [3:0]). Vectors 432A to 432D are then provided to LUT3-M modules 410A to 410D. Each of the lookup table modules 410 returns a mod-3 value as outputs 436A to 436D (also represented as m1 to m4). This method eliminates the complexity of custom mod-3 circuitry and is feasible because only a small number of values ​​exist in the lookup table. The values ​​436A and 436B (m1 and m2) are summed using adder 438A, and the 4-bit sum 439A is provided to another lookup table 410E, which outputs the value 440A (m5), which corresponds to the mod-3 value of 432A cascaded with 432B (i.e., z [15:8] Similarly, 436C through 436D (m3 and m4) are fed to adder 438B to produce a 4-bit sum 439B, which is then fed to another lookup table 410F, which outputs 440B (m6). This value corresponds to the mod-3 value of 432C cascaded with 432D (i.e., z [7:0]). Next, adder 438C is used to sum 440A and 440B (m5 and m6) to output a 4-bit sum 439C. The sum 439C is then provided to lookup table 410G, which outputs a 4-bit routing option 132, which corresponds to the mod-3 value of the first value 129. For example, this value can be used for... Figure 1 Routing selection within the context of dimensions.

[0090] In some implementations, the mod-3 circuit 130-3 can be used as a stand-alone circuit outside of the arithmetic circuit 126, which is used to find the mod-3 value of any 16-bit input. Similarly, its output can be wired to any other circuit to efficiently generate a mod-3 value for a given input. In some implementations, other computational components are used to achieve the same operation. For example, a demultiplexer can be used to convert the value in register 430A... z Divided into four equal vectors. The mod-3 circuit 130-3 can be implemented as a combinational circuit, but in other embodiments, the mod-3 circuit can be a sequential circuit, whose sub-components (e.g., registers 430A, LUTs 410A to 410G) are clocked. In the embodiments below, LUTs 410A to 410G are all individual LUTs, each with its own I / O, but in other embodiments, a single LUT (or more) Figure 4D A smaller number of LUTs can be used to compute mod-3 for all 4-bit values. In another implementation, LUTs can be used to simplify even more computations. For example, by storing the computation of mod-3 ( z 1+ z 2) Instead of calculating 436A to 436B, 439A and 440A independently, all possible values ​​can be replaced by a single 16-bit LUT, replacing LUTs 410A to 410B and adder 438A.

[0091] Turn Figures 5A to 5D LUT 410 can also be used in conjunction with other LUTs to calculate div 3 according to equation (2). z ). Figure 5A It shows that it can be used in div 3 ( z One implementation of the operation uses multiple LUTs. LUT 510A (also known as LUT3-D4) includes a div 3 value for each 4-bit binary number. When x and y When each bit is 4, LUT 510B (LUT3-D8) includes the value of component (2.4) of equation (2). When x and y When each bit is 8, the LUT 510C (LUT3-D16) includes the value of component (2.4). When x and y When each is 16 bits, LUT 510D (LUT3-D32) includes the value of component (2.4). LUTs 510A to 510D can be used by employing about z Equation (2) of the constituent parts is used to target z The maximum value is calculated using div 3.

[0092] Figure 5B Method 520 is illustrated, where LUTs 410 and 510 can be used to compute div3 for 16-bit values. z Similar to method 420, method 520 begins at 522, where z Divided into four 4-bit vectors z 1 ( z [15:12]), z 2 ( z [11:8]), z 3 ( z [7:4]) and z 4 ( z [3:0]). At position 524, use LUT 410 to target... z 1 to z 4. Calculate mod 3, and use LUT510A to target z 1 to z 4. Calculate div 3; these values ​​are stored as m1 to m4 and d1 to d4, such that m1 = mod 3. z 1) m2 = mod3 ( z 2) d1=div3( z 1) d2 = div3( z 2) etc. In 526, equation (1) is used to combine m1 and m2 to find m5, and to combine m3 and m4 to find m6 (as in 426 of method 420). Equation (2) uses d1, d2, m1, and m2 to target { z 1, z 2} Calculate div 3 (d5), and use d3, d4, m3, and m4 to target { z 3, z 4} Calculate div 3 (d6). This process is repeated in 528, which involves performing a lookup in LUT 510C to calculate the component (2.4) of equation (2) and summing it with d5*16 and d6. The result of the summation is div 3 ( z ).

[0093] With mod 3 ( z Similarly, if a proper LUT is implemented, then div 3( z It can be used for any width. of z To achieve. For example, when z When it's 32-bit, LUT 510D can be used to find div 3 ( z Various widths of LUTs can be used in the arithmetic circuit 126 of the routing circuit 120 as needed.

[0094] Method 520 thus exemplifies the div-n operation where n=3. Method 520 includes determining the equality sub-parts for the values ​​(from 522). z 1 to z 4) calculates the div-n value for each of the elements, thus producing the current set of div-n results at position 524. For example, this value here could be from... Figure 1 The second value is 139. (Note that there may be values ​​for...) z 1 to z The mod-n value of 4. These may be determined individually in some implementations, or "borrowed" from the execution of method 420 in other implementations. Method 520 continues at 526 by combining pairs of the current set of div-n results to obtain a new set of div-n results with a larger number of bits than the previous div-n results, the new set of div-n results becoming the current set of div-n results. In some implementations, when calculating a value with a bit width of 2... 2^k+1 When the output div value (e.g., the second value 139) is obtained, the given pair of the current set of the div-n result includes the first sub-part of the address (x') and the immediately following lower significant sub-part of the address (y'), and combining the given pair includes the expression div n(x')•2. 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y')) to generate the corresponding one in the new set of div-n results. In addition, method 520 includes repeating the combination of the current set of div-n results at 528 until the new set of div-n results has a number of bits equal to the number of bits of the second value, which produces the div-n of the input value.

[0095] Figure 5C This example demonstrates how to use method 520 to calculate div 3 with respect to a specific number. z =55,618d, which can also be written as 1101 1001 0100 0010b. In 522, the 16-bit value is divided into four parts, and in 524, LUT 410 is used to calculate the mod 3 values ​​m1 to m4 (1d, 0d, 1d, and 2d respectively) using Equation 1. In addition, LUT 510 is used to calculate the div 3 values ​​d1 to d4 (4d, 3d, 1d, and 0d respectively). This process is repeated in 526 because LUT 410 is used to find the mod 3 for m1+m2 and m3+m4, thus producing m5=1 and m6=0 respectively. LUT 510B is used on m1 and m2 to find the component (2.4), while d1*16 is the component (2.1) and d2 is the component (2.2) of Equation (2), which produces d5. Similarly, LUT 510B is used on m3 and m4 to find component (2.4), which is applied to equation (2) to produce d6. Finally, in 528, equation (2) is applied by adding d5*256, d6, and the results of a table lookup on LUT 510C for the sum of m5 and m6, which produces div 3(55,618d)=18,539d.

[0096] Method 520 can be used to compute div 3 for any 16-bit binary number. Additionally, Method 520 can be extended to compute div 3 for larger values. Such computations can be performed using a circuit comprising a set of adders, LUT 410, and LUT 510, where the additional LUTs depend on the width of the input value.

[0097] Figure 5D An implementation of the div-3 circuit 140-3 is illustrated, which generates a 4-bit div-3 value from the input second value 139, thereby outputting a routing choice 142 for dimension b.

[0098] The div-3 circuit 140-3 receives the second value 139, which is 16 bits long, and uses it as... z Stored in register 530. Value z It is divided into four 4-bit vectors, 531A to 531D: z 1 (which includes) z [15:12]), z 2 (which includes) z [11:8]), z 3 (including) z [7:4]) and z 4 (which includes) z [3:0]). Circuit 140-3 also receives from mod-3 circuit 130-3 targeting z 1 (m1, indicated by reference numeral 535A in the attached diagram) z 2 (m2, indicated by reference numeral 535B in the attached map), z 3 (m3, indicated by reference numeral 535C in the attached diagram) and z The mod-3 value is 4 (m4, indicated by reference numeral 535D). Furthermore, circuit 140-3 also receives mod-3 values ​​m5 (reference numeral 535E) and m6 (reference numeral 535F) from mod-3 circuit 130-3, which are respectively for... z The mod-3 values ​​of the most significant 8 bits and the least significant 8 bits in the data.

[0099] First, the operation of circuit 140-3 is described at a higher level. Circuit 140-3 initially uses equation (2) to address... z The two halves of div 3 are calculated, where the value is... z Has composition value x and y .for z The "left" half z 1 corresponds to x and z 2 corresponds to y For these values ​​using equation (2), div 3 is d5, indicated by reference numeral 547A in the attached diagram. Similarly, for z The "right" half z 3 corresponds to x and z 4 corresponds to y For these values ​​using equation (2), div 3 is d6, indicated by reference numeral 547B in the attached diagram. This process is then repeated for... z =d5 / d6 cascade calculation div 3, where d5 is the component value x And d6 is a component value. y Equation (2) outputs route selection 142 for these values, which can be used in dimension b.

[0100] Now we can explain the operations of each of these div 3 calculations in more detail. For the left half of the second value 139 (by... z 1 and z 2. Calculate div 3 using equation (2). In this equation, z 1 is x and z 2 is y The element (2.1) of this equation is generated by the LSL-4 542A. The left shift circuit 542A receives the output of the LUT3-D4 510A-1 (which is div 3( x The input is shifted left by 4 bits to generate d1*16 or 533A. Element (2.2) of equation (2) is generated by LUT3-D4 510A-3, which is div 3(y), indicated by the reference numeral 534A. Furthermore, element (2.4) of equation (2) is generated by LUT3-D8 510B-1. (As...) Figure 5A As shown, lookup table 510B-1 takes two inputs: mod 3 ( x (also known as m1) and mod 3 ( y (also known as m2), and then outputs div 3, which is the sum of 1) m1 shifted left by 4 bits and 2) m2. This output is indicated by reference numeral 536A. Adder 547A then sums 533A, 534A and 536A to produce d5 (reference numeral 548), which is div 3 for the left half of the second value 139.

[0101] In order to target the right half of the second value 139 (by...) z 3 and z 4. Calculate div 3, and then use equation (2) again. In this equation, z 3 is x and z 4 y The element (2.1) of this equation is generated by the LSL-4 542B. The left shift circuit 542B receives the output of the LUT3-D4 510A-2 (which is div 3( x ), and shift the input left by 4 bits to generate d3*16 or 533B. The element (2.2) of equation (2) is generated by LUT3-D4 510A-4, which is div 3( y ), indicated by reference numeral 534B in the attached diagram. Furthermore, element (2.4) of equation (2) is generated by LUT3-D8 510B-2. For example Figure 5A As shown, lookup table 510B-2 takes two inputs: mod 3 ( x (also known as m3) and mod 3 ( y (Also known as m4), then outputs div 3, which is the sum of 1) m3 shifted left by 4 bits and 2) m4. This output is indicated by reference numeral 536B. Adder 547B then sums 533B, 534B, and 536B to produce d6 (reference numeral 554), which is div 3 for the left half of the second value 139.

[0102] Next, circuit 140-3 calculates div 3 by applying equation (2). z ),in z [15:8] Composition Values x ,and z [7:0] Composition Value y In summary, equation (2) is the sum of components (2.1), (2.2), and (2.4). The bit width of the calculated div 3 value is 16 bits; therefore, for this application of equation (2), k=3. Component (2.1) is the div 3 ( x Multiply by The left-shifted version. This is equivalent to making div 3 ( x Shift left by 8 bits. Circuit 140-3 has already calculated d5 as div 3 ( x Therefore, component (2.1) is calculated by shifting d5 (labeled 548) to the left to obtain the value 552. Component (2.2) of equation (2) is div 3 ( y It has already calculated d6 as div 3 ( y (See attached figure 554). Finally, the component (2.4) of equation (2) is calculated by LUT3-D16 (510C), which receives mod 3 ( x (m5) and mod 3 ( y (m6) is taken as input. The output of lookup table 510C is indicated by reference numeral 556 in the attached figure. In the case of calculating its components, equation (2) can therefore be calculated by summing values ​​552, 554 and 556 using adder 558 to produce div 3(z), which is route selection 142, which can be used for route dimension b.

[0103] Specific implementation of mod 15 and div 15

[0104] Another possible routing paradigm that is not a power of two is based on mod 15 and div 15. As shown below, elements that use the mod 3 / div 3 approach can be reused here. These two examples illustrate how a design can be adapted to any desired number of routing options that are not powers of two.

[0105] The inventors have recognized that mod 15 can be found using the following formula. z ) and div 15( z ),in z With a bit width of 2 k+1 The calculated z The most significant half of the value is determined by x It means, and z The least significant half of the bits are determined by y This indicates that, makes :

[0106] (3) ;as well as

[0107] (4) .

[0108] It can be seen that equation (3) depends on the mod-15 values ​​of the components x and y, while equation (4) is slightly more complex.

[0109] Equation (4) is the sum of the four components:

[0110] ;

[0111]

[0112]

[0113]

[0114] ;as well as

[0115] .

[0116] Depends on the combination x and y The magnitudes of k and n will have different values. x and y When each has 4 digits, n=4 and k=2. When... x and y When each bit is 8, n=8 and k=3.

[0117] Similar to the mod 3 / div 3 example, LUTs facilitate the calculation of mod 15 and div 15 values. Figure 6A An implementation of LUT 610 (also known as LUT15-M) is shown, which includes a mod 15 value for every possible 4-bit binary number. Therefore, LUT 610 enables fast computation of mod 15 for any 4-bit number.

[0118] As shown in equation (3), find the target z Mod 15 requires finding a mod that is compatible with mod 15. x ) and mod 15 ( y The sum of () mod 15. This sum can be wider than 4 bits. For example, if mod 15( x ) = 7 and mod 15 ( y If ) = 14, then mod 15( x )+mod 15( y =21, which is 10101b.

[0119] Figure 6A Function 611 (also known as mod15-F) describes the estimation of mod 15 ( x )+mod 15( y One possible way. The function shows the calculation of two different four-digit values: (1) tmp_mod15, which is equal to mod 15( x )+mod 15( y ), and (2) tmp_mod15_p1, which is equal to mod 15( x )+mod 15( y )+1, or add one to formula (1). Additionally, cout is the carry value of the most significant bit of tmp_mod15_p1, indicating a sum greater than 15. If cout=0, then tmp_mod15 is chosen as mod 15 ( z On the other hand, if cout=1, then tmp_mod15_p1 is chosen as mod 15(z). The operation of this function can be seen by considering several examples. If... x =7 and y =7, then tmp_mod15=14, tmp_mod15_p1=15, and cout=0. Because cout=0, tmp_mod15(14) is chosen as mod 15( z ).if x =7 and y =8, then tmp_mod15=15, tmp_mod15_p1=0 (this is a four-bit output, a five-bit output would be 10000b), and cout=1. Because cout=1, tmp_mod15_p1(0) is chosen as mod 15( z Finally, if x =7 and y =9, then tmp_mod15=16, tmp_mod15_p1=1 (this is a four-bit output, a five-bit output would be 10001b), and cout=1. Because cout=1, tmp_mod15_p1(1) is chosen as mod 15( z ).

[0120] Used to calculate mod 15 ( z One possible hardware implementation of function 611 is circuit 612. As shown in the figure, mod 15 ( x (Illustrated version 613A) and mod 15 ( y (Ref. 613B in the attached diagram) is supplied to adder 614, which generates two 4-bit outputs: sum 616A (equivalent to tmp_mod15 in function 611) and sum_p1 616B (equivalent to tmp_mod15_p1 in function 611). Adder 614 also generates cout 616C (carry value) for the calculation of sum_p1 616B. sum 616A and sum_p1 616B are supplied to multiplexer 617, which receives cout 616C as a selection signal. If cout 616C = 0, sum 616A is selected as output 618 to represent mod 15 ( z On the other hand, if cout 616C=1, then sum_p1 616B is chosen as the output 618 to represent mod 15. z This specific implementation avoids using a larger LUT.

[0121] In other possible hardware implementations, adder 614 is a composite adder that further optimizes circuitry 612. Instead of two separate "classical" addition operations (as shown in function 611), this composite adder can compute both tmp_mod_15 and tmp_mod_15_p1 using a single composite addition operation. Using a composite adder reduces the total number of operations required to implement function 611.

[0122] Figure 6B Method 620 is illustrated, in which LUT 610A and function 611 (which can be implemented by circuit 612) are used to calculate mod 15 for a 16-bit value. z At position 622, z Divided into four 4-bit vectors z 1 ( z [15:12]), z 2 ( z [11:8]), z 3 ( z [7:4]) and z 4 ( z [3:0]). At position 624, use LUT 610 to target... z 1 to z 4. Calculate mod 15; store these values ​​as m1 to m4, such that m1 = mod 15. z 1) m2 = mod 15 ( z 2) etc. In 626, function 611 is used to implement equation (3), which combines m1 and m2 to apply to { z 1, z 2} Calculate mod 15, and combine m3 and m4 to target { z 3, z 4) Calculate mod 15. The value m5 is calculated by executing function 611 on m1 and m2, and m6 is calculated by executing function 611 on m3 and m4. This process is repeated in 628, which includes executing function 611 on m5 and m6, which yields mod 15. z This method is applicable to any width. of z accomplish.

[0123] Figure 6C This example demonstrates how to use method 620 to calculate mod 15 of a specific number. z =55,618d, which can also be written as 1101 1001 0100 0010b. z The value can be divided by 15 3,707 times, leaving a remainder of 13. The same result can also be calculated by using mod 15 on the components of z in method 620. In 622, the 16-bit value is divided into four parts, and in 624, LUT 610A is used to calculate the mod-15 values ​​m1 to m4 (13, 9, 4, and 2 respectively). This process is repeated in 626 because m1 and m2 are used in function 611 to calculate mod 15 on the sum, resulting in m5 = 7. Similarly, m3 and m4 are added, and then function 611 is used to calculate mod 15 on the sum, resulting in m6 = 6. Finally, in 628, m5 and m6 are used in function 611 to calculate mod 15 on the sum, resulting in mod 15( z =55,618)=13.

[0124] Method 620 (which is an implementation of method 420) can be used to compute mod 15 for any 16-bit binary number. Additionally, method 620 can be extended to compute mod 15 for larger values. Such computation can be performed using a circuit that includes a set of adders, LUT 610, and implements function 611 (e.g., using circuit 612). Figure 6D This illustrates a possible specific implementation of the mod-15 circuit 130-15. A first value 129 is received as an input value. z Look up tables 610A to 610D (which are...) Figure 6A (The instance of lookup table 610 in the table) then targets z The four four-bit components are calculated modulo 15 and labeled as outputs m1 to m4. m1 and m2 are supplied to... Figure 6A The circuit 612 instance (612A) depicted produces output m5, while m3 and m4 are supplied to the second instance (612B) of circuit 612 to produce output m6. This process is then repeated, as m5 and m6 are supplied to the third instance (612C) of circuit 612. The output of 612C is modulo 15. z The 16-bit value of ) can be used for routing for dimension a.

[0125] LUT 610 (mod 15) x This can be combined with function 611. Figure 7A The other LUTs, left shifters, and adders shown are used to calculate div 15 according to equation (4). z The components of equation (4) can be calculated as follows: the component (4.1) that multiplies the value by a power of two can be implemented by a left shifter, which is used for receiving... z A portion of the output of the LUT 710A (LUT15-D4) is processed (in subsequent states, the component is calculated based on a left shift of d5 (4.1)); the component can be estimated using the LUT 710A (also known as LUT15-D4) (4.2), which includes calculations for mod 15 ( y The component can be estimated using any given value of div 15; depending on the size of the values ​​being combined, the component can be estimated using LUT 710B to 710D (4.3); the component can be estimated using an adder (4.4); and the component can also be estimated using LUT 710A (4.5), which includes values ​​between 0 and 28 (mod 15). x )+mod 15( y The maximum possible sum of the values ​​between div15 values. More specifically, LUT 710B (LUT15-D8) is used to estimate the components (4.3) when combining two 4-digit numbers. (But note that the output of lookup table 710B is the same as the input because div15(16) equals 1. Therefore, in Figure 7D The 710B is not used in the circuit shown. However, it is included. Figure 7A The middle shows with Figure 7C and Figure 7D The lookup table in the lookup table follows a continuous pattern. LUTs 710C (LUT15-D16) and 710D (LUT15-D32) are used to estimate components when combining two 8-bit or two 16-bit numbers (4.3). Figure 7D The example does not use lookup table 710D because the output is 16 bits, which means that only four-bit and eight-bit values ​​are combined.

[0126] Figure 7B Method 720 is illustrated, where LUTs 610 and 710 can be used with function 611 and other hardware to compute div15 for 16-bit values. z Similar to method 620, method 720 begins at 722, where... z Divided into four 4-bit vectors z 1 ( z [15:12]), z 2 ( z [11:8]), z 3 ( z [7:4]) and z 4 ( z [3:0]). At 724, LUT 610 is used to target... z 1 to z 4. Calculate mod 15 and use LUT 710A for... z 1 to z 4. Calculate div 15; these values ​​are stored as m1 to m4 and d1 to d4, such that m1 = mod 3( z 1) m2 = mod3 ( z 2) d1=div3( z 1) d2 = div3( z 2) etc. In 726, function 611 is used to combine m1 and m2 to find m5, and to combine m3 and m4 to find m6. Equation (4) uses d1, d2, m1 and m2 to target { z 1, z 2} Calculate div 15 (d5), and use d3, d4, m3, and m4 to target { z 3, z 4) Calculate div 15 (d6). This process is repeated in 728, which includes summing the following quantities: the lookup entry in LUT 710C used to calculate component (4.3), the lookup entries in LUT 710A used to calculate components (4.2) and (4.5), and a left shift operation on d5 used to calculate component (4.1). The result is div 15 ( z ).

[0127] Figure 7C This example demonstrates how to use method 720 to calculate div 15 with respect to a specific number. z =55,618d, which can also be written as 1101 1001 0100 0010b. In 722, the 16-bit value is divided into four parts, and in 724, LUT 710 is used to calculate the mod 15 values ​​m1 to m4 (13d, 9d, 4d, and 2d respectively). In addition, LUT 710A is used to calculate the div15 values ​​d1 to d4 (all of which are zero). In 726, function 611 is used to find the mod 15 for m1+m2 and m3+m4, thus producing m5=7 and m6=6 respectively. To calculate d5, the components (4.1), (4.2), (4.3), and (4.5) are summed, where (4.5) is div15((4.4) or mod 15( x )+mod 15( y )). Component (4.1) is calculated by left-shifting d1 (which is 0 in this case, and therefore (4.1) is also 0). Component (4.2) is the already calculated d2, which is also 0. For x =m1=13, component (4.3) is calculated by accessing LUT 710B. Component (4.4) is equal to mod 15. x )+mod 15( y =m1+m2=13+9=22. This can be achieved by searching for the corresponding value in LUT 710A. x The value d5 is obtained by taking the value 22 to get the component (4.5), which is 1. The value d5 is therefore equal to 0+0+13+1 or equal to 14. The value d6 is estimated in a similar way to get 4.

[0128] Perform a similar process in 728. To calculate div 15 ( z Then sum the components (4.1), (4.2), (4.3), and (4.5) again. Component (4.1) is calculated by left-shifting d5, which is equivalent to 14*256 (2 8 ) or 3,584. Component (4.2) is the already calculated d6, which is 4. For x =m5=7, by accessing LUT 710C to calculate component (4.3), this yields 119. Component (4.4) is equal to mod 15. x )+mod 15( y =m5 + m6 = 7 + 6 = 13. This is achieved by searching for the appropriate value in LUT 710A. x =13 to obtain the component (4.5), which is 0. Value div 15 ( z Therefore, it equals 3,584+4+119+0 or 3,707.

[0129] With mod 15 ( z Similarly, if a proper LUT is implemented, then div 15 ( z It can be used for any width. of z To achieve. For example, when z When the bit width is 32, LUT 710D can be used to find div 15(z). Therefore, LUTs of various widths can be used in the arithmetic circuit 126 of the routing circuit 120 as needed.

[0130] Figure 7D This is a block diagram of one implementation of circuit 140-15 in div 15. As shown in the figure, circuit 140-15 receives values. z and utilize Figure 7A The lookup table, left shift circuit, and adder described in the text are used to generate the value div 15. z Circuit 140-15 also receives values ​​m1, m2, m3, and m4 from circuit 130-15 (for...). z The mod 15 values ​​of the four four-bit components, and as a reference for z The two halves of the mod 15 values ​​m5 and m6 (also calculated by circuit 130-15).

[0131] It can be seen that, Figure 7D The circuit described in the diagram involves three calculations from equation (4). z The equation is calculated on the "left" half to produce d5, which is the output of adder 760A, whose four inputs are the four components of equation (4). z Equation (4) is recalculated on the "right" half to produce d6, which is the output of adder 760B, which also has four inputs similar to those for adder 760A. (Note that m1 is one of the inputs for adder 760A. This addend is equivalent to component (4.3), but since div 15(16) = 1, div 15(16) * m1 is simply equal to m1. The same observation applies to m3 and adder 760B.) Once d5 and d6 are calculated, equation (4) is estimated again using d5 and d6 along with inputs m5 and m6 from circuit 130-15. The output of adder 760C is div 15( z ), or routing for dimension b, 142.

[0132] Example Method

[0133] Figure 8 This is a flowchart of one embodiment of a method 800 for performing routing for a computer system. In various embodiments, method 800 is performed on the routing circuitry of the computer system.

[0134] Method 800 begins at step 810, which includes a routing circuit (e.g., routing circuit 120) of a computer system (e.g., computer system 100) receiving a request for a specific resource within a resource set (e.g., resource set 110) organized according to a multi-dimensional topology. The request includes an address (e.g., request address 104) having a first set and a second non-overlapping set of bits. The topology has a first dimension (e.g., dimension a) with n routing options and a second dimension (e.g., dimension b) with m routing options, where n and m are both integers greater than two, and where n is not a power of two.

[0135] In some implementations, the first set and the second set of bits are separated within the address by a set of intermediate bits. A first value is formed by masking the address with a first mask value, which includes the first set of bits and the second set of bits separated by the first set of intermediate bits. A second value is formed by masking the address with a different second mask value, which includes the first set of bits and the second set of bits separated by the second set of intermediate bits.

[0136] Method 800 continues in step 820, wherein the routing circuit determines a first route selection (e.g., route selection (a)) for a first dimension by performing a modulo-n operation (e.g., mod-n 130) on a first value formed from an address (e.g., first value 130), the first value comprising a set of first bits and a set of second bits. In some embodiments, the modulo-n operation includes determining a modulo-n value for each of the equal sub-parts of the first value, thereby producing a current set of modulo-n results. After this determination, pairs of the current sets of modulo-n results are combined to obtain a new set of modulo-n results having a larger number of bits than the previous modulo-n results, wherein the new set of modulo-n results becomes the current set of modulo-n results. The circuit then repeats the combination of the current sets of modulo-n results until the new set of modulo-n results has a single modulo-n result, the final result of the modulo-n operation on the first value. In some specific implementations, the given pair of the current set of modulo-n results includes the first sub-part (x) of the address and the immediately following lower significant sub-part (y) of the address, and the corresponding one in the new set of modulo-n results for the given pair is equal to mod n (mod n(x) + mod n(y)).

[0137] Next, in step 830, the routing circuit determines a second route selection (e.g., route selection (b) 142) for the second dimension by performing a div-n (e.g., div-n 140) operation on a second value formed by the address (e.g., second value 139), which includes a first set and a second set.

[0138] In some implementations, the div-n operation includes determining a div-n value for each of the equal subparts of the second value, thereby producing a current set of div-n results. The div-n operation also includes combining pairs of the current set of div-n results to obtain a new set of div-n results with a larger number of bits than the previous div-n results; this new set of div-n results becomes the current set of div-n results. Furthermore, the div-n operation includes repeatedly combining the current set of div-n results until the new set of div-n results has a number of bits equal to the number of bits of the second value. In some specific implementations, a given pair of the current set of div-n results includes a first subpart (x') of an address and the immediately following lower significant subpart (y') of the address. One of the corresponding subparts in the new set of div-n results for a given pair is equal to div n(x') • 2. 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y')), where the second value has a bit width of 2. 2^k+1 .

[0139] In step 840, the routing circuit activates one or more selection signals (e.g., selection signal 150 for dimensions a and b) based on the first and second routing selections. These one or more selection signals can be used to cause a specific resource to be selected in response to a request.

[0140] In some implementations, method 800 may further include checking the constraint set to prevent aliasing. In some cases, checking the second constraint set for the first and second dimensions may include ensuring that the first and second intermediate bit sets each contain an even number of zeros and an even number of ones.

[0141] Example device

[0142] Now for reference Figure 9 A block diagram illustrating an example embodiment of device 900 is shown. In some embodiments, the components of device 900 may be included within a system-on-a-chip. In some embodiments, device 900 may be included in a mobile computing device that may be battery-powered. Therefore, the power consumption of device 900 may be an important design consideration. In the illustrated embodiment, device 900 includes a structure 910, a computing complex 920, an input / output (I / O) bridge 950, a cache / memory controller 945, a graphics unit 975, and a display unit 965. In some embodiments, in addition to or in place of the illustrated components, device 900 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0143] Structure 910 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 900. In some embodiments, portions of structure 910 may be configured to implement various different communication protocols. In other embodiments, structure 910 may implement a single communication protocol, and components coupled to structure 910 may internally switch from a single communication protocol to other communication protocols.

[0144] In the illustrated implementation, computing complex 920 includes a bus interface unit (BIU) 925, a cache 930, and cores 935 and 940. In various implementations, computing complex 920 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 920 may include one, two, or four processor cores, or any other suitable number of processor cores. In one implementation, cache 930 is a set-associative L2 cache. In some implementations, cores 935 and 940 may include internal instruction and data caches. In some implementations, a coherence unit (not shown) in architecture 910, cache 930, or elsewhere in device 900 may be configured to maintain coherence between the various caches of device 900. BIU 925 may be configured to manage communication between computing complex 920 and other elements of device 900. Processor cores (such as cores 935 and 940) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0145] The cache / memory controller 945 can be configured to manage data transfer between the structure 910 and one or more caches and memories. For example, the cache / memory controller 945 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 945 may be directly coupled to memory. In some embodiments, the cache / memory controller 945 may include one or more internal caches.

[0146] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling may include intermediate elements. For example, in Figure 9 In this context, the graphics unit 975 can be described as being "coupled" to memory via structure 910 and cache / memory controller 945. In contrast, in... Figure 9 In the illustrated implementation, the graphics unit 975 is "directly coupled" to the structure 910 because there are no intermediate elements.

[0147] The graphics unit 975 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 975 may receive graphics-oriented instructions, such as OpenGL. ® Metal or Direct3D ® Instructions. The graphics unit 975 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 975 is typically configured to process large blocks of data in parallel and can build an image in a framebuffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 975 may include transformation, lighting, triangle, and rendering engines in one or more graphics processing pipelines. The graphics unit 975 can output pixel information for the displayed image. In various embodiments, the graphics unit 975 may include programmable shader circuitry, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or not).

[0148] Display unit 965 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 965 can be configured as a display pipeline. Additionally, display unit 965 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 965 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0149] I / O bridge 950 may include various components configured to implement functions such as Universal Serial Bus (USB) communication, security, audio, and low-power always-on functionality. I / O bridge 950 may also include interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 900 via I / O bridge 950.

[0150] In some embodiments, device 900 includes network interface circuitry (not explicitly shown) that can be connected to structure 910 or I / O bridge 950. This network interface circuitry can be configured to communicate via various networks, which may be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via WiFi), or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi Direct). In various embodiments, the network interface circuitry can provide device 900 with connectivity to various types of other devices and networks.

[0151] Example Application

[0152] Turn now Figure 10 This illustrates various types of systems that may include any of the circuits, devices, or systems discussed above. The system or device 1000, which may utilize one or more of the techniques described herein in combination with or otherwise, can be used in a wide range of fields. For example, the system or device 1000 may be used as part of the hardware of a system such as a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television).

[0153] Similarly, the disclosed components can be used in wearable device 1060, such as a smartwatch or health monitoring device. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendar, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0154] System or device 1000 can also be used in a variety of other environments. For example, system or device 1000 can be used in an environment of server computer systems (such as dedicated servers) or on shared hardware implementing cloud-based services 1070. Furthermore, system or device 1000 can be implemented in a wide range of dedicated everyday devices, including common household devices 1080 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the "Internet of Things" (IoT). Components can also be implemented in various modes of transportation. For example, system or device 1000 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 1090.

[0155] Figure 10 The applications illustrated are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0156] Example computer-readable media

[0157] Various example circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. Therefore, this disclosure is intended to support claims that cover not only devices including the disclosed circuits, but also storage media specifying circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., integrated circuits) including the disclosed circuits. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not manufacture those designs themselves.

[0158] Figure 11 This is a block diagram illustrating an example non-transitory computer-readable storage medium for storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1120 is configured to process design information 1115 stored on a non-transitory computer-readable medium 1110 and to manufacture an integrated circuit 1130 based on the design information 1115.

[0159] The non-transitory computer-readable storage medium 1110 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as hard disk drives or optical storage devices; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1110 may include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0160] Design information 1115 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1115 can be used by semiconductor manufacturing system 1120 to manufacture at least a portion of integrated circuit 1130. The format of design information 1115 can be recognized by at least one semiconductor manufacturing system 1120. In some embodiments, design information 1115 may also include one or more cell libraries specifying the synthesis, layout, or both of integrated circuit 1130. In some embodiments, design information is specified wholly or partially in the form of a netlist specifying cell library elements and their connectivity. Design information 1115 acquired separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 1115 may specify circuit elements to be manufactured but not their physical layout. In this case, design information 1115 may need to be combined with layout information to actually manufacture the specified circuit.

[0161] In various implementations, integrated circuit 1130 may include one or more custom macrocells, such as memory and analog or mixed-signal circuitry. In this case, design information 1115 may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0162] The semiconductor manufacturing system 1120 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1120 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0163] In various embodiments, integrated circuit 1130 is configured to operate according to a circuit design specified by design information 1115, which may include performing any of the functionalities described herein. Additionally, integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components. Furthermore, the functionalities described herein may be performed by multiple interconnected integrated circuits.

[0164] As used herein, a phrase in the form of "design information specifying the design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy this element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0165] This disclosure includes references to "implementation scheme" or groups of "implementation schemes" (e.g., "some implementation schemes" or "various implementation schemes"). An implementation scheme is a different specific implementation or instance of the disclosed concepts. References to "implementation scheme," "an implementation scheme," and "a particular implementation scheme," etc., do not necessarily refer to the same implementation scheme. A large number of possible implementation schemes are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0166] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantage described herein should not be construed as a claim limitation that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0167] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0168] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the filing of this application (or an application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0169] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations may be claimed in this application or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0170] In appropriate circumstances, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0171] Since the present disclosure is a legal document, various terms and phrases are subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0172] References to items in the singular form (i.e., a noun or noun phrase preceded by "a", "an", or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. A "plurality" of items means a collection of two or more items in the set of items.

[0173] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0174] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to".

[0175] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the statement "x or y" is equivalent to "x or y, or both", and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0176] The phrases "w, x, y, or z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "...at least one of w, x, y, and z" therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0177] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0178] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on certain other factors such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0179] The phrases "responding to" and "responding" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase "responding to B and executing A." This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase "responding" is synonymous with the phrase "at least partially responding to." Similarly, the phrase "responding to" is synonymous with the phrase "at least partially responding to."

[0180] Within this disclosure, different entities (which may be referred to differently as "units," "circuits," other components, etc.) may be described or claimed to be "configured to" perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered "configured" to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured" to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0181] In some cases, various units / circuits / components may be described herein as a collection of entities that perform tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated otherwise.

[0182] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0183] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the “component for [performing a function]” structure to state the elements of the claims.

[0184] Different “circuits” may be described in this disclosure. These circuits or “circuits” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0185] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and disclosed herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular "decoding unit" can be described as having the function of "executing the opcode of a processing instruction and routing that instruction to one or more functional units among a plurality of functional units," meaning that the decoding unit is "configured" to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0186] In various implementations, as described in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0187] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0188] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus, the apparatus comprising: Integrated circuit, the integrated circuit comprising: A set of storage locations arranged according to a hierarchical structure with multiple levels, the multiple levels including a first level with n hash options and a second level with m hash options, where n is an integer that is not a power of two; Hash circuit, the hash circuit being configured as follows: Receive a request to access a specific storage location in the set of storage locations, the request including an address having a first set and a non-overlapping second set; A first value is formed by masking the address with a first mask value, the first mask value including a first set of bits, a second set of bits, and a first set of intermediate bits that separates the first set of bits and the second set of bits; A second value is formed by masking the address with a second mask value, the second mask value including the first bit set, the second bit set, and a second intermediate bit set separating the first bit set and the second bit set; The first hash value for the first level is determined by performing a modulo-n operation on the first value; The second hash value for the second level is determined by performing a div-n operation on the second value; and Multiple selection signals are generated based on the first hash value and the second hash value, which can be used to select the specific storage location.

2. The apparatus of claim 1, wherein the specific storage location is a memory location, and wherein the set of storage locations is within the memory system of the computer system.

3. The apparatus of claim 1, wherein the first intermediate bit set and the second intermediate bit set have different numbers of bit sets.

4. The apparatus of claim 1, wherein the hash circuit includes a rule checking circuit configured to check an addressing constraint set to prevent aliasing, wherein the hash circuit is configured to check, for the first level and the second level, whether the first intermediate bit set and the second intermediate bit set each include an even number of zeros and an even number of ones.

5. The apparatus of claim 1, wherein the hash circuit comprises an arithmetic circuit, the arithmetic circuit further comprising a modulo-n circuit, the modulo-n circuit being configured to perform the modulo-n operation by means of the following steps: Determine the modulo-n value for each of the equal sub-parts of the first value, thereby producing the current set of modulo-n results; Pairs of the current set of modulo-n results are combined to obtain a new set of modulo-n results with a larger number of bits than the previous modulo-n results, wherein the new set of modulo-n results becomes the current set of modulo-n results; and Repeat the combination of the current set of modulo-n results until the new set of modulo-n results has a single modulo-n result, the single modulo-n result being the final result of the modulo-n operation on the first value.

6. The apparatus of claim 5, wherein the given pair of the current set of modulo-n results includes a first sub-part (x) of the address and the immediately following lower significant sub-part (y) of the address, and wherein the modulo-n circuit is configured to generate one of the corresponding pairs of the new set of modulo-n results formed by combining the given pairs by computing the expression mod n(mod n(x)+mod n(y)).

7. The apparatus of claim 5, wherein the arithmetic circuit further comprises a div-n circuit, the div-n circuit being configured to perform the div-n operation by means of the following steps: Determine the div-n value for each of the equal sub-parts of the second value, thereby producing the current set of div-n results; The pairs of the current set of div-n results are combined to obtain a new set of div-n results with a larger number of bits than the previous div-n results; this new set of div-n results becomes the current set of div-n results; and Repeat the combination for the current set of the div-n results until the number of bits in the new set of the div-n results is equal to the number of bits in the second value.

8. The apparatus of claim 7, wherein a given pair of the current set of div-n results includes a first sub-part (x') of the address and the immediately following lower significant sub-part (y') of the address, and wherein the div-n circuit is configured to compute the expression div n(x')•2 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y')) generates one of the corresponding values ​​in the new set of div-n results formed by combining the given pairs, wherein the second value has a bit width of 2. 2^k+1 .

9. The apparatus of claim 1, wherein the plurality of levels includes one or more other levels having corresponding options, each of the corresponding options being an integer power of two, and wherein the hash circuit is configured to perform corresponding routing for the one or more other levels using one or more XOR operations on the corresponding values ​​formed from the address via masking.

10. A method, the method comprising: A request for a specific resource within a resource set is received at a routing circuit of a computer system comprising a resource set organized according to a topology having multiple dimensions. The request includes an address having a first set and a non-overlapping second set. The topology has a first dimension with n routing options and a second dimension with m routing options, where n and m are integers greater than two and where n is not a power of two. The routing circuit determines a first route selection for the first dimension by performing a modulo-n operation on a first value formed from the address, wherein the first value includes a first set of bits and a second set of bits. The routing circuit determines a second route selection for the second dimension by performing a div-n operation on a second value formed from the address, the second value including the first set of bits and the second set of bits; as well as The routing circuit activates one or more selection signals based on the first routing selection and the second routing selection, the one or more selection signals being able to cause the specific resource to be selected in response to the request. The first set and the second set of bits are separated within the address by a set of intermediate bits. The first value is formed by masking the address with a first mask value, which includes the first set of bits and the second set of bits separated by a first set of intermediate bits. The second value is formed by masking the address with a different second mask value, which includes the first set of bits and the second set of bits separated by a second set of intermediate bits.

11. The method of claim 10, wherein performing the modulo-n operation comprises: Determine the modulo-n value for each of the equal sub-parts of the first value, thereby producing the current set of modulo-n results; Pairs of the current set of modulo-n results are combined to obtain a new set of modulo-n results with a larger number of bits than the previous modulo-n results, wherein the new set of modulo-n results becomes the current set of modulo-n results; and Repeat the combination of the current set of modulo-n results until the new set of modulo-n results has a single modulo-n result, the single modulo-n result being the final result of the modulo-n operation on the first value; and The execution of the div-n operation includes: Determine the div-n value for each of the equal sub-parts of the second value, thereby producing the current set of div-n results; The pairs of the current set of div-n results are combined to obtain a new set of div-n results with a larger number of bits than the previous div-n results; this new set of div-n results becomes the current set of div-n results; and Repeat the combination for the current set of the div-n results until the number of bits in the new set of the div-n results is equal to the number of bits in the second value.

12. The method of claim 11, wherein a given pair of the current set of modulo-n results comprises a first sub-part (x) of the address and a immediately lower significant sub-part (y) of the address, and wherein one of the corresponding pairs in the new set of modulo-n results for the given pair is equal to mod n(mod n(x) + mod n(y)).

13. The method of claim 11, wherein a given pair of the current set of div-n results comprises a first sub-part (x') of the address and the immediately following lower significant sub-part (y') of the address, and wherein one of the corresponding pairs in the new set of div-n results for the given pair is equal to div n(x')•2. 2^k +div n(y')+div n(mod n(x')·2 2^k +mod n(y')), where the second value has a bit width of 2. 2^k+1 .

14. The method of claim 10, further comprising checking the constraint set to prevent aliasing.

15. The method of claim 14, wherein checking the constraint sets for the first dimension and the second dimension includes ensuring that the first set of intermediate bits and the second set of intermediate bits each include an even number of zeros and an even number of ones.

16. An apparatus comprising: Integrated circuit, the integrated circuit comprising: According to a memory system arranged in a hierarchical structure with multiple dimensions, the multiple dimensions include a first dimension with n hash options and a second dimension with m hash options, where n and m are integers greater than two, and where n is not a power of two; Hash circuit, the hash circuit being configured as follows: Receive a request to access a specific memory location in the memory system, the request including a memory address having a first bit set and a second bit set separated by an intermediate bit set, the first bit set and the second bit set together encoding the first dimension and the second dimension; A first hash value for the first dimension is determined by performing a modulo-n operation on a first value formed by the memory address using a first mask value, the first mask value including a first set of bits, a second set of bits, and a first set of intermediate bits; A second hash value for the second dimension is determined by performing a div-n operation on the second value formed by the memory address using a second mask value, the second mask value including the first bit set, the second bit set, and the second middle bit set; and Multiple selection signals are generated based on the first hash value and the second hash value, which can be used to select the specific memory location.

17. The apparatus of claim 16, wherein the plurality of dimensions comprises: The memory controller dimension specifies one of a plurality of memory controllers in the memory system. A memory plane dimension, wherein the memory plane dimension specifies one of a plurality of memory planes for a given memory controller; A storage bank dimension, wherein the storage bank dimension specifies one of a plurality of storage banks for a given memory controller and memory plane; A row dimension, which specifies one of a plurality of rows for a given memory bank, memory plane, and memory controller; as well as A column dimension, which specifies one of a plurality of columns for a given bank, memory plane, and memory controller.

18. The apparatus of claim 16, wherein the first intermediate bit set and the second intermediate bit set have different numbers of bit sets.

19. The apparatus of claim 18, wherein the hash circuit includes a rule checking circuit configured to enforce a set of addressing constraints, wherein, For the first dimension and the second dimension, the addressing constraint set specifies that the first intermediate bit set and the second intermediate bit set include an even number of zeros and an even number of ones.

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