Display substrate and display device

Abstract

The invention discloses a display substrate (100) and a display device (500). The display substrate (100) comprises a substrate (110), a shift register (120) and a clock signal line (130), wherein the shift register (120) and the clock signal line (130) are arranged on the substrate (110); the shift register (120) comprises an input circuit (121), an output circuit (122), a first control circuit (123), a second control circuit (124), a first noise reduction circuit (125) and a second noise reduction circuit (126). The input circuit (121) comprises a first transistor (M1) and a second transistor (M2), a second electrode of the first transistor (M1) is connected with a first electrode of the second transistor (M2), a grid electrode of the first transistor (M1) is connected with a grid electrode of the second transistor (M2) and serves as a control end of the input circuit (121), and the first electrode of the first transistor (M1) serves as an input end of the input circuit (121); the first electrode of the first transistor (M1) is used as an input end of the input circuit (121), the second electrode of the second transistor (M2) is used as an output end of the input circuit (121), the first transistor (M1) and the second transistor (M2) are oxide transistors, and the second node (N2) is connected with a second voltage signal only through the second control circuit (124) and performs potential pull-down only through the second control circuit (124). Therefore, the service life of the display substrate (100) is longer.

Description

Display substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the market has placed higher demands on low-cost, narrow-frame, and lightweight designs for display devices. Against this backdrop, Gate Driver on Array (GOA) technology for display substrates has emerged and has become a research hotspot for major manufacturers.

[0003] GOA technology integrates the gate driver circuit onto the display substrate with the pixel array. This allows the gate driver circuit to directly provide gate drive signals to the pixel array, eliminating the need for additional gate driver chips and corresponding binding structures. This reduces costs and border widths. Typically, GOA technology uses multiple cascaded shift registers to enable pixel arrays row by row, enabling display products to display colorful images.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate, while employing oxide transistors, pulls down the potential of a second node solely through a second control circuit. This allows the second node to be pulled up to a high level after the first node is reset. This avoids noise introduced by clock signal variations, making it easier for the second node to be pulled up to a high level, thereby preventing poor driving performance in a gate drive circuit employing the shift register. Furthermore, the shift register has a greater margin for variations in the threshold voltage of the transistors, maintaining stable performance after reliability testing, thereby extending the service life of the display substrate employing the shift register.

[0006] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate and a shift register and a clock signal line arranged on the base substrate; the shift register includes an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit; the output end of the input circuit, the control end of the output circuit and the control end of the second control circuit are connected to a first node, the input end of the input circuit is connected to a first scan input end, and the input end of the output circuit is connected to the clock signal line; the output end of the first control circuit, the input end of the second control circuit, the control end of the first noise reduction circuit and the control end of the second noise reduction circuit are connected to a second node, and the output end of the first control circuit, the input end of the second control circuit, the control end of the first noise reduction circuit and the control end of the second noise reduction circuit are connected to a second node, The input end is configured to receive a first voltage signal, and the output end of the first noise reduction circuit and the output end of the second noise reduction circuit are configured to receive a second voltage signal; the input circuit includes a first transistor and a second transistor, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the first transistor is connected to the gate of the second transistor and serves as the control end of the input circuit, the first electrode of the first transistor serves as the input end of the input circuit, and the second electrode of the second transistor serves as the output end of the input circuit, the first transistor and the second transistor are both oxide transistors, the second node is connected to the second voltage signal only through the second control circuit, and the potential is pulled down only through the second control circuit.

[0007] For example, the display substrate provided by one embodiment of the present disclosure also includes a first voltage line and a second voltage line located on the base substrate, the first voltage line is configured to apply the first voltage signal, and the second voltage line is configured to apply the second voltage signal; the second node is connected to the second voltage line only through the second control circuit.

[0008] For example, in the display substrate provided in an embodiment of the present disclosure, the channel width-to-length ratio of the first transistor is in the range of 6-14, and the channel width-to-length ratio of the second transistor is in the range of 6-14.

[0009] For example, in the display substrate provided in an embodiment of the present disclosure, the channel width-to-length ratio of the first transistor is in the range of 8-12, and the channel width-to-length ratio of the second transistor is in the range of 8-12.

[0010] For example, in the display substrate provided in one embodiment of the present disclosure, the shift register further includes a third noise reduction circuit, the control end of the third noise reduction circuit is connected to the second node, the input end of the third noise reduction circuit is connected to the second electrode of the first transistor, and the output end of the third noise reduction circuit is configured to receive the second voltage signal; the third noise reduction circuit is configured to respond to the voltage on the second node to reduce the noise of the second electrode of the first transistor through the second voltage signal.

[0011] For example, in a display substrate provided in an embodiment of the present disclosure, the third noise reduction circuit includes a third transistor, the gate of the third transistor serves as a control end of the third noise reduction circuit, the first electrode of the third transistor serves as an input end of the third noise reduction circuit, and the second electrode of the third transistor serves as an output end of the third noise reduction circuit.

[0012] For example, in the display substrate provided in an embodiment of the present disclosure, the channel length of the third transistor is greater than 5 micrometers.

[0013] For example, in the display substrate provided in one embodiment of the present disclosure, the shift register further includes a reset circuit, the input end of the reset circuit is connected to the first node, and the output end of the reset circuit is connected to the second scan input end; the reset circuit is configured to respond to a reset signal on the control end of the reset circuit to reset the first node through the second scan input end.

[0014] For example, in a display substrate provided in an embodiment of the present disclosure, the reset circuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the gate of the fifth transistor and serves as the control end of the reset transistor, the first electrode of the fourth transistor is connected to the second electrode of the fifth transistor, the second electrode of the fourth transistor serves as the output end of the reset circuit, the first electrode of the fifth transistor serves as the input end of the reset circuit, and the fourth transistor and the fifth transistor are oxide transistors.

[0015] For example, in the display substrate provided in an embodiment of the present disclosure, the channel width-to-length ratio of the fourth transistor is in the range of 6-14, and the channel width-to-length ratio of the fifth transistor is in the range of 6-14.

[0016] For example, in the display substrate provided in an embodiment of the present disclosure, the channel width-to-length ratio of the fourth transistor is in the range of 8-12, and the channel width-to-length ratio of the fifth transistor is in the range of 8-12.

[0017] For example, in the display substrate provided in one embodiment of the present disclosure, the shift register further includes a fourth noise reduction circuit, the control end of the fourth noise reduction circuit is connected to the second node, the input end of the fourth noise reduction circuit is connected to the first electrode of the fourth transistor, and the output end of the fourth noise reduction circuit is configured to receive the second voltage signal; the fourth noise reduction circuit is configured to respond to the voltage on the second node to perform noise reduction on the first electrode of the fourth transistor through the second voltage signal.

[0018] For example, in a display substrate provided in an embodiment of the present disclosure, the fourth noise reduction transistor includes a sixth transistor, the gate of the sixth transistor serves as the control end of the fourth noise reduction circuit, the first electrode of the sixth transistor serves as the input end of the fourth noise reduction circuit, and the second electrode of the sixth transistor serves as the output end of the fourth noise reduction circuit.

[0019] For example, in the display substrate provided in an embodiment of the present disclosure, the channel length of the sixth transistor is greater than 5 micrometers.

[0020] For example, in a display substrate provided in an embodiment of the present disclosure, the first control circuit includes a seventh transistor, the first electrode of the seventh transistor serves as the input end of the first control circuit, the second electrode of the seventh transistor serves as the output end of the first control circuit, and the gate of the seventh transistor serves as the control end of the first control circuit.

[0021] For example, in a display substrate provided in an embodiment of the present disclosure, the seventh transistor includes: a first semiconductor block, including a first end and a second end; a second semiconductor block, including a third end and a fourth end; and a first floating electrode, overlapping the first semiconductor block and located between the first end and the second end; and a second floating electrode, overlapping the second semiconductor block and located between the third end and the fourth end, the first electrode of the seventh transistor is connected to the first end and the third end, and the second electrode of the seventh transistor is connected to the second end and the fourth end.

[0022] For example, in a display substrate provided in an embodiment of the present disclosure, the first floating electrode and the second floating electrode are a continuous integral structure.

[0023] For example, in the display substrate provided in one embodiment of the present disclosure, the second control circuit includes an eighth transistor, the gate of the eighth transistor serves as the control end of the second control circuit, the first electrode of the eighth transistor serves as the input end of the second control circuit, and the second electrode of the eighth transistor serves as the output end of the second control circuit.

[0024] For example, in the display substrate provided in one embodiment of the present disclosure, the output circuit includes a ninth transistor, the gate of the ninth transistor serves as the control end of the output circuit, the first electrode of the ninth transistor serves as the input end of the output circuit, and the second electrode of the ninth transistor serves as the output end of the output circuit.

[0025] For example, in a display substrate provided in an embodiment of the present disclosure, the first noise reduction circuit includes a tenth transistor, the second noise reduction circuit includes an eleventh transistor, the gate of the tenth transistor serves as the control end of the first noise reduction circuit, the first electrode of the tenth transistor serves as the input end of the first noise reduction circuit, the second electrode of the tenth transistor serves as the output end of the first noise reduction circuit, the gate of the eleventh transistor serves as the control end of the second noise reduction circuit, the first electrode of the eleventh transistor serves as the input end of the second noise reduction circuit, and the second electrode of the eleventh transistor serves as the output end of the second noise reduction circuit.

[0026] For example, in the display substrate provided in one embodiment of the present disclosure, the shift register further includes a first clear circuit and a second clear circuit; the input end of the first clear circuit is connected to the first node, and the output end of the first clear circuit is configured to receive the second voltage signal, the input end of the second clear circuit is connected to the output end, and the output end of the second clear circuit is configured to receive the second voltage signal; the first clear circuit is configured to respond to a clear control signal to reset the first node through the second voltage signal, and the second clear circuit is configured to respond to a clear control signal to reset the output end through the second voltage signal.

[0027] For example, in a display substrate provided in an embodiment of the present disclosure, the first clearing circuit includes a twelfth transistor, the second clearing circuit includes a thirteenth transistor, the gate of the twelfth transistor is the control end of the first clearing circuit, the first pole of the twelfth transistor is the input end of the first clearing circuit, the second pole of the twelfth transistor is the output end of the first clearing circuit, the gate of the thirteenth transistor is the control end of the second clearing circuit, the first pole of the thirteenth transistor is the input end of the second clearing circuit, and the second pole of the thirteenth transistor is the output end of the second clearing circuit.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any one of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0030] FIG1 is a schematic diagram of a shift register in a gate drive circuit provided by the present disclosure;

[0031] FIG2 is a timing diagram of a driving signal of a shift register in a gate driving circuit provided by the present disclosure;

[0032] FIG3 is a schematic diagram of a display substrate provided in one embodiment of the present disclosure;

[0033] FIG4 is a schematic diagram of a shift register in a display substrate provided by an embodiment of the present disclosure;

[0034] FIG5 is a timing diagram of driving signals of a shift register in a display substrate provided by an embodiment of the present disclosure;

[0035] FIG6 is a schematic diagram of a seventh transistor in a display substrate provided by an embodiment of the present disclosure;

[0036] FIG7 is a diagram showing simulation results of a shift register provided by the present disclosure;

[0037] FIG8 is a diagram showing simulation results of a shift register provided by an embodiment of the present disclosure; and

[0038] FIG9 is a schematic diagram of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. In addition, when the number of a component or element is not specifically stated below in the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "a plurality" refers to at least two.

[0041] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Since the source and drain of the transistor are symmetrical, they are structurally indistinguishable and can therefore be replaced with each other. In the embodiments of the present disclosure, to distinguish the source and drain of the transistor, one of the source and drain is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type transistors and P-type transistors. When an N-type transistor is used, a high level is input to the gate, and the first and second electrodes are conductive; when a P-type transistor is used, a low level is input to the gate, and the first and second electrodes are conductive. The following embodiments are described using N-type transistors as an example, but the embodiments of the present disclosure include but are not limited to these. The transistors in the embodiments of the present disclosure may also be P-type transistors. It is understandable that replacing an N-type transistor with a P-type transistor is something that a person skilled in the art can easily think of without inventive effort, and therefore falls within the scope of protection of the embodiments of the present disclosure.

[0042] The display substrate's gate driver circuit (GOA) implements a shift register function, providing a pulse signal with a specific duration to all gate lines row by row within a frame. This pulse signal duration is typically one to several times the charging time allocated for each pixel row, and the waveform of this pulse signal is typically a square wave. Simultaneously, the display substrate's source driver circuit, in conjunction with this pulse signal, provides video signal voltage (display data) to all pixel rows row by row, thereby achieving normal image display.

[0043] Typically, the gate drive circuit includes multiple GOA unit circuits, which can also be called shift registers or shift register units. For small and medium-sized display products, such as mobile phones, tablets, etc., a single-sided drive method is generally adopted, that is, corresponding to each gate line, a GOA unit circuit is used to drive it, one side drives the odd-numbered rows of gate lines, and the other side drives the even-numbered rows of gate lines, and the two sides are turned on alternately. For medium and large-sized display products, such as laptops, monitors, televisions, etc., a double-sided drive method is generally adopted, that is, corresponding to each gate line, a GOA unit circuit is used on the left and right to drive it, and the GOA unit circuits on both sides of the gate line simultaneously output exactly the same pulse signal to the gate line to reduce the output delay time.

[0044] As shown above, during the operation of the gate drive circuit, each GOA unit circuit will output a pulse signal to its corresponding gate line in each frame. The driving signal of the GOA unit circuit usually includes a start signal (Input), a clock signal (CLK), a low-level signal (VGL), a reset signal (RESET), and an optional high-level signal (VGH); the start signal is generally generated by a certain level of GOA unit circuit preceding the current level of GOA unit circuit; for the first one or several GOA unit circuits, a dedicated square wave signal will be provided as a start signal, which is used to provide a start signal to them at the beginning of each frame, generally called an STV signal.

[0045] The output signal of the GOA unit circuit is generally an output signal (OUTPUT) or a gate drive signal provided to the gate line; the start signal of the subsequent GOA unit circuit can share the output signal, or it can be a start signal generated separately (the last GOA unit circuit does not need to output a start signal, and its reset signal is also provided by the system, or a dedicated reset circuit will be made to provide it with a reset signal. This circuit is generally composed of several transistors and occupies an area smaller than the area of ​​a GOA unit circuit).

[0046] FIG1 is a schematic diagram of a shift register in a gate driving circuit provided by the present disclosure; FIG2 is a timing diagram of a driving signal of a shift register in a gate driving circuit provided by the present disclosure.

[0047] As shown in Figure 1, the shift register 20 includes a first input transistor M1, a second input transistor M2, an output transistor M9, a first reset transistor M4, a second reset transistor M5, a first control transistor M7, a second control transistor M8, a first noise reduction transistor M10, a second noise reduction transistor M11, a third noise reduction transistor M3, a fourth noise reduction transistor M6, a first auxiliary reset transistor M14 and a second auxiliary reset transistor M15, a first clear transistor M12, a second clear transistor M13 and a capacitor C.

[0048] As shown in Figures 1 and 2, the second electrode of the second input transistor M2, the first electrode of the second reset transistor M5, the gate of the output transistor M9, and the first electrode of the capacitor C are connected to the first node N1. The first electrode of the output transistor M9 is connected to the clock signal line CLK, and the second electrode of the output transistor M9 serves as the output terminal Gout of the shift register 20. The first node N1 can serve as a pull-up node. After the second input transistor M2 writes the input signal to the first node N1, the output transistor M9 can respond to the signal on the first node N1 to output the clock signal on the clock signal line CLK as a gate drive signal. The second electrode of the first control transistor M7, the first electrode of the second control transistor M8, the gate of the first noise reduction transistor M10, and the gate of the second noise reduction transistor M11 are connected to the second node N2. The second node N2 can serve as a pull-down node. The first control transistor M7 can write the high-voltage signal on the first electrode of the first control transistor M7 to the second node N2. The first noise reduction transistor M10 and the second noise reduction transistor M11 can respond to the signal on the second node N2 to reduce noise on the first node N1 and the output terminal Gout of the shift register, respectively.

[0049] As shown in Figures 1 and 2, during phases T1 and T2, the second node N2 remains at a low level due to the action of the first auxiliary reset transistor M14 and the second control transistor M8. During phase T3, i.e., after the output terminal Gout of the shift register 20 outputs the aforementioned gate drive signal, the first reset transistor M4 and the second reset transistor M5 respond to the reset signal Reset to reset the first node N1. Simultaneously, the second auxiliary reset transistor M15 also responds to the reset signal Reset to reset the second node N2, causing the second node N2 to also remain at a low level during phase T3. During phase T4, the second node N2 needs to remain at a high level to control the first noise reduction transistor M10 and the second noise reduction transistor M11 to reduce noise at the first node N1 and the output terminal Gout of the shift register, respectively. However, during phase T3, the second auxiliary reset transistor M15 also responds to the reset signal Reset to reset the second node N2. Consequently, the second node N2 cannot be pulled high during this period. During phase T4, the first node N1 is affected by the noise of the clock signal, making it difficult for the second node N2 to be pulled high. Consequently, the gate driver circuit using this shift register may experience poor driving. In particular, after undergoing reliability testing, the gate driver circuit using this shift register may be more susceptible to poor driving due to the aforementioned reasons.

[0050] In response to the above problems, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate and a shift register and a clock signal line arranged on the base substrate; the shift register includes an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit; the output end of the input circuit, the control end of the output circuit and the control end of the second control circuit are connected to a first node, the input end of the input circuit is connected to a first scan input end, and the input end of the output circuit is connected to the clock signal line; the output end of the first control circuit, the input end of the second control circuit, the control end of the first noise reduction circuit and the control end of the second noise reduction circuit are connected to a second node, and the input end of the first control circuit is configured to be connected to a first The output terminal of the first noise reduction circuit and the output terminal of the second noise reduction circuit are configured to receive a second voltage signal; the input circuit includes a first transistor and a second transistor, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the first transistor is connected to the gate of the second transistor and serves as a control terminal of the input circuit, the first electrode of the first transistor serves as the input terminal of the input circuit, and the second electrode of the second transistor serves as the output terminal of the input circuit, the first transistor and the second transistor are both oxide transistors, the second node receives the second voltage signal only through the second control circuit, and the potential is pulled down only through the second control circuit. Thus, under the premise of using oxide transistors, the display substrate only pulls down the potential of the second node through the second control circuit, so that after the first node is reset, the second node can be pulled up to a high level, which is offset from the noise caused by the change of the clock signal, making it easier for the second node to be pulled up to a high level, thereby avoiding driving problems caused by the gate drive circuit using the shift register; in addition, the shift register has a larger margin for changes in the threshold voltage of the transistor, and can still maintain stable performance after reliability testing, thereby extending the service life of the display substrate using the shift register.

[0051] Hereinafter, the display substrate and the display device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] One embodiment of the present disclosure provides a display substrate. Figure 3 is a schematic diagram of a display substrate provided in one embodiment of the present disclosure; Figure 4 is a schematic diagram of a shift register in a display substrate provided in one embodiment of the present disclosure; and Figure 5 is a timing diagram of a drive signal for a shift register in a display substrate provided in one embodiment of the present disclosure.

[0053] As shown in Figures 3 and 4, the display substrate 100 includes a base substrate 110, a shift register 120 disposed on the base substrate 110, and a clock signal line 130. The shift register 120 includes an input circuit 121, an output circuit 122, a first control circuit 123, a second control circuit 124, a first noise reduction circuit 125, and a second noise reduction circuit 126. It should be noted that the display substrate 100 may include multiple shift registers 120, which are cascaded to form a gate drive circuit, namely, a GOA (Gate On Array) circuit.

[0054] As shown in Figure 3, the base substrate 110 includes a display area 112 and a peripheral area 114. The peripheral area 114 includes a first sub-peripheral area 114A and a second sub-peripheral area 114B located on either side of the display area 112. The shift register 120 can be disposed in the first sub-peripheral area 114A and the second sub-peripheral area 114B, i.e., on the left and right sides of the display area 112. The display area 112 includes a plurality of gate lines 1124 and a plurality of sub-pixels 1120. The plurality of gate lines 1124 is used to drive the plurality of sub-pixels 1120. The peripheral area 114 of the base substrate 110 may also include a binding area 118 located below the display area 112 for binding to an external driver IC.

[0055] As shown in Figures 4 and 5, the input circuit 121 includes a control terminal, an input terminal, and an output terminal; the output short circuit 122 includes a control terminal, an input terminal, and an output terminal; and the second control circuit 124 includes a control terminal, an input terminal, and an output terminal. The output terminal of the input circuit 121, the control terminal of the output circuit 122, and the control terminal of the second control short circuit 124 are connected to the first node N1; the input terminal of the input circuit 121 is connected to the first scan input terminal VDS, and the control terminal of the input circuit 121 is connected to the input control terminal Input; the input terminal of the output circuit 122 is connected to the clock signal line 130, and the output terminal of the output circuit 122 can serve as the output terminal Gout of the shift register 120; the input terminal of the second control circuit 124 is connected to the second node N2, and the output terminal of the second control circuit 124 is connected to the second voltage signal terminal VGL. The input circuit 121 is configured to respond to the driving signal on the input control terminal Input and write the voltage input by the first scan input terminal VDS into the first node N1; the output circuit 122 is configured to respond to the voltage on the first node N1 and output the clock signal on the clock signal line 130 as a gate driving signal from the output terminal Gout.

[0056] 4 and 5 , the shift register 120 further includes a capacitor C, one end of which is connected to the first node N1, and the other end of which is connected to the output end of the output circuit 122. The capacitor C can maintain the voltage on the first node N1.

[0057] As shown in Figures 4 and 5 , the first control circuit 123 includes a control terminal, an input terminal, and an output terminal; the first noise reduction circuit 125 includes a control terminal, an input terminal, and an output terminal; and the second noise reduction circuit 126 includes a control terminal, an input terminal, and an output terminal. The output terminal of the first control circuit 123, the input terminal of the second control circuit 124, the control terminal of the first noise reduction circuit 125, and the control terminal of the second noise reduction circuit 126 are connected to a second node N2. The input terminal of the first control circuit 123 is connected to the first voltage signal terminal VDD and is configured to receive a first voltage signal. The output terminal of the first noise reduction circuit 125 and the output terminal of the second noise reduction circuit 126 are respectively connected to the second voltage signal terminal VGL and are configured to receive a second voltage signal. The control terminal and input terminal of the first control circuit 123 are both connected to the first voltage signal terminal VDD, and thus can be regarded as a diode, inputting the first voltage signal on the first voltage signal terminal VDD to the second node N2. The second control circuit 124 is configured to respond to the voltage on the first node N1 and pull down the potential on the second node N2 via the second voltage signal on the second voltage signal terminal VGL. Therefore, the first node N1 and the second node N2 can serve as inverters to each other. It should be noted that the first node N1 can serve as a pull-up node, and the second node N2 can serve as a pull-down node.

[0058] As shown in Figures 4 and 5, the input terminal of the first noise reduction circuit 125 is connected to the first node N1, and the input terminal of the second noise reduction circuit 126 is connected to the output terminal of the output circuit 122. Therefore, when the voltage on the second node N2 is at a high level, the first noise reduction circuit 125 and the second noise reduction circuit 126 can respond to the voltage on the second node N2 to reduce noise on the first node N1 and the output terminal of the output circuit 122, respectively, through the second voltage signal on the second voltage signal terminal VGL.

[0059] As shown in Figures 4 and 5, the input circuit 121 includes a first transistor M1 and a second transistor M2. The second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The gate of the first transistor M1 is connected to the gate of the second transistor M2 and serves as the control terminal of the input circuit 121. The first electrode of the first transistor M1 serves as the input terminal of the input circuit 121, and the second electrode of the second transistor M2 serves as the output terminal of the input circuit 121. The first transistor M1 and the second transistor M2 are both oxide transistors. The second node N2 is connected to the second voltage signal only through the second control circuit 124, and the potential is pulled down only by the second control circuit 124. It should be noted that the above-mentioned oxide transistor refers to a transistor whose semiconductor layer is made of an oxide semiconductor material, and the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0060] In the display substrate provided by the embodiments of the present disclosure, since both the first and second transistors are oxide transistors, they have advantages such as high efficiency and large on-state current. Therefore, a shift register using oxide transistors has good performance. Furthermore, since the input circuit includes the first and second transistors, when the first transistor is in a long-term bias state and becomes conductive, the second transistor can still function as a cutoff, preventing leakage in the input circuit and thereby increasing the service life of the shift register.

[0061] On the other hand, under the premise that the shift register adopts the above-mentioned oxide transistor, the shift register only connects the second voltage signal to the second node through the second control circuit, and only pulls down the potential of the second node through the second control circuit, so that after the first node is reset, the second node can be pulled up to a high level, which is offset from the noise caused by the change of the clock signal, and it is easier to pull the second node to a high level, thereby avoiding poor driving of the gate drive circuit using the shift register; in addition, the shift register has a larger margin for changes in the threshold voltage of the transistor, and can still maintain stable performance after reliability testing, thereby extending the service life of the display substrate using the shift register.

[0062] In some examples, as shown in FIG. 3 , in the display area 112 , a plurality of sub-pixels 1120 are arranged in an array along a first direction X and a second direction Y to form a plurality of pixel rows arranged along the second direction Y; a gate line 1124 is connected to the plurality of sub-pixels 1120 in the same pixel row to provide them with gate drive signals.

[0063] In some examples, as shown in FIG3 , the display substrate 100 may include a plurality of clock signal lines 130 ; each clock signal line 130 may extend at least partially along the second direction Y. A dedicated square wave signal is provided to the first one or more shift registers 120 as a start signal STV, which is used to provide a start signal thereto at the beginning of each frame.

[0064] In some examples, as shown in FIG3 , the display substrate 100 adopts a head-to-head driving method, that is, two shift registers 120 are provided on both sides of the same pixel row (or gate line), and gate drive signals are provided to the pixel row from both ends of the pixel row (or gate line). Of course, the embodiments of the present disclosure include but are not limited to this, and the display substrate may also adopt an odd-even interlace driving method, that is, a shift register is provided on a single side of the same pixel row (gate line), so that a single side of the pixel row provides a gate drive signal to the pixel row (gate line), and the shift registers corresponding to the odd pixel rows are located on one side, and the shift registers corresponding to the even pixel rows are located on the other side.

[0065] For example, the base substrate may be a flexible substrate or a rigid substrate, which is not limited in the embodiments of the present disclosure. The base substrate may be a glass substrate, a plastic substrate, a quartz substrate, or a metal substrate, or may be a substrate formed of an organic material. For example, the above-mentioned organic material may include resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0066] In some examples, as shown in Figures 3 and 4 , the display substrate 100 further includes a first voltage line 141 and a second voltage line 142 located on the base substrate 110. The first voltage line 141 is configured to apply a first voltage signal, and the second voltage line 142 is configured to apply a second voltage signal. The second node N2 is connected to the second voltage line 142 only via the second control circuit 124. Thus, the display substrate can utilize the second voltage line to apply the second voltage signal to the second node via the second control circuit.

[0067] For example, the first voltage signal may be a high level signal, and the second voltage signal may be a low level signal. Of course, the embodiments of the present disclosure include but are not limited to this.

[0068] In some examples, the channel width-to-length ratio of the first transistor M1 is in the range of 6 to 14, and the channel width-to-length ratio of the second transistor M2 is in the range of 6 to 14. As a result, the first transistor M1 and the second transistor M2 have large on-state currents, thereby quickly charging or discharging the first node N1, thereby improving the driving performance of the shift register.

[0069] In some examples, the channel width-to-length ratio of the first transistor M1 is in a range of 8-12, for example, 10; and the channel width-to-length ratio of the second transistor M2 is in a range of 8-12, for example, 10. As a result, the first transistor M1 and the second transistor M2 have relatively large on-state currents, thereby quickly charging or discharging the first node N1, thereby improving the driving performance of the shift register; on the other hand, when the first transistor and the second transistor adopt the above-mentioned channel width-to-length ratio, the layout can be further optimized.

[0070] For example, the channel length of the first transistor M1 may be 5 microns, and the channel width of the first transistor M1 is greater than 30 microns, such as 50 microns; the channel length of the second transistor M2 may be 5 microns, and the channel width of the second transistor M2 is greater than 30 microns, such as 50 microns.

[0071] In some examples, as shown in FIG4 and FIG5 , the shift register 120 further includes a third noise reduction circuit 127 . The control terminal of the third noise reduction circuit 127 is connected to the second node N2 , the input terminal of the third noise reduction circuit 127 is connected to the second electrode of the first transistor M1 , that is, connected to the first electrode of the second transistor M2 , and the output terminal of the third noise reduction circuit 127 is configured to receive a second voltage signal. The third noise reduction circuit 127 is configured to respond to the voltage on the second node N2 and reduce the noise of the second electrode of the first transistor M1 , that is, reduce the noise of the first electrode of the second transistor M2 , through the second voltage signal. Thus, the shift register can timely reduce the noise of the second electrode of the first transistor through the second voltage signal via the third noise reduction circuit, thereby preventing the second transistor from being in a long-term bias state after the first transistor becomes conductive, thereby having a longer service life.

[0072] In some examples, as shown in Figures 4 and 5, the third noise reduction transistor 127 includes a third transistor M3; the gate of the third transistor M3 serves as the control terminal of the third noise reduction circuit 127 and is connected to the second node N2; the first electrode of the third transistor M3 serves as the input terminal of the third noise reduction circuit 127 and is connected to the second electrode of the first transistor M1; the second electrode of the third transistor M3 serves as the output terminal of the third noise reduction circuit 127, is connected to the second voltage line 142, and is configured to receive the second voltage signal.

[0073] In some examples, the channel length of the third transistor M3 is greater than 5 microns, such as 8 microns, thereby improving the high voltage resistance and better reducing the noise of the second electrode of the first transistor after the first transistor becomes conductive.

[0074] In some examples, as shown in FIG4 and FIG5 , the shift register 120 further includes a reset circuit 128, wherein an input terminal of the reset circuit 128 is connected to the first node N1, and an output terminal of the reset circuit 128 is connected to the second scan input terminal VSD. The reset circuit 128 is configured to respond to a reset signal at a control terminal of the reset circuit 128 to reset the first node N1 via the second scan input terminal VSD. It should be noted that the description herein is of a forward scan scenario, in which the first scan input terminal is a high-level signal and the second scan input terminal is a low-level signal. However, embodiments of the present disclosure include but are not limited to this, and the display substrate may also perform a reverse scan scenario, in which the first scan input terminal is a low-level signal and the second scan input terminal is a high-level signal.

[0075] In some examples, as shown in Figures 4 and 5, the reset circuit 128 includes a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is connected to the gate of the fifth transistor M5 and serves as a control terminal of the reset transistor 128 to be connected to the reset signal; the first electrode of the fourth transistor M4 is connected to the second electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 serves as an output terminal of the reset circuit 128. The first electrode of the fifth transistor M5 serves as an input terminal of the reset circuit 128; the fourth transistor M4 and the fifth transistor M5 are oxide transistors.

[0076] In the display substrate provided in this example, since the fourth transistor and the fifth transistor are oxide transistors, they have advantages such as high efficiency and large on-state current. Therefore, the shift register using oxide transistors has better performance. In addition, since the reset circuit includes the above-mentioned fourth transistor and the fourth transistor, when the fourth transistor is in a long-term bias state and becomes conductive, the fifth transistor can still function as a cutoff, avoiding leakage in the input circuit, thereby improving the service life of the shift register. It should be noted that when performing reverse scanning, the above-mentioned reset circuit can serve as an input circuit, and the above-mentioned input circuit can serve as a reset circuit.

[0077] In some examples, as shown in Figures 4 and 5, the channel width-to-length ratio of the fourth transistor M4 is in the range of 6 to 14, and the channel width-to-length ratio of the fifth transistor M5 is in the range of 6 to 14. As a result, the fourth transistor M4 and the fifth transistor M5 have large on-state currents, thereby quickly charging or discharging the first node N1, thereby improving the driving performance of the shift register.

[0078] In some examples, the channel width-to-length ratio of the fourth transistor M4 is in a range of 8-12, for example, 10; and the channel width-to-length ratio of the fifth transistor M5 is in a range of 8-12, for example, 10. As a result, the fourth transistor M4 and the fifth transistor M5 have relatively large on-state currents, thereby quickly charging or discharging the first node N1, thereby improving the driving performance of the shift register; on the other hand, when the fourth transistor and the fifth transistor adopt the above-mentioned channel width-to-length ratio, the layout can be further optimized.

[0079] For example, the channel length of the fourth transistor M4 may be 5 microns, and the channel width of the fourth transistor M4 is greater than 30 microns, for example, 50 microns; the channel length of the fifth transistor M5 may be 5 microns, and the channel width of the fifth transistor M2 is greater than 30 microns, for example, 50 microns.

[0080] In some examples, as shown in Figures 4 and 5, the shift register 120 further includes a fourth noise reduction circuit 129. The control terminal of the fourth noise reduction circuit 129 is connected to the second node N2. The input terminal of the fourth noise reduction circuit 129 is connected to the first electrode of the fourth transistor M4, that is, connected to the second electrode of the fifth transistor M5. The output terminal of the fourth noise reduction circuit 129 is configured to receive a second voltage signal. The fourth noise reduction circuit 129 is configured to respond to the voltage on the second node N2 and reduce the noise of the first electrode of the fourth transistor M4 using the second voltage signal. Thus, the shift register can timely reduce the noise of the first electrode of the fourth transistor using the second voltage signal through the fourth noise reduction circuit, thereby preventing the fifth transistor from being in a long-term bias state after the fourth transistor becomes conductive, thereby having a longer service life.

[0081] In some examples, as shown in Figures 4 and 5, the fourth noise reduction transistor 129 includes a sixth transistor M6, the gate of the sixth transistor M6 serves as the control end of the fourth noise reduction circuit 129, the first electrode of the sixth transistor M6 serves as the input end of the fourth noise reduction circuit 129, and the second electrode of the sixth transistor M6 serves as the output end of the fourth noise reduction circuit 129.

[0082] In some examples, the channel length of the sixth transistor M6 is greater than 5 microns, such as 8 microns, thereby improving high voltage resistance and better reducing noise on the first electrode of the fourth transistor after the fourth transistor is conductive.

[0083] In some examples, as shown in Figures 4 and 5, the first control circuit 123 includes a seventh transistor M7, a first electrode of the seventh transistor M7 serves as an input terminal of the first control circuit 123, a second electrode of the seventh transistor M7 serves as an output terminal of the first control circuit 123, and a gate of the seventh transistor M7 serves as a control terminal of the first control circuit 123.

[0084] For example, as shown in FIG4 and FIG5 , the gate and the first electrode of the seventh transistor M7 are both connected to the first voltage line 141 , so that the seventh transistor M7 can be regarded as a diode, and applies the first voltage signal to the second node N2 .

[0085] During research, the inventors of this application noted that because the first electrode of the seventh transistor is connected to the first voltage line, which typically has high static electricity, the seventh transistor is susceptible to damage due to static electricity discharge. Therefore, the seventh transistor needs to have strong resistance to static electricity discharge. To address this issue, this disclosure specifically proposes a transistor with strong resistance to static electricity discharge.

[0086] Figure 6 is a schematic diagram of a seventh transistor in a display substrate provided in one embodiment of the present disclosure. As shown in Figure 6, the seventh transistor M7 includes a first semiconductor block 071, a second semiconductor block 072, a first floating electrode 073, and a second floating electrode 074. The first semiconductor block 071 includes a first terminal 071A and a second terminal 071B; the second semiconductor block 072 includes a third terminal 072A and a fourth terminal 072B; the first floating electrode 073 is coupled to the first semiconductor block 071 and is located between the first terminal 071A and the second terminal 071B; the second floating electrode 074 is coupled to the second semiconductor block 072 and is located between the third terminal 072A and the fourth terminal 072B. The first electrode 076 of the seventh transistor M7 is connected to the first terminal 071A and the third terminal 072A, and the second electrode 077 of the seventh transistor M7 is connected to the second terminal 071B and the fourth terminal 072B. With this configuration, the seventh transistor has two channels, thereby improving its ability to resist electrostatic discharge. Furthermore, the first and second floating electrodes can increase the lengths of the first and second semiconductor blocks without changing the channel width-to-length ratio. This significantly improves the seventh transistor's ability to resist electrostatic discharge, resulting in greater stability and a longer service life for the shift register.

[0087] In some examples, as shown in FIG. 6 , the first floating electrode 073 and the second floating electrode 074 are a continuous, integrated structure.

[0088] In some examples, as shown in FIG6 , the first semiconductor block 071 and the second semiconductor block 072 are arranged in the same layer and spaced apart from each other; the gate 075 of the seventh transistor M7 is located on a side of the first semiconductor block 071 and the second semiconductor block 072 away from the first floating electrode 073 and the second floating electrode 074. It should be noted that a gate insulating layer is provided between the first electrode 076 of the seventh transistor M7 and the first semiconductor block 071 and the second semiconductor block 072; and a gate insulating layer is provided between the second electrode 077 of the seventh transistor M7 and the first semiconductor block 071 and the second semiconductor block 072.

[0089] In some examples, the channel width-to-length ratio of the seventh transistor M7 is 1:1; for example, the channel width of the seventh transistor M7 is 10 micrometers, and the channel length of the seventh transistor M7 is 10 micrometers.

[0090] In some examples, the second control circuit 124 includes an eighth transistor M8; the gate of the eighth transistor M8 serves as the control terminal of the second control circuit 124 and is connected to the first node N1; the first electrode of the eighth transistor M8 serves as the input terminal of the second control circuit 124 and is connected to the second node N2; the second electrode of the eighth transistor M8 serves as the output terminal of the second control circuit 124 and is connected to the second voltage line 142.

[0091] In some examples, the output circuit 122 includes a ninth transistor M9; the gate of the ninth transistor M9 serves as a control terminal of the output circuit 122 and is connected to the first node N1; the first electrode of the ninth transistor M9 serves as an input terminal of the output circuit 122 and is connected to the clock signal line 130; the second electrode of the ninth transistor M9 serves as an output terminal of the output circuit 122 and as an output terminal Gout of the shift register 120.

[0092] In some examples, the first noise reduction circuit 125 includes a tenth transistor M10, and the second noise reduction circuit 126 includes an eleventh transistor M11; the gate of the tenth transistor M10 serves as the control terminal of the first noise reduction circuit 125 and is connected to the second node N2; the first electrode of the tenth transistor M10 serves as the input terminal of the first noise reduction circuit 125 and is connected to the first node N1; the second electrode of the tenth transistor M10 serves as the output terminal of the first noise reduction circuit 125 and is connected to the second voltage line 142; the gate of the eleventh transistor M11 serves as the control terminal of the second noise reduction circuit 126 and is connected to the second node N2; the first electrode of the eleventh transistor M11 serves as the input terminal of the second noise reduction circuit 126 and is connected to the output terminal of the output circuit 122; the second electrode of the eleventh transistor M11 serves as the output terminal of the second noise reduction circuit 126 and is connected to the second voltage line 142.

[0093] In some examples, as shown in Figures 4 and 5, the shift register 120 also includes a first clear circuit 210 and a second clear circuit 220; the input end of the first clear circuit 210 is connected to the first node N1, and the output end of the first clear circuit 210 is configured to receive a second voltage signal, the input end of the second clear circuit 220 is connected to the output end, and the output end of the second clear circuit 220 is configured to receive a second voltage signal; the first clear circuit 210 is configured to respond to the clear control signal to reset the first node N1 through the second voltage signal, and the second clear circuit 220 is configured to respond to the clear control signal to reset the output end through the second voltage signal.

[0094] In some examples, as shown in Figures 4 and 5, the first clearing circuit 210 includes a twelfth transistor M12, and the second clearing circuit 220 includes a thirteenth transistor M13. The gate of the twelfth transistor M12 is the control end of the first clearing circuit 210, the first pole of the twelfth transistor M12 is the input end of the first clearing circuit 210, and the second pole of the twelfth transistor M12 is the output end of the first clearing circuit 210; the gate of the thirteenth transistor M13 is the control end of the second clearing circuit 220, the first pole of the thirteenth transistor M13 is the input end of the second clearing circuit 220, and the second pole of the thirteenth transistor M13 is the output end of the second clearing circuit 220.

[0095] The following describes an operation mode of the shift register provided by the embodiment of the present disclosure in conjunction with the shift register shown in Figure 4 and the timing diagram shown in Figure 5. It should be noted that the embodiment of the present disclosure includes but is not limited to the following specific operation mode.

[0096] As shown in Figures 4 and 5, in stage T1, the start signal Input is at a high level, and the first transistor M1 and the second transistor M2 respond to the start signal Input to write the high-level signal connected to the first scan input terminal VDS into the first node N1; at the same time, the eighth transistor M8 responds to the voltage on the first node N1 to pull down the point on the second node N2 through the second voltage signal.

[0097] As shown in Figures 4 and 5, in stage T2, the start signal Input is at a low level, and the first transistor M1 and the second transistor M2 are turned off; the first node N1 is pulled high again under the bootstrap effect of the capacitor C, and the ninth transistor M9 responds to the voltage on the first node N1 and outputs the clock signal on the clock signal line 130.

[0098] As shown in Figures 4 and 5, during phase T3, the reset signal Reset is at a high level. The fourth transistor M4 and the fifth transistor M5 respond to the reset signal and pull down the potential of the first node N1 via the second voltage signal. Simultaneously, the seventh transistor M7 charges the second node N2, pulling up the potential of the second node N2. The tenth transistor M10 and the eleventh transistor M11 respond to the voltage on the second node N2 and, via the second voltage signal, perform noise reduction on the first node N1 and the output terminal Gout of the shift register, respectively.

[0099] As shown in Figures 4 and 5, in phase T4, the potential on the second node N2 is pulled high. In response to the voltage on the second node N2, the tenth transistor M10 and the eleventh transistor M11 respectively reduce noise on the first node N1 and the output terminal Gout of the shift register through the second voltage signal.

[0100] Thus, the shift register receives the second voltage signal to the second node only through the second control circuit, and pulls down the potential of the second node only through the second control circuit, so that after the first node is reset, the second node can be pulled up to a high level, which is offset from the noise caused by the change of the clock signal, making it easier for the second node to be pulled up to a high level, thereby avoiding poor driving of the gate drive circuit using the shift register; in addition, the shift register has a larger margin for changes in the threshold voltage of the transistor

[0101] (margin), and after a reliability test, it can still maintain stable performance, thereby extending the service life of a display substrate using the shift register.

[0102] It should be noted that the transistors in the above embodiments may all be thin film transistors or field effect transistors or other switching devices with the same characteristics; the transistors in the above embodiments may all be oxide transistors. Taking a thin film transistor as an example, the active layer (channel region) of the transistor adopts an oxide semiconductor material, such as indium gallium tin oxide (IGZO), while the gate, source, drain, etc. adopt metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is directly described as the second pole.

[0103] Figure 7 is a diagram showing simulation results of a shift register provided by the present disclosure; Figure 8 is a diagram showing simulation results of a shift register provided by an embodiment of the present disclosure. Figure 7 is a timing diagram of various signals of the shift register (15T1C) shown in Figure 1, and Figure 8 is a timing diagram of various signals of the shift register (13T1C) shown in Figure 4.

[0104] As shown in FIG7 , after the first node N1 is reset, the first node N1 is affected by the noise of the clock signal, making it difficult to pull the second node N2 high, thereby causing the shift register to output other pulse signals, resulting in poor driving.

[0105] As shown in Figure 8, after the first node of the shift register provided by the embodiment of the present disclosure is reset, the second node can be pulled up to a high level. This can offset the noise caused by the clock signal changes, making it easier for the second node to be pulled up to a high level, thereby avoiding the output of other pulse signals. As a result, the gate drive circuit using this shift register can avoid driving problems.

[0106] At least one embodiment of the present disclosure further provides a display device. Figure 9 is a schematic diagram of a display device provided in one embodiment of the present disclosure. As shown in Figure 9, the display device 500 includes a display substrate 100 provided in any of the above examples. As a result, the display device can achieve superior performance, higher reliability, and a longer service life.

[0107] For example, the display device may be an electronic product with a display function, such as a television, a monitor, an electronic picture frame, an electronic photo frame, a navigator, a laptop computer, a tablet computer, or a smart phone.

[0108] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. This method can be used to manufacture the display substrate provided in any embodiment of the present disclosure. For example, it can be used to manufacture the display substrate shown in FIG. 3 . This method includes steps S101 to S102.

[0109] Step S110: providing a base substrate.

[0110] For example, the base substrate may be a flexible substrate or a rigid substrate, which is not limited in the embodiments of the present disclosure. The base substrate may be a glass substrate, a plastic substrate, a quartz substrate, or a metal substrate, or may be a substrate formed of an organic material. For example, the above-mentioned organic material may include resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0111] Step S102: forming a register unit and a clock signal line on the substrate; the shift register includes an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit; the output end of the input circuit, the control end of the output circuit and the control end of the second control circuit are connected to the first node, the input end of the input circuit is connected to the first scan input end, and the input end of the output circuit is connected to the clock signal line; the output end of the first control circuit, the input end of the second control circuit, the control end of the first noise reduction circuit and the control end of the second noise reduction circuit are connected to the second node, the input end of the first control circuit is configured to receive a first voltage signal, the output end of the first noise reduction circuit and the output end of the second noise reduction circuit are configured to receive a second voltage signal; the input circuit includes a first transistor and a second transistor, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the first transistor is connected to the gate of the second transistor and serves as the control end of the input circuit, the first electrode of the first transistor serves as the input end of the input circuit, and the second electrode of the second transistor serves as the output end of the input circuit, the first transistor and the second transistor are both oxide transistors, the second node is connected to the second voltage signal only through the second control circuit, and the potential is pulled down only through the second control circuit.

[0112] Regarding the technical effects of the method for manufacturing the display substrate provided in the above embodiment, reference may be made to the technical effects of the display substrate provided in the embodiments of the present disclosure, which will not be repeated here.

[0113] In some examples, forming a shift register on a substrate includes: sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the substrate. The semiconductor layer may include an active layer of a transistor used in the shift register; the first insulating layer may be a gate insulating layer of the transistor used in the shift register; the first conductive layer may include a gate of the transistor used in the shift register; the second conductive layer may include a first electrode and a second electrode of the transistor used in the shift register; and the third conductive layer may include connecting structures such as conductive blocks and connecting electrodes for connecting different transistors.

[0114] For example, the first insulating layer, the second insulating layer, and the third insulating layer may be made of an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, or an organic insulating material, such as resin.

[0115] For example, sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the substrate includes forming corresponding material layers (e.g., a semiconductor material layer, an insulating material layer, or a conductive material layer), and then using a patterning process to form corresponding pattern structures (e.g., an active layer, an electrode pattern, a trace, a via, etc.). The patterning process is, for example, a photolithography process, which includes, for example: coating a photoresist layer on the material layer to be patterned, exposing the photoresist layer using a mask, developing the exposed photoresist layer to obtain a photoresist pattern, etching the structural layer using the photoresist pattern, and then optionally removing the photoresist pattern.

[0116] It should be noted that in various embodiments of the present disclosure, the process of the method for manufacturing a display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the process of the manufacturing method described above includes multiple operations that appear in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The manufacturing method described above can be performed once or multiple times according to predetermined conditions.

[0117] There are a few points to note:

[0118] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0119] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0120] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a shift register and a clock signal line arranged on the base substrate; Wherein, the shift register comprises an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit; The output end of the input circuit, the control end of the output circuit, and the control end of the second control circuit are connected to the first node, the input end of the input circuit is connected to the first scan input end, and the input end of the output circuit is connected to the clock signal line; The output end of the first control circuit, the input end of the second control circuit, the control end of the first noise reduction circuit and the control end of the second noise reduction circuit are connected to a second node, the input end of the first control circuit is configured to receive a first voltage signal, and the output end of the first noise reduction circuit and the output end of the second noise reduction circuit are configured to receive a second voltage signal; The input circuit includes a first transistor and a second transistor, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the first transistor is connected to the gate of the second transistor and serves as a control terminal of the input circuit, the first electrode of the first transistor serves as an input terminal of the input circuit, and the second electrode of the second transistor serves as an output terminal of the input circuit. The first transistor and the second transistor are both oxide transistors, the second node is connected to the second voltage signal only through the second control circuit, and the potential is pulled down only through the second control circuit.

2. The display substrate according to claim 1, further comprising a first voltage line and a second voltage line located on the base substrate, the first voltage line being configured to apply the first voltage signal, and the second voltage line being configured to apply the second voltage signal; The second node is connected to the second voltage line only through the second control circuit.

3. The display substrate according to claim 1, wherein: The channel width-to-length ratio of the first transistor is in the range of 6-14, and the channel width-to-length ratio of the second transistor is in the range of 6-14.

4. The display substrate according to claim 3, wherein: The channel width-to-length ratio of the first transistor is in the range of 8-12, and the channel width-to-length ratio of the second transistor is in the range of 8-12.

5. The display substrate according to any one of claims 1 to 4, wherein: The shift register further includes a third noise reduction circuit, wherein a control terminal of the third noise reduction circuit is connected to the second node, an input terminal of the third noise reduction circuit is connected to the second electrode of the first transistor, and an output terminal of the third noise reduction circuit is configured to receive the second voltage signal; The third noise reduction circuit is configured to respond to the voltage on the second node to reduce noise on the second electrode of the first transistor via the second voltage signal.

6. The display substrate according to claim 5, wherein: The third noise reduction circuit includes a third transistor, a gate of the third transistor serves as a control end of the third noise reduction circuit, a first electrode of the third transistor serves as an input end of the third noise reduction circuit, and a second electrode of the third transistor serves as an output end of the third noise reduction circuit.

7. The display substrate according to claim 6, wherein: The channel length of the third transistor is greater than 5 micrometers.

8. The display substrate according to any one of claims 1 to 7, wherein: The shift register further comprises a reset circuit, wherein an input end of the reset circuit is connected to the first node, and an output end of the reset circuit is connected to the second scan input end; The reset circuit is configured to respond to a reset signal on a control terminal of the reset circuit to reset the first node through the second scan input terminal.

9. The display substrate according to claim 8, wherein: The reset circuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the gate of the fifth transistor and serves as a control terminal of the reset transistor, the first electrode of the fourth transistor is connected to the second electrode of the fifth transistor, the second electrode of the fourth transistor serves as an output terminal of the reset circuit, and the first electrode of the fifth transistor serves as an input terminal of the reset circuit. The fourth transistor and the fifth transistor are oxide transistors.

10. The display substrate according to claim 9, wherein: The channel width-to-length ratio of the fourth transistor is in the range of 6-14, and the channel width-to-length ratio of the fifth transistor is in the range of 6-14.

11. The display substrate according to claim 10, wherein: The channel width-to-length ratio of the fourth transistor is in the range of 8-12, and the channel width-to-length ratio of the fifth transistor is in the range of 8-12.

12. The display substrate according to claim 8, wherein: The shift register further includes a fourth noise reduction circuit, wherein a control terminal of the fourth noise reduction circuit is connected to the second node, an input terminal of the fourth noise reduction circuit is connected to the first electrode of the fourth transistor, and an output terminal of the fourth noise reduction circuit is configured to receive the second voltage signal; The fourth noise reduction circuit is configured to respond to the voltage on the second node to reduce noise on the first electrode of the fourth transistor via the second voltage signal.

13. The display substrate according to claim 12, wherein: The fourth noise reduction transistor includes a sixth transistor, a gate of the sixth transistor serves as a control terminal of the fourth noise reduction circuit, a first electrode of the sixth transistor serves as an input terminal of the fourth noise reduction circuit, and a second electrode of the sixth transistor serves as an output terminal of the fourth noise reduction circuit.

14. The display substrate according to claim 13, wherein: The channel length of the sixth transistor is greater than 5 micrometers.

15. The display substrate according to any one of claims 1 to 14, wherein: The first control circuit includes a seventh transistor, a first electrode of the seventh transistor serves as an input end of the first control circuit, a second electrode of the seventh transistor serves as an output end of the first control circuit, and a gate of the seventh transistor serves as a control end of the first control circuit.

16. The display substrate according to claim 15, wherein: The seventh transistor comprises: A first semiconductor block including a first end and a second end; A second semiconductor block including a third end and a fourth end; and a first floating electrode, overlapping the first semiconductor block and located between the first end and the second end; and a second floating electrode, which is connected to the second semiconductor block and is located between the third end and the fourth end; The first electrode of the seventh transistor is connected to the first end and the third end, and the second electrode of the seventh transistor is connected to the second end and the fourth end.

17. The display substrate according to claim 16, wherein: The first floating electrode and the second floating electrode are a continuous integrated structure.

18. The display substrate according to any one of claims 1 to 17, wherein: The second control circuit includes an eighth transistor, a gate of the eighth transistor serves as a control terminal of the second control circuit, a first electrode of the eighth transistor serves as an input terminal of the second control circuit, and a second electrode of the eighth transistor serves as an output terminal of the second control circuit.

19. The display substrate according to any one of claims 1 to 17, wherein: The output circuit includes a ninth transistor, a gate of the ninth transistor serves as a control terminal of the output circuit, a first electrode of the ninth transistor serves as an input terminal of the output circuit, and a second electrode of the ninth transistor serves as an output terminal of the output circuit.

20. The display substrate according to any one of claims 1 to 17, wherein: The first noise reduction circuit includes a tenth transistor, and the second noise reduction circuit includes an eleventh transistor. The gate of the tenth transistor serves as the control end of the first noise reduction circuit, the first electrode of the tenth transistor serves as the input end of the first noise reduction circuit, and the second electrode of the tenth transistor serves as the output end of the first noise reduction circuit. The gate of the eleventh transistor serves as the control end of the second noise reduction circuit, the first electrode of the eleventh transistor serves as the input end of the second noise reduction circuit, and the second electrode of the eleventh transistor serves as the output end of the second noise reduction circuit.

21. The display substrate according to any one of claims 1 to 20, wherein: The shift register further includes a first clearing circuit and a second clearing circuit; The input end of the first clearing circuit is connected to the first node, the output end of the first clearing circuit is configured to receive the second voltage signal, the input end of the second clearing circuit is connected to the output end, and the output end of the second clearing circuit is configured to receive the second voltage signal; The first clearing circuit is configured to respond to a clearing control signal to reset the first node through the second voltage signal, and the second clearing circuit is configured to respond to a clearing control signal to reset the output terminal through the second voltage signal.

22. The display substrate according to claim 21, wherein: The first clearing circuit includes a twelfth transistor, the second clearing circuit includes a thirteenth transistor, the gate of the twelfth transistor is the control end of the first clearing circuit, the first pole of the twelfth transistor is the input end of the first clearing circuit, and the second pole of the twelfth transistor is the output end of the first clearing circuit. The gate of the thirteenth transistor is the control end of the second clearing circuit, the first pole of the thirteenth transistor is the input end of the second clearing circuit, and the second pole of the thirteenth transistor is the output end of the second clearing circuit.

23. A display device comprising the display substrate according to any one of claims 1 to 22.

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