Electronic device including display driver circuit that adaptively stores images

Abstract

An example electronic device may include a display panel, a display driver circuit operably coupled to the display panel and including a memory, and a processor operably coupled to the display driver circuit. The processor may be configured to: identify a refresh rate; and according to the identified refresh rate, providing a first signal to the display driver circuit indicating that one or more images provided from the processor are stored in the memory such that the images are displayed on the display panel according to the refresh rate, or providing a second signal to the display driver circuit indicating that the one or more images provided from the processor are stored in the memory such that the images are displayed on the display panel according to the refresh rate. The second signal indicates that the one or more images are bypassed being stored in the memory.

Description

Technical Field

[0001] The following description relates to an electronic device including a display driver circuit that adaptively stores an image. Background Art

[0002] The electronic device may include a display panel. For example, the electronic device may include a display driver circuit operably coupled to the display panel. For example, the display driver circuit may display an image obtained from a processor of the electronic device on the display panel.

[0003] The above information may be provided as related art for the purpose of assisting understanding of the present disclosure. No claim or determination is made as to whether any of the above information may be applicable as prior art related to the present disclosure. Summary of the invention

[0004] Technical Solution

[0005] An electronic device is provided. The electronic device may include a display panel. The electronic device may include a display driver circuit operably coupled to the display panel and including a memory. The electronic device may include a processor operably coupled to the display driver circuit. The display driver circuit may be configured to display a first image obtained from the processor on the display panel in a first time interval. The display driver circuit may be configured to store the first image obtained from the processor in the first time interval in the memory based on the first image being maintained on the display panel in a second time interval after the first time interval. The display driver circuit may be configured to bypass storing the first image in the memory in the first time interval based on the first image being changed to the second image in the second time interval.

[0006] An electronic device is provided. The electronic device may include a switch. The electronic device may include a display panel. The electronic device may include a processor. The electronic device may include a display driver circuit that is operably coupled to a display panel 340 and includes a memory that can be connected to the processor through a switch. The display driver circuit may be configured to display a first image obtained from the processor on the display panel. The display driver circuit may be configured to store the first image in the memory based on connecting the processor and the memory through the switch when the first image is obtained from the processor. The display driver circuit may be configured to bypass storing the first image in the memory based on disconnecting the memory from the processor through the switch when the first image is obtained from the processor.

[0007] An electronic device is provided. The electronic device may include a display panel. The electronic device may include a display driver circuit operably coupled to the display panel and including a memory. The electronic device may include a processor operably coupled to the display driver circuit. The processor may be configured to identify a refresh rate. The processor may be configured to provide a first signal to the display driver circuit in response to the refresh rate being lower than a reference refresh rate, the first signal indicating that one or more images to be provided from the processor for display on the display panel according to the refresh rate are stored in the memory. The processor may be configured to provide a second signal to the display driver circuit in response to the refresh rate being higher than or equal to the reference refresh rate, indicating bypassing the storage of the one or more images in the memory.

[0008] An electronic device is provided. The electronic device may include a display panel. The electronic device may include a display driver circuit operably coupled to the display panel and including a memory. The electronic device may include a processor operably coupled to the display driver circuit. The processor may be configured to identify a refresh rate. The processor may be configured to provide a first signal to the display driver circuit, the first signal indicating that one or more images to be provided from the processor for display on the display panel according to the refresh rate are stored in the memory, or to provide a second signal to the display driver circuit, the second signal indicating that the storage of the one or more images in the memory is bypassed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of the first mode is shown.

[0010] Figure 2 An example of the second mode is shown.

[0011] Figure 3 is a simplified block diagram of an exemplary electronic device.

[0012] Figure 4 An exemplary method of adaptively storing a first image is shown.

[0013] Figure 5 An example of storing the first image is shown.

[0014] Figure 6 An example of bypassing storage of the first image is shown.

[0015] Figure 7 An exemplary method of again providing the first image to the display driver circuit is shown.

[0016] Figure 8 An exemplary method of maintaining an image displayed on a display panel after a refresh rate change is shown.

[0017] Fig. 9 An exemplary method of performing a single display of the second image or a plurality of displays of the second images according to the length of the second time interval is shown.

[0018] Fig.10 An example in which multiple displays of the second image are performed is shown.

[0019] Fig.11 An exemplary method of performing a single display of the second image or a plurality of displays of the second images according to a time length is shown.

[0020] Fig.12 An exemplary method of performing a single display of the second image or a plurality of displays of the second image according to the length of the first time interval is shown.

[0021] Fig.13 An exemplary method of storing a second image in a second time interval independently of a predetermined signal indicating that the second image displayed in the second time interval is changed to a third image in a third time interval is shown.

[0022] Fig.14 An example is shown in which the second image is stored in the second time interval independently of a predetermined signal indicating that the second image displayed in the second time interval is changed to a third image in the third time interval.

[0023] Fig.15 is a flow chart illustrating an exemplary method of providing a first signal or a second signal according to a refresh rate.

[0024] Fig.16 An exemplary method of storing one or more images based on a first signal provided based on a refresh rate lower than a reference refresh rate is shown.

[0025] Fig.17 An exemplary method of bypassing storage of one or more images based on a second signal provided based on a refresh rate that is greater than or equal to a reference refresh rate is shown.

[0026] Fig.18 is a flow chart illustrating an exemplary method of storing an image in a memory within an initial time interval when a second signal is provided after a first signal is provided.

[0027] Fig.19 An exemplary method of storing an image in a memory during an initial time interval when a second signal is provided after a first signal is provided is shown.

[0028] Fig. 20 is a flow chart illustrating an exemplary method of providing a third signal.

[0029] Fig.21 An exemplary method of storing an image based on a third signal is shown.

[0030] Fig. 22 An exemplary method of delaying display of an image is shown.

[0031] Fig.23 is a block diagram of an electronic device in a network environment according to various embodiments.

[0032] Fig.24 is a block diagram of a display module according to various embodiments. DETAILED DESCRIPTION

[0033] The electronic device may include a processor, a display driver circuit, and a display panel. For example, the display driver circuit may display an image obtained by the processor on the display panel. For example, the display driver circuit may display an image on the display panel based on a first mode or a second mode.

[0034] For example, the first mode may indicate a mode for displaying an image through a memory (e.g., a graphic random access memory (GRAM)) in a display driver circuit. For example, the display driver circuit may display an image on a display panel by storing data for displaying an image obtained from a processor in the memory and scanning the data stored in the memory based on the first mode. For example, the first mode may indicate a command mode of a display serial interface (DSI). Figure 1 The first mode will be described.

[0035] For example, unlike the first mode, the second mode may indicate a mode for displaying an image without using a memory. For example, the second mode may indicate a mode provided by a display driver circuit that does not include a memory. For example, the display driver circuit may display an image obtained from a processor on a display panel based on the second mode. For example, the second mode may indicate a video mode of a DSI. Figure 2 The second mode will be described.

[0036] Figure 1 An example of the first mode is shown.

[0037] refer to Figure 1In operation 101, the display driver circuit 160 may provide a synchronization signal to the processor 150 for the first mode. For example, the synchronization signal may be provided from the display driver circuit 160 to the processor 150 to identify the timing when the processor 150 provides an image to the display driver circuit 160. For example, the synchronization signal may be provided from the display driver circuit 160 to the processor 150 to identify the timing of storing (or writing) data obtained from the processor 150 and used to display an image in a memory within the display driver circuit 160. For example, since the state of the display driver circuit 160 (or the state of the memory) is not recognized by the processor 150 in the first mode, the display driver circuit 160 may provide the synchronization signal to the processor 150. For example, the synchronization signal may be a tearing effect (TE) signal. For example, the processor 150 may obtain the synchronization signal from the display driver circuit 160.

[0038] In operation 103, the processor 150 may provide the display driver circuit 160 with data for displaying an image obtained by the processor 150 in response to the synchronization signal. For example, the display driver circuit 160 may obtain the data from the processor 150.

[0039] In operation 105 , the display driver circuit 160 may store or record the data in a memory.

[0040] In operation 107 , the display driver circuit 160 may display an image on the display panel by scanning the data stored in the memory.

[0041] As mentioned above, Figure 2 Compared to the second mode shown in FIG. 1 , the first mode may further include storing data in the memory by the display driver circuit 160 as in operation 105, and scanning the data stored in the memory by the display driver circuit 160 as in operation 107. For example, compared to the second mode, the first mode may cause additional power consumption by storing data and scanning data.

[0042] For example, in response to a synchronization signal from the display driver circuit 160 to the processor 150, the image newly obtained in the first mode can be provided from the processor 150 to the display driver circuit 160. On the other hand, based on the synchronization signal from the processor (for example, Figure 2 The timing identified by the processor 250 shown in FIG. 2 provides the newly acquired image in the second mode to the display driver circuit (for example, Figure 2 ). For example, the first mode may have a lower responsiveness than the second mode.

[0043] Figure 2 An example of the second mode is shown.

[0044] refer to Figure 2 In operation 201, the processor 250 may provide an image to the display driver circuit 260 for the second mode. Figure 1 Unlike the first mode shown in FIG. 2 , the processor 250 may provide the image to the display driver circuit 260 based on the timing identified by the processor 250. For example, the transmission throughput from the processor 250 to the display driver circuit 260 in operation 201 may be less than that in operation 202. Figure 1 The transmission throughput from the processor 150 to the display driver circuit 160 in operation 103 of FIG. For example, the transmission from the processor 150 to the display driver circuit 160 in the first mode may be a data burst transmission, unlike the transmission from the processor 250 to the display driver circuit 260 in operation 201. For example, the display driver circuit 260 may obtain an image from the processor 250.

[0045] In operation 203 , the display driver circuit 260 may display an image obtained from the processor 250 on a display panel.

[0046] As described above, unlike the first mode, the second mode may be provided by a display driver circuit 260 that does not include a memory or does not use a memory. For example, since the second mode is provided without using a memory, the second mode may result in greater power consumption than the first mode when the image displayed on the display panel is continuously maintained. For example, unlike the first mode in which the display driver circuit 160 may continuously maintain the image displayed on the display panel by repeatedly scanning the data stored in the memory, the processor 250 may repeatedly send the image to the display driver circuit 260 within the second mode to continuously maintain the image displayed on the display panel. For example, since the processor 250 performs repeated transmission in the second mode, the second mode may result in greater power consumption than the first mode when the image displayed on the display panel is continuously maintained.

[0047] The electronic device described below may include a display driver circuit that adaptively stores an image for a second mode. For example, when an image displayed on a display panel is continuously maintained, the electronic device may reduce power consumed by displaying the image based on storing the image in a memory in the display driver circuit. The components of the electronic device may be Figure 3 Shown in.

[0048] Figure 3 is a simplified block diagram of an exemplary electronic device.

[0049] refer to Figure 3 , the electronic device 300 may include a processor 310 , a display driver circuit 320 , and a display panel 340 .

[0050] For example, processor 310 may include Fig.23 At least a portion of the processor 2320 of the processor 2320. For example, the processor 310 can be connected to the display driver circuit 320 through the interface 315. For example, the interface 315 can be used to provide an image from the processor 310 to the display driver circuit 320. For example, the processor 310 can be operably coupled to the display driver circuit 320 through the interface 315. As a non-limiting example, the interface 315 can include a mobile industry processor interface (MIPI).

[0051] For example, the display driver circuit 320 may include Fig.24 At least a portion of the display driver integrated circuit (IC) 2430 of the display driver circuit 320. For example, the display driver circuit 320 may include a memory 325. For example, the memory 325 may include Fig.24 At least a portion of the memory 2433 of the display driver circuit 320. For example, the display driver circuit 320 may further include a switch 330. For example, the memory 325 may be connected to the processor 310 through the switch 330. For example, the memory 325 may be connected to the processor 310 through the switch 330 in a first state 331. For example, the memory 325 may be disconnected from the processor 310 through the switch 330 in a second state 332.

[0052] Figure 3 An example is shown in which the switch 330 is included in the display driver circuit 320, but the switch 330 may be located outside the display driver circuit 320. Figure 3 However, it is not limited to this.

[0053] For example, the display panel 340 may include Fig.24 At least a portion of the display 2410 of the display panel 340. For example, the display panel 340 may include a low temperature poly-crystalline oxide thin film transistor (LTPO TFT) or a low temperature poly-silicon thin film transistor (LTPS TFT). However, it is not limited thereto. For example, the display panel 340 may be operably coupled to the display driver circuit 320.

[0054] For example, the processor 310 and the display driver circuit 320 may be configured to perform operations to be described below.

[0055] Figure 4 An exemplary method for adaptively storing a first image is illustrated. The method may be performed by Figure 3 The processor 310 and the display driver circuit 320 execute.

[0056] refer to Figure 4 In operation 401, the processor 310 may provide the first image to the display driver circuit 320 within a first time interval. For example, the first image may be sent from the processor 310 to the display driver circuit 320 based on the second mode. For example, the first time interval may correspond to a period of a vertical synchronization signal. For example, the first time interval may correspond to a refresh rate of the first image. For example, the refresh rate of the first image may indicate a frequency targeted (or identified) for displaying the image when obtaining or rendering the first image. For example, the first time interval may be a time interval identified for the first image when obtaining or rendering the first image.

[0057] In operation 403, the display driver circuit 320 may display the first image obtained from the processor 310 on the display panel 340 within the first time interval. For example, the display driver circuit 320 may display the first image on the display panel 340 based on the second mode. For example, displaying the first image obtained from the processor 310 within the first time interval may include displaying the first image obtained from the processor 310 within at least a portion of the first time interval. However, it is not limited thereto.

[0058] In operation 405, the display driver circuit 320 may identify whether the first image is maintained on the display panel 340 during a second time interval immediately following (after) the first time interval. Figure 5 The predetermined signal 550 shown will be Figure 6 The predetermined signal 650 shown and / or will be Fig.14 The identification is performed by using the predetermined signal 1450 shown. However, it is not limited thereto. The predetermined signal 450, the predetermined signal 650 and / or the predetermined signal 1450 may be referred to as, for example, a still indication. For example, the still indication includes a sticky mark indication (or sticky mark) and / or an in-operation indication (or in-operation).

[0059] For example, the display driver circuit 320 may perform operation 407 based on identifying that the first image is to be maintained on the display panel 340 during the second time interval, and bypass performing operation 407 based on identifying that the first image is to be changed to the second image during the second time interval.

[0060] Figure 4An example of performing operation 405 after performing operations 401 and 403 is illustrated, but operation 405 may be performed before performing operation 401. For example, identifying whether to keep the first image on the display panel 340 in the second time interval may be performed in a third time interval before the first time interval. For example, identifying whether to keep the first image on the display panel 340 in the second time interval may be performed in a third time interval before the first time interval. For example, the identification of operation 405 may be performed based on a predetermined signal provided from the processor 310 to the display driver circuit 320. For example, the predetermined signal may be received in the third time interval. For example, the predetermined signal may be provided from the processor 310 to the display driver circuit 320 through a front porch portion of a vertical synchronization signal for displaying the first image. For example, the predetermined signal may indicate that the first image to be displayed on the display panel 340 in the first time interval is to be maintained in the second time interval. For example, the predetermined signal may indicate that the first image to be displayed on the display panel 340 in the first time interval is to be changed to the second image in the second time interval. For example, the display driver circuit 320 may perform operation 407 based on obtaining a predetermined signal indicating that the first image is to be maintained for the second time interval from the processor 310 before the first image is obtained. As a non-limiting example, the predetermined signal may be obtained from the processor 310 through a front porch portion of a vertical synchronization signal for displaying the first image. For example, the display driver circuit 320 may bypass the execution of operation 407 based on obtaining a predetermined signal indicating that the first image is to be changed to the second image for the second time interval from the processor 310 before the first image is obtained. As a non-limiting example, the predetermined signal may be obtained from the processor 310 through a front porch portion of a vertical synchronization signal for displaying the first image. For example, the display driver circuit 320 may bypass the execution of operation 407 based on recognizing that a predetermined signal indicating that the first image is to be maintained for the second time interval is not obtained from the processor 310 before the first image is obtained. However, it is not limited thereto.

[0061] In operation 407, under the condition that the first image is to be maintained on the display panel 340 for the second time interval, the display driver circuit 320 may store the first image in the memory 325. For example, storing the first image in the memory 325 may be initiated from a timing recognized by the processor 310 among the processor 310 and the display driver circuit 320. For example, the display driver circuit 320 may be executed in response to a synchronization signal from the display driver circuit. Figure 1 Unlike operation 103, storing the first image in the memory 325 may be performed based on the timing identified by the processor 310. Figure 5 The first image is described as being stored in the memory 325 .

[0062] Figure 5 An example of storing the first image is shown.

[0063] Reference Figure 5 , the display driver circuit 320 may obtain a first image from the processor 310 through the interface 315 within a first time interval 510 corresponding to a period of the vertical synchronization signal. For example, a state of the interface 315, such as a state 590, may be indicated according to the first image sent from the processor 310 to the display driver circuit 320 within the first time interval 510. For example, as indicated by an arrow 579, the display driver circuit 320 may display the first image obtained from the processor 310 through the interface 315 on the display panel 340 based on the vertical synchronization signal (or the start timing 511 of the vertical synchronization signal).

[0064] For example, the display driver circuit 320 may store or record the first image obtained from the processor 310 in the memory 325 based on recognizing that the first image is to be maintained in the second time interval 520 immediately following (after) the first time interval 510. For example, the storing of the first image in the memory 325 may be performed based on the start timing 511 of the vertical synchronization signal, such as indicated by arrow 580.

[0065] For example, identifying that the first image is to be maintained within the second time interval 520 may be performed within the third time interval 530 prior to the first time interval 510. For example, the processor 310 may provide a predetermined signal 550 to the display driver circuit 320 within the third time interval 530, the predetermined signal 550 indicating that the first image to be displayed from the first time interval 510 is to be maintained on the display panel 340. For example, the predetermined signal 550 may be obtained from the processor 310 through the front porch portion of the vertical synchronization signal for displaying the first image. For example, the predetermined signal 550 obtained from the processor 310 through the front porch portion may indicate that the first image is stored or recorded in the memory 325. For example, the first image may be stored based on the storage location (e.g., the address of the register) of the predetermined signal 550 obtained from the processor 310 through the front porch portion. However, it is not limited thereto. For example, as shown by arrow 581, the display driver circuit 320 may store the first image obtained from the processor 310 within the first time interval 510 in the memory 325 based on the predetermined signal 550. On the other hand, as shown by arrow 578, the display driver circuit 320 may display on the display panel 340 a third image obtained from the processor 310 through the interface 315 within the third time interval 530. For example, the predetermined signal 550 may be obtained from the processor 310 while the third image is transmitted from the processor 310 within the third time interval 530. However, this is not limited thereto. For example, the predetermined signal 550 may be obtained from the processor 310 at a timing within the third time interval 530 after the transmission of the third image is completed. For example, the predetermined signal 550 may be transmitted from the processor 310 to the display driver circuit 320 based on a diversity scheme. For example, the predetermined signal 550 may be transmitted from the processor 310 based on the address value of each of the plurality of registers in the display driver circuit 320. For example, the processor 310 may provide the predetermined signal 550 to the display driver circuit 320 through a plurality of transmissions within the third time interval 530. For example, a plurality of transmissions may be performed to increase the reception rate of the predetermined signal 550. However, this is not limited thereto.

[0066] For example, the predetermined signal 550 may be provided by various methods. For example, between the predetermined signal 550 and the predetermined signal (e.g., Figure 6In the predetermined signal 650 in the display panel 340, a predetermined signal may be provided from the processor 310 at each time interval. For another example, the predetermined signal 550 may be provided from the processor 310 in response to recognizing that the image will remain on the display panel 340 for two or more time intervals, and not provided from the processor 310 when the image remains on the display panel 340. For example, the processor 310 may control the display driver circuit 320 to bypass storing the image in the memory 325 by providing the predetermined signal 650 to be shown below in response to recognizing a change in the image. However, it is not limited thereto.

[0067] For example, the predetermined signal 550 may indicate that one or more images provided from the processor 310 to the display driver circuit 320 are to be stored in the memory 325 until a signal is obtained from the processor 310 to be transmitted through the display driver circuit 320 after obtaining the predetermined signal 550. Figure 6 For another example, the predetermined signal 550 may indicate that the image (e.g., Figure 5 The first image of FIG. 1 is stored in the memory 325. However, this is not limited to this.

[0068] For example, as indicated by arrow 582, the display driver circuit 320 may maintain the first image displayed on the display panel 340 within the second time interval 520 by scanning the first image stored in the memory 325 within the second time interval 520. For example, maintaining the first image within the second time interval 520 may indicate that the first image is not changed to another image (e.g., the second image in the above example). For example, as indicated by arrow 583, the scanning may be performed based on the vertical synchronization signal (or the start timing 521 of the vertical synchronization signal). On the other hand, the processor 310 may avoid providing the first image to the display driver circuit 320 within the second time interval 520. For example, the state of the interface 315 within the second time interval 520, such as state 591, may be indicated.

[0069] Return to reference Figure 3 In a case where a first image displayed on the display panel 340 within a first time interval is to be maintained within a second time interval, the display driver circuit 320 may set the state of the switch 330 to the first state 331, and store the first image in the memory 325 connected to the processor 310 through the switch 330 in the first state 331.

[0070] On the other hand, under the condition that the first image displayed on the display panel 340 in the first time interval is to be changed to the second image in the second time interval, the display driver circuit 320 can bypass storing the first image in the memory 325 by setting the state of the switch 330 to the second state 332 and disconnecting the memory 325 from the processor 310 through the switch 330 in the second state 332. Figure 6 The description bypasses storing the first image in memory 325 .

[0071] Figure 6 An example of bypassing storage of the first image is described.

[0072] Reference Figure 6 , the display driver circuit 320 may obtain a first image from the processor 310 through the interface 315 within a first time interval 510 corresponding to a period of the vertical synchronization signal. For example, a state of the interface 315, such as a state 590, may be indicated according to the first image sent from the processor 310 to the display driver circuit 320 within the first time interval 510. For example, as indicated by an arrow 579, the display driver circuit 320 may display the first image obtained from the processor 310 through the interface 315 on the display panel 340 based on the vertical synchronization signal (or the start timing 511 of the vertical synchronization signal).

[0073] For example, the display driver circuit 320 may bypass or avoid storing or recording the first image obtained from the processor 310 in the memory 325 based on recognizing that the first image will be changed to the second image in the second time interval 520 immediately following (after) the first time interval 510 .

[0074] For example, identifying that the first image is to be changed to the second image within the second time interval 520 may be performed within the third time interval 530 prior to the first time interval 510. For example, identifying that the first image is to be changed to the second image within the second time interval 520 may be performed by identifying that the display driver circuit 320 does not obtain the predetermined signal 550 from the processor 310 within the third time interval 530 prior to the first time interval 510. For example, identifying that the first image is to be changed to the second image within the second time interval 520 may be performed based on the display driver circuit 320 obtaining the predetermined signal 650 from the processor 310 within the third time interval 530. For example, within the third time interval 530, the processor 310 may provide the display driver circuit 320 with the predetermined signal 650 indicating that the first image to be displayed from the first time interval 510 is changed within the second time interval 520. For example, the predetermined signal 650 may be obtained from the processor 310 through a front porch portion of a vertical synchronization signal for displaying the first image. For example, the predetermined signal 650 obtained from the processor 310 through the front porch portion may indicate bypassing or avoiding storing the first image in the memory 325. For example, bypassing the storage of the first image may be identified based on the storage location (e.g., the address of the register) of the predetermined signal 650 obtained from the processor 310 through the front porch portion. For example, the address of the predetermined signal 650 may be different from the address of the predetermined signal 550. However, it is not limited thereto. For example, as shown by arrow 681, the display driver circuit 320 may bypass storing the first image obtained from the processor 310 in the first time interval 510 in the memory 325 based on the predetermined signal 650. On the other hand, as shown by arrow 578, the display driver circuit 320 may display the third image obtained from the processor 310 through the interface 315 in the third time interval 530 on the display panel 340. For example, the predetermined signal 650 may be obtained from the processor 310 while the third image is sent from the processor 310 in the third time interval 530. However, it is not limited thereto. For example, the predetermined signal 650 may be obtained from the processor 310 at a timing in the third time interval 530 after the transmission of the third image is completed. For example, the predetermined signal 650 may be sent from the processor 310 to the display driver circuit 320 based on a diversity scheme. However, it is not limited to this.

[0075] For example, as indicated by arrow 682, display driver circuit 320 may display on display panel 340 a second image obtained from processor 310 via interface 315 during second time interval 520. For example, a state of interface 315, such as state 691, may be indicated based on the second image sent from processor 310 to display driver circuit 320 during second time interval 520.

[0076] For example, the predetermined signal 650 may be provided by various methods. For example, among the predetermined signal 550 and the predetermined signal 650, one predetermined signal may be provided from the processor 310 at each time interval. For another example, the predetermined signal 650 may be provided from the processor 310 in response to recognizing that the image is to be changed on the display panel 340, and when the image is to be changed on the display panel 340 at each time interval after the predetermined signal 650 is provided from the processor 310, the predetermined signal 650 is not provided from the processor 310. For example, the processor 310 may control the display driver circuit 320 to store the image in the memory 325 by providing the predetermined signal 550 in response to recognizing that the image is to be maintained for two or more time intervals. However, it is not limited thereto.

[0077] For example, the predetermined signal 650 may indicate that one or more images provided from the processor 310 to the display driver circuit 320 are bypassed from being stored in the memory 325 until the predetermined signal 550 is obtained from the processor 310 after the predetermined signal 650 is obtained. For another example, the predetermined signal 650 may indicate that only images (e.g., images obtained after (or immediately after) the predetermined signal 650 is obtained from the processor 310) are to be stored in the memory 325. Figure 6 The first image of the image) is stored in the memory 325 and is bypassed. However, this is not limited to this.

[0078] As described above, the display driver circuit 320 in the electronic device 300 can recognize whether the image is to be maintained or changed, and store the image obtained from the processor 310 in the memory 325 under the condition that the image is to be maintained. For example, the electronic device 300 can reduce the power consumed in displaying the image during the second mode while maintaining the image by having the display driver circuit 320 scan the image in the memory 325 instead of the processor 310 repeatedly sending the image to the display driver circuit 320.

[0079] Figure 7 An exemplary method of providing the first image to the display driver circuit again is shown. The method may be performed by Figure 3 Executed by processor 310.

[0080] Figure 7 Operation 701 and operation 703 can be combined with Figure 5 The description shows that the predetermined signal 550 is related.

[0081] refer to Figure 7In operation 701, the processor 310 may recognize that the predetermined signal is not provided to the display driver circuit 320, the predetermined signal indicating that the first image is maintained on the display panel 340 in a second time interval immediately following (after) the first time interval. For example, the processor 310 may recognize that the first image is to be maintained on the display panel 340 in the second time interval at a first timing in a third time interval before the first time interval. For example, the processor 310 may recognize that the predetermined signal is not provided to the display driver circuit 320 based on recognizing that the time length between the first timing and the second timing is shorter than the time length for providing the predetermined signal to the display driver circuit 320, wherein the second timing is the start timing of the first time interval. For another example, the processor 310 may recognize that the predetermined signal is not provided to the display driver circuit 320 based on recognizing that the change of the state of the switch 330 to the first state 331 will be performed after the first image is sent to the display driver circuit 320 in response to providing the predetermined signal to the display driver circuit 320 in the third time interval. For another example, the processor 310 may recognize that the predetermined signal is not provided to the display driver circuit 320 based on recognizing that a portion of the first image provided from the processor 310 when the predetermined signal is provided to the display driver circuit 320 in the third time interval is not stored in the memory 325. For another example, the processor 310 may recognize that the predetermined signal is not provided to the display driver circuit 320 based on recognizing that the predetermined signal is not provided through the front porch portion of the vertical synchronization signal (for example, corresponding to the first time interval) for displaying the first image. However, it is not limited thereto.

[0082] In operation 703, based on the identification in operation 701, the processor 310 may provide the first image to the display driver circuit 320 in the first time interval, and may provide the first image to the display driver circuit 320 again in the second time interval. For example, since the display driver circuit 320 does not obtain the predetermined signal from the processor 310 in the third time interval, the display driver circuit 320 may bypass storing the first image obtained from the processor 310 in the first time interval in the memory 325 in the second time interval, and display the first image obtained from the processor 310 in the first time interval on the display panel 340. For example, since the storage of the first image in the first time interval is bypassed, the display driver circuit 320 may display the first image provided again from the processor 310 in the second time interval on the display panel 340. For example, the display driver circuit 320 may store the first image provided again from the processor 310 in the second time interval in the memory 325 based on obtaining the predetermined signal from the processor 310 in the first time interval indicating that the first image is to be kept on the display panel 340 in the fourth time interval immediately following (after) the second time interval. For example, the predetermined signal may be provided from the processor 310 to the display driver circuit 320 through a front porch portion of a vertical synchronization signal corresponding to the second time interval. However, it is not limited thereto.

[0083] As described above, when the predetermined signal is not provided to the display driver circuit 320 , the processor 310 of the electronic device 300 may reduce interruption of display on the display panel 340 by transmitting the first image to the display driver circuit 320 again.

[0084] Figure 8 An exemplary method of maintaining an image displayed on a display panel after a refresh rate change is shown. The method may be performed by Figure 3 The processor 310 and the display driver circuit 320 execute.

[0085] refer to Figure 8 In operation 801, the processor 310 may recognize that a first image displayed on the display panel 340 from a first time interval will be maintained for a plurality of time intervals including the first time interval and a second time interval immediately following (after) the first time interval, or recognize that the first image will be maintained for the plurality of time intervals. For example, the processor 310 may recognize, based on the recognition, that a refresh rate for displaying the first image will be changed from a first refresh rate corresponding to each of the plurality of time intervals to a second refresh rate lower than the first refresh rate.

[0086] In operation 803, the processor 310 may provide a signal indicating that the refresh rate is changed from the first refresh rate to the second refresh rate to the display driver circuit 320. For example, the refresh rate is recognized by the processor 310 and the display driver circuit 320 during the second mode, but the first image is maintained on the display panel 340 by scanning the first image stored in the display driver circuit 320, so the processor 310 may provide the signal to the display driver circuit 320. For example, the signal may be Figure 5 The predetermined signal 550 is provided to the display driver circuit 320. For example, the signal provided to the display driver circuit 320 may indicate that the period of the vertical synchronization signal is changed from the first period to the second period longer than the first period. For example, the signal may indicate a third time interval having a length longer than each of the plurality of time intervals as the time interval immediately following (after) the plurality of time intervals. However, this is not limited thereto.

[0087] In operation 805, the display driver circuit 320 may maintain the first image on the display panel 340 by scanning the first image stored in the memory 325 within the third time interval based on the signal provided from the processor 310. For example, scanning the first image in operation 805 may be performed based on the second refresh rate. For example, scanning the first image based on the second refresh rate (e.g., 30 Hertz (Hz)) may include completing scanning of the first image stored in the memory 325 within a portion of the third time interval corresponding to the second refresh rate (e.g., a time interval corresponding to 120 Hz). In this case, displaying the first image on the display panel 340 may be stopped within another portion of the third time interval (e.g., a time interval corresponding to 40 Hz). However, it is not limited thereto.

[0088] although Figure 8 Although not shown in the figure, the processor 310 may recognize that the first image is to be maintained on the display panel 340 for a plurality of other time intervals including the third time interval based on the second refresh rate, and may provide a signal indicating that the second refresh rate is to be changed to a third refresh rate lower than the second refresh rate to the display driver circuit 320 based on recognizing that the first image is to be maintained for a plurality of other time intervals. For example, the signal may be Figure 5 The predetermined signal 550 of the electronic device 300 may be a predetermined signal 550. For example, in response to the signal, the display driver circuit 320 may maintain the first image on the display panel 340 by scanning the first image stored in the memory 325 based on the third refresh rate. For example, the second refresh rate may be an intermediate refresh rate for reducing flicker caused on the display panel 340 displaying the first image due to a direct change from the first refresh rate to the third refresh rate. For example, the electronic device 300 may reduce flicker caused on the display panel 340 by changing the first refresh rate to the third refresh rate through the second refresh rate.

[0089] although Figure 8 An example in which the processor 310 recognizes that the first image is continuously maintained on the display panel 340 is illustrated, but the recognition that the first image is continuously maintained on the display panel 340 may also be performed by the display driver circuit 320. For example, the display driver circuit 320 may change the cycle of scanning the first image from the first cycle to a second cycle longer than the first cycle in response to recognizing that a reference time has passed since the timing at which the first image is obtained from the processor 310 (or the timing at which the first image is stored in the memory 325). For example, the display driver circuit 320 may change the cycle of scanning the first image from the second cycle to a third cycle longer than the second cycle in response to recognizing that a reference time has passed since the timing at which the first image is scanned based on the second cycle. As a non-limiting example, the processor 310 may be in a low power state or a sleep state, and the cycle of scanning the first image changes from the first cycle to the third cycle through the second cycle.

[0090] As described above, under the condition that the image is continuously maintained on the display panel 340 , the electronic device 300 can reduce the power consumed for displaying the image by changing the cycle of scanning the image stored in the memory 325 .

[0091] Fig. 9 An exemplary method of performing a single display of a second image or a plurality of displays of a second image according to the length of the second time interval is shown. The method may be performed by Figure 3 The display driver circuit 320 performs.

[0092] The following example Fig. 9 Operations 901 to 911 of the present invention illustrate that when a display is displayed on the display panel 340, Figure 4 The description of exemplifies operations performed in the display driver circuit 320 when the second image is changed from the first image in the second time interval, but this is only for convenience of description. Fig. 9 Operations 901 to 911 may also be applied to Figure 4 The description exemplifies that a first image is displayed on the display panel 340 during a first time interval.

[0093] refer to Fig. 9In operation 901, the display driver circuit 320 may identify whether the length of the second time interval immediately following (after) the first time interval is longer than the reference length. For example, because the probability of an afterimage caused by a hysteresis in a driving transistor for driving an organic light emitting diode (or sub-pixel) in the display panel 340 may increase as the length of time from the end timing of displaying an image to the start timing of displaying the next (subsequent) image increases, the display driver circuit 320 may identify whether the length is longer than the reference length. For example, the display driver circuit 320 may perform operation 903 based on the length being longer than the reference length, and may perform operation 905 based on the length being shorter than or equal to the reference length.

[0094] In operation 903, under the condition that the length is longer than the reference length, the display driver circuit 320 may perform a plurality of displays of the second image on the display panel 340 within the second time interval. For example, the display driver circuit 320 may display the second image obtained from the processor 310 within a portion of the second time interval on the display panel 340 in response to the length being longer than the reference length, and store the second image obtained from the processor 310 within the portion of the second time interval in the memory 325. For example, storing the second image in the memory 325 may be performed independently of whether a predetermined signal indicating that the second image is maintained on the display panel 340 within a third time interval immediately following (after) the second time interval is obtained from the processor 310. For example, the display driver circuit 320 may display the second image on the display panel 340 by scanning the second image stored in the memory 325 within another portion of the second time interval after the portion of the second time interval. For example, a first display of the plurality of displays may be performed based on obtaining a second image from the processor 310 within the portion of the second time interval, and at least one second display of the plurality of displays (e.g., at least one display immediately following (or after) the first display) may be performed based on scanning a second image stored in the memory 325 within the portion of the second time interval. Fig.10 The plurality of displays are shown.

[0095] Fig.10 An example in which multiple displays of the second image are performed is shown.

[0096] refer to Fig.10, the display driver circuit 320 may obtain the second image provided through the interface 315 from the processor 310 based on the timing 1021, which is the start timing of the second time interval 1020 corresponding to the refresh rate for the second image. For example, the state of the interface 315, such as the state 1000, may be indicated according to the second image sent from the processor 310 to the display driver circuit 320 within the portion 1023 of the second time interval 1020. As a non-limiting example, the portion 1023 of the second time interval 1020 may correspond to the maximum speed of the transmission of the second image from the processor 310 to the display driver circuit 320 performed using the interface 315. For example, the maximum speed may indicate the maximum speed available through the interface 315. For example, as indicated by the arrow 1090, the display driver circuit 320 may display the second image obtained from the processor 310 within the portion 1023 of the second time interval 1020 on the display panel 340. For example, the display of the second image within the portion 1023 of the second time interval 1020 may be the first display of the plurality of displays.

[0097] For example, as indicated by arrow 1091, based on the length of the second time interval 1020 being longer than the reference length, the display driver circuit 320 may store the second image obtained from the processor 310 within the portion 1023 of the second time interval 1020 in the memory 325. For example, storing the second image in the memory 325 may be independent of whether a predetermined signal (e.g., Figure 5 For example, even when the predetermined signal is not obtained from the processor 310, the display driver circuit 320 may store the second image in the memory 325 based on the length of the second time interval 1020 being longer than the reference length.

[0098] For example, as indicated by arrow 1092, the display driver circuit 320 may scan the second image stored in the memory 325 based on the timing 1022, which is the end timing of the portion 1023 of the second time interval 1020 or the start timing of another portion 1024 of the second time interval 1020. For example, another portion 1024 of the second time interval 1020 may correspond to the maximum speed. However, it is not limited thereto. For example, another portion 1024 of the second time interval 1020 may be different from the maximum speed. For example, as indicated by arrow 1093, the display driver circuit 320 may display the second image on the display panel 340 within another portion 1024 of the second time interval 1020 by scanning the second image. For example, the display of the second image within another portion 1024 of the second time interval 1020 may be at least one second display among the plurality of displays. For example, the display of the second image within another portion 1024 of the second time interval 1020 may be performed to reduce the probability of causing an afterimage on the display panel 340. For example, the display driver circuit 320 may perform display of the second image within another portion 1024 of the second time interval 1020 so as to reduce the afterimage caused on the display panel 340 according to the length of time from timing 1022 which is the end timing of portion 1023 of the second time interval 1023 to timing 1025 which is the end timing of the second time interval 1020.

[0099] Return to reference Fig. 9 In operation 905, under the condition that the length is shorter than or equal to the reference length, the display driver circuit 320 may perform a single display of the second image on the display panel 340 within the second time interval. For example, since the fact that the length is shorter than or equal to the reference length indicates that the probability of causing an afterimage on the display panel 340 is relatively low, the display driver circuit 320 may perform a single display.

[0100] In operation 907, the display driver circuit 320 may identify whether the second image is to be maintained in a third time interval immediately following (after) the second time interval. For example, operation 907 may correspond to Figure 4 Operation 405.

[0101] For example, the display driver circuit 320 may perform operation 909 based on identifying that the second image is to be maintained for the third time interval, and perform operation 911 based on identifying that the second image is to be changed to the third image for the third time interval.

[0102] In operation 909, under the condition that the second image displayed on the display panel 340 is to be maintained in the third time interval, the display driver circuit 320 may store the second image obtained from the processor 310 in the second time interval in the memory 325. For example, the display driver circuit 320 may store the second image in the memory 325 based on obtaining a predetermined signal indicating that the second image is to be maintained in the third time interval from the processor 310 in a first time interval before the second time interval.

[0103] In operation 911, under the condition that the second image displayed on the display panel 340 is to be changed to the third image in the third time interval, the display driver circuit 320 may bypass storing the second image obtained from the processor 310 in the second time interval in the memory 325. For example, the display driver circuit 320 may bypass storing the second image in the memory 325 based on recognizing that a predetermined signal is not obtained in the first time interval or a predetermined signal indicating that the second image is changed to the third image in the third time interval is obtained in the first time interval.

[0104] Fig. 9 An example in which operation 907 is performed after operation 901 is performed is illustrated, but this is only for the convenience of description. For example, operations 901 and 907 may be performed in parallel. For example, operation 907 may be performed before operation 901 is performed. For example, the display driver circuit 320 may perform at least one second display among the plurality of displays and store the second image to display the second image in the third interval when the length is longer than the reference length and the second image is to be maintained within the third time interval, store the second image to perform at least one second display when the length is longer than the reference length and the second image is to be changed to the third image within the third time interval, store the second image to display the second image in the third time interval when the length is shorter than or equal to the reference length and the second image is to be maintained within the third time interval, and bypass storing the second image when the length is shorter than or equal to the reference length and the second image is to be changed to the third image within the third time interval.

[0105] As described above, the electronic device 300 may store an image in the memory 325 to reduce an afterimage caused on the display panel 340 .

[0106] Fig.11 An exemplary method of performing a single display of a second image or a plurality of displays of a second image according to a time length is shown. The method may be performed by Figure 3 The display driver circuit 320 performs.

[0107] The following example Fig.11 Operations 1101 to 1113 illustrate the Figure 4The description exemplifies operations performed within the display driver circuit 320 when a second image changed from a first image is displayed on the display panel 340 within the second time interval, but this is only for convenience of description. Fig.11 Operations 1101 to 1113 can also be applied to Figure 4 The description of the illustrated embodiment shows that a first image is displayed on the display panel 340 during a first time interval.

[0108] refer to Fig.11 In operation 1101, the display driver circuit 320 may identify the time length between the end timing of the last display of the first image in the first time interval and the start timing of the display of the second image in the second time interval. For example, because the probability of an afterimage caused by a hysteresis in a driving transistor for driving an organic light emitting diode in the display panel 340 may increase as the time length from the end timing of displaying an image to the start timing of displaying the next (subsequent) image increases, the display driver circuit 320 may identify the time length. The time length will be in Fig.10 Shown in.

[0109] In operation 1103, the display driver circuit 320 may identify whether the time length is longer than a reference length. For example, the reference length may be Fig. 9 For example, the display driver circuit 320 may perform operation 1105 based on the time length being longer than the reference length, and perform operation 1107 based on the time length being shorter than or equal to the reference length.

[0110] In operation 1105, under the condition that the time length is longer than the reference length, the display driver circuit 320 may perform a plurality of displays of the second image on the display panel 340 within the second time interval. For example, in response to the time length being longer than the reference length, the display driver circuit 320 may display the second image obtained from the processor 310 within a portion of the second time interval on the display panel 340, and store the second image obtained from the processor 310 within the portion of the second time interval in the memory 325. For example, the storing of the second image in the memory 325 may be performed regardless of whether a predetermined signal indicating that the second image is to be maintained on the display panel 340 within a third time interval immediately following (after) the second time interval is obtained from the processor 310. For example, the display driver circuit 320 may display the second image on the display panel 340 by scanning the second image stored in the memory 325 within another portion of the second time interval after the portion of the second time interval. For example, a first display of the plurality of displays may be performed based on obtaining a second image from the processor 310 within the portion of the second time interval, and at least one second display of the plurality of displays (e.g., at least one display immediately following (or after) the first display) may be performed based on scanning a second image stored in the memory 325 within the portion of the second time interval. The plurality of displays may be performed based on Fig.10 Shown in.

[0111] refer to Fig.10 , the display driver circuit 320 may obtain the second image provided through the interface 315 from the processor 310 based on the timing 1021, which is the start timing of the second time interval 1020 corresponding to the refresh rate of the second image. For example, the state of the interface 315, such as the state 1000, may be indicated according to the second image sent from the processor 310 to the display driver circuit 320 within the portion 1023 of the second time interval 1020. As a non-limiting example, the portion 1023 of the second time interval 1020 may correspond to the maximum speed of the transmission of the second image from the processor 310 to the display driver circuit 320 performed using the interface 315. For example, the maximum speed may indicate the maximum speed available through the interface 315. For example, as shown by the arrow 1090, the display driver circuit 320 may display the second image obtained from the processor 310 on the display panel 340 within the portion 1023 of the second time interval 1020. For example, the display of the second image within the portion 1023 of the second time interval 1020 may be the first display of the plurality of displays.

[0112] For example, the display driver circuit 320 may identify the time length 1030 from the timing 1031 as the end timing of the display of the first image to the timing 1021, so as to reduce the afterimage caused on the display panel 340. For example, as shown by arrow 1094, the display driver circuit 320 may store the second image obtained from the processor 310 in the portion 1023 of the second time interval 1020 in the memory 325 based on the time length 1030 being longer than the reference length. For example, the display driver circuit 320 may be independent of whether a predetermined signal (e.g., Figure 5 The display driver circuit 320 may store the second image in the memory 325 based on the predetermined signal 550 of the display driver circuit 320. For example, even when the predetermined signal is not obtained from the processor 310 within the first time interval 1032, the display driver circuit 320 may store the second image in the memory 325 based on the time length 1030 being longer than the reference length.

[0113] For example, as indicated by arrow 1092, the display driver circuit 320 may scan the second image stored in the memory 325 based on the timing 1022, which is the end timing of the portion 1023 of the second time interval 1020 or the start timing of another portion 1024 of the second time interval 1020. For example, the other portion 1024 of the second time interval 1020 may correspond to the maximum speed. However, it is not limited thereto. For example, the other portion 1024 of the second time interval 1020 may be different from the maximum speed. For example, as indicated by arrow 1093, the display driver circuit 320 may display the second image on the display panel 340 within the other portion 1024 of the second time interval 1020 by scanning the second image. For example, the display of the second image within the other portion 1024 of the second time interval 1020 may be at least one second display among the plurality of displays. For example, the display of the second image within the other portion 1024 of the second time interval 1020 may be performed to reduce the probability of causing an afterimage on the display panel 340.

[0114] Return to reference Fig.11 , under the condition that the time length is shorter than or equal to the reference length, the display driver circuit 320 may perform a single display of the second image on the display panel 340 within the second time interval in operation 1107. For example, since the fact that the time length is shorter than or equal to the reference length indicates that the probability of causing an afterimage on the display panel 340 is relatively low, the display driver circuit 320 may perform a single display.

[0115] In operation 1109, the display driver circuit 320 may identify whether the second image is to be maintained in a third time interval immediately following (after) the second time interval. For example, operation 1109 may correspond to Figure 4 Operation 405.

[0116] For example, the display driver circuit 320 may perform operation 1111 based on the second image being maintained for the third time interval, and may perform operation 1113 based on the second image being changed to the third image for the third time interval.

[0117] In operation 1111, under the condition that the second image displayed on the display panel 340 is to be maintained in the third time interval, the display driver circuit 320 may store the second image obtained from the processor 310 in the second time interval in the memory 325. For example, based on obtaining a predetermined signal indicating that the second image is to be maintained in the third time interval, the display driver circuit 320 may store the second image from the processor 310 in the memory 325 in the first time interval before the second time interval.

[0118] In operation 1113, in the case where the second image displayed on the display panel 340 is changed to the third image in the third time interval, the display driver circuit 320 may bypass storing the second image obtained from the processor 310 in the second time interval in the memory 325. For example, the display driver circuit 320 may bypass storing the second image in the memory 325 based on recognizing that a predetermined signal is not obtained in the first time interval or obtaining a predetermined signal indicating that the second image is changed to the third image in the third time interval.

[0119] Fig.11 An example of performing operation 1109 after performing operation 1103 is illustrated, but this is only for the convenience of description. For example, operations 1103 and 1109 may be performed in parallel. For example, operation 1109 may be performed before performing operation 1103. For example, the display driver circuit 320 may perform at least one second display among the multiple displays and store the second image to display the second image in the third time interval when the time length is longer than the reference length and the second image is to be maintained in the third time interval, store the second image to perform at least one second display when the time length is longer than the reference length and the second image is to be changed to the third image in the third time interval, store the second image to display the second image in the third time interval when the time length is shorter than or equal to the reference length and the second image is to be maintained in the third time interval, and bypass storing the second image when the time length is shorter than or equal to the reference length and the second image is to be changed to the third image in the third time interval.

[0120] As described above, the electronic device 300 may store an image in the memory 325 to reduce an afterimage caused on the display panel 340 .

[0121] Fig.12An exemplary method of performing a single display of the second image or a plurality of displays of the second image according to the length of the first time interval is shown. The method may be performed by Figure 3 The display driver circuit 320 performs.

[0122] The following example Fig.12 Operations 1201 to 1211 of the present invention illustrate that when a display panel 340 is displayed by Figure 4 The description of exemplifies operations performed in the display driver circuit 320 when the second image changed from the first image is displayed in the second time interval, but this is only for convenience of description. Fig.12 Operations 1201 to 1211 may also be applied in Figure 4 The description of the illustrated embodiment shows that a first image is displayed on the display panel 340 during a first time interval.

[0123] refer to Fig.12 In operation 1201, the display driver circuit 320 may identify whether the length of the first time interval before the second time interval is longer than the reference length. For example, because the probability of an afterimage caused by a hysteresis in a driving transistor for driving an organic light emitting diode (or sub-pixel) in the display panel 340 may increase as the length of time from the end timing of displaying an image to the start timing of displaying the next (subsequent) image increases, the display driver circuit 320 may identify whether the length is longer than the reference length. For example, the display driver circuit 320 may perform operation 1203 based on the length being longer than the reference length, and may perform operation 1205 based on the length being shorter than or equal to the reference length.

[0124] In operation 1203, under the condition that the length is longer than the reference length, the display driver circuit 320 may perform a plurality of displays of the second image on the display panel 340 within the second time interval. For example, in response to the length being longer than the reference length, the display driver circuit 320 may display the second image obtained from the processor 310 within a portion of the second time interval on the display panel 340, and store the second image obtained from the processor 310 within the portion of the second time interval in the memory 325. For example, storing the second image in the memory 325 may be performed independently of whether a predetermined signal indicating that the second image is maintained on the display panel 340 within a third time interval immediately following (after) the second time interval is obtained from the processor 310. For example, the display driver circuit 320 may display the second image on the display panel 340 by scanning the second image stored in the memory 325 within another portion of the second time interval after the portion of the second time interval. For example, a first display of the plurality of displays may be performed based on obtaining a second image from the processor 310 within the portion of the second time interval, and at least one second display of the plurality of displays (e.g., at least one display immediately following (or after) the first display) may be performed based on scanning a second image stored in the memory 325 within the portion of the second time interval. The plurality of displays may be performed based on Fig.10 Shown in.

[0125] refer to Fig.10 , the display driver circuit 320 may obtain the second image provided through the interface 315 from the processor 310 based on the timing 1021, which is the start timing of the second time interval 1020 corresponding to the refresh rate of the second image. For example, the state of the interface 315, such as the state 1000, may be indicated according to the second image sent from the processor 310 to the display driver circuit 320 within the portion 1023 of the second time interval 1020. As a non-limiting example, the portion 1023 of the second time interval 1020 may correspond to the maximum speed of the transmission of the second image from the processor 310 to the display driver circuit 320 performed using the interface 315. For example, the maximum speed may indicate the maximum speed available through the interface 315. For example, as shown by the arrow 1090, the display driver circuit 320 may display the second image obtained from the processor 310 on the display panel 340 within the portion 1023 of the second time interval 1020. For example, the display of the second image within the portion 1023 of the second time interval 1020 may be the first display of the plurality of displays.

[0126] For example, the display driver circuit 320 may identify the length of the first time interval 1032 before the second time interval 1020 to reduce the afterimage caused on the display panel 340. For example, as indicated by arrow 1095, based on the length of the first time interval 1032 being longer than the reference length, the display driver circuit 320 may store the second image obtained from the processor 310 in the memory 325 within the portion 1023 of the second time interval 1020. For example, storing the second image in the memory 325 may be independent of whether a predetermined signal (e.g., Figure 5 For example, even when the predetermined signal is not obtained from the processor 310 within the first time interval 1032, the display driver circuit 320 may store the second image in the memory 325 based on the length of the first time interval 1032 being longer than the reference length.

[0127] For example, as indicated by arrow 1092, the display driver circuit 320 may scan the second image stored in the memory 325 based on the timing 1022, which is the end timing of the portion 1023 of the second time interval 1020 or the start timing of the other portion 1024 of the second time interval 1020. For example, the other portion 1024 of the second time interval 1020 may correspond to the maximum speed. However, it is not limited thereto. For example, the other portion 1024 of the second time interval 1020 may be different from the maximum speed. For example, as indicated by arrow 1093, the display driver circuit 320 may display the second image on the display panel 340 within the other portion 1024 of the second time interval 1020 by scanning the second image. For example, the display of the second image within the other portion 1024 of the second time interval 1020 may be at least one second display among the plurality of displays. For example, the display of the second image within the other portion 1024 of the second time interval 1020 may be performed to reduce the probability of causing an afterimage on the display panel 340.

[0128] Return to reference Fig.12 In operation 1205, under the condition that the time length is shorter than or equal to the reference length, the display driver circuit 320 may perform a single display of the second image on the display panel 340 within the second time interval. For example, since the fact that the time length is shorter than or equal to the reference length indicates that the probability of causing an afterimage on the display panel 340 is relatively low, the display driver circuit 320 may perform a single display.

[0129] In operation 1207, the display driver circuit 320 may identify whether the second image is to be maintained in a third time interval immediately following (after) the second time interval. For example, operation 1207 may correspond to Figure 4 Operation 405.

[0130] For example, the display driver circuit 320 may perform operation 1209 based on the second image being maintained for the third time interval, and may perform operation 1211 based on the second image being changed to the third image for the third time interval.

[0131] In operation 1209, under the condition that the second image displayed on the display panel 340 is to be maintained in the third time interval, the display driver circuit 320 may store the second image obtained from the processor 310 in the second time interval in the memory 325. For example, based on obtaining a predetermined signal indicating that the second image is to be maintained in the third time interval, the display driver circuit 320 may store the second image from the processor 310 in the memory 325 in the first time interval before the second time interval.

[0132] In operation 1211, in the case where the second image displayed on the display panel 340 is to be changed to the third image within the third time interval, the display driver circuit 320 may bypass storing the second image obtained from the processor 310 within the second time interval in the memory 325. For example, based on recognizing that a predetermined signal is not obtained within the first time interval or a predetermined signal indicating that the second image is to be changed to the third image within the third time interval is obtained, the display driver circuit 320 may bypass storing the second image in the memory 325.

[0133] Fig.12 An example in which operation 1207 is performed after operation 1201 is performed is illustrated, but this is only for the convenience of description. For example, operations 1201 and 1207 may be performed in parallel. For example, operation 1207 may be performed before operation 1201 is performed. For example, the display driver circuit 320 may perform at least one second display among the plurality of displays and store the second image to display the second image in the third time interval when the time length is longer than the reference length and the second image is to be maintained in the third time interval, store the second image to perform at least one second display when the time length is longer than the reference length and the second image is to be changed to the third image in the third time interval, store the second image to display the second image in the third time interval when the time length is shorter than or equal to the reference length and the second image is to be maintained in the third time interval, and bypass storing the second image when the time length is shorter than or equal to the reference length and the second image is to be changed to the third image in the third time interval.

[0134] As described above, the electronic device 300 may store an image in the memory 325 to reduce an afterimage caused on the display panel 340 .

[0135] Fig.13An exemplary method of storing a second image in a second time interval independently of a predetermined signal indicating that the second image displayed in the second time interval is changed to a third image in a third time interval is shown.

[0136] refer to Fig.13 In operation 1301, the display driver circuit 320 may display the first image by scanning the first image in the first time interval. For example, the display driver circuit 320 may display the first image in the first time interval by scanning the first image stored in the memory 325 in the fourth time interval before the first time interval. As a non-limiting example, storing the first image in the fourth time interval may be performed based on obtaining a predetermined signal indicating that the first image is to be maintained in the first time interval from the processor 310 in the fifth time interval before the fourth time interval.

[0137] In operation 1303, during the first time interval, the display driver circuit 320 may obtain a predetermined signal from the processor 310, the predetermined signal indicating that the second image to be provided from the processor 310 during the second time interval immediately following (after) the first time interval is to be changed to a third image during the third time interval immediately following (after) the second time interval. For example, the predetermined signal may indicate that the second image obtained from the processor 310 during the second time interval is stored in the memory 325.

[0138] In operation 1305, the display driver circuit 320 may store the second image obtained from the processor 310 in the second time interval in the memory 325 independently of the predetermined signal obtained in operation 1303. As a non-limiting example, the display driver circuit 320 may store the second image in the memory 325 regardless of the predetermined signal in order to prevent or reduce the display of the image from being interrupted in the third time interval due to failure to obtain the third image from the processor 310 in the third time interval. Fig.14 It is shown that the second image is stored in the memory 325 independently of the predetermined signal.

[0139] Fig.14 The illustration shows an example in which the second image is stored in the second time interval independently of a predetermined signal indicating that the second image displayed in the second time interval is changed to a third image in the third time interval.

[0140] Reference Fig.14, the display driver circuit 320 may obtain a predetermined signal 1450 from the processor 310 within the first time interval 1410. For example, the predetermined signal 1450 may indicate that the second image is changed to the third image within the third time interval 1430 immediately following (after) the second time interval 1420. For example, the predetermined signal 1450 may indicate that the second image provided from the processor 310 is bypassed or avoided from being stored in the memory 325 within the second time interval 1420. For example, the predetermined signal 1450 may be obtained through a front porch portion of a vertical synchronization signal for displaying the second image. However, it is not limited thereto.

[0141] For example, the display driver circuit 320 may obtain the second image provided from the processor 310 based on the timing 1421, which is the start timing of the second time interval 1420. For example, as indicated by the arrow 1490, the display driver circuit 320 may display the second image provided by the processor 310 on the display panel 340. For example, as indicated by the arrow 1491, the display driver circuit 320 may store the second image provided by the processor 310 in the memory 325. For example, the storing of the second image in the memory 325 may be performed independently of the predetermined signal 1450. As a non-limiting example, under the condition that a first image before the second image is displayed based on scanning a first image stored in the memory 325 for at least one time interval before the second time interval 1420, the display driver circuit 320 may store the second image in the memory 325 differently from the information indicated by the predetermined signal 1450. For example, since a change from the first image to the second image may cause an afterimage on the display panel 340, the display driver circuit 320 may store the second image in the memory 325 independently of obtaining the predetermined signal 1450. Although in Fig.14 Although not shown in the figure, the display driver circuit 320 may display the second image on the display panel 340 by scanning the second image stored in the memory 325. The display of the second image according to the scanning of the second image may be performed within the second time interval 1420 or the third time interval 1430. For example, since the second image may be maintained within the third time interval 1430 unlike the information indicated by the predetermined signal 1450, the display driver circuit 320 may store the second image in the memory 325.

[0142] As described above, the electronic device 300 can reduce power consumed for displaying an image by adaptively storing the image in the memory 325 within the display driver circuit 320 in the second mode.

[0143] The operation of the display driver circuit 320 that adaptively stores the image from the processor 310 in the memory 325 shown by the above description may be performed based on a predetermined signal (e.g., the predetermined signal 550, the predetermined signal 650, and / or the predetermined signal 1450) provided from the processor 310. For example, as in the following example, the predetermined signal may be provided to the display driver circuit 320 based on the recognition (or determination) of the processor 310. In the following description, the predetermined signals may be referred to as a first signal, a second signal, a third signal, and a fourth signal.

[0144] Fig.15 is a flow chart illustrating an exemplary method of providing a first signal or a second signal according to a refresh rate.

[0145] refer to Fig.15 In operation 1501, the processor 310 may identify a refresh rate. For example, the refresh rate may indicate a refresh rate identified or targeted when the processor 310 obtains or renders an image to be provided to the display driver circuit 320. For example, the refresh rate may correspond to the refresh rate of the first image and the refresh rate of the second image shown in the above description.

[0146] In operation 1503, the processor 310 may identify whether the refresh rate is lower than a reference refresh rate. For example, the reference refresh rate may be a parameter provided to identify whether a single display of an image or multiple displays of an image is performed within a time interval (e.g., a time interval corresponding to the refresh rate). For example, the fact that the refresh rate is lower than the reference refresh rate may indicate that the probability of an afterimage occurring when a single display of an image is performed within the time interval is relatively high. For example, the fact that the refresh rate is higher than or equal to the reference refresh rate may indicate that the probability of an afterimage occurring when a single display of an image is performed within the time interval is relatively low. For example, the reference refresh rate may be a current refresh rate (e.g., the refresh rate), a threshold refresh rate, or a predetermined refresh rate. For example, the fact that the refresh rate is lower than the reference refresh rate may include lowering the refresh rate. For example, the fact that the refresh rate is higher than the reference refresh rate may include increasing the refresh rate.

[0147] For example, the processor 310 may perform operation 1505 under the condition that the refresh rate is lower than the reference refresh rate, and may perform operation 1507 under the condition that the refresh rate is higher than the reference refresh rate.

[0148] In operation 1505, in response to the refresh rate being lower than the reference refresh rate, the processor 310 may provide a first signal (e.g., a sticky flag indication (enabled)) to the display driver circuit 320, the first signal indicating that one or more images provided from the processor 310 according to the refresh rate for display on the display panel 340 are to be stored in the memory 325. As a non-limiting example, the first signal may be provided from the processor 310 to the display driver circuit 320 through a front porch portion of a vertical synchronization signal or in a front porch portion of a vertical synchronization signal. As a non-limiting example, the first signal may correspond at least in part to Figure 5 A predetermined signal 550 is provided.

[0149] For example, the first signal may indicate that one or more images are kept stored in the memory 325 according to the first signal until the second signal shown in operation 1507 is provided from the processor 310 to the display driver circuit 320. For example, the first signal may indicate that the state of the switch 330 is maintained in the first state 331 until the second signal is provided from the processor 310 to the display driver circuit 320.

[0150] Available in Fig.16 Storing one or more images according to the first signal is shown.

[0151] Fig.16 An exemplary method of storing one or more images based on a first signal provided based on a refresh rate lower than a reference refresh rate is shown.

[0152] refer to Fig.16 As shown in state 1601, the processor 310 may provide a first image to the display driver circuit 320 through the interface 315 within a first time interval 1611. For example, in response to the refresh rate being lower than the reference refresh rate, the processor 310 may provide a first signal 1621 to the display driver circuit 320 at a timing 1620 within the front porch portion of the vertical synchronization signal corresponding to the first time interval 1611. For example, the first signal 1621 may indicate that one or more images provided from the processor 310 to the display driver circuit 320 are stored in the memory 325 until the second signal is provided to the display driver circuit 320. For example, the first signal 1621 may indicate that the switch 330 is maintained in the first state 331 until the second signal is provided to the display driver circuit 320.

[0153] For example, as indicated by arrow 1631, the display driver circuit 320 may display the first image provided from the processor 310 in the first time interval 1611 on the display panel 340. For example, as indicated by arrow 1632, the display driver circuit 320 may store (or record) the first image provided from the processor 310 in the first time interval 1611 in the memory 325 based on the first signal 1621 obtained at the timing 1620. For example, as indicated by arrow 1633, the display driver circuit 320 may display the first image again on the display panel 340 in the first time interval 1611 by scanning the first image stored in the memory 325. As a non-limiting example, displaying the first image by scanning the first image stored in the memory 325 may be performed to reduce the occurrence of an afterimage on the display panel 340.

[0154] For example, as indicated by state 1602 , processor 310 may provide a second image to display driver circuit 320 via interface 315 in a second time interval 1612 immediately following (or following) first time interval 1611 .

[0155] For example, as indicated by arrow 1634, the display driver circuit 320 may display the second image provided from the processor 310 in the second time interval 1612 on the display panel 340. For example, as indicated by arrow 1635, the display driver circuit 320 may store (or record) the second image provided from the processor 310 in the second time interval 1612 in the memory 325 based on the first signal 1621 obtained at the timing 1620. For example, as indicated by arrow 1636, the display driver circuit 320 may display the second image again on the display panel 340 in the second time interval 1612 by scanning the second image stored in the memory 325. As a non-limiting example, displaying the second image by scanning the second image stored in the memory 325 may be performed to reduce the occurrence of an afterimage on the display panel 340.

[0156] For example, as shown in state 1603 , the processor 310 may again provide the second image to the display driver circuit 320 through the interface 315 in a third time interval 1613 immediately following (after) the second time interval 1612 .

[0157] For example, as indicated by arrow 1637, the display driver circuit 320 may display the second image provided from the processor 310 in the third time interval 1613 on the display panel 340. For example, as indicated by arrow 1638, the display driver circuit 320 may store (or record) the second image provided from the processor 310 in the third time interval 1613 in the memory 325 based on the first signal 1621 obtained at the timing 1620. For example, the second image provided by the processor 310 in the third time interval 1613 is the same as the second image stored in the memory 325 in the second time interval 1612, but the display driver circuit 320 may store the second image in the memory 325 again based on the first signal 1621. For example, since the fact that the image provided by the processor 310 in the third time interval 1613 is the same as the image stored in the memory 325 can be recognized after completing the acquisition of the image in the third time interval 1613, the display driver circuit 320 may store the second image in the memory 325 again. For example, as indicated by arrow 1639, the display driver circuit 320 may display the second image again on the display panel 340 within the third time interval 1613 by scanning the second image stored in the memory 325. As a non-limiting example, displaying the second image by scanning the second image stored in the memory 325 may be performed to reduce the occurrence of an afterimage on the display panel 340.

[0158] For example, as indicated by state 1604 , processor 310 may provide a third image to display driver circuit 320 via interface 315 in a fourth time interval 1614 that immediately follows (or is subsequent to) third time interval 1613 .

[0159] For example, as indicated by arrow 1640, the display driver circuit 320 may display the third image provided from the processor 310 in the fourth time interval 1614 on the display panel 340. For example, as indicated by arrow 1641, the display driver circuit 320 may store (or record) the third image provided from the processor 310 in the fourth time interval 1614 in the memory 325 based on the first signal 1621 obtained at the timing 1620. For example, as indicated by arrow 1642, the display driver circuit 320 may display the third image again on the display panel 340 in the fourth time interval 1614 by scanning the third image stored in the memory 325. As a non-limiting example, displaying the third image by scanning the third image stored in the memory 325 may be performed to reduce the occurrence of an afterimage on the display panel 340.

[0160] although Fig.16It is shown that the first image is displayed again by scanning the first image stored in the memory 325 within the first time interval 1611, but the display of the first image again by scanning the first image stored in the memory 325 within the first time interval 1611, which is a time interval immediately after the first signal 1621 is obtained, may be bypassed according to the time length of the image before the first image is maintained on the display panel 340. For example, unlike the display of the second image again by scanning the second image within the second time interval 1612, the display of the second image again by scanning the second image within the third time interval 1613, and the display of the third image again by scanning the third image within the fourth time interval 1614, the display of the first image again by scanning the first image within the first time interval 1611 may be bypassed under the condition that the time length is shorter than or equal to the reference length. For example, the display of the first image again by scanning the first image within the first time interval 1611 may be performed, such as the display of the second image again by scanning the second image within the second time interval 1612, the display of the second image again by scanning the second image within the third time interval 1613, and the display of the third image again by scanning the third image within the fourth time interval 1614. However, it is not limited to this.

[0161] As described above, in response to the first signal 1621, the display driver circuit 320 may store each image (e.g., the first image, the second image, and the third image) obtained from the processor 310 in the memory 325 within each of the first to fourth time intervals 1611 to 1614, which are time intervals after obtaining the first signal 1621.

[0162] As described above, the processor 310 may provide the display driver circuit 320 with a first signal 1621 to perform multiple displays of a single image on the display panel 340 during a time interval corresponding to a refresh rate lower than the reference refresh rate. For example, the multiple displays may include a first display and a second display immediately following (after) the first display. For example, the display driver circuit 320 may perform the first display by displaying a single image obtained from the processor 310 on the display panel 340 during a portion of the time interval and storing the single image in the memory 325. For example, the display driver circuit 320 may perform the second display by displaying a single image on the display panel 340 based on scanning a single image stored in the memory 325 during another portion of the time interval. For example, the display driver circuit 320 may bypass performing the second display in an initial time interval (e.g., the first time interval 1611) among a plurality of time intervals (e.g., the first time interval 1611 to the fourth time interval 1614) after obtaining the first signal 1621. However, it is not limited thereto. As a non-limiting example, instead of storing the image in the memory 325 according to the first signal 1621 , whether to perform a second display (or whether to perform multiple displays) may be identified or determined by the processor 310 and the display driver circuit 320 .

[0163] Return to reference Fig.15 In operation 1507, in response to the refresh rate being higher than or equal to the reference refresh rate, the processor 310 may provide the display driver circuit 320 with a second signal (e.g., a sticky flag indication (disabled)) indicating bypassing storage of one or more images in the memory 325. As a non-limiting example, the second signal may be provided from the processor 310 to the display driver circuit 320 via a front porch portion of the vertical synchronization signal or in a front porch portion of the vertical synchronization signal. As a non-limiting example, the second signal may correspond at least in part to Figure 6 As a non-limiting example, the location where the second signal is stored in the display driver circuit 320 may be different from the location where the first signal is stored in the display driver circuit 320. For example, the address of the second signal may be different from the address of the first signal.

[0164] For example, the second signal may indicate that the storage of one or more images in the memory 325 is bypassed according to the second signal until the first signal is provided from the processor 310 to the display driver circuit 320. For example, the second signal may indicate that the state of the switch 330 is maintained in the second state 332 until the first signal is provided from the processor 310 to the display driver circuit 320.

[0165] Can be used Fig.17 Storing one or more images according to the second signal is shown.

[0166] Fig.17 An exemplary method of bypassing storage of one or more images based on a second signal provided based on a refresh rate that is greater than or equal to a reference refresh rate is shown.

[0167] refer to Fig.17 As shown in state 1701, processor 310 may provide a first image to display driver circuit 320 via interface 315 within a first time interval 1711. For example, by Fig.17 Each of the first to fifth time intervals 1711 to 1715 shown can be compared to the Fig.16 Each of the illustrated first to fourth time intervals 1611 to 1614 is short. However, it is not limited thereto.

[0168] For example, in response to the refresh rate being higher than or equal to the reference refresh rate, the processor 310 may provide the display driver circuit 320 with a second signal 1721 at a timing 1720 within the front porch portion of the vertical synchronization signal corresponding to the first time interval 1711. For example, the second signal 1721 may indicate that storage of one or more images provided from the processor 310 to the display driver circuit 320 in the memory 325 is bypassed until the first signal (e.g., Fig.16 The first signal 1621 of the embodiment of the present invention is provided to the display driver circuit 320. For example, the second signal 1721 may instruct the switch 330 to maintain the second state 332 until the first signal (eg, the first signal 1621) is provided to the display driver circuit 320.

[0169] For example, as indicated by arrow 1731, the display driver circuit 320 may display the first image provided from the processor 310 in the first time interval 1711 on the display panel 340. For example, as indicated by arrow 1732, the display driver circuit 320 may bypass storing (or recording) the first image provided from the processor 310 in the first time interval 1711 in the memory 325 based on the second signal 1721 obtained from the timing 1720. For example, since each of the first to fifth time intervals 1711 to 1715 is shorter than each of the first to fourth time intervals 1611 to 1614, the probability that an afterimage occurs on the display panel 340 may be relatively low. For example, since the probability is relatively low, the display driver circuit 320 may perform a single display in the first time interval 1711.

[0170] For example, as indicated by state 1702 , processor 310 may provide a second image to display driver circuit 320 via interface 315 in a second time interval 1712 immediately following (or following) first time interval 1711 .

[0171] For example, as indicated by arrow 1733, the display driver circuit 320 may display the second image provided from the processor 310 in the second time interval 1712 on the display panel 340. For example, as indicated by arrow 1734, the display driver circuit 320 may bypass storing (or recording) the second image provided from the processor 310 in the second time interval 1712 in the memory 325 based on the second signal 1721 obtained at the timing 1720. For example, since each of the first to fifth time intervals 1711 to 1715 is shorter than each of the first to fourth time intervals 1611 to 1614, the probability that an afterimage occurs on the display panel 340 may be relatively low. For example, since the probability is relatively low, the display driver circuit 320 may perform a single display in the second time interval 1712.

[0172] For example, as shown in the state 1703, the processor 310 may again provide the second image to the display driver circuit 320 through the interface 315 in the third time interval 1713 immediately following (after) the second time interval 1712. For example, in response to recognizing that there is no image to be changed from the second image in the third time interval 1713 immediately following (after) the second time interval 1712, the processor 310 may again provide the second image to the display driver circuit 320 in the third time interval 1713.

[0173] For example, as indicated by arrow 1735, the display driver circuit 320 may display the second image provided again from the processor 310 in the third time interval 1713 on the display panel 340. For example, as indicated by arrow 1736, the display driver circuit 320 may bypass storing (or recording) the second image provided from the processor 310 in the third time interval 1713 in the memory 325 based on the second signal 1721 obtained at the timing 1720. For example, since each of the first to fifth time intervals 1711 to 1715 is shorter than each of the first to fourth time intervals 1611 to 1614, the probability that an afterimage occurs on the display panel 340 may be relatively low. For example, since the probability is relatively low, the display driver circuit 320 may perform a single display in the third time interval 1713.

[0174] For example, as indicated by the state 1704, the processor 310 may again provide the second image to the display driver circuit 320 via the interface 315 in a fourth time interval 1714 immediately following (after) the third time interval 1713. For example, in response to recognizing that there is no image to be changed from the second image in the fourth time interval 1713 immediately following (after) the third time interval 1713, the processor 310 may again provide the second image to the display driver circuit 320 in the fourth time interval 1714.

[0175] For example, as indicated by arrow 1737, the display driver circuit 320 may display the second image provided again from the processor 310 in the fourth time interval 1714 on the display panel 340. For example, as indicated by arrow 1738, the display driver circuit 320 may bypass storing (or recording) the second image provided from the processor 310 in the fourth time interval 1714 in the memory 325 based on the second signal 1721 obtained at the timing 1720. For example, since each of the first to fifth time intervals 1711 to 1715 is shorter than each of the first to fourth time intervals 1611 to 1614, the probability that an afterimage occurs on the display panel 340 may be relatively low. For example, since the probability is relatively low, the display driver circuit 320 may perform a single display in the fourth time interval 1714.

[0176] For example, as indicated by state 1705 , processor 310 may provide a third image to display driver circuit 320 via interface 315 in a fifth time interval 1715 that immediately follows (or is subsequent to) fourth time interval 1714 .

[0177] For example, as indicated by arrow 1739, the display driver circuit 320 may display the third image provided again from the processor 310 in the fifth time interval 1715 on the display panel 340. For example, as indicated by arrow 1740, the display driver circuit 320 may bypass storing (or recording) the third image provided from the processor 310 in the fifth time interval 1715 in the memory 325 based on the second signal 1721 obtained at the timing 1720. For example, since each of the first to fifth time intervals 1711 to 1715 is shorter than each of the first to fourth time intervals 1611 to 1614, the probability that an afterimage occurs on the display panel 340 may be relatively low. For example, since the probability is relatively low, the display driver circuit 320 may perform a single display in the fifth time interval 1715.

[0178] As described above, in response to the second signal 1721, the display driver circuit 320 may bypass storing each of the images (e.g., the first image, the second image, and the third image) obtained from the processor 310 in the memory 325 within each of the first to fifth time intervals 1711 to 1715 which are time intervals after obtaining the second signal 1721.

[0179] As described above, the processor 310 may provide the second signal 1721 to the display driver circuit 320 to perform a single display of a single image on the display panel 340 during one time interval corresponding to a refresh rate higher than or equal to the reference refresh rate.

[0180] Fig.18 is a flow chart illustrating an exemplary method of storing an image in a memory within an initial time interval when a second signal is provided after a first signal is provided.

[0181] Fig.18 Operations 1801 to 1805 may be performed, for example, Fig.15 The operation 1505 is performed afterwards.

[0182] Reference Fig.18 In operation 1801, the display driver circuit 320 may display a first image on the display panel 340 based on scanning a first image stored in the memory 325 according to a first signal.

[0183] In operation 1803 , the display driver circuit 320 may obtain a second signal from the processor 310 after or while displaying the first image on the display panel 340 .

[0184] In operation 1805, the display driver circuit 320 may store the second image immediately following (after) the first image obtained from the processor 310 in the memory 325 independently of the second signal within an initial time interval among a plurality of time intervals after obtaining the second signal. Fig.19 Storing the second image in the memory 325 independently of the second signal during the initial time interval is shown in FIG.

[0185] Fig.19 An exemplary method of storing an image in a memory during an initial time interval when a second signal is provided after a first signal is provided is shown.

[0186] refer to Fig.19, the processor 310 may provide the first signal 1621 to the display driver circuit 320 at timing 1920. For example, the display driver circuit 320 may display the first image on the display panel 340 as indicated by arrow 1932 based on scanning the first image stored in the memory 325 according to the first signal 1621 as indicated by arrow 1931.

[0187] For example, when the first image remains on the display panel 340, the processor 310 may provide the second signal 1721 to the processor 310 at timing 1940. For example, as shown in state 1901, the processor 310 may provide the second image to the display driver circuit 320 through the interface 315 within the first time interval 1911.

[0188] For example, the display driver circuit 320 may store the second image in the memory 325 within the first time interval 1911, although the second signal 1721 is obtained at the timing 1940, as indicated by the arrow 1933. For example, in order to reduce the occurrence of an afterimage on the display panel 340 according to the change from the first image to the second image, the display driver circuit 320 may store the second image in the memory 325 independently of (or regardless of) obtaining the second signal 1721 from the timing 1940. For example, based on the second signal 1721 obtained after the first signal 1621, the display driver circuit 320 may avoid applying the setting according to the second signal 1721 (e.g., bypassing the operation of storing the image in the memory 325) to the first time interval 1911 immediately after the timing when the second signal 1721 is obtained. However, it is not limited thereto.

[0189] For example, as indicated by arrow 1934, the display driver circuit 320 may display the second image obtained from the processor 310 in the first time interval 1911 on the display panel 340. For example, as indicated by arrow 1935, the display driver circuit 320 may display the second image on the display panel 340 by scanning the second image stored in the memory 325 in the first time interval 1911. For example, displaying the second image on the display panel 340 by scanning the second image may be performed in order to reduce an afterimage that may be caused by a change from the first image to the second image.

[0190] For example, as indicated by state 1902 , processor 310 may provide a third image to display driver circuit 320 via interface 315 in a second time interval 1912 immediately following (or following) first time interval 1911 .

[0191] For example, as indicated by arrow 1936, the display driver circuit 320 may display the third image provided from the processor 310 in the second time interval 1912 on the display panel 340. For example, as indicated by arrow 1937, the display driver circuit 320 may bypass storing the third image provided from the processor 310 in the second time interval 1912 in the memory 325 based on the second signal 1721 obtained at timing 1940. For example, unlike the first time interval 1911, the display driver circuit 320 may operate according to the second signal 1721 in the second time interval 1912.

[0192] For example, whether to store the second image in the memory 325 within the first time interval 1911 regardless of the second signal 1721 may be identified based on the time length 1950 of the first image before the second image is maintained on the display panel 340. For example, the display driver circuit 320 may identify the time length 1950 in response to the second signal 1721 obtained from the processor 310 at the timing 1940. For example, in response to the time length 1950 being longer than the reference length, the display driver circuit 320 may store the second image immediately following (after) the first image obtained from the processor 310 in the memory 325 within an initial time interval (e.g., the first time interval 1911) among a plurality of time intervals after obtaining the second signal 1721. The second image may be displayed on the display panel 340 by scanning the second image stored in the memory 325 within the initial time interval (e.g., the first time interval 1911). For example, with Fig.19 Unlike the example shown, in response to the time length 1950 being shorter than or equal to the reference length, the display driver circuit 320 may bypass storing the second image in the memory 325 during the initial time interval. For example, since the fact that the time length is shorter than or equal to the reference length indicates that the probability of an afterimage caused by the change from the first image to the second image is relatively low, the display driver circuit 320 may operate according to the setting based on the second signal 1721 (e.g., bypassing the operation of storing the image in the memory 325).

[0193] With through Figures 15 to 19Unlike the first signal 1621 and the second signal 1721 shown, the processor 310 may provide a third signal (e.g., an on-the-fly indication) (or an on-the-fly indication (enable)) applied to one time interval to the display driver circuit 320. For example, unlike the first signal and the second signal that may be applied to two or more time intervals, the third signal may be provided from the processor 310 to the display driver circuit 320 to control the operation of the display driver circuit 320 within one time interval. For example, the third signal may be provided from the processor 310 to the display driver circuit 320 to store an image provided from the processor 310 to the display driver circuit 320 within the time interval in the memory 325. For example, the first signal, the second signal, and the third signal may not be obtained from the processor 310 after the third signal is obtained. In the case of a signal in the first signal and the third signal, the display driver circuit 320 may bypass storing the image provided from the processor 310 to the display driver circuit 320 in the memory 325 in another time interval immediately following (after) the time interval. For example, in response to the third signal obtained after the first signal, the display driver circuit 320 may store the image provided by the processor 310 in the time interval in the memory 325, and avoid or bypass storing the image provided from the processor 310 to the display driver circuit 320 in accordance with the first signal in another time interval immediately following (after) the time interval. For example, the third signal may be used to set the state of the switch 330 in the time interval to the first state 331, and set the state of the switch 330 in the next (subsequent) time interval to the second state 332.

[0194] As a non-limiting example, the location where the third signal is stored in the display driver circuit 320 may be different from the location where each of the first signal and the second signal is stored in the display driver circuit 320. For example, the address of the third signal may be different from the address of each of the first signal and the second signal. The operation according to the third signal may be performed in the display driver circuit 320. Fig. 20 Shown in.

[0195] Fig. 20 is a flow chart illustrating an exemplary method of providing a third signal.

[0196] refer to Fig. 20In operation 2001, the processor 310 may identify an image to be maintained on the display panel 340 for a reference time or longer. For example, the processor 310 may identify that the image is maintained for more than the reference time based on identifying that an image immediately following (after) the image to be provided to the display driver circuit 320 is not obtained or rendered. For example, the processor 310 may identify the image to reduce a refresh rate shown on the display panel 340 or a refresh rate within the display panel 340. However, it is not limited thereto.

[0197] In operation 2003, in response to the above-mentioned image, the processor 310 may provide a third signal for the image (e.g., an in-progress indication (or an in-progress indication (enabled))) to the display driver circuit 320, indicating that the image provided from the processor 310 for display on the display panel 340 is stored in the memory 325.

[0198] The display driver circuit 320 may operate according to the third signal. Fig.21 Shown in.

[0199] Fig.21 An exemplary method of storing an image based on a third signal is shown.

[0200] refer to Fig.21 As shown in the state 2101, the processor 310 may provide the first image to the display driver circuit 320 through the interface 315 within the first time interval 2111. For example, in response to the first image being maintained on the display panel 340 for more than the reference time, the processor 310 may provide the display driver circuit 320 with a third signal 2121 at a timing 2120 within the front porch portion of the vertical synchronization signal corresponding to the first time interval 2111. For example, unlike the first signal 1621, the third signal 2121 may indicate that the first image is stored in the memory 325 within the first time interval 2111, and that the storage of the image provided from the processor 310 is bypassed within at least one time interval immediately following (after) the first time interval 2111. For example, unlike the first signal 1621, the third signal 2121 may be provided only for storing the first image in the memory 325.

[0201] For example, as indicated by arrow 2131, the display driver circuit 320 may display the first image provided from the processor 310 in the first time interval 2111 on the display panel 340. For example, as indicated by arrow 2132, the display driver circuit 320 may store (or record) the first image provided from the processor 310 in the first time interval 2111 in the memory 325 based on the third signal 2121 obtained at the timing 2120. For example, as indicated by arrow 2133, the display driver circuit 320 may display the first image again on the display panel 340 in the first time interval 2111 by scanning the first image stored in the memory 325. As a non-limiting example, displaying the first image by scanning the first image stored in the memory 325 may be performed to reduce the occurrence of an afterimage on the display panel 340.

[0202] For example, as indicated by arrow 2134, the display driver circuit 320 may display the first image on the display panel 340 by scanning the first image stored in the memory 325 in the second time interval 2112 immediately following (after) the first time interval 2111. For example, the length of the second time interval 2112 may correspond to the length of the first time interval 2111. However, this is not limited thereto. Fig.21 Different from the illustration, the length of the second time interval 2112 may be longer than the length of the first time interval 2111 to gradually reduce the refresh rate shown on the display panel 340 .

[0203] For example, as indicated by state 2102 , processor 310 may provide a second image to display driver circuit 320 via interface 315 during a third time interval 2113 .

[0204] For example, as indicated by arrow 2135, the display driver circuit 320 may display the second image provided from the processor 310 in the third time interval 2113 on the display panel 340. For example, since the third signal 2121 obtained from the processor 310 at timing 2120 is not applied to the third time interval 2113 unlike the first signal 1621, the display driver circuit 320 may bypass storing the second image in the memory 325 in the third time interval 2113, as indicated by arrow 2136. Fig.21 Not shown, but as indicated by arrow 2136, even when the first signal 1621 is obtained from the processor 310 before the third signal 2121 is obtained at timing 2120, the display driver circuit 320 may bypass storing the second image in the memory 325 within the third time interval 2113.

[0205] Return to reference Fig. 20, the processor 310 may provide the display driver circuit 320 with a third signal at a timing later than the timing at which it is recognized that the image to be provided to the display driver circuit 320 is maintained on the display panel 340 for a reference time or longer. The delayed provision of the third signal may be performed by Fig. 22 Shown.

[0206] Fig. 22 An exemplary method of delaying display of an image is shown.

[0207] refer to Fig. 22 As shown in state 2201 , the processor 310 may provide the display driver circuit 320 with a first image to be newly displayed on the display panel 340 within a first time interval 2211 through the interface 315 .

[0208] For example, as indicated by arrow 2231 , the display driver circuit 320 may display, on the display panel 340 , a first image obtained from the processor 310 within a first time interval 2211 .

[0209] For example, as indicated by the state 2202, the processor 310 may provide the first image to the display driver circuit 320 again through the interface 315 within the second time interval 2212. For example, even when the processor 310 recognizes within the portion 2250 of the first time interval 2211 that the first image is to be maintained within the second time interval 2212, the processor 310 may provide the first image to the display driver circuit 320 again from the start timing 2251 of the second time interval 2212 so as to display a second image different from the first image within the portion 2250 of the first time interval 2211. For example, the first image provided again to the display driver circuit 320 may be an image with reduced afterimages. For example, the first display of the plurality of displays of the first image may be performed after the portion 2250 of the first time interval 2211.

[0210] For example, as indicated by arrow 2232 , the display driver circuit 320 may again display the first image obtained from the processor 310 on the display panel 340 within the second time interval 2212 .

[0211] For example, in response to recognizing that the first image is to be held for more than the reference time within the second time interval 2212, the processor 310 may provide the third signal 2121 to the display driver circuit 320 at the timing 2220 within the front porch portion of the vertical synchronization signal. For example, as indicated by the state 2203, after providing the third signal 2121, the processor 310 may again provide the first image to the display driver circuit 320 through the interface 315 within the third time interval 2213.

[0212] For example, as indicated by arrow 2234, the display driver circuit 320 may again display the first image obtained from the processor 310 on the display panel 340 within the third time interval 2213. For example, as indicated by arrow 2233, the display driver circuit 320 may store the first image obtained from the processor 310 in the memory 325 within the third time interval 2213.

[0213] For example, as indicated by arrow 2235, the display driver circuit 320 may display the first image again on the display panel 340 within the third time interval 2213 by scanning the first image stored in the memory 325. As a non-limiting example, displaying the first image by scanning the first image stored in the memory 325 may be performed to reduce the occurrence of an afterimage on the display panel 340. However, it is not limited thereto. For example, according to the recognition (or determination) of the display driver circuit 320, displaying the first image by scanning the first image may not be performed within the third time interval 2213.

[0214] Although not shown with reference to the drawings, the processor 310 may provide the display driver circuit 320 with a fourth signal (e.g., an in-operation indication (disabled)) which is opposite to the third signal, indicating that the image provided to the display driver circuit 320 is bypassed from being stored in the memory 325. For example, the display driver circuit 320 may bypass storing the image provided by the processor 310 in the memory 325 in a time interval immediately after receiving the fourth signal based on the fourth signal. For example, after displaying the first image on the display panel 340 based on scanning the first image stored in the memory 325 according to the first signal, the processor 310 may provide the display driver circuit 320 with a fourth signal for the second image. For example, the display driver circuit 320 may store the second image in the memory 325 independently of the fourth signal. For example, the display driver circuit 320 may identify the length of time for which the first image is maintained on the display panel in response to the fourth signal. For example, in response to the time length being longer than the reference length, the display driver circuit 320 may display the second image obtained from the processor on the display panel within the time interval of the second image, store the second image in the memory within the time interval, and scan the second image stored in the memory within the time interval to display the second image on the display panel again. For example, in response to the time length being shorter than or equal to the reference length, the display driver circuit 320 may display the second image from the processor on the display panel within the time interval, and bypass storing the second image in the memory within the time interval. For example, the fourth signal may indicate a setting that indicates bypassing storing the image in the memory 325. According to an embodiment, the fourth signal may not be defined in the electronic device 300.

[0215] Fig.2323 is a block diagram showing an electronic device 2301 in a network environment 2300 according to various embodiments. Fig.23 , the electronic device 2301 in the network environment 2300 may communicate with the electronic device 2302 via the first network 2398 (e.g., a short-range wireless communication network), or communicate with at least one of the electronic device 2304 or the server 2308 via the second network 2399 (e.g., a long-range wireless communication network). According to an embodiment, the electronic device 2301 may communicate with the electronic device 2304 via the server 2308. According to an embodiment, the electronic device 2301 may include a processor 2320, a memory 2330, an input module 2350, a sound output module 2355, a display module 2360, an audio module 2370, a sensor module 2376, an interface 2377, a connection terminal 2378, a haptic module 2379, a camera module 2380, a power management module 2388, a battery 2389, a communication module 2390, a user identification module (SIM) 2396, or an antenna module 2397. In some embodiments, at least one component (e.g., the connection terminal 2378) may be omitted from the electronic device 2301, or one or more other components may be added to the electronic device 2301. In some embodiments, some components (e.g., the sensor module 2376, the camera module 2380, or the antenna module 2397) may be implemented as a single component (e.g., the display module 2360).

[0216] The processor 2320 may execute, for example, software (e.g., program 2340) to control at least one other component (e.g., hardware or software component) of the electronic device 2301 coupled to the processor 2320, and may perform various data processing or calculations. According to an embodiment, as at least part of the data processing or calculation, the processor 2320 may store a command or data received from another component (e.g., sensor module 2376 or communication module 2390) in the volatile memory 2332, process the command or data stored in the volatile memory 2332, and store the resulting data in the non-volatile memory 2334. According to an embodiment, the processor 2320 may include a main processor 2321 (e.g., a central processing unit (CPU) or an application processor (AP)) or an auxiliary processor 2323 (e.g., a graphics processing unit (GPU), a neural processing unit (NPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that may operate independently of the main processor 2321 or in conjunction with the main processor 2321. For example, when the electronic device 2301 includes a main processor 2321 and an auxiliary processor 2323, the auxiliary processor 2323 may be adapted to consume less power than the main processor 2321 or be specific to a specified function. The auxiliary processor 2323 may be implemented separately from the main processor 2321 or as a part of the main processor 2321.

[0217] The auxiliary processor 2323 may replace the main processor 2321 when the main processor 2321 is in an inactive (e.g., sleep) state, or control at least some of the functions or states related to at least one of the components of the electronic device 2301 (e.g., display module 2360, sensor module 2376, or communication module 2390) together with the main processor 2321 when the main processor 2321 is in an active state (e.g., executing an application). According to an embodiment, the auxiliary processor 2323 (e.g., an image signal processor or a communication processor) may be implemented as a part of another component (e.g., a camera module 2380 or a communication module 2390) that is functionally related to the auxiliary processor 2323. According to an embodiment, the auxiliary processor 2323 (e.g., a neural processing unit) may include a hardware structure specified for artificial intelligence model processing. The artificial intelligence model may be generated by machine learning. Such learning may be performed, for example, by the electronic device 2301 in which artificial intelligence is executed or via a separate server (e.g., server 2308). The learning algorithm may include, but is not limited to, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q network, or a combination of two or more thereof, but is not limited thereto. The artificial intelligence model may additionally or alternatively include a software structure in addition to a hardware structure.

[0218] The memory 2330 may store various data used by at least one component of the electronic device 2301 (e.g., the processor 2320 or the sensor module 2376). The various data may include, for example, input data or output data of software (e.g., the program 2340) and commands related thereto. The memory 2330 may include a volatile memory 2332 or a non-volatile memory 2334.

[0219] The program 2340 may be stored as software in the memory 2330 , and may include, for example, an operating system (OS) 2342 , middleware 2344 , or an application 2346 .

[0220] The input module 2350 may receive a command or data to be used by another component (e.g., the processor 2320) of the electronic device 2301 from outside (e.g., a user) of the electronic device 2301. The input module 2350 may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus).

[0221] The sound output module 2355 can output sound signals to the outside of the electronic device 2301. The sound output module 2355 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or playing recordings. The receiver may be used to receive incoming calls. Depending on the embodiment, the receiver may be implemented as being separated from the speaker or as a part of the speaker.

[0222] The display module 2360 can visually provide information to the outside of the electronic device 2301 (e.g., a user). The display module 2360 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling a corresponding one of the display, the hologram device, and the projector. According to an embodiment, the display module 2360 may include a touch sensor adapted to detect a touch, or a pressure sensor adapted to measure the strength of a force caused by a touch.

[0223] The audio module 2370 can convert sound into an electrical signal, and vice versa. According to an embodiment, the audio module 2370 can obtain sound via the input module 2350, or output sound via the sound output module 2355 or an earphone of an external electronic device (e.g., electronic device 2302) directly (e.g., wired) or wirelessly coupled to the electronic device 2301.

[0224] The sensor module 2376 may detect an operating state (e.g., power or temperature) of the electronic device 2301 or an environmental state (e.g., a state of a user) outside the electronic device 2301, and then generate an electrical signal or data value corresponding to the detected state. According to an embodiment, the sensor module 2376 may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0225] The interface 2377 may support one or more designated protocols for the electronic device 2301 to be directly (e.g., wired) or wirelessly coupled to an external electronic device (e.g., the electronic device 2302). According to an embodiment, the interface 2377 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0226] The connection end 2378 may include a connector, via which the electronic device 2301 may be physically connected to an external electronic device (eg, the electronic device 2302). Depending on the embodiment, the connection end 2378 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

[0227] The haptic module 2379 may convert the electric signal into mechanical stimulation (eg, vibration or movement) or electric stimulation that can be recognized by the user via tactile sensation or kinesthetic sensation. According to an embodiment, the haptic module 2379 may include, for example, a motor, a piezoelectric element, or an electric stimulator.

[0228] The camera module 2380 may capture a still image or a moving image. According to an embodiment, the camera module 2380 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0229] The power management module 2388 may manage power supplied to the electronic device 2301. According to one embodiment, the power management module 2388 may be implemented as, for example, at least a portion of a power management integrated circuit (PMIC).

[0230] The battery 2389 may supply power to at least one component of the electronic device 2301. According to an embodiment, the battery 2389 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0231] The communication module 2390 can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 2301 and an external electronic device (e.g., electronic device 2302, electronic device 2304, or server 2308), and perform communication via the established communication channel. The communication module 2390 may include one or more communication processors that can operate independently of the processor 2320 (e.g., application processor (AP)) and support direct (e.g., wired) communication or wireless communication. According to an embodiment, the communication module 2390 may include a wireless communication module 2392 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 2394 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules can communicate with the external electronic device via a first network 2398 (e.g., a short-range communication network 2398, such as Bluetooth TM, Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA)) or a second network 2399 (e.g., the second network 2399, for example, a long-distance communication network such as a traditional cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single chip), or may be implemented as multiple components separated from each other (e.g., multiple chips). The wireless communication module 2392 may identify and authenticate the electronic device 2301 in a communication network (e.g., the first network 2398 or the second network 2399) using user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the subscriber identification module 2396.

[0232] The wireless communication module 2392 can support 5G networks and next-generation communication technologies (e.g., new radio (NR) access technology) after the 4G network. NR access technology can support enhanced mobile broadband (eMBB), massive machine type communication (mMTC), or ultra-reliable and low-latency communication (URLLC). The wireless communication module 2392 can support high-frequency bands (e.g., mmWave (millimeter wave) bands) to achieve, for example, high data transmission rates. The wireless communication module 2392 can support various technologies for ensuring performance on high-frequency bands, such as, for example, beamforming, massive multiple input and multiple output (massive MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, or massive antennas. The wireless communication module 2392 can support various requirements specified in the electronic device 2301, an external electronic device (e.g., electronic device 2304), or a network system (e.g., a second network 2399). According to an embodiment, the wireless communication module 2392 can support a peak data rate for implementing eMBB (e.g., 20 Gbps or greater), loss coverage for implementing mMTC (e.g., 2364 dB or less), or U-plane delay for implementing URLLC (e.g., 0.5 ms or less for each of the downlink (DL) and uplink (UL), or 23 ms or less for a round trip).

[0233] The antenna module 2397 may transmit a signal or power to or receive a signal or power from the outside of the electronic device 2301 (e.g., an external electronic device). According to an embodiment, the antenna module 2397 may include an antenna including a radiation element formed of or including a conductive material or a conductive pattern formed in or on a substrate (e.g., a printed circuit board (PCB)). According to an embodiment, the antenna module 2397 may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication scheme used in a communication network such as the first network 2398 or the second network 2399 may be selected from the plurality of antennas by, for example, the communication module 2390 (e.g., the wireless communication module 2392). Then, a signal or power may be transmitted or received between the communication module 2390 and the external electronic device via the selected at least one antenna. According to an embodiment, another component (e.g., a radio frequency integrated circuit (RFIC)) other than the radiation element may be additionally formed as a part of the antenna module 2397.

[0234] According to various embodiments, the antenna module 2397 may form a millimeter wave antenna module. According to an embodiment, the millimeter wave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., millimeter wave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving signals of the specified high frequency band.

[0235] At least some of the above components may be coupled to each other and transmit signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, general purpose input and output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI)).

[0236] According to an embodiment, a command or data may be sent or received between the electronic device 2301 and the external electronic device 2304 via a server 2308 coupled to the second network 2399. Each of the electronic devices 2302 or 2304 may be a device of the same type or a different type as the electronic device 2301. According to an embodiment, all or some operations to be performed at the electronic device 2301 may be performed at one or more of the external electronic devices 2302, 2304, or 2308. For example, if the electronic device 2301 should automatically perform a function or service, or in response to a request from a user or another device, the electronic device 2301 may request one or more external electronic devices to perform at least a portion of the function or service instead of or in addition to performing the function or service. The one or more external electronic devices receiving the request may perform at least a portion of the requested function or service, or an additional function or additional service related to the request, and transmit the result of the execution to the electronic device 2301. The electronic device 2301 may provide the result as at least a part of the reply to the request with or without further processing the result. To this end, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device 2301 may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In an embodiment, the external electronic device 2304 may include an Internet of Things (IoT) device. The server 2308 may be an intelligent server using machine learning and / or a neural network. According to an embodiment, the external electronic device 2304 or the server 2308 may be included in the second network 2399. The electronic device 2301 may be applied to intelligent services (e.g., smart homes, smart cities, smart cars, or healthcare) based on 5G communication technology or IoT-related technologies.

[0237] Fig.24 2400 is a block diagram illustrating a display module 2360 according to various embodiments. Fig.24, the display module 2360 may include a display 2410 and a display driver integrated circuit (DDI) 2430 for controlling the display 2410. The DDI 2430 may include an interface module 2431, a memory 2433 (e.g., a buffer memory), an image processing module 2435, or a mapping module 2437. The DDI 2430 may receive image information containing image data or an image control signal corresponding to a command to control image data from another component of the electronic device 2301 via the interface module 2431. For example, according to an embodiment, the image information may be received from a processor 2320 (e.g., a main processor 2321 (e.g., an application processor)) or an auxiliary processor 2323 (e.g., a graphics processing unit) that operates independently of the function of the main processor 2321. The DDI 2430 may communicate with the touch circuit 2350 or the sensor module 2376, for example, via the interface module 2431. The DDI 2430 may also store at least a portion of the received image information in the memory 2433, for example, frame by frame. The image processing module 2435 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least a portion of the image data. According to an embodiment, the pre-processing or post-processing may be performed, for example, at least in part based on one or more characteristics of the image data or one or more characteristics of the display 2410. The mapping module 2437 may generate a voltage value or a current value corresponding to the image data pre-processed or post-processed by the image processing module 2435. According to an embodiment, the generation of the voltage value or the current value may be performed, for example, at least in part based on one or more attributes of the pixel (e.g., an array of pixels, such as RGB stripes or a pentile structure, or the size of each sub-pixel). At least some pixels of the display 2410 may be driven, for example, at least in part based on the voltage value or the current value, so that visual information (e.g., text, an image, or an icon) corresponding to the image data may be displayed via the display 2410.

[0238] According to an embodiment, the display module 2360 may further include a touch circuit 2450. The touch circuit 2450 may include a touch sensor 2451 and a touch sensor IC 2453 for controlling the touch sensor 2451. The touch sensor IC 2453 may control the touch sensor 2451 to sense a touch input or a hovering input relative to a specific position on the display 2410. To achieve this, for example, the touch sensor 2451 may detect (e.g., measure) a change in a signal (e.g., voltage, light amount, resistance, or amount of one or more charges) corresponding to a specific position on the display 2410. The touch circuit 2450 may provide input information (e.g., position, area, pressure, or time) indicating a touch input or a hovering input detected via the touch sensor 2451 to the processor 2320. According to an embodiment, at least a portion of the touch circuit 2450 (e.g., the touch sensor IC 2453) may be formed as a part of the display 2410 or the DDI 2430, or as a part of another component (e.g., the auxiliary processor 2323) provided outside the display module 2360.

[0239] According to an embodiment, the display module 2360 may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor, or an illumination sensor) of the sensor module 2376 or a control circuit for at least one sensor. In this case, the at least one sensor or the control circuit for at least one sensor may be embedded in a portion of a component (e.g., the display 2410, the DDI 2430, or the touch circuit 2350) of the display module 2360. For example, when the sensor module 2376 embedded in the display module 2360 includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor may obtain biometric information (e.g., a fingerprint image) corresponding to a touch input received via a portion of the display 2410. As another example, when the sensor module 2376 embedded in the display module 2360 includes a pressure sensor, the pressure sensor may obtain pressure information corresponding to a touch input received via a portion or the entire area of ​​the display 2410. According to an embodiment, the touch sensor 2451 or the sensor module 2376 may be arranged between pixels in a pixel layer of the display 2410, or arranged above or below the pixel layer.

[0240] As described above, the electronic device 300 may include a display panel 340, a display driver circuit 320 operably coupled to the display panel 340 and including a memory 325, and a processor 310 operably coupled to the display driver circuit 320. According to an embodiment, the display driver circuit 320 may be configured to display a first image obtained from the processor 310 on the display panel 340 during a first time interval. According to an embodiment, the display driver circuit 320 may be configured to store the first image obtained from the processor 310 during the first time interval in the memory 325 based on the first image being maintained on the display panel 340 during a second time interval immediately following (after) the first time interval. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the first image during the first time interval based on the first image being changed to the second image during the second time interval.

[0241] According to an embodiment, the display driver circuit 320 may be configured to maintain the first image displayed on the display panel 340 during the second time interval by scanning the first image stored in the memory 325 during the second time interval. According to an embodiment, the processor 310 may be configured to avoid providing the first image to the display driver circuit 320 during the second time interval.

[0242] According to an embodiment, the display driver circuit 320 may be configured to display the second image obtained from the processor 310 within the second time interval on the display panel 340 .

[0243] According to an embodiment, storing the first image in the memory 325 may start from a timing recognized by the processor 310 in the processor 310 and the display driver circuit 320 .

[0244] According to an embodiment, the display driver circuit 320 may be configured to identify whether a predetermined signal is obtained from the processor 310 within a third time interval before the first time interval. According to an embodiment, the display driver circuit 320 may be configured to store the first image in the memory 325 within the first time interval based on the third time interval in which the predetermined signal is obtained. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the first image in the memory 325 within the first time interval based on the third time interval in which the predetermined signal is not obtained. According to an embodiment, the processor 310 may be configured to provide the predetermined signal to the display driver circuit 320 within the third time interval through a plurality of transmissions.

[0245] According to an embodiment, the display driver circuit 320 may be configured to store the first image in the memory 325 by connecting the memory 325 and the processor 310 via the switch 330 of the electronic device 300 during the first time interval. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the first image in the memory 325 by disconnecting the processor 310 from the memory 325 through the switch during the first time interval.

[0246] According to an embodiment, the processor 310 may be configured to: based on recognizing that the first image displayed on the display panel 340 is maintained within a plurality of time intervals including the first time interval and the second time interval, provide a signal to the display driver circuit 320 in which a third time interval having a length longer than each of the plurality of time intervals is indicated as a time interval immediately following (after) the plurality of time intervals. According to an embodiment, the display driver circuit 320 may be configured to maintain the first image displayed on the display panel 340 within the third time interval by scanning the first image stored in the memory 325 within the third time interval.

[0247] According to an embodiment, the display driver circuit 320 may be configured to perform multiple displays of the second image on the display panel 340 within the second time interval based on the length of the second time interval being longer than the reference length. According to an embodiment, the first display of the multiple displays may be performed based on obtaining the second image from the processor 310 within a portion of the second time interval. According to an embodiment, at least one second display of the multiple displays immediately following (after) the first display may be performed based on scanning the second image stored in the memory 325 within a portion of the second time interval. According to an embodiment, the display driver circuit 320 may be configured to perform a single display of the second image on the display panel 340 in the second time interval based on the length being shorter than or equal to the reference length. According to an embodiment, the display driver circuit 320 may be configured to store the second image in the memory 325 within the second time interval in which the single display of the second image is performed based on the second image being to be maintained on the display panel 340 within a third time interval immediately following (after) the second time interval. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the second image in the memory 325 within the second time interval in which the single display of the second image is performed based on the second image being changed to the third image within the third time interval in which the second image is changed to the third image within the third time interval.

[0248] According to an embodiment, the display driver circuit 320 may be configured to identify a time length between an end timing of displaying a first image within a first time interval and a start timing of displaying a second image within a second time interval. According to an embodiment, the display driver circuit 320 may be configured to perform multiple displays of the second image on the display panel 340 within the second time interval based on the time length being longer than a reference length. According to an embodiment, a first display among the multiple displays may be performed based on obtaining the second image from the processor 310 within a portion of the second time interval from the start timing. According to an embodiment, at least one second display immediately following (after) the first display among the multiple displays may be performed based on scanning a second image stored in the memory 325 within a portion of the second time interval.

[0249] According to an embodiment, the display driver circuit 320 may be configured to perform a single display of the second image on the display panel 340 in the second time interval based on the time length being shorter than or equal to the reference length. According to an embodiment, the display driver circuit 320 may be configured to store the second image in the memory 325 in the second time interval when performing the single display of the second image based on the second image being to be maintained on the display panel 340 in a third time interval immediately following (after) the second time interval. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the second image in the memory 325 in the second time interval based on the second image being to be changed to the third image in the third time interval.

[0250] According to an embodiment, the display driver circuit 320 may be configured to perform a plurality of displays of the second image on the display panel 340 within the second time interval based on the length of the first time interval being longer than the reference length. According to an embodiment, a first display of the plurality of displays may be performed based on obtaining the second image from the processor 310 within the portion of the second time interval. According to an embodiment, at least one second display of the plurality of displays immediately following (after) the first display may be performed based on scanning the second image stored in the memory 325 within the portion of the second time interval.

[0251] According to an embodiment, the display driver circuit 320 may be configured to perform a single display of the second image on the display panel 340 within the second time interval based on the length being shorter than or equal to the reference length. According to an embodiment, the display driver circuit 320 may be configured to store the second image in the memory 325 within the second time interval when the single display of the second image is performed, based on the second image being to be maintained on the display panel 340 within a third time interval immediately following (after) the second time interval. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the second image in the memory 325 within the second time interval when the single display of the second image is performed, based on the second image being to be changed to the third image within the third time interval.

[0252] According to an embodiment, the display driver circuit 320 may be configured to store the first image in the memory 325 when providing a video mode of a display serial interface (DSI).

[0253] As described above, the electronic device 300 may include a display driver circuit 320, a display panel 340, a processor 310, and a memory 325, the display driver circuit 320 including a switch, the memory 325 being operably coupled to the display panel 340 and being connectable to the processor 310 through the switch. According to an embodiment, the display driver circuit 320 may be configured to display a first image obtained from the processor 310 on the display panel 340. According to an embodiment, the display driver circuit 320 may be configured to: while obtaining the first image from the processor 310, store the first image in the memory 325 based on connecting the processor 310 and the memory 325 through the switch. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the first image in the memory 325 based on disconnecting the memory 325 from the processor 310 through the switch when obtaining the first image from the processor 310.

[0254] As described above, the electronic device 300 may include a display panel 340, a display driver circuit 320 operably coupled to the display panel 340 and including a memory 325, and a processor 310 operably coupled to the display driver circuit 320. According to an embodiment, the processor 310 may be configured to identify a refresh rate. According to an embodiment, the processor 310 may be configured to provide a first signal to the display driver circuit 320 according to the identified refresh rate, the first signal indicating that one or more images to be provided from the processor 310 for display on the display panel 340 according to the refresh rate are stored in the memory 325. According to an embodiment, the processor 310 may be configured to provide a second signal to the display driver circuit 320 indicating to bypass storing one or more images in the memory 325 according to the identified refresh rate.

[0255] As described above, the electronic device 300 may include a display panel 340, a display driver circuit 320 operably coupled to the display panel 340 and including a memory 325, and a processor 310 operably coupled to the display driver circuit 320. According to an embodiment, the processor 310 may be configured to identify a refresh rate. According to an embodiment, the processor 310 may be configured to provide a first signal to the display driver circuit 320 in response to the refresh rate being lower than a reference refresh rate, the first signal indicating that one or more images to be provided from the processor 310 for display on the display panel 340 according to the refresh rate are stored in the memory 325. According to an embodiment, the processor 310 may be configured to provide a second signal to the display driver circuit 320 in response to the refresh rate being higher than or equal to the reference refresh rate, indicating that the storage of one or more images in the memory 325 is bypassed.

[0256] According to an embodiment, each of the first signal and the second signal may be provided from the processor 310 through a front porch portion of a vertical synchronization signal or in a front porch portion of a vertical synchronization signal.

[0257] According to an embodiment, the display driver circuit 320 may be configured to maintain storing the one or more images in the memory 325 based on the first signal until the second signal is obtained from the processor 310 .

[0258] According to an embodiment, the display driver circuit 320 may be configured to maintain bypassing storing the one or more images in the memory 325 based on the second signal until the first signal is obtained from the processor 310 .

[0259] According to an embodiment, the processor 310 may be configured to provide a first signal to the display driver circuit 320 to perform multiple displays of a single image on the display panel 340 within a time interval corresponding to a refresh rate lower than a reference refresh rate. According to an embodiment, the processor 310 may be configured to provide a second signal to the display driver circuit 320 to perform a single display of a single image on the display panel 340 within a time interval corresponding to a refresh rate higher than or equal to the reference refresh rate. According to an embodiment, the multiple displays may include a first display and a second display immediately following (after) the first display. According to an embodiment, the display driver circuit 320 may be configured to perform the first display by displaying a single image obtained from the processor 310 on the display panel 340 and storing the single image in the memory 325 within a portion of the time interval corresponding to the refresh rate lower than the reference refresh rate. According to an embodiment, the display driver circuit 320 may be configured to perform the second display by displaying the single image on the display panel 340 based on scanning the single image stored in the memory 325 at another portion of the time interval corresponding to the refresh rate lower than the reference refresh rate.

[0260] According to an embodiment, the display driver circuit 320 may be configured to bypass performing the second display in an initial time interval among a plurality of time intervals after obtaining the first signal, the plurality of time intervals respectively corresponding to refresh rates lower than the reference refresh rate. According to an embodiment, the display driver circuit 320 may be configured to perform the second display in each of one or more time intervals immediately following (after) the initial time interval among the plurality of time intervals.

[0261] According to an embodiment, it can be recognized by the display driver circuit 320 and the display driver circuit 320 in the processor 310 by scanning images held in two or more time intervals respectively corresponding to refresh rates lower than the reference refresh rate in the memory 325 using the display driver circuit 320 operating based on the first signal.

[0262] According to an embodiment, the processor 310 may be configured to: after displaying the first image on the display panel 340 based on scanning the first image stored in the memory 325 according to the first signal, provide the second signal to the display driver circuit 320. According to an embodiment, the display driver circuit 320 may be configured to store the second image immediately following (after) the first image in the memory 325 independently of the second signal, the second image being obtained from the processor 310 in an initial time interval among a plurality of time intervals after obtaining the second signal. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the image in the memory 325 based on the second signal, the image being obtained in each of one or more time intervals immediately following the initial time interval among the plurality of time intervals.

[0263] According to an embodiment, the processor 310 may be configured to: after displaying the first image on the display panel 340 based on scanning the first image stored in the memory 325 according to the first signal, provide the second signal to the display driver circuit 320. According to an embodiment, the display driver circuit 320 may be configured to identify the time length for which the first image is maintained on the display panel 340 in response to the second signal. According to an embodiment, the display driver circuit 320 may be configured to store the second image immediately following (after) the first image obtained from the processor 310 in an initial time interval among a plurality of time intervals after obtaining the second signal in the memory 325, and in response to the time length being longer than a reference length, display the second image on the display panel 340 by scanning the second image stored in the memory 325 in the initial time interval. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the second image in the memory 325 in the initial time interval in response to the time length being shorter than or equal to the reference length.

[0264] According to an embodiment, the processor 310 may be configured to identify an image to be maintained for a time longer than or equal to a reference time on the display panel 340. According to an embodiment, the processor 310 may be configured to provide the display driver circuit 320 with a third signal for the image, the third signal indicating that the image to be provided from the processor 310 for display on the display panel 340 in response to the image is stored in the memory 325.

[0265] According to an embodiment, the third signal for the image may be provided from the processor 310 through a front porch portion of a vertical synchronization signal or in a front porch portion of a vertical synchronization signal.

[0266] According to an embodiment, an address of the third signal for the image may be different from an address of each of the first signal and the second signal.

[0267] According to an embodiment, the display driver circuit 320 may be configured to obtain another image immediately following (after) the image from the processor 310 after obtaining the third signal. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the another image in the memory 325. According to an embodiment, the display driver circuit 320 may be configured to bypass storing the another image in the memory 325 in response to the third signal for the image obtained after obtaining the first signal, by releasing a setting for storing one or more images obtained from the processor 310 after obtaining the image in the memory 325 according to the first signal.

[0268] According to an embodiment, the processor 310 may be configured to, after displaying the first image on the display panel 340 based on scanning the first image stored in the memory 325 according to the first signal, provide a fourth signal to the display driver circuit 320 indicating bypassing of storing the second image provided from the processor 310 for display on the display panel 340 in the memory 325. According to an embodiment, the display driver circuit 320 may be configured to store the second image in the memory 325 independently of the fourth signal.

[0269] According to an embodiment, the display driver circuit 320 may be configured to identify, in response to the fourth signal, the length of time for which the first image is maintained on the display panel 340. According to an embodiment, the display driver circuit 320 may be configured to, in response to the length of time being longer than the reference length, store the second image in the memory 325 within the time interval, and display the second image again on the display panel 340 by scanning the second image stored in the memory 325 within the time interval, and display the second image obtained from the processor 310 on the display panel 340 within the time interval for the second image. According to an embodiment, the display driver circuit 320 may be configured to: in response to the length of time being shorter than or equal to the reference length, display the second image obtained from the processor 310 on the display panel 340, and bypass storing the second image in the memory 325 within the time interval.

[0270] According to an embodiment, the display driver circuit 320 may be configured to store one or more images in the memory 325 according to the first signal when providing a video mode of a display serial interface (DSI).

[0271] According to an embodiment, storing one or more images in the memory 325 according to the first signal may start from a timing recognized by the processor 310 in the processor 310 and the display driver circuit 320 .

[0272] The electronic device according to various embodiments may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, a home appliance, etc. According to an embodiment of the present disclosure, the electronic device is not limited to the above-mentioned electronic devices.

[0273] It should be understood that the various exemplary embodiments of the present disclosure and the terms used therein are not intended to limit the technical features set forth herein to specific embodiments, and are intended to include various changes, equivalents or replacements of the corresponding embodiments. With respect to the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that, unless otherwise explicitly stated in the relevant context, the singular form of the noun corresponding to the project may include one or more things. As used herein, each of phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include any one or all possible combinations of the items listed together in the corresponding phrase in the phrase. As used herein, terms such as "first" and "second" or "first" and "second" may be used to simply distinguish a corresponding component from another component, and do not limit the component in other aspects (e.g., importance or order). It should be understood that if an element (e.g., a first element) is referred to as being “coupled,” “coupled to,” “connected to,” or “connected to” another element (e.g., a second element) with or without the term “operably” or “communicatively,” the element may be coupled to the other element directly (e.g., by wire), wirelessly, or via a third element.

[0274] As used in conjunction with various embodiments of the present disclosure, the term "module" may include a unit implemented in hardware, software, or firmware, or any combination thereof, and may be used interchangeably with other terms (e.g., "logic," "logic block," "component," or "circuit"). A module may be a single integrated component or its smallest unit or portion adapted to perform one or more functions. For example, according to an embodiment, a module may be implemented in the form of an application specific integrated circuit (ASIC).

[0275] Various embodiments as described herein may be implemented as software (e.g., program 2340) including one or more instructions stored in a storage medium (e.g., internal memory 2336 or external memory 2338) that can be read by a machine (e.g., electronic device 2301). For example, a processor (e.g., processor 2320) of a machine (e.g., electronic device 2301) may call at least one of the one or more instructions stored in the storage medium and execute it with or without one or more other components under the control of the processor. This allows the machine to be operated to perform at least one function or operation according to at least one instruction called. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" means that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but the term does not distinguish between data stored semi-permanently in the storage medium and data temporarily stored in the storage medium.

[0276] According to an embodiment, the method according to various embodiments of the present disclosure may be included and provided in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or distributed online (e.g., downloaded or uploaded) via an application store (e.g., PlayStore™), or distributed directly between two user devices (e.g., smart phones). If distributed online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium, such as a memory of a manufacturer's server, an application store's server, or a relay server.

[0277] According to various embodiments, each of the above-mentioned components (e.g., a module or a program) may include a single entity or multiple entities, and some of the multiple entities may be separately provided in different components. According to various embodiments, one or more of the above-mentioned components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, according to various embodiments, the integrated component may still perform one or more functions of each of the multiple components in the same or similar manner as performed by a corresponding one of the multiple components before integration. According to various embodiments, the operations performed by a module, a program, or another component may be performed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be performed in a different order or omitted, or one or more other operations may be added.

Claims

1. An electronic device, comprising: Display panel; a display driver circuit operably coupled to the display panel, the display driver circuit comprising a memory; and a processor operably coupled to the display driver circuit, the processor being configured to: Identify the refresh rate, and Depending on the refresh rate identified: providing a first signal to the display driver circuit, the first signal indicating storage in the memory of one or more images to be provided from the processor for display on the display panel according to the refresh rate; or A second signal is provided to the display driver circuit, the second signal indicating bypassing storage of the one or more images in the memory.

2. The electronic device according to claim 1, wherein: The processor is configured to: In response to the refresh rate being lower than a reference refresh rate, providing the first signal to the display driver circuit; and In response to the refresh rate being higher than or equal to the reference refresh rate, the second signal is provided to the display driver circuit.

3. The electronic device according to claim 2, wherein: Each of the first signal and the second signal is provided from the processor through or in a front porch portion of a vertical synchronization signal.

4. The electronic device according to claim 2, wherein: The display driver circuit is configured to maintain the one or more images stored in the memory based on the first signal until the second signal is obtained from the processor.

5. The electronic device according to claim 2, wherein: The display driver circuit is configured to maintain bypassing storing the one or more images in the memory based on the second signal until the first signal is obtained from the processor.

6. The electronic device according to claim 2, wherein: The processor is configured to: providing the first signal to the display driver circuit to perform multiple displays of a single image on the display panel during time intervals corresponding to the refresh rate that is lower than the reference refresh rate; and The second signal is provided to the display driver circuit to perform a single display of the single image on the display panel during a time interval corresponding to the refresh rate that is higher than or equal to the reference refresh rate.

7. The electronic device according to claim 6, wherein: The plurality of displays include a first display and a second display subsequent to the first display, and Wherein the display driver circuit is configured as: performing the first display by displaying the single image obtained from the processor on the display panel and storing the single image in the memory for a portion of the time interval corresponding to the refresh rate lower than the reference refresh rate; and The second display is performed by displaying the single image on the display panel based on scanning the single image stored in the memory during another portion of the time interval corresponding to the refresh rate lower than the reference refresh rate.

8. The electronic device according to claim 7, wherein: The display driver circuit is configured as follows: bypassing the second display in an initial time interval among a plurality of time intervals after the first signal is obtained, the plurality of time intervals respectively corresponding to the refresh rates lower than the reference refresh rate; and The second displaying is performed in each of one or more time intervals after the initial time interval among the plurality of time intervals.

9. The electronic device according to claim 2, wherein: Scanning the image in the memory held in two or more time intervals respectively corresponding to the refresh rates lower than the reference refresh rate using the display driver circuit operating based on the first signal is recognized by the display driver circuit and the display driver circuit in the processor.

10. The electronic device according to claim 2, wherein: The processor is further configured to: after displaying the first image on the display panel based on scanning the first image stored in the memory according to the first signal, provide the second signal to the display driving circuit, The display driver circuit is configured to store a second image subsequent to the first image in the memory independently of the second signal, the second image being obtained from the processor in an initial time interval of a plurality of time intervals after obtaining the second image.

11. The electronic device according to claim 10, wherein: The display driver circuit is configured to bypass storing an image in the memory based on the second signal, the image being obtained in each of one or more time intervals after the initial time interval in the plurality of time intervals.

12. The electronic device according to claim 2, wherein: The processor is further configured to: after displaying the first image on the display panel based on scanning the first image stored in the memory according to the first signal, provide the second signal to the display driving circuit, Wherein the display driver circuit is configured as: identifying, in response to the second signal, a length of time that the first image remains on the display panel; In response to the time length being longer than a reference length, storing in the memory a second image subsequent to the first image obtained from the processor in an initial time interval among a plurality of time intervals after obtaining the second signal, and displaying the second image on the display panel by scanning the second image stored in the memory in the initial time interval; and In response to the time length being shorter than or equal to the reference length, storing the second image in the memory during the initial time interval is bypassed.

13. The electronic device according to claim 2, wherein: The processor is further configured to: identifying an image to be maintained on the display panel for a time longer than or equal to a reference time; and In response to the image, a third signal for the image is provided to the display driver circuit, the third signal indicating that the image to be provided from the processor for display on the display panel is stored in the memory.

14. The electronic device according to claim 13, wherein: The third signal for the image is provided from the processor through or in a front porch portion of a vertical synchronization signal.

15. The electronic device according to claim 13, wherein: The address of the third signal for the image is different from the address of each of the first signal and the second signal.

Images