Display panel, pixel circuit and driving method thereof

Abstract

The invention discloses a display panel, a pixel circuit and a driving method thereof, and relates to the technical field of display. The pixel circuit comprises a driving transistor (T3), a compensation circuit (2), a write-in circuit (4), a first reset circuit (1) and a second reset circuit (7). A first electrode of the driving transistor (T3) is used for receiving a first power supply signal (VDD), and a second electrode of the driving transistor (T3) is connected with the light-emitting device (LD) through the first light-emitting control circuit (5); one of a first pole and a second pole of the driving transistor (T3) is connected with a grid electrode of the driving transistor (T3) through the compensation circuit (2), and the other one receives a data signal (DA) through the write-in circuit (4); the first reset circuit (1) is connected with one of the first pole and the second pole of the driving transistor (T3) and is used for inputting a first reset signal (Vinit); the second reset circuit (7) is connected with one of the first pole and the second pole of the driving transistor (T3) and is used for inputting a second reset signal (Vref); the polarity of the first reset signal (Vinit) is opposite to that of the second reset signal (Vref).

Description

Display panel, pixel circuit and driving method thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a pixel circuit, and a driving method for the pixel circuit. Background Art

[0002] For display panels that use organic light-emitting diodes as light-emitting devices, the brightness of the light-emitting devices is generally controlled by pixel circuits. However, existing display panels have difficulty in stably maintaining the brightness of the screen when switching between high and low frequencies, and there is hysteresis in the screen and the risk of screen flickering.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The present disclosure provides a display panel, a pixel circuit, and a driving method of the pixel circuit.

[0006] According to one aspect of the present disclosure, there is provided a pixel circuit including a driving transistor, a compensation circuit, a writing circuit, a first reset circuit and a second reset circuit;

[0007] The first electrode of the driving transistor is used to receive a first power supply signal, and the second electrode is connected to the light emitting device through a first light emitting control circuit;

[0008] One of the first electrode and the second electrode of the driving transistor is connected to its gate via the compensation circuit, and the other receives a data signal via the writing circuit;

[0009] The first reset circuit is connected to one of the first and second electrodes of the driving transistor for inputting a first reset signal; the second reset circuit is connected to one of the first and second electrodes of the driving transistor for inputting a second reset signal; the first reset signal and the second reset signal have opposite polarities.

[0010] In an exemplary embodiment of the present disclosure, the first reset circuit and the compensation circuit are connected to the second electrode of the driving transistor, and the second reset circuit and the writing circuit are connected to the first electrode of the driving transistor.

[0011] In an exemplary embodiment of the present disclosure, the first reset circuit, the second reset circuit, and the compensation circuit are connected to the second electrode of the driving transistor, and the writing circuit is connected to the first electrode of the driving transistor.

[0012] In an exemplary embodiment of the present disclosure, the compensation circuit and the first reset circuit are connected to a first electrode of the driving transistor, and the second reset circuit and the write circuit are connected to a second electrode of the driving transistor.

[0013] In an exemplary embodiment of the present disclosure, the first reset circuit, the second reset circuit, and the compensation circuit are connected to a first electrode of the driving transistor, and the writing circuit is connected to a second electrode of the driving transistor.

[0014] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a tank circuit, a first light emitting control circuit, and a second light emitting control circuit;

[0015] The first electrode of the driving transistor receives the first power supply signal through the first light emitting control circuit, and the second electrode is connected to the light emitting device through the second light emitting control circuit;

[0016] The energy storage circuit is connected to the gate of the driving transistor and can receive the first power supply signal.

[0017] In an exemplary embodiment of the present disclosure, the compensation circuit includes a compensation transistor, the write circuit includes a write transistor, the first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the first light-emitting control circuit includes a first light-emitting control transistor, and the second light-emitting control circuit includes a second light-emitting control transistor; and the energy storage circuit includes a storage capacitor.

[0018] According to one aspect of the present disclosure, a driving method of a pixel circuit is provided, wherein the pixel circuit includes a driving transistor, a compensation circuit, a writing circuit, a first reset circuit, a second reset circuit, a first light emitting control circuit, and a second light emitting control circuit;

[0019] The first electrode of the driving transistor receives a first power supply signal through the first light-emitting control circuit, and the second electrode is connected to the light-emitting device through the second light-emitting control circuit; one of the first electrode and the second electrode of the driving transistor is connected to its gate through the compensation circuit, and the other receives a data signal through the writing circuit; the first reset circuit is connected to one of the first electrode and the second electrode of the driving transistor; and the second reset circuit is connected to one of the first electrode and the second electrode of the driving transistor;

[0020] The driving method includes:

[0021] In a first reset phase of a write frame, the write circuit, the first reset circuit, the first light-emitting control circuit, and the second light-emitting control circuit are turned off; the second reset circuit is turned on, and a second reset signal is input through the second reset circuit;

[0022] In a second reset phase of a write frame, the write circuit, the second reset circuit, the first light-emitting control circuit, and the second light-emitting control circuit are turned off; the compensation circuit and the first reset circuit are turned on, and a first reset signal is input through the first reset circuit; the first reset signal and the second reset signal have opposite polarities;

[0023] During a write phase of a write frame, the first reset circuit, the second reset circuit, the first light-emitting control circuit, and the second light-emitting control circuit are turned off; the write circuit and the compensation circuit are turned on, and a data signal is input through the write circuit;

[0024] In a third reset phase of the write frame, the compensation circuit, the write circuit, the second reset circuit, and the first light-emitting control circuit are turned off; the first reset circuit and the second light-emitting control circuit are turned on, and the first reset signal is input through the first reset circuit;

[0025] During the light emitting phase of the writing frame, the compensation circuit, the writing circuit, the first reset circuit, and the second reset circuit are turned off; and the first light emitting control circuit and the second light emitting control circuit are turned on.

[0026] In an exemplary embodiment of the present disclosure, the driving method further includes:

[0027] In the first reset phase of the holding frame, the writing circuit, the first reset circuit, the first light-emitting control circuit, and the second light-emitting control circuit are turned off; the second reset circuit is turned on, and the second reset signal is input through the second reset circuit;

[0028] In the second reset phase of the holding frame, the writing circuit, the second reset circuit, the first light-emitting control circuit, and the second light-emitting control circuit are turned off; the compensation circuit and the first reset circuit are turned on, and the first reset signal is input through the first reset circuit;

[0029] In the third reset phase of the hold frame, the compensation circuit, the write circuit, the second reset circuit and the first light-emitting control circuit are turned off; the first reset circuit and the second light-emitting control circuit are turned on, and the first reset signal is input through the first reset circuit.

[0030] In an exemplary embodiment of the present disclosure, the driving method further includes:

[0031] In the fourth reset phase of the hold frame, the first reset circuit, the second reset circuit, the first light-emitting control circuit and the second light-emitting control circuit are turned off; the write circuit and the compensation circuit are turned on, and the data signal is input through the write circuit.

[0032] In an exemplary embodiment of the present disclosure, the compensation circuit is turned on during the first reset phase of the write frame and the hold frame.

[0033] In an exemplary embodiment of the present disclosure, the number of the pixel circuits is plural and they are arrayed along the row direction and the column direction;

[0034] The first light emitting control circuit can be turned on in response to a first light emitting control signal, and the second light emitting control circuit can be turned on in response to a second light emitting control signal; the writing circuit can be turned on in response to a first scanning signal;

[0035] The first light emission control signal input to the pixel circuits in the nth row is multiplexed into a second light emission control signal input to the pixel circuits in the (n+i)th row.

[0036] In an exemplary embodiment of the present disclosure, the number of the pixel circuits is plural and they are arrayed along the row direction and the column direction;

[0037] The write circuit can be turned on in response to a first scan signal, and the second reset circuit can be turned on in response to a second reset control signal;

[0038] The first scanning signal input to the pixel circuits in the nth row is multiplexed into a second reset control signal input to the pixel circuits in the (n+j)th row.

[0039] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of pixel circuits arranged in an array along row and column directions, the pixel circuits comprising a plurality of transistors, storage capacitors, data lines, and power lines, the transistors comprising a drive transistor, a write transistor, a compensation transistor, a first emission control transistor, a second emission control transistor, a first reset transistor, and a second reset transistor;

[0040] The first electrode of the driving transistor is connected to the power line through the first light-emitting control transistor, and the second electrode is connected to the light-emitting device through the second light-emitting control transistor; one of the first electrode and the second electrode of the driving transistor is connected to its gate through the compensation transistor, and the other is connected to the data line through the write transistor; the first reset transistor is connected to one of the first electrode and the second electrode of the driving transistor; the second reset transistor is connected to one of the first electrode and the second electrode of the driving transistor; the storage capacitor is connected to the gate of the driving transistor and the power line; the power line is used to input a first power signal, and the data line is used to transmit a data signal;

[0041] The display panel includes:

[0042] substrate;

[0043] a circuit layer, provided on one side of the substrate and comprising the pixel circuit;

[0044] A plurality of light emitting devices are arranged on a side of the circuit layer away from the substrate, and one of the light emitting devices is connected to the second electrode of the second light emitting control transistor of the pixel circuit.

[0045] In an exemplary embodiment of the present disclosure, the circuit layer includes:

[0046] A first reset signal network is connected to the first electrode of the first reset transistor and is used to transmit a first reset signal; the first reset signal network includes a first signal line and a second signal line located in different layers and connected; the first signal line extends along the row direction, and the second signal line extends along the column direction.

[0047] In an exemplary embodiment of the present disclosure, the circuit layer includes:

[0048] A second reset signal network is connected to the first electrode of the second reset transistor and is used to transmit a second reset signal; the second reset signal network includes a third signal line and a fourth signal line located in different layers and connected; the third signal line extends along the row direction, and the fourth signal line extends along the column direction.

[0049] In an exemplary embodiment of the present disclosure, the circuit layer further includes:

[0050] a light shielding layer, provided on one side of the substrate;

[0051] a first semiconductor layer, provided on a side of the light shielding layer away from the light shielding layer, and including active portions of the driving transistor, the writing transistor, the first light emission control transistor, the second light emission control transistor, the first reset transistor, and the second reset transistor;

[0052] a first gate layer, disposed on a side of the first semiconductor layer away from the substrate and overlapping the first semiconductor layer; the first gate layer includes a first plate of the storage capacitor, and gates of the drive transistor, the write transistor, the first light-emitting control transistor, the second light-emitting control transistor, the first reset transistor, and the second reset transistor;

[0053] a second gate layer, provided on a side of the first gate layer away from the substrate, and comprising a second plate of the storage capacitor;

[0054] a second semiconductor layer, provided on a side of the second gate layer away from the substrate, and including an active portion of the compensation transistor;

[0055] a third gate layer, disposed on a side of the second semiconductor layer away from the substrate and overlapping the second semiconductor layer; the third gate layer includes a gate of the compensation transistor, the first signal line, and the third signal line;

[0056] a first source-drain layer, provided on a side of the third gate layer away from the substrate, and comprising the second signal line and the fourth signal line;

[0057] The second source-drain layer is provided on a side of the first source-drain layer away from the substrate and includes the power line and the data line.

[0058] In an exemplary embodiment of the present disclosure, the pixel circuits in each column are divided into a plurality of circuit groups distributed along the row direction, and the same circuit group includes two adjacent columns of pixel circuits;

[0059] The two columns of pixel circuits in the same circuit group are symmetrical about a symmetry axis extending along the column direction; and the two adjacent circuit groups are symmetrical about a symmetry axis extending along the column direction.

[0060] In an exemplary embodiment of the present disclosure, the first signal line and the third signal line are alternately distributed along the column direction; the second signal line and the fourth signal line are alternately distributed along the row direction;

[0061] The second signal lines and the circuit groups are alternately distributed along the row direction; the second signal lines are simultaneously connected to the first electrodes of the first reset transistors of the pixel circuits adjacent thereto;

[0062] A fourth signal line is provided between the two columns of pixel circuits in the same circuit group; the fourth signal line is simultaneously connected to the first electrodes of the second reset transistors of the two adjacent columns of pixel circuits.

[0063] In an exemplary embodiment of the present disclosure, one first signal line overlaps with an active portion of each of the first reset transistors in a row of the pixel circuits.

[0064] In an exemplary embodiment of the present disclosure, the active portion of the first reset transistor includes two channel portions and a connecting doped portion connecting the two channel portions;

[0065] The first signal line includes a line body extending along the row direction and a plurality of overlapping portions distributed along the row direction, wherein the overlapping portions are connected to the line body and extend along the column direction;

[0066] Each overlapping portion of a first signal line overlaps with at least one channel portion of the active portion of each first reset transistor in a row of pixel circuits and the connecting doped portion; the line body of a first signal line overlaps with at least one channel portion of the active portion of each first reset transistor in a row of pixel circuits.

[0067] In an exemplary embodiment of the present disclosure, the second plates of the pixel circuits in the same column are connected to the same power line;

[0068] In any row of the pixel circuits, the second plates of the storage capacitors of two adjacent pixel circuits belonging to different circuit groups are connected.

[0069] In an exemplary embodiment of the present disclosure, one power line is connected to a column of pixel circuits, and the power line and the active portion of the driving transistor, the active portion of the compensation transistor, and the storage capacitor of the column of pixel circuits connected thereto overlap.

[0070] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0072] FIG1 is a schematic diagram of a display area and a peripheral area of ​​a display panel according to an embodiment of the present disclosure.

[0073] FIG2 is a cross-sectional schematic diagram of an embodiment of a display panel disclosed herein.

[0074] FIG3 is a schematic diagram of a first embodiment of a pixel circuit according to the present disclosure.

[0075] FIG4 is a schematic diagram of a second embodiment of a pixel circuit according to the present disclosure.

[0076] FIG5 is a schematic diagram of a third embodiment of a pixel circuit according to the present disclosure.

[0077] FIG6 is a schematic diagram of a fourth embodiment of a pixel circuit according to the present disclosure.

[0078] FIG. 7 is a timing diagram of an embodiment of a driving method for a pixel circuit disclosed herein.

[0079] FIG8 is a timing diagram of another embodiment of the driving method of the pixel circuit disclosed herein.

[0080] FIG9 is a timing diagram of another embodiment of the driving method of the pixel circuit disclosed herein.

[0081] FIG. 10 is a partial top view of an embodiment of a display panel according to the present disclosure.

[0082] FIG11 is a partial top view of a light shielding layer and a first semiconductor layer in one embodiment of a display panel disclosed herein.

[0083] FIG12 is a partial top view of the first semiconductor layer and the first gate layer in one embodiment of the display panel disclosed herein.

[0084] FIG13 is a partial top view of the first semiconductor layer to the second semiconductor layer in one embodiment of the display panel disclosed herein.

[0085] FIG14 is a partial top view of the first semiconductor layer to the third gate layer in one embodiment of the display panel disclosed herein.

[0086] FIG15 is a partial top view of the first semiconductor layer to the first source and drain layer in one embodiment of the display panel disclosed herein.

[0087] 16 to 23 are partial top views of each film layer in an embodiment of the display panel disclosed herein.

[0088] FIG24 is a partial top view of the light shielding layer and the first source and drain layer in one embodiment of the display panel disclosed herein.

[0089] FIG25 is a partial top view of the first semiconductor layer to the first source and drain layer in another embodiment of the display panel disclosed herein.

[0090] FIG26 is a partial top view of the first semiconductor layer to the first source and drain layer in another embodiment of the display panel disclosed herein.

[0091] FIG27 is a partial top view of the first semiconductor layer to the first source and drain layer in another embodiment of the display panel disclosed herein.

[0092] FIG28 is a partial top view of the light shielding layer and the first source and drain layer in one embodiment of the display panel disclosed herein.

[0093] FIG29 is a partial top view of another embodiment of the display panel disclosed herein.

[0094] FIG30 is a partial top view of the first source and drain layer in FIG28.

[0095] FIG31 is a partial top view of the second source / drain layer in FIG29 . DETAILED DESCRIPTION

[0096] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0097] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0098] The row direction X and column direction Y herein are merely two intersecting directions; they can also be perpendicular to each other. In the drawings of this disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limiting. If the display panel is rotated, the actual orientations of the row direction X and column direction Y may change.

[0099] In this context, "overlapping" of feature A and feature B means that the orthographic projection of feature A on the substrate at least partially overlaps with the orthographic projection of feature B on the substrate. Alternatively, the orthographic projections of feature A and feature B on a plane parallel to the substrate may at least partially overlap.

[0100] As shown in FIG1 , the present disclosure further provides a display panel, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA, or a discontinuous area surrounding the display area AA.

[0101] As shown in Figure 2, the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. The light-emitting devices LD are distributed along the row direction X and the column direction Y. The driving circuit in the driving backplane BP can drive the light-emitting devices LD to emit light to display images.

[0102] As shown in Figures 1 and 2, the light-emitting device LD can be located in the display area AA. It can be an OLED (organic light-emitting diode) using organic light-emitting materials; it can also be an LED (light-emitting diode) using inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also be a device such as QLED (quantum dot diode). There is no special limitation on the specific structure of the display panel here, as long as it can display images.

[0103] As shown in Figure 2, using an OLED as an example, the light-emitting device LD may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked sequentially in a direction away from the driving backplane BP. By applying a first power signal VDD to the first electrode ANO and a second power signal VSS to the second electrode CAT, the light-emitting layer EL is excited to emit light. The specific principles are not detailed here. Furthermore, to define the range of the light-emitting device LD, a pixel definition layer PDL may be provided on the driving backplane BP. The pixel definition layer PDL may have openings exposing each first electrode ANO, thereby defining the range of the light-emitting device LD through each opening.

[0104] The driving circuit may include pixel circuits located in the display area AA and peripheral circuits located in the peripheral area WA. The pixel circuits may be distributed along the row direction X and the column direction Y. One pixel circuit may be connected to the first electrode of one light-emitting device LD, and a row of pixel circuits may be connected to the first electrode of each light-emitting device in the row. Of course, the same pixel circuit may be connected to the first electrodes of multiple light-emitting devices LD.

[0105] The peripheral circuit can be connected to the light-emitting device LD through the pixel circuit and apply a first power signal VDD to the first electrode ANO of the light-emitting device LD. The peripheral circuit may also include a gate drive circuit and a light-emitting drive circuit for scanning the pixel circuit. Simultaneously, the peripheral circuit may also be connected to the second electrode CAT of the light-emitting device LD and apply a second power signal VSS to the second electrode CAT. The pixel circuit can control the current passing through the light-emitting device LD, thereby controlling the brightness of the light-emitting device LD.

[0106] Taking a pixel circuit as an example, as shown in FIG3 to FIG6 , as shown in FIG1 , the pixel circuit may include a driving transistor T3 , a compensation circuit 2 , a writing circuit 4 , a first reset circuit 1 and a second reset circuit 7 , wherein:

[0107] The first electrode of the driving transistor T3 can receive the first power supply signal VDD, and the second electrode is connected to the light emitting device through the first light emitting control circuit 5;

[0108] One of the first electrode and the second electrode of the driving transistor T3 is connected to its gate via the compensation circuit 2 , and the other receives the data signal DA via the writing circuit 4 .

[0109] The first reset circuit 1 is connected to one of the first and second electrodes of the driving transistor T3 and receives a first reset signal Vinit. The second reset circuit 7 is connected to one of the first and second electrodes of the driving transistor T3 and receives a second reset signal Vref. The first reset signal Vinit and the second reset signal Vref have opposite polarities.

[0110] In the pixel circuit of the disclosed embodiment, a second reset signal Vref is input to at least one of the first and second electrodes of the driving transistor T3 via a second reset circuit 7. This increases the bias voltage applied to the driving transistor T3, improving hysteresis and maintaining image brightness during high- and low-frequency switching. This reduces the risk of screen flicker and enhances the display quality of the display panel. Simultaneously, a first reset signal Vinit is input to the gate of the driving transistor T3 via the first reset circuit 1, eliminating the influence of the data from the previous frame.

[0111] As shown in FIG3 , in some embodiments of the present disclosure, the pixel circuit further includes a tank circuit 3 , a first light emitting control circuit 5 and a second light emitting control circuit 6 ;

[0112] A first electrode of the driving transistor T3 can receive a first power supply signal VDD via a first light-emitting control circuit 5, and a second electrode thereof is connected to the light-emitting device via a second light-emitting control circuit 6. The energy storage circuit 3 can be connected to the gate of the driving transistor T3 and can receive the first power supply signal VDD for continuously controlling the voltage of the driving transistor T3.

[0113] The write circuit 4 can be turned on in response to the first scan signal G1, the compensation circuit 2 can be turned on in response to the second scan signal G2, the first reset circuit 1 can be turned on in response to the first reset control signal Re1, the second reset circuit 7 can be turned on in response to the second reset control signal Re2, the first light-emitting control circuit 5 can be turned on in response to the first light-emitting control signal EM1, and the second light-emitting control circuit 6 can be turned on in response to the second light-emitting control signal EM2.

[0114] Furthermore, each pixel circuit may include multiple transistors and capacitors, and the active parts of each transistor may be arranged in the same layer, and may all be made of semiconductor materials such as polysilicon; alternatively, the active parts of some transistors may be in different layers from the active parts of other transistors, for example, the active parts of all transistors may be polysilicon, and the active parts of some transistors may be metal oxides such as IGZO.

[0115] Each transistor can include a gate, a first electrode, and a second electrode. The first electrode and the second electrode can be turned on and off by controlling the voltage of the gate. The first electrode can be a source electrode, and the second electrode can be a drain electrode. Of course, the first electrode can also be a drain electrode and the second electrode can also be a source electrode. Specifically, if the signal is input from the first electrode, the first electrode is the source electrode and the second electrode is the drain electrode. If the signal is input from the second electrode electrode, the second electrode is the source electrode and the first electrode is the drain electrode. In other words, if both the first electrode and the second electrode of the same transistor require input signals, the source and drain electrodes will switch depending on the input signal.

[0116] The transistor can be a P-type transistor or an N-type transistor. For example, for a P-type transistor, when the gate receives a high level, the first and second terminals are turned off; when the gate receives a low level, the first and second terminals are turned on. For an N-type transistor, when the gate receives a high level, the first and second terminals are turned on; when the gate receives a low level, the first and second terminals are turned off.

[0117] As shown in Figures 3-6 and 10-23, the write circuit 4 includes a write transistor T4, which can be turned on and off by a first scan signal G1 transmitted to the gate of the write transistor T4. The compensation circuit 2 includes a compensation transistor T2, which can be turned on and off by a second scan signal G2 transmitted to the gate of the compensation transistor T2.

[0118] The first reset circuit 1 includes a first reset transistor T1, and the first reset transistor T1 can be controlled to be turned on and off by a first reset control signal Re1 transmitted to the gate of the first reset transistor T1. The second reset circuit 7 includes a second reset transistor T7, and the second reset transistor T7 can be controlled to be turned on and off by a second reset control signal Re2 transmitted to the gate of the second reset transistor T7.

[0119] The first emission control circuit 5 includes a first emission control transistor T5, and the first emission control transistor T5 is controlled to be turned on and off by a first emission control signal EM1 transmitted to the gate of the first emission control transistor T5. The second emission control circuit 6 includes a second emission control transistor T6, and the second emission control transistor T6 is controlled to be turned on and off by a second emission control signal EM2 transmitted to the gate of the second emission control transistor T6.

[0120] The energy storage circuit 3 includes a storage capacitor Cst, a first plate Cst1 of which can be connected to the gate of the driving transistor T3, and a second plate Cst2 of which can be used to receive the first power signal VDD.

[0121] The gate of the first light-emitting control transistor T5 is connected to the first light-emitting control line EML1 that transmits the first light-emitting control signal EM1, the first electrode can be connected to a power line VDL for receiving the first power signal VDD, and the second electrode is connected to the first electrode of the driving transistor T3 at the N2 node.

[0122] The second electrode of the driving transistor T3 and the first electrode of the second emission control transistor T6 are connected to the N3 node. The second electrode of the second emission control transistor T6 is connected to the first electrode of the light-emitting device. The gate of the second emission control transistor T6 can be connected to the second emission control line EML2 that transmits the second emission control signal EM2. The first plate Cst1 of the storage capacitor Cst is connected to the gate of the driving transistor T3 at the N1 node, and the second plate Cst2 is connected to the power line VDL that transmits the first power signal VDD. The first electrode of the write transistor T4 can be connected to the data line DAL that transmits the data signal DA, and the second electrode can be connected to the first electrode or the second electrode of the driving transistor T3. The gate of the compensation transistor T2 can be connected to the second scan line GL2 that transmits the second scan signal G2. The first electrode can be connected to the N2 node or the N3 node, and the second electrode is connected to the N1 node.

[0123] The first reset transistor T1 has a gate connected to a first reset control line REL1 that transmits a first reset control signal Re1, a first electrode connected to a first reset signal line that transmits a first reset signal Vinit, and a second electrode connected to the N2 node or the N3 node. The second reset transistor T7 has a gate connected to a second reset control line REL2 that transmits a second reset control signal Re2, a first electrode connected to a second reset signal line that transmits a second reset signal Vref, and a second electrode connected to the N2 node or the N3 node.

[0124] Different schemes of the pixel circuit are exemplarily described below according to different connection positions of the write transistor T4, the compensation transistor T2, the first reset transistor T1 and the second reset transistor T7:

[0125] First embodiment

[0126] As shown in Figure 3, the first reset circuit 1 and the compensation circuit 2 are both connected to the second electrode of the driving transistor T3, and the second reset circuit 7 and the write circuit 4 are both connected to the first electrode of the driving transistor T3. For example, the second electrode of the first reset transistor T1, the first electrode of the compensation transistor T2, the second electrode of the driving transistor T3, and the first electrode of the second emission control transistor T6 are connected to the N3 node; the second electrode of the compensation transistor T2, the first plate Cst1 of the storage capacitor Cst, and the gate of the driving transistor T3 are connected to the N1 node; the second electrode of the second reset transistor T7, the second electrode of the write transistor T4, the second electrode of the first emission control transistor T5, and the first electrode of the driving transistor T3 are connected to the N2 node.

[0127] Second embodiment

[0128] As shown in Figure 4, the first reset circuit 1, the second reset circuit 7, and the compensation circuit 2 are connected to the second electrode of the driving transistor T3, and the write circuit 4 is connected to the first electrode of the driving transistor T3. For example, the second electrode of the first reset transistor T1, the second electrode of the second reset transistor T7, the first electrode of the compensation transistor T2, the first electrode of the second emission control transistor T6, and the second electrode of the driving transistor T3 are connected to the N3 node; the second electrode of the write transistor T4, the first electrode of the driving transistor T3, and the first electrode of the first emission control transistor T5 are connected to the N2 node; the second electrode of the compensation transistor T2, the first plate Cst1 of the storage capacitor Cst, and the gate of the driving transistor T3 are connected to the N1 node.

[0129] Third embodiment

[0130] As shown in Figure 5, the compensation circuit 2 and the first reset circuit 1 are connected to the first electrode of the driving transistor T3, and the second reset circuit 7 and the write circuit 4 are connected to the second electrode of the driving transistor T3. For example, the second electrode of the first reset circuit 1, the first electrode of the compensation circuit 2, the second electrode of the first emission control transistor T5, and the first electrode of the driving transistor T3 are connected to the N2 node; the second electrode of the compensation circuit 2, the gate of the driving transistor T3, and the first plate Cst1 of the storage capacitor Cst are connected to the N1 node; the second electrode of the second reset circuit 7, the second electrode of the write transistor T4, the second electrode of the driving transistor T3, and the first electrode of the second emission control transistor T6 are connected to the N3 node.

[0131] Fourth embodiment

[0132] As shown in Figure 6, the first reset circuit 1, the second reset circuit 7, and the compensation circuit 2 are connected to the first electrode of the driving transistor T3, and the write circuit 4 is connected to the second electrode of the driving transistor T3. For example, the second electrode of the first reset transistor T1, the second electrode of the second reset transistor T7, the first electrode of the compensation transistor T2, the second electrode of the first emission control transistor T5, and the first electrode of the driving transistor T3 are connected to the N2 node; the second electrode of the write transistor T4, the second electrode of the driving transistor T3, and the first electrode of the second emission control transistor T6 are connected to the N3 node; the second electrode of the compensation transistor T2, the gate of the driving transistor T3, and the first plate Cst1 of the storage capacitor Cst are connected to the N1 node.

[0133] The principle of the above pixel circuit is described below in conjunction with the driving method of the pixel circuit disclosed in the present invention:

[0134] When displaying an image, the display panel can divide a display frame into a write frame and at least one hold frame after the write frame. The write frame duration can be the same at different refresh rates. By adjusting the hold frame duration, the actual display effect can be adjusted to meet the corresponding refresh rate, which is particularly suitable for situations where frequency reduction is required. The write frame can be reset, write the data signal DA, and emit light. The hold frame does not write the data signal DA or emit light, and only performs the reset process. In other words, the hold frame is used to achieve frequency reduction through interpolation.

[0135] Taking a display frame including a writing frame and a holding frame, and the compensation transistor T2 being an N-type transistor and the other transistors being P-type transistors as an example, the driving method of the pixel circuit of the above embodiment is described:

[0136] As shown in FIG7 to FIG9, the writing frame may include the first to third reset stages (t1, t2, t4), the writing stage t3 and the light-emitting stage t5, and the holding frame may include the first to third reset stages (t6-t8) but does not include the light-emitting stage. Therefore, no light may be emitted in the holding frame. Specifically:

[0137] In the first reset phase t1 of the write frame, the write circuit 4 , the first reset circuit 1 , the first light-emitting control circuit 5 and the second light-emitting control circuit 6 can be turned off; the second reset circuit 7 is turned on, and the second reset signal Vref is input through the second reset circuit 7 .

[0138] For example, the first scan signal G1, the first reset control signal Re1, the first emission control signal EM1, and the second emission control signal EM2 are all high, turning off the write transistor T4, the first reset control transistor, the first emission control transistor T5, and the second emission control transistor T6. The second reset control signal Re2 is low, turning on the second reset control transistor. The second reset signal Vref is input through the second reset transistor T7 to refresh the N2 node. The second reset signal Vref can be a high-level signal, thereby adding a large bias voltage to the drive transistor T3 to improve hysteresis, allowing the screen brightness to be maintained during high-low frequency switching, reducing the risk of screen flickering, and improving the display quality of the display panel. At the same time, when the second reset signal Vref is high, the gate-source (gate and first electrode) voltage difference of the drive transistor T3 can turn on the drive transistor T3, refreshing the N2 node and the N3 node at the same time.

[0139] In the second reset stage t2 of the write frame, the write circuit 4, the second reset circuit 7, the first light-emitting control circuit 5 and the second light-emitting control circuit 6 can be turned off; the compensation circuit 2 and the first reset circuit 1 are turned on, and the first reset signal Vinit is input through the first reset circuit 1; the first reset signal Vinit and the second reset signal Vref have opposite polarities.

[0140] For example, the first scan signal G1, the second reset control signal Re2, the first emission control signal EM1, and the second emission control signal EM2 are all high, and the write transistor T4, the second reset transistor T7, the first emission control transistor T5, and the second emission control transistor T6 are all turned off. The second scan signal G2 and the first reset control signal Re1 are both low, and the compensation transistor T2 and the first reset transistor T1 are turned on. The first reset signal Vinit is input through the first reset transistor T1 to reset the N1 and N3 nodes, eliminating residual voltage and avoiding the influence of the previous frame image. The first reset signal Vinit and the second reset signal Vref have opposite polarity. For example, the first reset signal Vinit is a low-level signal, and the second reset signal Vref is a high-level signal.

[0141] In the writing phase t3 of the writing frame, the first reset circuit 1, the second reset circuit 7, the first light-emitting control circuit 5 and the second light-emitting control circuit 6 are turned off; the writing circuit 4 and the compensation circuit 2 are turned on, and the data signal DA is input through the writing circuit 4.

[0142] For example, when the first reset control signal Re1, the second reset control signal Re2, the first emission control signal EM1, and the second emission control signal EM2 are high, the first reset transistor T1, the second reset transistor T7, the first emission control transistor T5, and the second emission control transistor T6 are turned off. When the first scan signal G1 and the second scan signal G2 are low, the write transistor T4 and the compensation transistor T2 are turned on. At this time, the data signal DA can be written to the N1 node through the write transistor T4 and the compensation transistor T2 until the voltage at the N1 node reaches Vdata + Vth, so that the gate-source voltage difference Vgs of the drive transistor T3 equals Vth. At this time, the drive transistor T3 is turned off. Vth is the threshold voltage of the drive transistor T3, and Vdata is the voltage of the data signal. Thus, the threshold voltage is written to the N1 node and stored in the storage capacitor Cst.

[0143] In the third reset stage t4 of the write frame, the compensation circuit 2, the write circuit 4, the second reset circuit 7 and the first light-emitting control circuit 5 are turned off; the first reset circuit 1 and the second light-emitting control circuit 6 are turned on, and the first reset signal Vinit is input through the first reset circuit 1.

[0144] For example, the first scanning signal G1, the second scanning signal G2, the second reset control signal Re2 and the first light-emitting control signal EM1 are at a high level, the compensation transistor T2, the write transistor T4, the second reset transistor T7 and the first light-emitting control transistor T5 are turned off; the first reset control signal Re1 and the second light-emitting control signal EM2 are at a low level, the first reset transistor T1 and the second light-emitting control transistor T6 are turned on; the first reset signal Vinit is input to the N4 node through the first reset transistor T1 and the second light-emitting control transistor T6 to reset the first electrode of the light-emitting device and eliminate the influence of the previous frame image.

[0145] In the light emitting phase t5 of the writing frame, the compensation circuit 2, the writing circuit 4, the first reset circuit 1 and the second reset circuit 7 are turned off; and the first light emitting control circuit 5 and the second light emitting control circuit 6 are turned on.

[0146] For example, the first scanning signal G1, the second scanning signal G2, the second reset control signal Re2 and the second reset control signal Re2 are at a high level, the compensation transistor T2, the write transistor T4, the first reset transistor T1 and the second reset transistor T7 are turned off; the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level, so that the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on.

[0147] Under the action of the storage capacitor Cst, the driving transistor T3 outputs current, and the output current satisfies the following formula: I=(μWCox / 2L)(Vgs-Vth) 2 ;

[0148] I is the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0149] According to the above formula for the output current of the driving transistor T3, the gate voltage Vdata+Vth and the source voltage VDD of the driving transistor T3 in the pixel circuit of the present disclosure are substituted into the above formula to obtain: the output current of the driving transistor T3 I=(μWCox / 2L)(Vdata+Vth-VDD-Vth) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3 and is only related to Vdata, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled solely by the voltage of the data signal DA, thereby controlling the brightness of the light-emitting device.

[0150] As shown in Figures 7 to 9, in the first reset phase t6 of the holding frame, the write circuit 4, the first reset circuit 1, the first light-emitting control circuit 5 and the second light-emitting control circuit 6 are turned off; the second reset circuit 7 is turned on, and the second reset signal Vref is input through the second reset circuit 7.

[0151] The actions performed in the first reset phase of the hold frame can be the same as those performed in the first reset phase of the write frame and will not be described in detail here. In the first reset phase, the N2 node can be refreshed, and the second reset signal Vref can be a high-level signal, thereby adding a large bias voltage to the drive transistor T3 to improve hysteresis, so that the brightness of the screen can be maintained when switching between high and low frequencies. At the same time, when the second reset signal Vref is high, the gate-source (gate and first pole) voltage difference of the drive transistor T3 can turn on the drive transistor T3, refreshing the N2 node while refreshing the N3 node.

[0152] In the second reset phase t7 of the holding frame, the write circuit 4, the second reset circuit 7, the first light-emitting control circuit 5 and the second light-emitting control circuit 6 are turned off; the compensation circuit 2 and the first reset circuit 1 are turned on, and the first reset signal Vinit is input through the first reset circuit 1.

[0153] The operations performed in the second reset phase of the hold frame are the same as those performed in the second reset phase of the write frame and are not described in detail here. The first reset signal Vinit is input through the first reset transistor T1 to reset the N1 and N3 nodes, eliminating residual voltage and avoiding the influence of the previous frame image.

[0154] In the third reset phase t8 of the hold frame, the compensation circuit 2, the write circuit 4, the second reset circuit 7 and the first light-emitting control circuit 5 are turned off; the first reset circuit 1 and the second light-emitting control circuit 6 are turned on, and the first reset signal Vinit is input through the first reset circuit 1.

[0155] The actions performed in the third reset phase of the hold frame are the same as those performed in the third reset phase of the write frame and are not described in detail here. A first reset signal Vinit is input to the N4 node via the first reset transistor T1 and the second light-emission control transistor T6, resetting the first electrode of the light-emitting device and eliminating the influence of the previous frame image.

[0156] Furthermore, as shown in Figures 7-9, in some embodiments of the present disclosure, during the first reset phase t1 of the write and hold frames, the compensation circuit 2 can be turned on. For example, the second scan signal G2 is set to a low level, turning on the compensation transistor T2, and refreshing the N1 node using the second reset signal Vref. Since the second reset signal Vref is at a high level, leakage can be prevented and internal defects of the driving transistor T3 can be improved. Of course, during the first reset phase, the compensation circuit 2 can also be turned off.

[0157] Furthermore, as shown in FIG8 , in some embodiments of the present disclosure, in the hold frame, the driving transistor T3 may be refreshed using the data signal DA, and the driving method further includes:

[0158] In the fourth reset phase t9 of the hold frame, the first reset circuit 1, the second reset circuit 7, the first light-emitting control circuit 5 and the second light-emitting control circuit 6 are turned off; the write circuit 4 and the compensation circuit 2 are turned on, and the data signal DA is input through the write circuit 4.

[0159] For example, the first reset control signal Re1, the second reset control signal Re2, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are all high levels, the first reset transistor T1, the second reset transistor T7, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off; the first scan signal G1 and the second scan signal G2 are low levels, the write transistor T4 and the compensation transistor T2 are turned on, the data signal DA is input through the write circuit 4, and the driving transistor T3 is refreshed by the data signal DA, that is, the N2, N3 and N1 nodes are refreshed to improve hysteresis.

[0160] The fourth reset stage may be located before the third reset stage and after the second reset stage, and the operation of the fourth reset stage may be the same as that of the writing stage. However, since the compensation frame does not have a light-emitting stage, the frame is kept non-luminous.

[0161] Furthermore, as shown in FIG9 , in some embodiments, during the write frame, the third reset phase can be positioned after the write phase, and between the light-emitting phases, the duration between the write phase and the third reset phase can be longer than the duration of the write phase, thereby extending the threshold voltage write time. Accordingly, during the hold frame, the duration between the fourth reset phase and the third reset phase can be the same as the duration between the write phase and the third reset phase, and shorter than the duration of the fourth reset phase. Of course, in some embodiments, the duration between the write phase and the third reset phase can also be shorter than the duration of the write phase.

[0162] It can be concluded from the above driving method that, for the pixel circuits in the same row, the first light-emitting control signal EM1 and the second light-emitting signal received therefrom have a timing difference, and are not synchronization signals. Therefore, the difference between the first light-emitting control signal EM1 and the second light-emitting signal of the pixel circuits in different rows can be utilized to multiplex the first light-emitting control signal EM1 and the second light-emitting signal, without having to independently provide the first light-emitting control signal EM1 and the second light-emitting signal for each row of pixel circuits.

[0163] In some embodiments of the present disclosure, the first light-emitting control signal EM1 input to the pixel circuits in the nth row can be multiplexed into the second light-emitting control signal EM2 input to the pixel circuits in the (n+i)th row. That is, the first light-emitting control signal EM1 input to the pixel circuits in the nth row also serves as the second light-emitting control signal EM2 input to the pixel circuits in the (n+i)th row, where n and i are positive integers, and i can be 1, 2, etc. This simplifies the structure of the light-emitting drive circuit, reduces space occupation, improves operating efficiency, and reduces inter-row brightness differences (the brightness of light-emitting devices corresponding to pixel circuits in different rows).

[0164] In some embodiments of the present disclosure, the first scan signal G1 input to the pixel circuits in the nth row can be multiplexed as the second reset control signal Re2 input to the pixel circuits in the (n+j)th row. That is, the first scan signal G1 for the pixel circuits in the nth row also serves as the second reset control signal Re2 for the pixel circuits in the (n+i)th row, where n and j are positive integers, and j can be 1, 2, etc., and j can be equal to i. This simplifies the structure of the gate drive circuit, reduces space usage, improves operating efficiency, and reduces brightness differences between rows.

[0165] It should be noted that although the steps of the driving method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0166] The present disclosure also provides a display panel, which may include the pixel circuit of any of the above embodiments. The specific structure and beneficial effects of the pixel circuit can be referred to the above embodiments and will not be described in detail here. The display panel will be described in detail below in conjunction with the pixel circuit:

[0167] As shown in Figure 2 , the driving backplane BP may include a substrate SU and a circuit layer CL. The substrate SUSU may be made of a flexible, transparent material such as polyimide, or a rigid, transparent material such as glass. The circuit layer CL is disposed on one side of the substrate SU and includes pixel circuits. Light-emitting devices may be disposed on the side of the circuit layer CL away from the substrate SU, with each light-emitting device connected to the second electrode of a second light-emitting control transistor T6 in each pixel circuit.

[0168] The circuit layer CL is described in detail below:

[0169] As shown in FIG2 , the compensation transistor T2 of the pixel circuit is an N-type transistor, and the other transistors are P-type transistors. The circuit layer CL includes a light shielding layer BSM, a first semiconductor layer SE1, a first gate layer GA1, a second gate layer GA2, a second semiconductor layer IG, a third gate layer GA3, a first source and drain layer SD1, and a second source and drain layer SD2, which are sequentially distributed in a direction away from the substrate SU.

[0170] The light shielding layer BSM is provided on one side of the substrate SU and can be made of metal or other conductive and light shielding materials. The light shielding layer BSM can at least overlap with the driving transistor T3 to prevent the bottom signal and light from affecting the driving transistor T3.

[0171] As shown in Figures 10, 11, and 16, in some embodiments of the present disclosure, the light shielding layer BSM includes a plurality of light shielding units BSU distributed in an array, each light shielding unit BSU overlapping the active portion of each driving transistor T3. Light shielding units BSU in the same row are connected, and light shielding units BSU in the same column can be connected via a connecting line BSL, so that the light shielding layer BSM is connected as a whole. At the same time, the light shielding layer BSM can be connected to the power line VDL, or it can also be connected to other constant DC signals. On the one hand, it reduces the impedance of signal transmission. On the other hand, it can also provide signal shielding through the DC signal. Taking the connection of the light shielding layer BSM to the power line VDL as an example, a first power bus and a second power bus can be provided in the peripheral area WA. Each power line VDL can be connected to the first power bus, transmitting the first power signal VDD through the first power bus. The second power bus can be connected to the second electrode of the light-emitting device, transmitting the second power signal VSS through the second power bus. At the same time, the connecting line BSL of the light shielding layer BSM can be connected to the first power bus in the peripheral area WA. Of course, the light shielding unit BSU or the connecting line BSL may also be connected to the power line VDL in the display area AA.

[0172] As shown in Figures 10 to 12 and 17, the first semiconductor layer SE1 is arranged on a side of the light-shielding layer BSM away from the light-shielding layer BSM, and the material of the first semiconductor layer SE1 may be polycrystalline silicon, which may include an active portion of a driving transistor T3, a write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1 and a second reset transistor T7.

[0173] In some embodiments of the present disclosure, the first semiconductor layer SE1 may include first to fifth semiconductor portions (P1-P5), the active portion of the first reset transistor T1 is located in the first semiconductor portion P1; the active portions of the write transistor T4 and the first light-emitting control transistor T5 are located in the second semiconductor portion P2; the active portion of the drive transistor T3 is located in the third semiconductor portion P3, and the third semiconductor portion P3 may be connected to the second semiconductor portion P2; the active portion of the second light-emitting control transistor T6 is located in the fourth semiconductor portion P4; and the active portion of the second reset transistor T7 is located in the fifth semiconductor portion P5.

[0174] As shown in Figures 10, 12 and 18, the first gate layer GA1 is arranged on the side of the first semiconductor layer SE1 away from the substrate SU, and overlaps with the first semiconductor layer SE1; the first gate layer GA1 may include the first electrode Cst1 of the storage capacitor Cst, the gates of the driving transistor T3, the writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1 and the second reset transistor T7.

[0175] In some embodiments of the present disclosure, the first gate layer GA1 may include a first plate Cst1 of a storage capacitor Cst and a first scan line GL1, a first light emitting control line EML1, a second light emitting control line EML2, a first reset control line REL1, and a second reset control line REL2 extending along a row direction X, wherein:

[0176] The first electrode Cst1 overlaps with the third semiconductor portion, and the overlapping area is the gate of the driving transistor T3; the first scan line GL1 overlaps with the second semiconductor portion, and the overlapping area is the gate of the write transistor T4; the first light-emitting control line EML1 overlaps with the second semiconductor portion, and the overlapping area is the gate of the first light-emitting control transistor T5; the second light-emitting control line EML2 overlaps with the fourth semiconductor layer, and the overlapping area is the gate of the second light-emitting control transistor T6; the first reset control line REL1 overlaps with the first semiconductor portion, and the overlapping area is the gate of the first reset transistor T1; the second reset control line REL2 overlaps with the fifth semiconductor portion P5, and the overlapping area is the gate of the second reset transistor T7.

[0177] As shown in FIG10 , FIG13 and FIG19 , the second gate layer GA2 is provided on a side of the first gate layer GA1 away from the substrate SU and includes a second plate Cst2 of the storage capacitor Cst, which overlaps the first plate Cst1 .

[0178] As shown in Figures 10, 13 and 20, the second semiconductor layer IG may be provided on the side of the second gate layer GA2 away from the substrate SU and include a sixth semiconductor portion P6, which is the active portion of the compensation transistor T2. The material of the second semiconductor layer IG may be a metal oxide such as IGZO.

[0179] As shown in Figures 10, 14, and 21, the third gate layer GA3 can be disposed on a side of the second semiconductor layer IG away from the substrate SU and overlap the second semiconductor layer IG. The third gate layer GA3 may include the gate of the compensation transistor T2 and the second scan line GL2. The region where the second scan line GL2 overlaps the second semiconductor layer IG serves as the gate of the compensation transistor T2.

[0180] In addition, in some embodiments, as shown in Figures 13 and 19, the second gate layer GA2 may further include an auxiliary scan line GLs, which may extend along the row direction X and overlap with the second semiconductor layer IG. The overlapping region may serve as the gate of the compensation transistor T2. That is, the compensation transistor T2 includes a top gate (the second scan line GL2) and a bottom gate (the auxiliary scan line GLs). The second scan lines GL2 are arranged in a one-to-one overlapping manner, and the two can be connected in the peripheral area WA, thereby simultaneously transmitting the second scan signal G2 and improving signal stability. At the same time, the auxiliary scan line GLs can also shield the active portion of the compensation transistor T2 to prevent the influence of the signal and light below.

[0181] As shown in FIG. 10 , FIG. 15 and FIG. 22 , the first source-drain layer SD1 may be disposed on a side of the third gate layer GA3 away from the substrate SU, and may connect part of the transistors and the storage capacitor Cst.

[0182] In some embodiments of the present disclosure, the first source-drain layer SD1 may include first to sixth connection portions (S1-S6). The first connection portion S1 may be connected to the second electrode of the second reset transistor T7, the second electrode of the write transistor T4, and the second electrode of the first emission control transistor T5 via a contact hole. The second connection portion S2 may be connected to the second electrode of the compensation transistor T2 and the first plate Cst1 of the storage capacitor Cst (the gate of the drive transistor T3) via a contact hole. To facilitate connection, a through-hole for the contact hole to pass through may be provided in the second plate Cst2. The third connection portion S3 may be connected to the second electrode of the first reset transistor T1, the first electrode of the second emission control transistor T6, and the second electrode of the drive transistor T3 via a contact hole. The fourth connection portion S4 may be connected to the first electrode and the second plate Cst2 of the first emission control transistor T5 via a contact hole and may be connected to the power line VDL. The fifth connection portion S5 may be connected to the first electrode of the write transistor T4 via a contact hole and may be connected to the data line DAL. The sixth connection portion S6 may be connected to the second electrode of the second emission control transistor T6 via a contact hole and may be connected to the first electrode of the light-emitting device LS.

[0183] As shown in Figures 15 and 22, in some embodiments of the present disclosure, for the first connection portion S1 of a pixel circuit, it can extend along the column direction Y and overlap with at least part of the first scan line GL1, the second scan line GL2 and the second electrode Cst2 of the pixel circuit.

[0184] As shown in Figures 25 and 30, in some embodiments of the present disclosure, the first connection portion S1 of a pixel circuit may extend along the column direction Y and overlap with the first scan line GL1 and the second scan line GL2 of the pixel circuit, while not overlapping with the second electrode Cst2. This prevents parasitic capacitance from being generated between the second electrode Cst2 and the first connection portion S1, thereby reducing the parasitic capacitance on the first connection portion S1 and achieving more accurate reset. For example, the first connection portion S1 may include a first segment S11 and a second segment S12. The first segment S11 may extend along the row direction X and overlap with the first scan line GL1. One end of the first segment S11 is connected to the second electrode of the second reset transistor T7. The second segment S12 may extend along the column direction Y and connect the first segment S11, the second electrode of the write transistor T4, and the second electrode of the first emission control transistor T5. The second segment S12 may overlap with the second semiconductor portion P2 but not overlap with the second electrode Cst2.

[0185] As shown in Figures 10 and 23, the second source-drain layer SD2 is disposed on a side of the first source-drain layer SD1 away from the substrate SU and includes a power line VDL and a data line DAL extending along the column direction Y. The power line VDL can be connected to the fourth connection portion S4 via a contact hole, thereby connecting to the first electrode and second plate Cst2 of the first light-emission control transistor T5 to transmit a first power signal VDD. The data line DAL can be connected to the fifth connection portion S5 via a contact hole, thereby connecting to the first electrode of the write transistor T4 to transmit a data signal DA. Furthermore, the second source-drain layer SD2 may further include an adapter portion AP, which can be connected to the sixth connection portion S6 via a contact hole. The first electrode of the light-emitting device can be connected to the sixth connection portion via the adapter portion AP.

[0186] The following describes the scheme of inputting the first reset signal Vinit and the second reset signal Vref:

[0187] Routes for transmitting the first reset signal Vinit and the second reset signal Vref may be set in any one or more layers from the first gate layer GA1 to the second source / drain layer SD2 , and connected to the first electrode of the first reset transistor T1 and the first electrode of the second reset transistor T7 .

[0188] In order to reduce impedance and increase refresh speed, a mesh structure formed by wirings on different layers may be used to transmit the first reset signal Vinit.

[0189] In some embodiments of the present disclosure, the circuit layer CL may include a first reset signal network that may be connected to the first electrode of the first reset transistor T1 for transmitting a first reset signal Vinit. The first reset signal network may include a first signal line VIL1 and a second signal line VIL2 located on different layers and connected to each other. The first signal line VIL1 may extend in a row direction X, and the second signal line VIL2 may extend in a column direction Y.

[0190] As shown in Figures 14, 15, 21, and 22, for example, a first signal line VIL1 is located in the third gate layer GA3, and a second signal line VIL2 can be located in the first source / drain layer SD1, with the two connected via contact holes. There are multiple first signal lines VIL1 and second signal lines VIL2, with each first signal line VIL1 spaced apart along the column direction Y and each second signal line VIL2 spaced apart along the row direction X. A first signal line VIL1 overlaps with each first semiconductor portion P1 of the active portion of the first reset transistor T1 of a pixel circuit in the same row along the row direction X. A second signal line VIL2 can be provided between two adjacent columns of pixel circuits.

[0191] In some embodiments of the present disclosure, the circuit layer CL may include a second reset signal Vref network, which may be connected to the first electrode of the second reset transistor T7 for transmitting the second reset signal Vref; the second reset signal Vref network includes a third signal line VRL1 and a fourth signal line VRL2 located in different layers and connected; the third signal line VRL1 extends along the row direction X, and the fourth signal line VRL2 extends along the column direction Y.

[0192] As shown in Figures 14, 15, 21, and 22, for example, a third signal line VRL1 is located in the third gate layer GA3, and a fourth signal line VRL2 can be located in the first source / drain layer SD1, with the two connected via a contact hole. Multiple third signal lines VRL1 and fourth signal lines VRL2 are provided, with each third signal line VRL1 spaced apart along the column direction Y, and each fourth signal line VRL2 spaced apart along the row direction X. A third signal line VRL1 overlaps with each fifth semiconductor portion P5 of the active portion of the second reset transistor T7 of a pixel circuit in the same row along the row direction X. A fourth signal line VRL2 can be provided between two adjacent columns of pixel circuits.

[0193] In some embodiments of the present disclosure, each column of pixel circuits may be divided into a plurality of circuit groups distributed along the row direction X, and the same circuit group may include two adjacent columns of pixel circuits.

[0194] Two columns of pixel circuits in the same circuit group may be symmetrical about a symmetry axis extending along the column direction Y. Two adjacent circuit groups may be symmetrical about a symmetry axis extending along the column direction Y. That is, in two adjacent columns of pixel circuits, any two adjacent pixel circuits in the row direction X are symmetrical. Symmetry here means that the patterns from the first semiconductor layer SE1 to the first source and drain layer SD1 are symmetrical about the symmetry axis.

[0195] As shown in Figures 15 and 22, in some embodiments, the second signal line VIL2 and the fourth signal line VRL2 can be alternately distributed along the row direction X. The first reset signal Vinit and the second reset signal Vref are both DC signals, which can shield signal crosstalk between different pixel circuits.

[0196] The second signal line VIL2 is alternately arranged with each circuit group along the row direction X, i.e., one second signal line VIL2 is provided between two adjacent circuit groups. The second signal line VIL2 is also connected to the first electrode of the first reset transistor T1 of the pixel circuit adjacent thereto. For example, the second signal line VIL2 has a first lead portion VIL21 extending in both directions along the row direction X. The first lead portion VIL21 can be connected to the first signal line VIL1 through a contact hole and can be connected to the first electrode of the first reset transistor T1 of the pixel circuits on both sides of the second signal line VIL2.

[0197] A fourth signal line VRL2 is provided between two columns of pixel circuits in the same circuit group. The fourth signal line VRL2 is also connected to the first electrode of the second reset transistor T7 of the pixel circuit adjacent to it. For example, the fourth signal line VRL2 has a second lead portion VRL21 extending in both directions along the row direction X. The second lead portion VRL21 can be connected to the third signal line VRL1 through a contact hole and can also be connected to the first electrode of the second reset transistor T7 of the pixel circuits on both sides of the fourth signal line VRL2.

[0198] As shown in Figures 12 to 14 and 21, in some embodiments of the present disclosure, the active portion of the first reset transistor T1 can be shielded by the first signal line VIL1. For example, a first signal line VIL1 can overlap with the active portion of each first reset transistor T1 of a row of pixel circuits. The shielding effect of the first reset signal Vinit can prevent the upper signal from interfering with the first reset transistor T1, and the first signal line VIL1 can block light to reduce the impact of light on the first reset transistor T1. At the same time, a parasitic capacitance can be formed between the active portion of the first reset transistor T1 and the first signal line VIL1. The parasitic capacitance transmitted by the first signal can stabilize the voltage of the active portion of the first reset transistor T1 to prevent leakage. For example:

[0199] As shown in Figures 12-14 and 17, the active portion of the first reset transistor T1 may include two channel portions CP and a connecting doped portion DP connecting the two channel portions CP. The first reset control line REL1 may overlap both channel portions CP but not the connecting doped portion DP. The region where the first reset control line REL1 overlaps with the channel portions CP serves as the gate of the first reset transistor T1, meaning that the first reset transistor T1 has two gates. The two connected channels can reduce the risk of leakage, preventing leakage in the first reset transistor T1.

[0200] The first signal line VIL1 may include a line body VL1 extending along the row direction X and a plurality of overlapping portions VL2 distributed along the row direction X. Each overlapping portion VL2 is connected to the same side of the line body VL1 and each overlapping portion VL2 extends along the column direction Y.

[0201] Each overlapping portion VL2 of a first signal line VIL1 can overlap at least one channel portion CP and a connecting doped portion DP of each first reset transistor T1 in a row of pixel circuits. The body VL1 of a first signal line VIL1 overlaps at least one channel portion CP of each first reset transistor T1 in a row of pixel circuits. Consequently, the body VL1 and overlapping portion VL2 shield the channel portion CP and the connecting doped portion DP. Furthermore, parasitic capacitance can be formed between the overlapping portion VL2 and the connecting doped portion DP, helping to prevent leakage.

[0202] As shown in FIG26 , in some embodiments of the present disclosure, the fourth signal line VRL2 connecting two adjacent pixel circuits in the same row within a circuit group includes a first extension VRL22 that protrudes toward at least one side along the row direction X. The first extension VRL22 is located between the second electrodes Cst2 of the two columns of pixel circuits. The first extension VRL22 can increase the local line width of the fourth signal line VRL2, thereby reducing resistance. Furthermore, the first extension VRL22 can overlap with the sixth semiconductor portion P6, fully utilizing space and increasing line width. Furthermore, the second lead portion VRL21 can be wider than the third signal line VRL1 and overlap with the third signal line VRL1. The second lead portion VRL21 can also increase the local line width of the fourth signal line VRL2, thereby reducing resistance.

[0203] As shown in FIG. 27 , in some embodiments of the present disclosure, a second signal line VIL2 connecting two adjacent pixel circuits in the same row of two adjacent circuit groups may include a second extension portion VIL22 that protrudes along at least one side along the row direction X. The second extension portion VIL22 may be located between the second plates Cst2 of the storage capacitors Cst of the two pixel circuits, thereby increasing the local line width of the second signal line VIL2 and reducing resistance. Simultaneously, the second signal line VIL2 may include a third extension portion VIL23 that protrudes along at least one side along the row direction X. The third extension portion VIL23 is located between two adjacent overlapping portions VL2 and does not overlap with the overlapping portions VL2. The third extension portion VIL23 overlaps the line body VL1 connected to the pixel circuits in the current row, the second emission control line EML2, and the third signal line VRL1 connected to the pixel circuits in the next row. The first lead portion VIL21 further protrudes outward from the third extension portion VIL23. The third extension portion VIL23 increases the local line width of the second signal line VIL2, thereby reducing resistance.

[0204] In addition, the data line DAL may overlap the second extension portion VIL22 and the third extension portion VIL23 , and the third extension portion VIL23 may shield the data signal from interference by the line body VL1 , the second emission control line EML2 , and the third signal line VRL1 .

[0205] As shown in FIG. 28 and FIG. 30 , the embodiments shown therein are combined with the solutions of FIG. 25 to FIG. 27 described above, which will not be described in detail here.

[0206] As shown in Figure 10, in some embodiments of the present disclosure, the second plate Cst2 of the storage capacitor Cst of the same column pixel circuit can be connected to the same power line VDL. At the same time, in any row of pixel circuits, the second plates Cst2 of two adjacent pixel circuits belonging to different circuit groups can be connected as an integrated structure, while the second plates Cst2 belonging to the same circuit group can be disconnected in the row direction X. Two adjacent power lines VDL can be connected by the interconnected second plates Cst2, which is beneficial to increase the area of ​​the path for transmitting the first power signal VDD and reduce the impedance. Furthermore, the power lines VDL connected to the two pixel circuits of the same circuit group can be connected as an integrated structure along the row direction X, thereby connecting all power lines VDL as a whole.

[0207] As shown in Figures 29 and 31, in some embodiments of the present disclosure, the power lines VDL connecting two pixel circuits of the same circuit group may be spaced apart along the row direction X, that is, the two are disconnected, and the fourth signal line VRL2 connecting two columns of pixel circuits of the same circuit group may be located between the two power lines VDL, and partially overlap or not overlap with the power line VDL, thereby reducing the parasitic capacitance of the fourth signal line VRL2, thereby reducing the voltage drop, and making the reset of the pixel circuits in the same column more uniform.

[0208] As shown in Figure 10, in some embodiments of the present disclosure, a power line VDL overlaps with the active part of the driving transistor T3 and the storage capacitor Cst of a column of pixel circuits connected thereto, blocking the N1 node. At the same time, it can also overlap with the active part of the compensation transistor T2, so that the power line VDL can play a signal shielding role, ensuring that the voltage of the N1 node and the compensation transistor T2 is stable and not prone to leakage, and can block light, reducing the impact of light on the driving transistor T3 and the compensation transistor T2.

[0209] As shown in Figure 24, in some embodiments of the present disclosure, overlapping light shielding units BSU of the driving transistors T3 of the same circuit group can be connected as an integrated structure. The light shielding units BSU of adjacent circuit groups can also be connected via wiring. Furthermore, to improve light transmittance, the connecting lines BSL of the light shielding layer BSM can be overlapped with the second signal line VIL2 and the fourth signal line VRL2 to reduce light obstruction.

[0210] Furthermore, the circuit layer CL may further include a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2, a first insulating layer IL1, a third gate insulating layer GI3, a second insulating layer IL2, a first planar layer PLN1, and a second planar layer PLN2, wherein:

[0211] A light shielding layer (BSM) is stacked on the substrate (SU). A buffer layer (BUF) may cover the light shielding layer (BSM). The buffer layer (BUF) may be made of inorganic materials such as silicon nitride and silicon oxide. The buffer layer (BUF) may be a single layer or a multilayer structure, and the materials of different layers may be different. The first semiconductor layer (SE1) is disposed on the surface of the buffer layer (BUF) away from the substrate (SU).

[0212] The first gate insulating layer GI1 covers the first semiconductor layer SE1 and may be made of inorganic materials such as silicon nitride and silicon oxide. The first gate layer GA1 is disposed on a surface of the first gate insulating layer GI1 away from the substrate SU.

[0213] The second gate insulating layer GI2 covers the first gate layer GA1 and may be made of inorganic materials such as silicon nitride and silicon oxide. The second gate layer GA2 is disposed on a surface of the second gate insulating layer GI2 away from the substrate SU.

[0214] The first insulating layer IL1 may cover the second gate layer GA2 and may be made of inorganic materials such as silicon nitride and silicon oxide. The first insulating layer IL1 may be a single layer or a multilayer structure, and the materials of different layers may be different. The second semiconductor layer SE2 is disposed on the surface of the first insulating layer IL1 away from the substrate SU.

[0215] The third gate insulating layer GI3 covers the second semiconductor layer SE2 and may be made of inorganic materials such as silicon nitride and silicon oxide. The third gate layer GA3 is disposed on a surface of the third gate insulating layer GI3 away from the substrate SU.

[0216] The second insulating layer IL2 may cover the third gate layer GA3 and may be made of inorganic materials such as silicon nitride and silicon oxide. The second insulating layer IL2 may be a single layer or a multilayer structure, and the materials of different layers may be different. The first source and drain layer SD1 is disposed on the surface of the second insulating layer IL2 away from the substrate SU.

[0217] The first planarization layer PLN1 can cover the first source / drain layer SD1. The first planarization layer PLN1 can be made of an organic material such as a resin. Planarization can be achieved through leveling of the organic material. The second source / drain layer SD2 can be disposed on a surface of the first planarization layer PLN1 away from the substrate SU. Furthermore, in some embodiments, a passivation layer can cover the first source / drain layer SD1, and the first planarization layer PLN1 can then cover the passivation layer.

[0218] The second planar layer PLN2 can cover the second source / drain layer SD2 and can be made of an organic material such as resin. The first electrode of the light emitting device LD and the pixel definition layer PDL can be provided on the surface of the second planar layer PLN2 away from the substrate SU.

[0219] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A pixel circuit comprising a driving transistor, a compensation circuit, a writing circuit, a first reset circuit and a second reset circuit; The first electrode of the driving transistor is used to receive a first power supply signal, and the second electrode is connected to the light emitting device through a first light emitting control circuit; One of the first electrode and the second electrode of the driving transistor is connected to its gate through the compensation circuit, and the other receives a data signal through the writing circuit; The first reset circuit is connected to one of the first and second electrodes of the driving transistor for inputting a first reset signal; the second reset circuit is connected to one of the first and second electrodes of the driving transistor for inputting a second reset signal; the first reset signal and the second reset signal have opposite polarities.

2. The pixel circuit according to claim 1, wherein: The first reset circuit and the compensation circuit are connected to the second electrode of the driving transistor, and the second reset circuit and the writing circuit are connected to the first electrode of the driving transistor.

3. The pixel circuit according to claim 1, wherein: The first reset circuit, the second reset circuit and the compensation circuit are connected to the second electrode of the driving transistor, and the writing circuit is connected to the first electrode of the driving transistor.

4. The pixel circuit according to claim 1, wherein: The compensation circuit and the first reset circuit are connected to a first electrode of the driving transistor, and the second reset circuit and the writing circuit are connected to a second electrode of the driving transistor.

5. The pixel circuit according to claim 1, wherein: The first reset circuit, the second reset circuit and the compensation circuit are connected to a first electrode of the driving transistor, and the writing circuit is connected to a second electrode of the driving transistor.

6. The pixel circuit according to any one of claims 1 to 5, wherein: The pixel circuit further includes an energy storage circuit, a first light emitting control circuit and a second light emitting control circuit; The first electrode of the driving transistor receives the first power supply signal through the first light emitting control circuit, and the second electrode is connected to the light emitting device through the second light emitting control circuit; The energy storage circuit is connected to the gate of the driving transistor and can receive the first power supply signal.

7. The pixel circuit according to claim 6, wherein: The compensation circuit includes a compensation transistor, the write circuit includes a write transistor, the first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the first light-emitting control circuit includes a first light-emitting control transistor, and the second light-emitting control circuit includes a second light-emitting control transistor; the energy storage circuit includes a storage capacitor.

8. A driving method of a pixel circuit, the pixel circuit comprising a driving transistor, a compensation circuit, a writing circuit, a first reset circuit, a second reset circuit, a first light emitting control circuit and a second light emitting control circuit; The first electrode of the driving transistor receives the first power supply signal through the first light-emitting control circuit, and the second electrode is connected to the light-emitting device through the second light-emitting control circuit; one of the first electrode and the second electrode of the driving transistor is connected to its gate through the compensation circuit, and the other receives the data signal through the writing circuit; the first reset circuit is connected to one of the first electrode and the second electrode of the driving transistor; The second reset circuit is connected to one of the first electrode and the second electrode of the driving transistor; The driving method comprises: In a first reset phase of a write frame, turning off the write circuit, the first reset circuit, the first light-emitting control circuit, and the second light-emitting control circuit; Turning on the second reset circuit and inputting a second reset signal through the second reset circuit; In the second reset phase of the write frame, the write circuit, the second reset circuit, the first light control circuit and the second light control circuit are turned off; the compensation circuit and the first reset circuit are turned on, and a first reset signal is input through the first reset circuit; the first reset signal has opposite polarity to the second reset signal; In the writing phase of the writing frame, the first reset circuit, the second reset circuit, the first light-emitting control circuit and the second light-emitting control circuit are turned off; the writing circuit and the compensation circuit are turned on, and a data signal is input through the writing circuit; In the third reset phase of the write frame, the compensation circuit, the write circuit, the second reset circuit and the first light-emitting control circuit are turned off; the first reset circuit and the second light-emitting control circuit are turned on, and the first reset signal is input through the first reset circuit; During the light emitting phase of the writing frame, the compensation circuit, the writing circuit, the first reset circuit and the second reset circuit are turned off; and the first light emitting control circuit and the second light emitting control circuit are turned on.

9. The driving method according to claim 8, wherein: The driving method further includes: In the first reset phase of the holding frame, the writing circuit, the first reset circuit, the first light-emitting control circuit and the second light-emitting control circuit are turned off; the second reset circuit is turned on, and the second reset signal is input through the second reset circuit; In the second reset phase of the holding frame, the writing circuit, the second reset circuit, the first light-emitting control circuit and the second light-emitting control circuit are turned off; the compensation circuit and the first reset circuit are turned on, and the first reset signal is input through the first reset circuit; In the third reset phase of the holding frame, the compensation circuit, the writing circuit, the second reset circuit and the first light-emitting control circuit are turned off; the first reset circuit and the second light-emitting control circuit are turned on, and the first reset signal is input through the first reset circuit.

10. The driving method according to claim 9, wherein: The driving method further includes: In the fourth reset stage of the holding frame, the first reset circuit, the second reset circuit, the first light-emitting control circuit and the second light-emitting control circuit are turned off; the write circuit and the compensation circuit are turned on, and the data signal is input through the write circuit.

11. The driving method according to claim 9, wherein: During the first reset phase of the write frame and the hold frame, the compensation circuit is turned on.

12. The driving method according to any one of claims 8 to 11, wherein: The number of the pixel circuits is multiple and they are arrayed in the row direction and the column direction; The first light-emitting control circuit can be turned on in response to a first light-emitting control signal, and the second light-emitting control circuit can be turned on in response to a second light-emitting control signal; the writing circuit can be turned on in response to a first scanning signal; The first light emission control signal input to the pixel circuits in the nth row is multiplexed into a second light emission control signal input to the pixel circuits in the (n+i)th row.

13. The driving method according to any one of claims 8 to 11, wherein: The number of the pixel circuits is multiple and they are arrayed in the row direction and the column direction; The write circuit can be turned on in response to a first scan signal, and the second reset circuit can be turned on in response to a second reset control signal; The first scanning signal input to the pixel circuits in the nth row is multiplexed into a second reset control signal input to the pixel circuits in the (n+jth) row.

14. A display panel, comprising a plurality of pixel circuits arranged in an array along a row direction and a column direction, the pixel circuit comprising a plurality of transistors, a storage capacitor, a data line and a power line, the transistors comprising a driving transistor, a writing transistor, a compensation transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor and a second reset transistor; The first electrode of the driving transistor is connected to the power line through the first light-emitting control transistor, and the second electrode is connected to the light-emitting device through the second light-emitting control transistor; one of the first electrode and the second electrode of the driving transistor is connected to its gate through the compensation transistor, and the other is connected to the data line through the write transistor; the first reset transistor is connected to one of the first electrode and the second electrode of the driving transistor; the second reset transistor is connected to one of the first electrode and the second electrode of the driving transistor; the storage capacitor is connected to the gate of the driving transistor and the power line; The power line is used to input a first power signal, and the data line is used to transmit a data signal; The display panel comprises: substrate; A circuit layer, disposed on one side of the substrate and comprising the pixel circuit; A plurality of light emitting devices are arranged on a side of the circuit layer away from the substrate, and one of the light emitting devices is connected to a second electrode of a second light emitting control transistor of the pixel circuit.

15. The display panel according to claim 14, wherein: The circuit layer comprises: A first reset signal network is connected to the first electrode of the first reset transistor and is used to transmit a first reset signal; the first reset signal network includes a first signal line and a second signal line located in different layers and connected; the first signal line extends along the row direction, and the second signal line extends along the column direction.

16. The display panel according to claim 15, wherein: The circuit layer comprises: A second reset signal network is connected to the first electrode of the second reset transistor and is used to transmit a second reset signal; the second reset signal network includes a third signal line and a fourth signal line located in different layers and connected; the third signal line extends along the row direction, and the fourth signal line extends along the column direction.

17. The display panel according to claim 16, wherein: The circuit layer also includes: A light shielding layer, disposed on one side of the substrate; The first semiconductor layer is disposed on a side of the light shielding layer away from the light shielding layer, and includes the driving transistor, the writing transistor, the first light emission control transistor, and the second light emission control transistor. an active portion of a transistor, a first reset transistor, and a second reset transistor; A first gate layer is provided on a side of the first semiconductor layer away from the substrate and overlaps with the first semiconductor layer; the first gate layer includes a first plate of the storage capacitor, and gates of the driving transistor, the writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, the first reset transistor, and the second reset transistor; A second gate layer, disposed on a side of the first gate layer away from the substrate, and comprising a second electrode plate of the storage capacitor; A second semiconductor layer, disposed on a side of the second gate layer away from the substrate, and including an active portion of the compensation transistor; a third gate layer, disposed on a side of the second semiconductor layer away from the substrate and overlapping the second semiconductor layer; the third gate layer includes a gate of the compensation transistor, the first signal line and the third signal line; A first source-drain layer, provided on a side of the third gate layer away from the substrate, and comprising the second signal line and the fourth signal line; The second source-drain layer is disposed on a side of the first source-drain layer away from the substrate and includes the power line and the data line.

18. The display panel according to claim 16, wherein: The pixel circuits in each column are divided into a plurality of circuit groups distributed along the row direction, and the same circuit group includes the pixel circuits in two adjacent columns; The two columns of pixel circuits in the same circuit group are symmetrical about a symmetry axis extending along the column direction; and the two adjacent circuit groups are symmetrical about a symmetry axis extending along the column direction.

19. The display panel according to claim 18, wherein: The first signal lines and the third signal lines are alternately distributed along the column direction; the second signal lines and the fourth signal lines are alternately distributed along the row direction; The second signal line and the circuit group are alternately distributed along the row direction; the second signal line is simultaneously connected to the first electrode of the first reset transistor of the pixel circuit adjacent thereto; A fourth signal line is provided between two columns of pixel circuits in the same circuit group; the fourth signal line is simultaneously connected to the first electrodes of the second reset transistors of the two adjacent columns of pixel circuits.

20. The display panel according to claim 17, wherein: A first signal line overlaps with active portions of the first reset transistors of a row of the pixel circuits.

21. The display panel according to claim 20, wherein: The active portion of the first reset transistor includes two channel portions and a connecting doped portion connecting the two channel portions; The first signal line includes a line body extending along the row direction and a plurality of overlapping portions distributed along the row direction, wherein the overlapping portions are connected to the line body and extend along the column direction; Each overlapping portion of the first signal line overlaps with at least one channel portion of the active portion of each first reset transistor in a row of pixel circuits and the connecting doped portion; the line body of the first signal line overlaps with at least one channel portion of the active portion of each first reset transistor in a row of pixel circuits.

22. The display panel according to claim 18, wherein: The second electrodes of the pixel circuits in the same column are connected to the same power line; In any row of the pixel circuits, the second plates of the storage capacitors of two adjacent pixel circuits belonging to different circuit groups are connected.

23. The display panel according to claim 18, wherein: One of the power lines is connected to one column of the pixel circuits, and the power line overlaps with the active portion of the driving transistor, the active portion of the compensation transistor, and the storage capacitor of the column of the pixel circuits connected thereto.

Images