High resolution display circuit with global initialization

Abstract

A display may include an array of pixels. The pixel may include an organic light emitting diode, at most three thin film transistors, and at most two capacitors. The pixel may include a driving transistor, an emission transistor, and a selection transistor. The select transistor may be used to apply a reference voltage to the gate of the drive transistor during a global reset phase and during a global threshold voltage sampling phase, and may also be used to apply a data voltage to the gate of the drive transistor during a data programming phase. The drive transistor may receive a supply voltage that switches between a low voltage for the global reset phase and a high voltage for other operating phases. Configured and operated in this manner, the pixel does not need to include separate dedicated anode reset and initialization transistors.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 358,752 filed on July 25, 2023 and U.S. Provisional Patent Application No. 63 / 408,038 filed on September 19, 2022, which are hereby incorporated by reference in their entirety. Background Art

[0002] The present disclosure relates generally to electronic devices having displays, and more particularly to display driver circuits for displays such as organic light emitting diode (OLED) displays.

[0003] Electronic devices often include displays. For example, cell phones and portable computers typically include displays for presenting image content to a user. OLED displays have an array of display pixels based on light emitting diodes. In this type of display, each display pixel includes a light emitting diode and an associated transistor for controlling the application of a data signal to the light emitting diode to produce light. Designing display pixels can be challenging. Summary of the invention

[0004] An electronic device may include a display having an array of display pixels. Each display pixel may include at least an organic light emitting diode (OLED) that emits light and an associated transistor for controlling the operation of the pixel. According to one embodiment, the display pixel may include a light emitting diode, at most three transistors, and at most two capacitors. The display pixel may include a drive transistor, an emission transistor, and a selection transistor. The emission transistor, the drive transistor, and the diode may be coupled in series between a first power line and a second power line. A storage capacitor may be coupled across the gate and source nodes of the drive transistor. An additional capacitor may be coupled to the anode of the diode. The selection transistor may be configured to apply a reference voltage or a data voltage to the gate node of the drive transistor.

[0005] The display pixel can operate in a global reset phase, a global compensation phase, a data programming phase, and an emission phase to support threshold voltage elimination within the pixel. In the global reset phase, the first power line is pulled down to a reset voltage, and the emission transistor can be used to pass the reset voltage through the drive transistor to reset the diode. In the global reset phase, the selection transistors in all display pixels are asserted simultaneously to apply a reference voltage to the gate node of each drive transistor. In the global compensation phase, the first power line is pulled up to a positive power supply voltage to sample the threshold voltage of each drive transistor on the respective storage capacitors. In the data programming phase, the selection transistors of different rows can be activated in sequence to load the required data signal into each pixel. In the emission phase, the emission transistor can be activated so that the corresponding diode can emit a certain amount of light as a function of the data signal programmed into the pixel.

[0006] If desired, the emission transistor may be omitted from each pixel. In some embodiments, a row of pixels may be coupled to a single shared (common) emission transistor. The emission transistor may be coupled to a voltage line that may be switched between a high voltage and a low voltage using a power management circuit, or the emission transistor may be selectively coupled to a high voltage line or a low voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is an illustration of an illustrative electronic device with a display according to some embodiments.

[0008] Figure 2 is a diagram of an illustrative display having an array of organic light emitting diode display pixels according to some embodiments.

[0009] Figure 3 is a circuit diagram of an exemplary organic light emitting diode display pixel according to some embodiments.

[0010] Figure 4 is a diagram showing the operation according to some embodiments Figure 3 A timing diagram of exemplary waveforms involved in a display pixel.

[0011] Figure 5A is shown in accordance with some embodiments during the reset phase Figure 3 Illustration of a snapshot of display pixels.

[0012] Figure 5B is a diagram showing the compensation phase according to some embodiments Figure 3 Illustration of a snapshot of display pixels.

[0013] Figure 5C is shown in the programming stage according to some embodiments Figure 3Illustration of a snapshot of display pixels.

[0014] Figure 5D is a diagram showing the launch phase according to some embodiments Figure 3 Illustration of a snapshot of display pixels.

[0015] Figure 6 is a diagram showing a row of display pixels without any dedicated emission transistors according to some embodiments.

[0016] Figure 7 is a display operation according to some embodiments Figure 6 0048] A timing diagram of illustrative waveforms involved in a row of display pixels of the type shown in FIG.

[0017] Figure 8 is a diagram showing a row of display pixels coupled to a single row-by-row emission switch coupled to a power management circuit according to some embodiments.

[0018] Fig. 9 is a diagram showing a row of display pixels coupled to a single row-by-row emission switch that selectively couples to a high or low supply voltage line, according to some embodiments. DETAILED DESCRIPTION

[0019] Figure 1 An exemplary electronic device of the type that may be provided with a display is shown in FIG. Figure 1 As shown, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10. Storage and processing circuitry may include storage devices such as hard drive storage devices, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. Processing circuitry in control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

[0020] Input-output circuitry in device 10, such as input-output devices 12, may be used to allow data to be provided to device 10, and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scroll wheels, trackpads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user may control the operation of device 10 by supplying commands through input-output devices 12, and may receive status information and other output from device 10 using the output resources of input-output devices 12.

[0021] Input-output devices 12 may include one or more displays, such as display 14. Display 14 may be a touch screen display including a touch sensor for acquiring touch input from a user, or display 14 may be insensitive to touch. The touch sensor of display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch assembly, a force-based touch sensor structure, a light-based touch sensor, or other suitable touch sensor arrangements.

[0022] Control circuitry 16 may be used to run software, such as operating system code and application programs, on device 10. During operation of device 10, software running on control circuitry 16 may display images on display 14 using an array of pixels in display 14. Device 10 may be a tablet computer, laptop computer, desktop computer, display, cellular telephone, media player, watch device or other wearable electronic device, head-mounted device, glasses, or other suitable electronic device.

[0023] Display 14 may be an organic light emitting diode display or may be a display based on other types of display technology. Configurations in which display 14 is an organic light emitting diode (OLED) display are sometimes described herein as examples. However, this is merely illustrative. Any suitable type of display may be used in device 10 if desired.

[0024] Display 14 may have a rectangular shape (ie, display 14 may have a rectangular footprint and a rectangular perimeter edge extending around the rectangular footprint) or may have other suitable shapes. Display 14 may be planar or may have a curved profile.

[0025] Figure 2 A top view of a portion of display 14 is shown in FIG. Figure 2As shown, display 14 may have an array of pixels 22 formed on substrate 36. Substrate 36 may be formed of glass, metal, plastic, ceramic, porcelain, silicon, or other substrate materials. Pixels 22 may receive data signals via signal paths such as data lines D (sometimes referred to as data signal lines, column lines, etc.), and may receive one or more control signals via control signal paths such as horizontal control lines G (sometimes referred to as gate lines, scan lines, emission lines, row lines, etc.). There may be any suitable number of rows and columns of pixels 22 in display 14 (e.g., dozens or more, hundreds or more, or thousands or more).

[0026] Each pixel 22 may have a light emitting diode 26 that emits light 24 under the control of a pixel control circuit formed of a thin film transistor circuit or a bulk silicon transistor circuit (e.g., transistor 28 and a capacitor). Thin film transistor 28 may be a polysilicon thin film transistor, a semiconductor oxide thin film transistor (such as an indium gallium zinc oxide transistor), or a thin film transistor formed of other semiconductors. Pixels 22 may include light emitting diodes of different colors (e.g., red, green, and blue) to provide display 14 with the ability to display color images.

[0027] Source driver circuit 30 may be used to control the operation of pixel 22. Source driver circuit 30 may be formed from an integrated circuit, a thin film transistor circuit, and / or other suitable electronic circuitry. Figure 2 The source driver circuit 30 may include a circuit for communicating with system control circuits such as Figure 1 Path 32 may be formed by traces on a flexible printed circuit or other cables. During operation, the control circuit (e.g., Figure 1 Control circuitry 16 ) may provide circuitry 30 with information about an image to be displayed on display 14 .

[0028] To display an image on display pixels 22, source driver circuitry 30 may supply image data to data lines D (e.g., data lines extending along columns of pixels 22) while issuing clock signals and other control signals to supporting display driver circuitry such as gate driver circuitry 34 via paths 38. If desired, source driver circuitry 30 may also supply clock signals and other control signals to gate driver circuitry 34 on opposite edges of display 14 (e.g., gate driver circuitry may be formed on more than one side of the display pixel array).

[0029] The gate driver circuit 34 (sometimes referred to as a horizontal line control circuit or a row driver circuit) may be implemented as part of an integrated circuit and / or may be implemented using a thin film transistor circuit. The horizontal / row control lines G in the display 14 may carry gate line signals (scan line control signals), emission enable control signals, and / or other horizontal control signals for controlling each row of pixels. Therefore, the row control lines G are sometimes referred to as gate lines. There may be any suitable number of horizontal control signals for each row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.).

[0030] Certain applications require displays with high contrast and high resolution. Displays such as organic light emitting diode (OLED) displays can provide high resolution and high contrast. Display pixels in OLED displays may include thin film transistors that are affected by threshold voltage variations. Changes in transistor threshold voltages may result in uneven brightness between pixels in a display pixel array. In order to provide high contrast while ensuring sufficient brightness uniformity between pixels, intra-pixel (internal) threshold voltage compensation techniques may be used. However, conventional pixel architectures that support internal threshold voltage compensation include a large number of thin film transistors, which limits the maximum resolution that can be achieved by the display. For example, conventional OLED pixels that support intra-pixel threshold voltage compensation typically include seven or more transistors coupled to a light emitting diode.

[0031] According to one embodiment, Figure 3 is a circuit diagram of an exemplary organic light emitting diode (OLED) display pixel 22 that can reduce the number of transistors while still supporting intra-pixel (internal) threshold voltage compensation. Figure 3 As shown, the display pixel 22 includes only three thin film transistors (such as transistors Tdrive, Tem and Tsel), two capacitors (such as capacitors Cst and Ca), and an organic light emitting diode 26. Transistors Tdrive, Tem and Tsel can be n-type semiconductor oxide transistors. Semiconductor oxide transistors are defined as thin film transistors having a channel region formed of a semiconductor oxide material (e.g., indium gallium zinc oxide or IGZO, indium tin zinc oxide or ITZO, indium gallium tin zinc oxide or IGTZO, indium tin oxide or ITO, or other semiconductor oxide materials).

[0032] Semiconductor oxide transistors are significantly different from silicon transistors (i.e., transistors having a polysilicon channel region deposited using a low temperature process, sometimes referred to as LTPS or low temperature polysilicon). Semiconductor oxide transistors exhibit lower leakage than silicon transistors, so implementing at least some of the transistors within pixel 22 can help reduce flicker and uneven brightness (e.g., by preventing current from leaking away from the gate terminal of transistor Tdrive). If desired, at least some of the transistors within pixel 22 can be implemented as silicon transistors, so that pixel 22 has a hybrid configuration including a combination of semiconductor oxide transistors and silicon transistors (e.g., n-type LTPS transistors or p-type LTPS transistors). This document sometimes describes a configuration in which all transistors in a display pixel 22 are semiconductor oxide transistors as an example.

[0033] Transistor Tdrive (sometimes referred to herein as a "drive transistor") may have a drain terminal, a gate terminal coupled to node G, and a source terminal coupled to node S. The terms "source" and "drain" are sometimes used interchangeably when referring to the conductive terminals of the thin film transistor. Therefore, the source terminal and the drain terminal are sometimes referred to as "source-drain" terminals (e.g., the transistor has a gate terminal, a first source-drain terminal, and a second source-drain terminal). For example, the drain terminal of transistor Tdrive may be referred to as the first source-drain terminal, and the source terminal of transistor Tdrive may be referred to as the second source-drain terminal, or vice versa. Capacitor Cst (sometimes referred to as a storage capacitor) may be coupled across the gate and source terminals of transistor Tdrive and may be configured to store data values ​​for display 22.

[0034] The transistor Tem (sometimes referred to as an emission transistor) may have a source terminal coupled to the drain terminal of the transistor Tdrive, a drain terminal coupled to a positive power supply line 40 (e.g., a positive power supply line providing a positive power supply voltage ELVDD), and a gate terminal configured to receive an emission (control) signal EM. The pixel positive power supply voltage ELVDD may be 3V, 4V, 5V, 6V, 7V, 2V to 8V, greater than 6V, greater than 7V, greater than 8V, greater than 10V, greater than 12V, 6V-12V, 12V-20V, or any suitable positive power supply voltage level. The display pixel 22 has only one emission transistor.

[0035] Organic light emitting diode 26 may have an anode terminal coupled to the source terminal of drive transistor Tdrive and a cathode terminal coupled to ground power line 42 (e.g., a ground line providing ground power supply voltage ELVSS). Ground power supply voltage ELVSS may be 0V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, -8V, -9V, less than 2V, less than 1V, less than 0V, less than -5V, or any suitable ground or negative power supply voltage level. Connected in this manner, transistors Tem and Tdrive are said to be connected in series with diode 26.

[0036] The diode 26 may have an associated parasitic capacitance that may vary from pixel to pixel and over its service life. Relative to the storage capacitor Cst, the size of the diode parasitic capacitance may affect the amount of data voltage applied to both ends of the transistor Tdrive, thereby affecting the amount of drive current flowing into the diode 26 through the drive transistor, which directly affects the brightness of each pixel 22. To help mitigate the effects of variations in the diode parasitic capacitance on the pixel array, each display pixel 22 may be provided with a capacitor Ca coupled between the anode terminal of the diode 26 and the voltage line 44. The size of the capacitor Ca may be greater than the diode parasitic capacitance. The voltage line 44 may be configured to receive a ground voltage, a negative voltage, a positive voltage, a voltage equal to ELVSS, a voltage different from ELVSS, or other static (DC) reference voltages. Connected in this manner, the capacitor Ca may help mitigate variations in the diode parasitic capacitance, which may help improve brightness uniformity between pixels. The capacitor Ca may also be referred to as an auxiliary storage capacitor, while the capacitor Cst is used as a main storage capacitor. The capacitor Ca may also help extend the data range by capacitively coupling with Cst. Connected in this manner, only a portion of the applied Vdata appears between the gate and source nodes of the drive transistor. The larger data range helps relieve some of the burden on the source driver circuit 30 by increasing the grayscale step size. The use of capacitor Ca in pixel 22 is optional. Figure 3 In the pixel 22 , no additional transistor is coupled at the source terminal of Tdrive or the anode terminal of the diode 26 .

[0037] Transistor Tsel (sometimes referred to herein as a selection transistor, a gate voltage setting transistor, or a transfer transistor) may have a first source-drain terminal coupled to the gate terminal of transistor Tdrive, a second source-drain terminal coupled to the control voltage line 46, and a gate terminal configured to receive a scan (control) signal SC. Transistor Tsel may be used as a dual-purpose switch. During an initialization phase (e.g., during a reset phase and during a compensation phase), transistor Tsel may be used to apply a reference voltage Vref provided on the control (adjustable) voltage line 46 to the drive transistor. During a programming phase (e.g., during a data loading phase), transistor Tsel may be used to apply a data voltage Vdata provided on the voltage line 46 to the drive transistor. Therefore, voltage line 46 may sometimes be referred to as a reference line, a data line, or a dual-purpose reference-data line. The dual functionality of transistor Tsel, combined with the ability to switch ELVDD, enables intra-pixel threshold voltage compensation to be achieved without the need for additional transistors. Figure 3 In the example of FIG. 4 , the pixel 22 comprises only one transistor Tsel coupled at the gate terminal of the transistor Tdrive.

[0038] Figure 4 It is a combination of display operation Figure 3 A timing diagram of exemplary waveforms involved in a display pixel 22 of the type described. Prior to time t1, voltage ELVDD is asserted (e.g., driven high) during the emission phase, while all scan signals are low. Voltage ELVDD may then be pulsed low (e.g., power line 40 may be switched from a positive supply voltage level to a low voltage level or a reset voltage level).

[0039] At time t1, the scan signals of all rows in the pixel array may be asserted simultaneously. For example, when the voltage ELVDD is driven low, the scan signal SC1 corresponding to the first row of pixels in the array may be asserted at time t1, ..., the scan signal SC1 corresponding to the i-th row of pixels in the array may be asserted at time t1. i can be asserted at time t1, ..., the scan signal SC corresponding to the nth (last) row of pixels in the array n may be asserted at time t1. During this period, the emission signal is also high. The voltage ELVDD will be pulsed low until time t2 (e.g., ELVDD is driven back high at time t2). The period from time t1 to t2 is sometimes referred to as the reset phase. Since the scan signals for all rows in the pixel array are asserted at the same time, all pixels in the array will be reset at the same time, so the reset phase is sometimes referred to and defined as a "global" reset operation.

[0040] Figure 5A The global reset phase is shown Figure 3 A snapshot of the display pixel 22 in FIG. Figure 5AAs shown, voltage line 46 will be driven to a reference voltage Vref, and voltage ELVDD will be driven to a low voltage, such as a reset voltage Vreset. Reference voltage Vref may be greater than ELVSS, greater than Vreset, may be 0V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, -8V, -9V, less than 2V, less than 1V, less than 0V, less than -4V, or any suitable initialization or negative power supply voltage level. Voltages Vref, Vreset, and ELVSS should be carefully selected so that diode 26 is not turned on during the global reset phase and during the compensation phase to maximize the contrast of display 14. Reset voltage Vreset may be equal to ELVSS, may be different from ELVSS, less than Vref, may be 0V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, -8V, -9V, may be less than 2V, less than 1V, less than 0V, less than -5V, or any suitable reset or negative power supply voltage level. Since all scan signals are asserted during the reset phase, transistor Tsel will be turned on to drive the gate terminal of transistor Tdrive to the reference voltage Vref. Since the emission signal is asserted during the reset phase, the emission transistor Tem will also be turned on to drive the source node and anode terminal of transistor Tdrive to the voltage Vreset. By pulling ELVDD down to the reset voltage level Vreset, transistor Tem can be used to reset the anode terminal of diode 26 without using a separate dedicated anode reset transistor, which helps to further reduce the pixel circuit area. Therefore, transistor Tem is sometimes also referred to as an anode reset transistor.

[0041] At time t2, ELVDD is driven back to the positive supply voltage level while all scan signals and emission signals remain high. The emission signal may be de-asserted at time t3. After time t3, all scan signals may be de-asserted (e.g., driven low) simultaneously. The time period from time t2 to t3 is sometimes referred to as the compensation phase. Since the scan signals for all rows in the pixel array remain asserted at this time, all pixels in the array will be sampled simultaneously, so the compensation phase is sometimes referred to and defined as a "global" compensation operation.

[0042] Figure 5B 2 shows a snapshot of a display pixel 22 during the global compensation phase. Figure 5BAs shown, the voltage line 46 remains driven to the reference voltage Vref, and the voltage ELVDD will be driven back to the high (positive) power supply voltage level. Since all scan signals remain high during the compensation phase, the transistor Tsel will remain turned on to drive the gate terminal of the transistor Tdrive to the reference voltage Vref. Since the emission signal remains asserted during the compensation phase, the emission transistor Tem will also be turned on to drive the drain node of the transistor Tdrive to the positive power supply voltage ELVDD. As a result, the transistor Tdrive can pull its source node up to a threshold voltage Vth lower than its gate terminal until Tdrive is turned off (for example, the source terminal of Tdrive can be driven to Vref minus Vth, where Vth represents the threshold voltage of the drive transistor). Therefore, the threshold voltage Vth will be sampled across the storage capacitor Cst. The threshold voltage Vth of the drive transistor can be a positive value or a negative value.

[0043] Since the threshold voltage Vth of the drive transistor of each pixel is sampled across the capacitor Cst of the pixel, the compensation phase is sometimes referred to as a threshold voltage sampling phase or a threshold voltage compensation phase. The reference voltages Vref and ELVSS should be selected so that the diode 26 is not turned on during the global compensation phase (Vref-Vth-ELVSS) to maximize the contrast of the display 14. The reset phase and the compensation (threshold voltage sampling) phase may be collectively referred to and defined as a global initialization phase, which lasts from time t1 to time t3.

[0044] At time t3, the emission signal is driven low, and shortly thereafter, all scan signals are deasserted (e.g., driven low). The time period from time t3 to t4 is sometimes referred to as the programming phase, data programming phase, or data loading phase. During the data programming phase, the scan signal for each row may be pulsed high in turn to load the desired data signal. Figure 4 In the example, the scanning signal SC i Can be pulled high by pulses to i Loading. Figure 5C 2 shows a snapshot of a display pixel 22 during the programming phase. Figure 5CAs shown, a data signal voltage Vdata is provided on line 46, and when the scan signal SC is pulsed high during the programming phase, the gate terminal of the transistor Tdrive will be driven to Vdata. Since the emission signal EM is driven low, the transistor Tem will be turned off. As a result, the voltage across the capacitor Cst has nowhere to discharge. Since the threshold voltage Vth has been sampled across the capacitor Cst before, at some point before the end of the programming phase, the source node of the transistor Tdrive will be driven to [Vref-Vth+(Vdata-Vref)*Cst / (Cst+Ca+Coled)]. The capacitor Coled can represent the parasitic capacitance of the diode 26 in each display pixel. The pixels of each row in the array can be loaded in this way.

[0045] At time t4, the transmit signal EM is asserted to start the transmit phase. Figure 5D 2 shows a snapshot of a display pixel 22 during the emission phase. Figure 5D As shown, transistor Tsel is turned off, so the programming voltage maintained across the storage capacitor Cst (which is a combination of a portion of Vdata and the sampled Vth) has nowhere to discharge. Transistor Tsel should be a low leakage switch, such as a semiconductor oxide transistor or other type of thin film transistor that exhibits lower leakage than traditional silicon transistors, so that the charge stored on capacitor Cst is retained throughout the emission phase after programming. Transistor Tsel can also be a silicon transistor specifically designed to have low leakage, such as a silicon transistor manufactured using fully depleted silicon on insulator (FD-SOI) technology. Since transistor Tem is turned on during the emission phase, transistor Tem will pull up the drain node of transistor Tdrive, and current will flow through transistors Tem and Tdrive into the organic light emitting diode 26. The ELVDD and ELVSS voltages should be selected so that diode 26 has sufficient voltage margin throughout the operating life of display 14. The amount of current flowing into diode 26 during the emission phase determines the amount of light emitted by diode 26. Since the amount of the final emission current is related to (Vgs-Vth) 2 The final emission current will be a function of Vdata only, with the Vth term canceled out. Therefore, the resulting emission current will be independent of Vth. This operating scheme of internally sampling and canceling the drive transistor threshold voltage in this manner is sometimes referred to as in-pixel threshold voltage compensation or cancellation.

[0046] Figure 3 In the illustrated embodiment, the display pixel 22 includes at least one emission transistor Tem, which is merely illustrative and is not intended to limit the scope of the present embodiment. Figure 6 Another suitable arrangement is shown in which each display pixel 22' does not include any emission transistors. Figure 6The i-th pixel row in the pixel array is shown, which has a first display pixel 22'-1, ... in the first column, and an M-th display pixel 22'-M in the M-th (last) column. Pixel 22'-1 can receive a first data signal Vdata1 (or a reference voltage Vref), and pixel 22'-M can receive an M-th data signal VdataM (or a reference voltage Vref). Each display pixel 22' is connected to Figure 3 The pixel 22 in FIG. 1 is similar, but without the emission transistor Tem. Therefore, Figure 6 Each display pixel 22' in the display includes only two transistors Tdrive and Tsel, two capacitors Cst and Ca, and a light emitting diode 26. Each pixel 22' can receive a row-by-row scan signal SC i And the row-by-row power supply voltage ELVDD i In other words, the signal SC i and ELVDD i is the row-by-row control signal provided to the pixels 22' in the i-th row via the row control lines that span the width of the array. Using the row-by-row ELVDD i This is a departure from conventional pixel power supply schemes where ELVDD is a global supply voltage provided to each display pixel in the array via a global power supply network. The use of capacitor Ca is optional.

[0047] Figure 7 It is a display operation Figure 6 2 '. Since there is no emission transistor in each pixel 22', the diode 26 will start to emit light immediately after the data programming phase, so the pixel 22' needs to have a way to adjust the emission duty cycle. Figure 7 As shown, the various phases for each pixel row occur in a rolling (time-shifted) manner. For each row, the emission phase is followed by a reset phase. During the reset phase, ELVDD is pulsed low row by row while the scan signal is pulsed high. Subsequently, the compensation phase can be performed by driving ELVDD back high while repeatedly pulsing the scan signal to apply the reference voltage Vref to the gate terminal of the drive transistor. In other words, the compensation phase no longer occurs in a single stretch, but instead occurs via a series of pulses between each data input. The cumulative duration of all pulses adds up to the effective duration of the compensation phase.

[0048] For each row, a data programming phase may occur after the compensation phase, during which the desired Vdata is loaded into the desired pixels 22'. The time period from the start of the compensation phase to the completion of data programming should be the same for each row. Since the timing of each row is offset from row to row, it is possible that one row is emitting while another row is resetting or performing threshold compensation / sampling. This drive scheme allows the emission transistor to be removed while retaining the adjustability of the emission duty cycle by adjusting the duration of the compensation phase and / or the reset phase (e.g., so that each row can have the same emission time).

[0049] Figure 8 Another embodiment is shown in which each row of pixels 22' is coupled to a shared (common) emission transistor Tem'. Figure 8 As shown, each display pixel 22' does not include any emission transistor, but all pixels 22' of the row are connected to a common emission transistor Tem'. Figure 8 The i-th pixel row in the pixel array is shown, which has a first display pixel 22'-1, ..., in the first column and an M-th display pixel 22'-M in the M (last) column. Pixel 22'-1 can receive a first data signal Vdata1 (or a reference voltage Vref), and pixel 22'-M can receive an M-th data signal VdataM (or a reference voltage Vref). Each display pixel 22' is connected to Figure 3 The pixel 22 in FIG. 1 is similar, but without the emission transistor Tem. Therefore, Figure 8 Each display pixel 22' in comprises only two transistors Tdrive and Tsel, two capacitors Cst and Ca, and a light emitting diode 26. The use of capacitor Ca is optional.

[0050] The drain node of the drive transistor in each pixel 22' can be coupled to the shared emission transistor Tem' (e.g., only one emission transistor per row of pixels). The shared emission transistor Tem' has a first source-drain terminal coupled to the drain node of the drive transistor of each display pixel 22' in a given row I, a second source-drain terminal coupled to the voltage line 41, and a gate terminal configured to receive a row-by-row emission control signal EM i Voltage line 41 may be coupled to a power management circuit, such as power management circuit 50. Power management circuit 50 may be configured to switch the ELVDD voltage on line 41 between a positive supply voltage and a reset voltage or other low voltage. Using a shared emission transistor Tem' to connect each row to the supply voltage line 41 eliminates the need for a Figure 6 Separate row-by-row ELVDD lines are provided as shown in the example of . The size of the shared emission transistor Tem' should be large enough to drive an entire row of pixels 22'.

[0051] Figure 8 In the embodiment shown, the use of a power management circuit to switch the voltage line 41 is exemplary. Fig. 9 Another suitable arrangement is shown in which voltage line 41 is selectively coupled to high voltage line 52 (eg, providing high supply voltage VDD) using switch 56. H power line) and selectively coupled to a low voltage line 54 (eg, providing a low power supply voltage VDD) using a switch 58. L voltage VDD H can be a positive supply voltage level, while the voltage VDD L This may be a reset voltage or other low level.Switches 56 and 58 may be implemented as n-type transistors (as an example).

[0052] Switch 56 may be turned on (eg, by selectively asserting gate signal G H ), and switch 58 may also be turned on (e.g., by selectively asserting gate signal G L ). At any given time, only one of switches 56 and 58 should be turned on. Switch 58 should only be turned on during the reset phase to provide a low voltage VDD to voltage line 41 L In other operation phases (eg, in the emission phase, the threshold voltage compensation phase, or the data programming phase), the switch 56 should be turned on so that VDD is provided to the voltage line 41. H In the data programming phase, VDD may be alternatively provided to the voltage line 41. L However, the voltage line 41 is kept at VDD before and after data programming. H Unnecessary switching is avoided. Selectively coupling voltage line 41 to VDD H or VDD L The need for power management circuitry to actively switch ELVDD is eliminated, but at the expense of two extra transistors and two additional voltage lines 52 and 54 .

[0053] According to one embodiment, a display pixel is provided, which includes: a light emitting diode; a driving transistor having a first source-drain terminal coupled to a power line, a second source-drain terminal coupled to the light emitting diode, and a gate terminal; a storage capacitor coupled between the gate terminal and the second source-drain terminal of the driving transistor; and a selection transistor having a first source-drain terminal coupled to the gate terminal of the driving transistor, a second source-drain terminal coupled to a control voltage line, and a gate terminal configured to receive a scan signal; the selection transistor is configured to apply a reference voltage to the gate terminal of the driving transistor in a global reset phase and to apply a data voltage to the gate terminal of the driving transistor in a programming phase.

[0054] According to another embodiment, the display pixel includes an emission transistor having a first source-drain terminal coupled to the first source-drain terminal of the drive transistor, a second source-drain terminal coupled to the power line, and a gate terminal configured to receive an emission signal.

[0055] According to another embodiment, the display pixel includes an additional capacitor having a first terminal coupled to the anode of the light emitting diode and having a second terminal coupled to the static voltage line, the capacitance of the additional capacitor being greater than a parasitic capacitance of the light emitting diode.

[0056] According to another embodiment, during the global reset phase, the select transistor and the emission transistor are turned on.

[0057] According to another embodiment, during the global reset phase, the power line is driven to a low voltage to reset the anode of the light emitting diode.

[0058] According to another embodiment, in a global threshold voltage compensation phase after the global reset phase, the selection transistor and the emission transistor are turned on, and in the global threshold voltage compensation phase, the power line is driven to a high voltage.

[0059] According to another embodiment, in the programming phase, the selection transistor is turned on to apply the data voltage to the gate terminal of the driving transistor, and in the programming phase, the emission transistor is turned off.

[0060] According to another embodiment, the display pixel includes only three thin film transistors in total, including the drive transistor, the select transistor, and the emission transistor, and one or more capacitors.

[0061] According to another embodiment, the selection transistor includes a semiconductor oxide transistor having a channel region formed using a semiconductor oxide, or is a silicon transistor manufactured using a fully depleted silicon-on-insulator (FD-SOI) technology.

[0062] According to one embodiment, a method for operating a display having a pixel array is provided, the method comprising: in an emission phase, driving a power supply voltage high and driving an emission signal high so that the pixel array emits light; in a global reset phase, driving the power supply voltage low and simultaneously asserting scan signals for multiple rows in the pixel array; and in a programming phase, asserting these scan signals in sequence to load data into corresponding rows in the pixel array.

[0063] According to another embodiment, the method includes driving the power supply voltage high while providing a reference voltage to the plurality of rows in the pixel array during a global threshold voltage sampling phase.

[0064] According to another embodiment, the global threshold voltage sampling phase is after the global reset phase and before the programming phase.

[0065] According to another embodiment, at least some of the pixels in the pixel array include: a light emitting diode; a driving transistor coupled in series with the light emitting diode; a storage capacitor coupled across the gate and source terminals of the driving transistor; an emission transistor coupled in series with the driving transistor, the emission transistor having a source-drain terminal configured to receive the power supply voltage; and a gate voltage setting transistor coupled to the gate terminal of the driving transistor and configured to receive the reference voltage in the global reset phase and in the global threshold voltage sampling phase and to receive the data voltage in the programming phase.

[0066] According to another embodiment, at least some of the pixels in the pixel array further include an additional capacitor coupled between the anode of the light emitting diode and a static voltage line.

[0067] According to one embodiment, a display circuit is provided, which includes: a first pixel, the first pixel having a first light-emitting diode; a first driving transistor, the first driving transistor coupled in series with the first light-emitting diode; and a first transfer transistor, the first transfer transistor coupled at the gate terminal of the first driving transistor; a second pixel, the second pixel having a second light-emitting diode; a second driving transistor, the second driving transistor coupled in series with the second light-emitting diode; and a second transfer transistor, the second transfer transistor coupled at the gate terminal of the second driving transistor; and a scan line, the scan line coupled to the first transfer transistor in the first pixel and the second transfer transistor in the second pixel, the first pixel and the second pixel each including only two transistors and one or more capacitors.

[0068] According to another embodiment, the first pixel further includes a first capacitor coupled across the gate terminal and the source terminal of the first drive transistor.

[0069] According to another embodiment, the first pixel includes a second capacitor coupled between the anode of the first light emitting diode and a static voltage line.

[0070] According to another embodiment, the display circuit includes a row control line configured to provide a high voltage and a low voltage to drain terminals of the first drive transistor and the second drive transistor.

[0071] According to another embodiment, the display circuit includes: a third pixel, which has a third light-emitting diode, a third driving transistor coupled in series with the third light-emitting diode, and a third transfer transistor coupled at the gate terminal of the third driving transistor; a fourth pixel, which has a fourth light-emitting diode, a fourth driving transistor coupled in series with the fourth light-emitting diode, and a fourth transfer transistor coupled at the gate terminal of the fourth driving transistor, and an additional scan line coupled to the third transfer transistor in the third pixel and the fourth transfer transistor in the fourth pixel, the third pixel and the fourth pixel each including only two transistors and one or more capacitors, the first scan signal on the scan line is pulsed to perform a first reset operation, and the second scan signal on the additional scan line is pulsed after the first reset operation to perform a second reset operation.

[0072] According to another embodiment, the scan signal on the scan line is pulsed in a reset phase, pulsed in a data programming phase, and pulsed a plurality of times in a compensation phase between the reset phase and the data programming phase.

[0073] According to another embodiment, the duration of the compensation phase or the duration of the reset phase is adjusted to adjust the emission duty cycle of the first pixel and the second pixel.

[0074] According to another embodiment, the display circuit includes a shared emission transistor having a first source-drain terminal coupled to drain terminals of the first drive transistor and the second drive transistor, a second source-drain terminal configured to receive a high voltage and a low voltage from a power management circuit in different operating stages, and a gate terminal configured to receive an emission signal.

[0075] According to another embodiment, the display circuit includes a shared emission transistor having a first source-drain terminal coupled to the drain terminals of the first drive transistor and the second drive transistor, a second source-drain terminal coupled to the first voltage line, and a gate terminal configured to receive an emission signal; a first switch, the first switch is configured to selectively supply a high voltage from the second voltage line to the first voltage line, and a second switch, the second switch is configured to selectively supply a low voltage from a third voltage line to the first voltage line.

[0076] The foregoing is merely illustrative and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented individually or in any combination.

Claims

1. A display pixel, comprising: Light Emitting Diodes; a drive transistor having a first source-drain terminal coupled to a power line, a second source-drain terminal coupled to the light emitting diode, and a gate terminal; a storage capacitor coupled between the gate terminal and the second source-drain terminal of the drive transistor; and a selection transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a control voltage line, and a gate terminal configured to receive a scan signal, wherein the selection transistor is configured to apply a reference voltage to the gate terminal of the drive transistor in a global reset phase and to apply a data voltage to the gate terminal of the drive transistor in a programming phase.

2. The display pixel of claim 1 , further comprising: An emission transistor having a first source-drain terminal coupled to the first source-drain terminal of the drive transistor, a second source-drain terminal coupled to the power line, and a gate terminal configured to receive an emission signal.

3. The display pixel of claim 2, further comprising: An additional capacitor has a first terminal coupled to the anode of the light emitting diode and has a second terminal coupled to a static voltage line, wherein a capacitance of the additional capacitor is greater than a parasitic capacitance of the light emitting diode.

4. The display pixel of claim 2, wherein during the global reset phase, the select transistor and the emission transistor are turned on.

5. The display pixel of claim 4, wherein during the global reset phase, the power line is driven to a low voltage to reset the anode of the light emitting diode.

6. The display pixel of claim 5, wherein in a global threshold voltage compensation phase following the global reset phase, the select transistor and the emission transistor are turned on, and wherein in the global threshold voltage compensation phase, the power line is driven to a high voltage.

7. The display pixel of claim 6, wherein: In the programming phase, the selection transistor is turned on to apply the data voltage to the gate terminal of the driving transistor; as well as During the programming phase, the emission transistor is turned off.

8. The display pixel of claim 2, comprising only three thin film transistors in total and one or more capacitors, the three thin film transistors comprising the drive transistor, the select transistor, and the emission transistor.

9. The display pixel of claim 1, wherein the select transistor comprises a semiconducting oxide transistor having a channel region formed using a semiconducting oxide, or is a silicon transistor fabricated using a fully depleted silicon-on-insulator (FD-SOI) technology.

10. A method of operating a display having an array of pixels, the method comprising: In the emission phase, the power supply voltage is driven high and the emission signal is driven high, so that the pixel array emits light; In a global reset phase, the power supply voltage is driven low and scan signals of a plurality of rows in the pixel array are asserted simultaneously; as well as During the programming phase, the scan signals are asserted sequentially to load data into corresponding rows in the pixel array.

11. The method according to claim 10, further comprising: In the global threshold voltage sampling phase, the power supply voltage is driven high while providing a reference voltage to the plurality of rows in the pixel array. 12 . The method of claim 11 , wherein the global threshold voltage sampling phase is after the global reset phase and before the programming phase.

13. The method of claim 11 , wherein at least some pixels in the pixel array comprise: Light Emitting Diodes; a driving transistor, the driving transistor being coupled in series with the light emitting diode; a storage capacitor coupled across the gate and source terminals of the drive transistor; an emission transistor coupled in series with the drive transistor, the emission transistor having a source-drain terminal configured to receive the supply voltage; and A gate voltage setting transistor is coupled to the gate terminal of the driving transistor and is configured to receive the reference voltage in the global reset phase and in the global threshold voltage sampling phase and to receive a data voltage in the programming phase.

14. The method of claim 13, wherein the at least some pixels in the pixel array further comprise: An additional capacitor is coupled between the anode of the light emitting diode and a static voltage line.

15. Display circuit, including: a first pixel, the first pixel having a first light emitting diode; a first driving transistor, the first driving transistor being coupled in series with the first light emitting diode; and a first transfer transistor coupled at a gate terminal of the first drive transistor; a second pixel, the second pixel having a second light emitting diode; a second driving transistor, the second driving transistor being coupled in series with the second light emitting diode; and a second transfer transistor coupled at a gate terminal of the second drive transistor; and A scan line is coupled to the first transfer transistor in the first pixel and the second transfer transistor in the second pixel, wherein the first pixel and the second pixel each include only two transistors and one or more capacitors.

16. The display circuit of claim 15, wherein the first pixel further comprises a first capacitor coupled across the gate terminal and a source terminal of the first drive transistor. 17 . The display circuit of claim 16 , wherein the first pixel further comprises a second capacitor coupled between an anode of the first light emitting diode and a static voltage line.

18. The display circuit according to claim 16, further comprising: A row control line is configured to provide a high voltage and a low voltage to drain terminals of the first drive transistor and the second drive transistor.

19. The display circuit according to claim 15, further comprising: A third pixel, the third pixel comprising: a third light emitting diode; a third driving transistor, the third driving transistor being coupled in series with the third light emitting diode; and a third transfer transistor coupled at a gate terminal of the third drive transistor; A fourth pixel, the fourth pixel comprising: a fourth light emitting diode; a fourth driving transistor, the fourth driving transistor being coupled in series with the fourth light emitting diode; and a fourth transfer transistor coupled at a gate terminal of the fourth drive transistor; as well as An additional scan line coupled to the third transfer transistor in the third pixel and the fourth transfer transistor in the fourth pixel, wherein the third pixel and the fourth pixel each include only two transistors and one or more capacitors, wherein a first scan signal on the scan line is pulsed to perform a first reset operation, and wherein a second scan signal on the additional scan line is pulsed after the first reset operation to perform a second reset operation.

20. The display circuit of claim 15, wherein the scan signal on the scan line is pulsed in a reset phase, is pulsed in a data programming phase, and is pulsed a plurality of times in a compensation phase between the reset phase and the data programming phase.

21. The display circuit of claim 15, wherein a duration of the compensation phase or a duration of the reset phase is adjusted to adjust an emission duty cycle of the first pixel and the second pixel.

22. The display circuit according to claim 15, further comprising: a shared emission transistor having a first source-drain terminal coupled to drain terminals of the first drive transistor and the second drive transistor, a second source-drain terminal configured to receive a high voltage and a low voltage from a power management circuit at different operation stages, and a gate terminal configured to receive a transmission signal.

23. The display circuit according to claim 15, further comprising: a shared emission transistor having a first source-drain terminal coupled to drain terminals of the first drive transistor and the second drive transistor, a second source-drain terminal coupled to a first voltage line, and a gate terminal configured to receive an emission signal; a first switch configured to selectively supply a high voltage from a second voltage line to the first voltage line; and A second switch is configured to selectively supply a low voltage from a third voltage line to the first voltage line.

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