Array substrate and display device

Abstract

The array substrate comprises a plurality of pixel driving circuits and a plurality of grid lines. Each pixel driving circuit includes a driving transistor, a data write transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Each gate line is configured to provide a gate scan signal to a data write transistor in a corresponding pixel drive circuit. A gate of the driving transistor is connected to the third capacitor electrode. A first node connection line connects a second electrode of the first reset transistor with a third capacitor electrode. And the orthographic projection of the corresponding grid line on the substrate is basically not overlapped with the orthographic projection of the first node connecting line on the substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control brightness. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits and a plurality of gate lines; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line; each of the plurality of gate lines is configured to provide a gate scanning signal to the data writing transistor in the corresponding pixel driving circuit; the gate of the driving transistor is connected to the third capacitor electrode; the first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode; and the orthographic projection of the corresponding gate line on the substrate substrate does not substantially overlap with the orthographic projection of the first node connection line on the substrate substrate.

[0004] Optionally, an orthographic projection of the corresponding gate line on the base substrate is separated from an orthographic projection of the first node connection line on the base substrate by an orthographic projection of the second capacitor electrode of the first capacitor on the base substrate.

[0005] Optionally, the orthographic projection of the second capacitor electrode of the first capacitor on the substrate substantially does not overlap with the orthographic projection of the corresponding gate line on the substrate, and substantially does not overlap with the orthographic projection of the first node connection line on the substrate.

[0006] Optionally, the orthographic projection of the corresponding gate line on the base substrate is separated from the orthographic projection of the third capacitor electrode of the second capacitor on the base substrate by the orthographic projection of the second capacitor electrode of the first capacitor on the base substrate.

[0007] Optionally, the orthographic projection of the second capacitor electrode of the first capacitor on the substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate, and does not substantially overlap with the orthographic projection of the third capacitor electrode of the second capacitor on the substrate.

[0008] Optionally, an orthographic projection of the corresponding gate line on the substrate substantially does not overlap with an orthographic projection of the active layer of the first reset transistor and the second electrode on the substrate.

[0009] Optionally, the second electrode of the first reset transistor crosses the second capacitor electrode.

[0010] Optionally, the array substrate includes a plurality of second capacitor electrode lines extending in a direction substantially parallel to the second direction; wherein each of the plurality of second capacitor electrode lines includes a second capacitor electrode connected together of a pixel driving circuit in the same row; wherein each pixel driving circuit also includes a light emitting control transistor and a third reset transistor; wherein a connecting line in the corresponding second capacitor electrode line connecting two adjacent second capacitor electrodes of two adjacent pixel driving circuits in the same row separates the second electrode of the light emitting control transistor from the second electrode of the third reset transistor, and separates the second electrode of the light emitting control transistor from the first electrode of the driving transistor.

[0011] Optionally, each pixel driving circuit also includes a second node connection line, which is connected to the second electrode of the light-emitting control transistor through a third via, connected to the first electrode of the driving transistor through a fourth via, and connected to the second electrode of the third reset transistor through a fifth via; the second electrode of the light-emitting control transistor and the first electrode of the driving transistor are located in the first semiconductor material layer; the corresponding second capacitor electrode line is located in the first gate metal layer, and the first gate metal layer is located on the side of the first semiconductor material layer away from the substrate; the second electrode of the third reset transistor is located in the second semiconductor material layer, and the second semiconductor material layer is located on the side of the first gate metal layer away from the substrate; and the second node connection line is located in the first signal line layer, and the first signal line layer is located on the side of the second semiconductor material layer away from the substrate.

[0012] Optionally, the second node connection line crosses the corresponding second capacitor electrode line.

[0013] Optionally, the array substrate also includes a plurality of voltage supply lines; wherein each pixel driving circuit also includes a light emitting control transistor and a voltage supply connection line; a corresponding voltage supply line among the plurality of voltage supply lines is connected to the voltage supply connection line through an eighth via hole; the voltage supply connection line is connected to the first electrodes of two adjacent light emitting control transistors of two adjacent pixel driving circuits in the same row through a ninth via hole; the first electrodes of the two adjacent light emitting control transistors of the two adjacent pixel driving circuits in the same row are part of the overall structure; and the voltage supply connection line is connected to the second capacitor electrodes of the first capacitors of the two adjacent pixel driving circuits in the same row through different via holes, respectively.

[0014] Optionally, the voltage supply connection line includes a main line portion extending in a direction substantially parallel to the second direction; a first extension portion, a second extension portion and a third extension portion extending away from the main line portion; the first extension portion, the second extension portion and the third extension portion respectively extend in a direction substantially parallel to the first direction; the corresponding voltage supply line among the multiple voltage supply lines is connected to the first extension portion through the eighth via hole; the first extension portion is connected to the first electrodes of the two adjacent light emitting control transistors of the two adjacent pixel driving circuits in the same row through the ninth via hole; the second extension portion is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel driving circuit; and the third extension portion is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit.

[0015] Optionally, the voltage supply connection line has substantial mirror symmetry relative to a plane substantially parallel to the first direction and substantially perpendicular to the light emitting surface of the array substrate.

[0016] Optionally, each pixel driving circuit also includes a compensation transistor; wherein the positive projection of the voltage supply connection line on the substrate substrate at least partially surrounds the positive projection of two adjacent compensation transistors of two adjacent pixel driving circuits in the same row on the substrate substrate; and the main line portion intersects the active layers of two adjacent data writing transistors of two adjacent pixel driving circuits in the same row.

[0017] Optionally, each pixel driving circuit also includes a compensation transistor; wherein, at least a portion of the orthographic projection of the second extension portion on the substrate separates the orthographic projection of at least the active layer of the first reset transistor in the first adjacent pixel driving circuit on the substrate from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel driving circuit on the substrate; and at least a portion of the orthographic projection of the third extension portion on the substrate separates the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel driving circuit on the substrate from the orthographic projection of at least the active layer of the compensation transistor in the second adjacent pixel driving circuit on the substrate.

[0018] Optionally, the array substrate further includes a plurality of first reset signal lines and a plurality of data lines; wherein, at least a portion of the orthographic projection of each of the plurality of first reset signal lines on the base substrate separates the orthographic projection of at least a portion of a first corresponding data line among the plurality of data lines on the base substrate from the orthographic projection of at least a portion of a second corresponding data line among the plurality of data lines on the base substrate, wherein the first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit.

[0019] Optionally, the array substrate also includes a plurality of first reset signal lines; wherein each of the plurality of first reset signal lines includes a plurality of loops arranged along a direction substantially parallel to the first direction; and each of the plurality of loops is connected to first electrodes of two adjacent first reset transistors of two adjacent pixel driving circuits in the same row.

[0020] Optionally, the array substrate also includes an interconnected voltage supply network; wherein the interconnected voltage supply network includes a plurality of voltage supply lines, a plurality of second capacitor electrode lines, and a plurality of voltage supply connection lines; the plurality of voltage supply lines extend in a direction substantially parallel to the first direction; the plurality of second capacitor electrode lines extend in a direction substantially parallel to the second direction; each of the plurality of second capacitor electrode lines includes a second capacitor electrode of a pixel driving circuit in the same row; and each of the plurality of voltage supply connection lines connects a corresponding voltage supply line among the plurality of voltage supply lines with a corresponding second capacitor electrode line among the plurality of second capacitor electrode lines.

[0021] Optionally, each pixel driving circuit further includes a compensation transistor and a third node connection line; wherein the third node connection line is connected to the second electrodes of the compensation transistor and the data writing transistor through a sixth via hole, and is connected to the first capacitor electrode of the first capacitor and the fourth capacitor electrode of the second capacitor through a seventh via hole; the orthographic projection of the third node connection line on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor on the substrate; and the third node connection line extends in a direction substantially parallel to the extension direction of the active layer of the compensation transistor.

[0022] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the invention.

[0024] Figure 1 is a plan view of a display substrate according to some embodiments of the present disclosure.

[0025] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0027] Figure 3 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 4A Schematic diagram showing a current path in a pixel driving circuit at stage t1 of an image frame in some embodiments according to the present disclosure.

[0029] Figure 4B Schematic diagram showing a current path in a pixel driving circuit at phase t2 of an image frame in some embodiments according to the present disclosure.

[0030] Figure 4C Schematic diagram showing a current path in a pixel driving circuit at phase t3 of an image frame in some embodiments according to the present disclosure.

[0031] Figure 4D Schematic diagram showing a current path in a pixel driving circuit at phase t4 of an image frame in some embodiments according to the present disclosure.

[0032] Figure 4ESchematic diagram showing a current path in a pixel driving circuit at stage t5 of an image frame in some embodiments according to the present disclosure.

[0033] Figure 5A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0034] Figure 5B It is shown Figure 5A Schematic diagram of the arrangement of pixel driving circuits in an array substrate depicted in FIG.

[0035] Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG.

[0036] Figure 5D It is shown Figure 5A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG.

[0037] Figure 5E It is shown Figure 5A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG.

[0038] Fig. 5F It is shown Figure 5A A schematic diagram of a via extending through a first interlayer dielectric layer in an array substrate is depicted in FIG.

[0039] Figure 5G It is shown Figure 5A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in FIG.

[0040] Figure 5H It is shown Figure 5A A schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate is depicted in FIG.

[0041] Fig.5I It is shown Figure 5A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG.

[0042] Figure 5J It is shown Figure 5A Schematic diagram of a via extending through a passivation layer in an array substrate depicted in FIG.

[0043] Figure 5K It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0044] Figure 5L It is shown Figure 5ASchematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG.

[0045] Figure 5M It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0046] Figure 5N It is shown Figure 5A Schematic diagram of a via extending through a second planarization layer in an array substrate depicted in FIG.

[0047] Fig.5O It is shown Figure 5A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0048] Fig. 6A is along Figure 5A Cross-sectional view along line A-A'.

[0049] Figure 6B is along Figure 5A Cross-sectional view along line BB'.

[0050] Figure 6C is along Figure 5A Cross-sectional view along line C-C'.

[0051] Fig.6D is along Figure 5A Cross-sectional view along line D-D'.

[0052] Fig. 7A It is shown Figure 5A A schematic diagram of the structure of the second semiconductor material layer and the first signal line layer in the array substrate depicted in FIG.

[0053] Figure 7B is a schematic diagram showing the structure of a reset signal line network in some embodiments according to the present disclosure.

[0054] Figure 7C is a schematic diagram showing the structure of a voltage supply network in some embodiments according to the present disclosure.

[0055] Fig.7D is a schematic diagram showing the structure of a second signal line layer in four adjacent pixel driving circuits in the same row in an array substrate according to some embodiments of the present disclosure.

[0056] Fig. 8A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0057] Figure 8B It is shown Fig. 8ASchematic diagram of the arrangement of pixel driving circuits in an array substrate depicted in FIG.

[0058] Figure 8C It is shown Fig. 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG.

[0059] Fig.8D It is shown Fig. 8A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG.

[0060] Fig. 8E It is shown Fig. 8A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG.

[0061] Figure 8F It is shown Fig. 8A A schematic diagram of a via extending through a first interlayer dielectric layer in an array substrate is depicted in FIG.

[0062] Figure 8G It is shown Fig. 8A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in FIG.

[0063] Figure 8H It is shown Fig. 8A A schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate is depicted in FIG.

[0064] Fig.8I It is shown Fig. 8A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG.

[0065] Figure 8J It is shown Fig. 8A Schematic diagram of a via extending through a passivation layer in an array substrate depicted in FIG.

[0066] Figure 8K It is shown Fig. 8A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0067] Figure 8L It is shown Fig. 8A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG.

[0068] Figure 8M It is shown Fig. 8A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0069] Figure 8N It is shown Fig. 8A Schematic diagram of a via extending through a second planarization layer in an array substrate depicted in FIG.

[0070] Fig.8O It is shown Fig. 8A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0071] Fig. 9 It is shown Figure 5A or Fig. 8A A schematic diagram of the layout of corresponding gate lines in the array substrate relative to the first node connection line is depicted in FIG.

[0072] Fig.10 It is shown Figure 5A or Fig. 8A Schematic diagram of the layout of corresponding second capacitor electrode lines relative to the second node connection lines in the array substrate depicted in FIG.

[0073] Fig.11 is a schematic diagram showing the structure of a voltage supply connection line in some embodiments according to the present disclosure.

[0074] Fig.12 It is shown Figure 5A or Fig. 8A Schematic diagram of the layout of voltage supply connection lines in the array substrate relative to the second semiconductor material layer depicted in FIG.

[0075] Fig.13 is a schematic diagram showing the layout of a plurality of first reset signal lines relative to a plurality of data lines in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0076] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0077] The present disclosure particularly provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel drive circuits and a plurality of gate lines. Optionally, each pixel drive circuit in the plurality of pixel drive circuits includes a drive transistor, a data write transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Optionally, each gate line in the plurality of gate lines is configured to provide a gate scan signal to the data write transistor in the corresponding pixel drive circuit. Optionally, the gate of the drive transistor is connected to the third capacitor electrode. Optionally, the first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode. Optionally, the positive projection of the corresponding gate line on the substrate substrate does not overlap substantially with the positive projection of the first node connection line on the substrate substrate.

[0078] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T2C driving circuit. In some embodiments, each of the plurality of pixel driving circuits is an 8T2C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0079] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd. Each sub-pixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through each of a plurality of voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0080] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2A In some embodiments, the pixel driving circuit includes: a driving transistor T3; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4; a data writing transistor T4 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The gate of the driving transistor T3 is connected to the third capacitor electrode Ce3.

[0081] In some embodiments, the pixel driving circuit also includes a compensation transistor T2 having a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a first electrode of a driving transistor T3, and a second electrode connected to the first capacitor electrode Ce1, a fourth capacitor electrode Ce4, and a second electrode of a data writing transistor T4.

[0082] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the second electrode of the data write transistor T4, the second electrode of the compensation transistor T2, and the fourth capacitor electrode Ce4. The second capacitor electrode Ce2 of the first capacitor C1 is connected to a corresponding voltage supply line (e.g., a high voltage signal line) among a plurality of voltage supply lines Vdd.

[0083] In some embodiments, the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the first capacitor electrode Ce1. The third capacitor electrode Ce3 of the second capacitor C2 is connected to the gate of the driving transistor T3.

[0084] In some embodiments, the pixel driving circuit also includes a light emitting control transistor T5 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to a first electrode of the driving transistor T3 and a first electrode of the compensation transistor T2.

[0085] In some embodiments, the pixel driving circuit further includes at least one reset transistor. In some embodiments, the pixel driving circuit further includes a first reset transistor T1 having a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to a gate of the driving transistor T3 and a third capacitor electrode Ce3 of the second capacitor C2.

[0086] In some embodiments, the pixel driving circuit also includes a second reset transistor T7, which has a gate connected to a corresponding second control signal line among a plurality of second control signal lines SL2, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the second electrode of the driving transistor T3 and the anode of the light-emitting element LE.

[0087] In some embodiments, the pixel driving circuit also includes a third reset transistor T6, which has a gate connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to the third reset signal line Vint3, and a second electrode connected to the first electrode of the driving transistor T3, the second electrode of the light emitting control transistor T5, and the second electrode of the compensation transistor T2.

[0088] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor T3, the third capacitor electrode Ce3, and the second electrode of the first reset transistor T1. The second node N2 is connected to the first electrode of the driving transistor T3, the second electrode of the light emitting control transistor T5, the first electrode of the compensation transistor T2, and the second electrode of the third reset transistor T6. The third node N3 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The fourth node N4 is connected to the second electrode of the driving transistor T3, the second electrode of the second reset transistor T7, and the anode of the light emitting element LE.

[0089] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0090] The present disclosure may be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Figure 2A , the data writing transistor T4, the compensation transistor T2, the first reset transistor T1 and the third reset transistor T6 are n-type transistors, such as metal oxide transistors, and the driving transistor T3, the light emission control transistor T5 and the second reset transistor T7 are p-type transistors, such as polysilicon transistors. For p-type transistors, the effective control signal (e.g., the conduction control signal) is a low voltage signal, and the invalid control signal (e.g., the cut-off control signal) is a high voltage signal. For n-type transistors, the effective control signal (e.g., the conduction control signal) is a high voltage signal, and the invalid control signal (e.g., the cut-off control signal) is a low voltage signal.

[0091] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2B The pixel driving circuit includes: a driving transistor T3; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4; a data writing transistor T4 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The gate of the driving transistor T3 is connected to the third capacitor electrode Ce3.

[0092] In some embodiments, the pixel driving circuit also includes a compensation transistor T2 having a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a first electrode of a driving transistor T3, and a second electrode connected to the first capacitor electrode Ce1, a fourth capacitor electrode Ce4, and a second electrode of a data writing transistor T4.

[0093] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the second electrode of the data write transistor T4, the second electrode of the compensation transistor T2, and the fourth capacitor electrode Ce4. The second capacitor electrode Ce2 of the first capacitor C1 is connected to a corresponding voltage supply line (e.g., a high voltage signal line) among a plurality of voltage supply lines Vdd.

[0094] In some embodiments, the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the first capacitor electrode Ce1. The third capacitor electrode Ce3 of the second capacitor C2 is connected to the gate of the driving transistor T3.

[0095] In some embodiments, the pixel driving circuit also includes a light emitting control transistor T5 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to a first electrode of the driving transistor T3 and a first electrode of the compensation transistor T2.

[0096] In some embodiments, the pixel driving circuit further includes at least one reset transistor. In some embodiments, the pixel driving circuit further includes a first reset transistor T1 having a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to a gate of the driving transistor T3 and a third capacitor electrode Ce3 of the second capacitor C2.

[0097] In some embodiments, the pixel driving circuit also includes a control transistor T8 having a gate connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to the second electrode of the driving transistor T3, and a second electrode connected to the anode of the light emitting element LE.

[0098] The inventors of the present disclosure have discovered Figure 2A The problem of leakage current through the driving transistor T3 in the pixel driving circuit depicted in FIG. In one example, the reset signal provided by the corresponding third reset signal line Vint3 has a voltage level of 6V, and the reset signal provided by the corresponding first reset signal line Vint1 has a voltage level of -3V. The reset signal provided by the corresponding third reset signal line Vint3 may flow through the driving transistor T3 and the second reset transistor T7. The inventors of the present disclosure have found that by setting the control transistor T8, the leakage current through the driving transistor T3 and the second reset transistor T7 can be prevented or avoided.

[0099] In some embodiments, the pixel driving circuit also includes a second reset transistor T7, which has a gate connected to a corresponding second control signal line among a plurality of second control signal lines SL2, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to a second electrode of the control transistor T8 and an anode of the light-emitting element LE.

[0100] In some embodiments, the pixel driving circuit also includes a third reset transistor T6, which has a gate connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to the third reset signal line Vint3, and a second electrode connected to the first electrode of the driving transistor T3, the second electrode of the light emitting control transistor T5, and the second electrode of the compensation transistor T2.

[0101] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor T3, the third capacitor electrode Ce3, and the second electrode of the first reset transistor T1. The second node N2 is connected to the first electrode of the driving transistor T3, the second electrode of the light emitting control transistor T5, the first electrode of the compensation transistor T2, and the second electrode of the third reset transistor T6. The third node N3 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The fourth node N4 is connected to the second electrode of the control transistor T8, the second electrode of the second reset transistor T7, and the anode of the light emitting element LE.

[0102] The present disclosure may be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Figure 2B , the data writing transistor T4, the compensation transistor T2, the first reset transistor T1 and the third reset transistor T6 are n-type transistors, such as metal oxide transistors, while the driving transistor T3, the light emission control transistor T5, the second reset transistor T7 and the control transistor T8 are p-type transistors, such as polysilicon transistors. For p-type transistors, the effective control signal (e.g., the conduction control signal) is a low voltage signal, and the invalid control signal (e.g., the cut-off control signal) is a high voltage signal. For n-type transistors, the effective control signal (e.g., the conduction control signal) is a high voltage signal, and the invalid control signal (e.g., the cut-off control signal) is a low voltage signal.

[0103] Figure 3 is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Figure 2A , Figure 2B as well as Figure 3 During one frame of image, the operation of the pixel driving circuit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5.

[0104] In the first phase t1, the conduction control signal is provided to the gate of the first reset transistor T1 through the corresponding first control signal line among the plurality of first control signal lines SL1, so that the first reset transistor T1 is turned on, thereby allowing the reset signal from the first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor T1 to the second electrode of the first reset transistor T1, and then to the third capacitor electrode Ce3 and the gate of the driving transistor T3. The node N1 (the gate of the driving transistor T3) is reset. The conduction control signal is also provided to the gate of the compensation transistor T2 through the corresponding first control signal line among the plurality of first control signal lines SL1, so that the compensation transistor T2 is turned on. The conduction control signal is provided to the gate of the second reset transistor T7 through the corresponding second control signal line among the plurality of second control signal lines SL2, so that the second reset transistor T7 is turned on, thereby allowing the reset signal from the corresponding first reset signal line among the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the second reset transistor T7 to the second electrode of the second reset transistor T7, and then to the anode of the light emitting element LE. The node N4 (the anode of the light emitting element LE) is reset. The off light emission control signal is provided to the gate of the light emission control transistor T5 through each light emission control signal line among the plurality of light emission control signal lines em, so that the light emission control transistor T5 is turned off. The off control signal is provided to the gate of the third reset transistor T6 through the corresponding third control signal line among the plurality of third control signal lines SL3, so that the third reset transistor T6 is turned off. The off gate signal is provided to the gate of the data write transistor T4 through the corresponding gate line among the plurality of gate lines GL, so that the data write transistor T4 is turned off. Figure 4A Schematic diagram showing a current path in a pixel driving circuit at stage t1 of an image frame in some embodiments according to the present disclosure. Figure 4A The shaded arrow in represents the current at stage t1.

[0105] In the second stage t2, the conduction control signal is provided to the gate of the first reset transistor T1 through the corresponding first control signal line among the plurality of first control signal lines SL1, so that the first reset transistor T1 is turned on, and is also provided to the gate of the compensation transistor T2 through the corresponding first control signal line among the plurality of first control signal lines SL1, so that the compensation transistor T2 is turned on. The conduction control signal is provided to the gate of the second reset transistor T7 through the corresponding second control signal line among the plurality of second control signal lines SL2, so that the second reset transistor T7 is turned on. The conduction control signal is provided to the gate of the third reset transistor T6 through the corresponding third control signal line among the plurality of third control signal lines SL3, so that the third reset transistor T6 is turned on, thereby allowing the reset signal from the corresponding third reset signal line among the plurality of third reset signal lines Vint3 to be transmitted from the first electrode of the third reset transistor T6 to the second electrode of the third reset transistor T6, and then to the first electrode of the driving transistor T3, the second electrode of the light emission control transistor T5, and the second electrode of the compensation transistor T2. The node N2 (the first electrode of the driving transistor T3) is charged with the voltage of the corresponding third reset signal line among the plurality of third reset signal lines Vint3. In some embodiments, the voltage of a corresponding third reset signal line among the plurality of third reset signal lines Vint3 has a high voltage level (eg, 6V) to ensure that Vgs<Vth, thereby ensuring that the driving transistor T3 remains in the on state. Figure 4B Schematic diagram showing a current path in a pixel driving circuit at stage t2 of an image frame in some embodiments according to the present disclosure. Figure 4B The shaded arrow in represents the current in phase t2.

[0106] In the third stage t3 (Vth compensation stage), the cut-off control signal is provided to the gate of the third reset transistor T6 through the corresponding third control signal line among the plurality of third control signal lines SL3, so that the third reset transistor T6 is cut off. In the third stage t3, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the second reset transistor T7 and the control transistor T8 remain turned on. The first reset signal is provided through the corresponding first reset signal line among the plurality of first reset signal lines Vint1, and the first reset signal passes through the second reset transistor T7 and the driving transistor T3 to charge the node N2 (the first electrode of the driving transistor T3). When the node N2 is charged to the moment when Vgs=Vth, the driving transistor T3 is cut off. Vgs=VN1-VN2, where VN1 is the voltage level of the node N1, and VN2 is the voltage level of the node N2. In the third stage t3, VN1=the voltage level of the first reset signal provided by the first reset signal line Vint1. Therefore, VN2 = VN1 - Vgs = VN1 - Vth, that is, VN2 = Vint1 - Vth. Since the compensation transistor T2 is turned on in the third phase t3, VN3 = VN2 = VN1 - Vth, where VN3 is the voltage level of the node N3. Figure 4C Schematic diagram showing a current path in a pixel driving circuit at phase t3 of an image frame in some embodiments according to the present disclosure. Figure 4C The shaded arrow in represents the current during the t3 phase.

[0107] In phase t4 (data writing phase), the cut-off control signal is provided to the gate of the first reset transistor T1 through the corresponding first control signal line among the plurality of first control signal lines SL1, so that the first reset transistor T1 is cut off, and is also provided to the gate of the compensation transistor T2 through the corresponding first control signal line among the plurality of first control signal lines SL1, so that the compensation transistor T2 is cut off. The cut-off control signal is provided to the gate of the second reset transistor T7 through the corresponding second control signal line among the plurality of second control signal lines SL2, so that the second reset transistor T7 is cut off. The turn-on gate signal is provided to the gate of the data writing transistor T4 through the corresponding gate line among the plurality of gate lines GL, so that the data writing transistor T4 is turned on, thereby allowing the data signal provided through the data line DL to be transferred from the first electrode of the data writing transistor T4 to the second electrode of the data writing transistor T4, and then to the node N3. In phase t3, VN1=the voltage level of the first reset signal provided by the first reset signal line Vint1 (expressed as Vre1). In phase t4, the voltage level of the node N3 changes from (Vre1-Vth) to the voltage level of the data signal Vdata. The change amount is ΔVN3=Vdata-Vre1+Vth. The second capacitor C2 induces voltage coupling at the node N1 through ΔVN3. Due to the voltage coupling, VN1 changes to (Vre1+ΔVN3)=(Vre1+Vdata-Vre1+Vth)=(Vdata+Vth), where Vdata is the voltage level of the data voltage signal, and Vth is the voltage level of the threshold voltage Th of the PN junction of the driving transistor T3. Figure 4D Schematic diagram showing a current path in a pixel driving circuit at phase t4 of an image frame in some embodiments according to the present disclosure. Figure 4D The shaded arrow in represents the current during the t4 phase.

[0108] In phase t5 (light emitting phase), the on-light emitting control signal is provided to the gate of the light emitting control transistor T5 through the corresponding light emitting control signal line among the plurality of light emitting control signal lines em, so that the light emitting control transistor T5 is turned on, thereby allowing the voltage supply voltage signal provided through the corresponding voltage supply line among the plurality of voltage supply lines Vdd to be transmitted from the first electrode of the light emitting control transistor T5 to the second electrode of the light emitting control transistor T5, and then from the first electrode of the driving transistor T3 to the second electrode of the driving transistor T3, and then from the first electrode of the control transistor T8 to the second electrode of the control transistor T8, and to the anode of the light emitting element LE. The light emitting element is configured to emit light. Figure 4E Schematic diagram showing a current path in a pixel driving circuit at stage t5 of an image frame in some embodiments according to the present disclosure. Figure 4E The shaded arrow in represents the current during the t5 phase.

[0109] Figure 5A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 5B It is shown Figure 5A Schematic diagram of the arrangement of pixel driving circuits in an array substrate depicted in FIG. Figure 5A and Figure 5B A portion of an array substrate having two adjacent pixel driving circuits (including PDC1 and PDC2) is depicted.

[0110] Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG. Figure 5D It is shown Figure 5A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG. Figure 5E It is shown Figure 5A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG. Fig. 5F It is shown Figure 5A A schematic diagram of a via extending through a first interlayer dielectric layer in an array substrate is depicted in FIG. Figure 5G It is shown Figure 5A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in FIG. Figure 5H It is shown Figure 5A A schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate is depicted in FIG. Fig.5I It is shown Figure 5A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG. Figure 5J It is shown Figure 5A Schematic diagram of a via extending through a passivation layer in an array substrate depicted in FIG. Figure 5K It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 5L It is shown Figure 5A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG. Figure 5M It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Figure 5N It is shown Figure 5A Schematic diagram of a via extending through a second planarization layer in an array substrate depicted in FIG. Fig.5O It is shown Figure 5A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Fig. 6A is along Figure 5A Cross-sectional view along line A-A'. Figure 6B is along Figure 5A Cross-sectional view along line BB'. Figure 6C is along Figure 5A Cross-sectional view along line C-C'. Fig.6D is along Figure 5A Cross-sectional view along line D-D'.

[0111] Reference FIG. 5A to FIG. 5O as well as FIG. 6A to FIG. 6D In some embodiments, the array substrate includes: a substrate BS; a buffer layer BUF, which is located on the substrate BS; a first semiconductor material layer SML1, which is located on a side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI, which is located on a side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1, which is located on a side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN, which is located on a side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2, which is located on a side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1, which is located on a side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2, which is located on a side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; a second interlayer dielectric Layer ILD2, which is located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; the third gate metal layer Gate3, which is located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, which is located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1, which is located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, which is located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second planarization layer SD2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; the second planarization layer PLN2, which is located on the side of the second signal line layer SD2 away from the first planarization layer PLN1; and the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SD2.

[0112] Reference Figure 2B , Figure 5A , Figure 5C , FIG. 6A to FIG. 6DIn some embodiments, the first semiconductor material layer SML1 includes at least an active layer of multiple transistors (including a driving transistor T3, a light emitting control transistor T5, a second reset transistor T7, and a control transistor T8) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least a corresponding portion of a first electrode of multiple transistors (including a driving transistor T3, a light emitting control transistor T5, a second reset transistor T7, and a control transistor T8) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least a corresponding portion of a second electrode of multiple transistors (including a driving transistor T3, a light emitting control transistor T5, a second reset transistor T7, and a control transistor T8) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode of multiple transistors (including a driving transistor T3, a light emitting control transistor T5, a second reset transistor T7, and a control transistor T8) of a pixel driving circuit. Various suitable semiconductor materials can be used to manufacture the first semiconductor material layer SML1. Examples of semiconductor materials used to manufacture the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0113] exist Figure 5C In the figure, the corresponding Figure 5B 1 and 2. The pixel driving circuit of PDC2 in FIG. 1 is a pixel driving circuit of PDC2, and the reference numerals represent the components of each of the multiple transistors (T3, T5, T7 and T8) in the pixel driving circuit. For example, the driving transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The light emitting control transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. The second reset transistor T7 includes an active layer ACT7, a first electrode S7, and a second electrode D7. The control transistor T8 includes an active layer ACT8, a first electrode S8, and a second electrode D8.

[0114] Optionally, the active layers (ACT3, ACT5, ACT7 and ACT8), the first electrodes (S3, S5, S7 and S8) and the second electrodes (D3, D5, D7 and D8) of the respective transistors (T3, T5, T7 and T8) are located in the same layer.

[0115] In some embodiments, the active layers (ACT3, ACT7, and ACT8), at least a portion of the first electrodes (S3, S7, and S8), and at least a portion of the second electrodes (D3, D7, and D8) of the plurality of transistors (T3, T7, and T8) in the pixel driving circuit are part of the overall structure. Optionally, in the same pixel driving circuit, the portion (ACT5, S5, D5) of the light emitting control transistor T5 located in the first semiconductor material layer is spaced apart from the overall structure (T3, T7, and T8).

[0116] In some embodiments, the active layer and at least a portion of the first electrode of two adjacent light emitting control transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) are part of an integral structure. Optionally, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent light emitting control transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) are part of an integral structure. Optionally, the first electrodes of two adjacent light emitting control transistors in two adjacent pixel drive circuits in the same row are directly connected to each other.

[0117] Reference Figure 2B , Figure 5A , Figure 5D and FIG. 6A to FIG. 6D In some embodiments, the first gate metal layer Gate1 includes a plurality of light emitting control signal lines em in a pixel driving circuit, a plurality of second control signal lines SL2, at least a portion of a plurality of third control signal lines (for example, corresponding third control signal line first branches SL3-1), a second capacitor electrode Ce2 of the first capacitor C1, and a third capacitor electrode Ce3 of the second capacitor C2.

[0118] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first gate metal layer Gate1. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of light emitting control signal lines em in the pixel driving circuit, a plurality of second control signal lines SL2, at least a portion of a plurality of third control signal lines (for example, the corresponding third control signal line first branch SL3-1), the second capacitor electrode Ce2 of the first capacitor C1, and the third capacitor electrode Ce3 of the second capacitor C2 are located in the same layer.

[0119] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of light emitting control signal lines em and a second capacitor electrode Ce2 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of light emitting control signal lines em and the second capacitor electrode Ce2 are located in the same layer. In another example, by simultaneously performing the steps of forming a plurality of light emitting control signal lines em and forming the second capacitor electrode Ce2, a plurality of light emitting control signal lines em and a second capacitor electrode Ce2 may be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0120] Reference Figure 5D , multiple second capacitor electrodes in multiple pixel driving circuits are connected to each other and are part of the overall structure. By connecting the second capacitor electrodes to each other, the resistance of the multiple voltage supply lines Vdd can be reduced because the second capacitor electrodes are electrically connected to the multiple voltage supply lines Vdd. The inventors of the present disclosure have found that this structure improves the display uniformity of the array substrate.

[0121] Reference Figure 2B , Figure 5A , Figure 5E and FIG. 6A to FIG. 6D In some embodiments, the second gate metal layer Gate2 includes at least a portion of a plurality of gate lines in the pixel driving circuit (e.g., a corresponding gate line first branch GL-1), at least a portion of a plurality of first control signal lines (e.g., a corresponding first control signal line first branch SL1-1), at least a portion of a plurality of third control signal lines (e.g., a corresponding third control signal line second branch SL3-2), a first capacitor electrode Ce1 of the first capacitor C1, and a fourth capacitor electrode Ce4 of the second capacitor C2. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second gate metal layer Gate2. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, at least a portion of the multiple gate lines in the pixel driving circuit (for example, the corresponding gate line first branch GL-1), at least a portion of the multiple first control signal lines (for example, the corresponding first control signal line first branch SL1-1), at least a portion of the multiple third control signal lines (for example, the corresponding third control signal line second branch SL3-2), the first capacitor electrode Ce1 of the first capacitor C1, and the fourth capacitor electrode Ce4 of the second capacitor C2 are located on the same layer.

[0122] Optionally, the first capacitor electrode Ce1 of the first capacitor C1 and the fourth capacitor electrode Ce4 of the second capacitor C2 in the pixel driving circuit are parts of an integral structure.

[0123] Fig. 5F A via extending through the first interlayer dielectric layer ILD1 is depicted in FIG.

[0124] Reference Figure 2B , Figure 5A , Figure 5G as well as FIG. 6A to FIG. 6DIn some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT1 of a first reset transistor T1 in a pixel driving circuit, an active layer ACT2 of a compensation transistor T2, an active layer ACT4 of a data writing transistor T4, and an active layer ACT6 of a third reset transistor T6. Optionally, the second semiconductor material layer SML2 also includes at least a portion of a first electrode S1 of a first reset transistor T1 in a pixel driving circuit, at least a portion of a first electrode S2 of a compensation transistor T2, at least a portion of a first electrode S4 of a data writing transistor T4, and at least a portion of a first electrode S6 of a third reset transistor T6. Optionally, the second semiconductor material layer SML2 also includes at least a portion of a second electrode D1 of a first reset transistor T1 in a pixel driving circuit, at least a portion of a second electrode D2 of a compensation transistor T2, at least a portion of a second electrode D4 of a data writing transistor T4, and at least a portion of a second electrode D6 of a third reset transistor T6. Optionally, the second semiconductor material layer SML2 includes: an active layer ACT1, a first electrode S1, and a second electrode D1 of a first reset transistor T1 in a pixel driving circuit; an active layer ACT2, a first electrode S2, and a second electrode D2 of a compensation transistor T2; an active layer ACT4, a first electrode S4, and a second electrode D4 of a data writing transistor T4; and an active layer ACT6, a first electrode S6, and a second electrode D6 of a third reset transistor T6. In the present array substrate, at least the active layer ACT1 of the first reset transistor T1, the active layer ACT2 of the compensation transistor T2, the active layer ACT4 of the data writing transistor T4, and the active layer ACT6 of the third reset transistor T6 are located in a layer different from at least the active layer of other transistors of the pixel driving circuit. Various suitable semiconductor materials can be used to manufacture the second semiconductor material layer SML2. Examples of semiconductor materials used to manufacture the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0125] exist Figure 5G In the figure, the corresponding Figure 5B 2. The pixel driving circuit of PDC2 in FIG. 2 is shown in FIG. 2 , and the reference numerals represent components of each of the plurality of transistors (T1, T2, T4, and T6) in the pixel driving circuit. For example, the first reset transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The compensation transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The data writing transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The third reset transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6.

[0126] In some embodiments, the active layers (ACT2, ACT4, and ACT6), at least a portion of the first electrodes (S2, S4, and S6), and at least a portion of the second electrodes (D2, D4, and D6) of the plurality of transistors (T2, T4, and T6) in the pixel driving circuit are part of the overall structure. Optionally, in the same pixel driving circuit, at least a portion (ACT1, S1, D1) of the first reset transistor T1 located at the second semiconductor material layer is spaced apart from the overall structure (T2, T4, and T6).

[0127] In some embodiments, the active layer and at least a portion of the first electrode of two adjacent third reset transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) are part of the overall structure. Optionally, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent third reset transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) are part of the overall structure. Optionally, in the overall structure, the first electrodes of two adjacent third reset transistors in two adjacent pixel drive circuits in the same row are directly connected to each other.

[0128] In some embodiments, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent third reset transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row); the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent compensation transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row); and the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent data write transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) are part of the overall structure. Optionally, in the overall structure, the first electrodes of two adjacent third reset transistors in two adjacent pixel drive circuits in the same row are directly connected to each other.

[0129] Figure 5H A via extending through the second interlayer dielectric layer ILD2 is depicted in FIG.

[0130] Reference Figure 2B , Figure 5A , Fig.5I , FIG. 6A to FIG. 6DIn some embodiments, the third gate metal layer Gate3 includes at least a portion of a plurality of gate lines (e.g., the corresponding gate line second branch GL-2), at least a portion of a plurality of first control signal lines (e.g., the corresponding first control signal second branch SL1-2), at least a portion of a plurality of third control signal lines (e.g., the corresponding third control signal line third branch SL3-3), a plurality of second reset signal lines Vint2, and a plurality of third reset signal lines Vint3. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the third gate metal layer Gate3. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like.

[0131] Figure 5J A via extending through the passivation layer PVX is depicted in FIG.

[0132] Reference Figure 2B , Figure 5A , Figure 5K , FIG. 6A to FIG. 6D In some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines Vint1; a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a data connection line Cld, a voltage supply connection line Clv, a reset signal connection line Cli and a relay electrode RE.

[0133] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, a plurality of first reset signal lines Vint1, a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a data connection line Cld, a voltage supply connection line Clv, a reset signal connection line Cli and a relay electrode RE are located in the same layer.

[0134] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to the node N1. Fig. 6AIn the pixel driving circuit, the first node connection line Cln1 is connected to the third capacitor electrode Ce3 of the second capacitor C2 through the first via hole v1, and is connected to the first reset transistor T1 (for example, connected to the second electrode D1 of the first reset transistor T1) through the second via hole v2. Optionally, the first node connection line Cln1 corresponds to Figure 2B Node N1 depicted in FIG. In one example, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. In another example, the second via v2 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0135] In some embodiments, the second node connection line Cln2 connects multiple components of the pixel driving circuit to the node N2. Figure 6B In the pixel driving circuit, the second node connection line Cln2 is connected to the second electrode D5 of the light emitting control transistor T5 through the third via hole v3, connected to the first electrode S3 of the driving transistor T3 through the fourth via hole v4, and connected to the second electrode D6 of the third reset transistor T6 through the fifth via hole v5. Optionally, the second node connection line Cln2 corresponds to Figure 2B Node N2 depicted in FIG. In one example, the third via v3 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the fifth via v5 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0136] In some embodiments, the third node connection line Cln3 connects multiple components of the pixel driving circuit to the node N3. Figure 6C In the pixel driving circuit, the third node connection line Cln3 is connected to the second electrode of the compensation transistor T2 and the data writing transistor T4 through the sixth via hole v6, and is connected to the first capacitor electrode Ce1 of the first capacitor C1 and / or the fourth capacitor electrode Ce4 of the second capacitor C2 through the seventh via hole v7. Optionally, the third node connection line Cln3 corresponds to Figure 2B In one example, the sixth via v6 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2. In another example, the seventh via v7 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1.

[0137] In some embodiments, the voltage supply connection line Clv connects multiple components of the pixel driving circuit to corresponding voltage supply lines among the multiple voltage supply connection lines Vdd. Fig.6D , in the pixel driving circuit, a corresponding voltage supply line among a plurality of voltage supply lines Vdd is connected to the voltage supply connection line Clv through an eighth via v8. The voltage supply connection line Clv is connected to the second electrode S5 of the light emitting control transistor T5 through a ninth via v9, and is connected to the second capacitor electrode Ce2 of the first capacitor C1 through a tenth via v10. In one example, the eighth via v8 extends through the first planarization layer PLN1. In another example, the ninth via v9 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the tenth via v10 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN.

[0138] In some embodiments, reference Fig. 6A A corresponding first reset signal line among the plurality of first reset signal lines Vint1 is connected to the first electrode S1 of the first reset transistor T1 through an eleventh via hole v11. In an example, the eleventh via hole v11 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0139] Fig. 7A It is shown Figure 5A Schematic diagram of the structure of the second semiconductor material layer and the first signal line layer in the array substrate depicted in FIG. Fig. 7A , the orthographic projection of the third node connection line Cln3 on the substrate substrate BS overlaps at least partially (e.g., at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98% or at least 99%) with the orthographic projection of the active layer ACT2 of the compensation transistor T2 on the substrate substrate BS. Optionally, the third node connection line Cln3 extends in a direction substantially parallel to the extension direction of the active layer ACT2 of the compensation transistor T2. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate substrate BS overlaps at least partially with the orthographic projection of the first electrode S2 of the compensation transistor T2 on the substrate substrate. Optionally, an orthographic projection of the third node connection line Cln3 on the base substrate BS at least partially overlaps with an orthographic projection of the second electrode D2 of the compensation transistor T2 on the base substrate BS.

[0140] Reference Figure 5K and Fig.6D In some embodiments, the voltage supply connection line Clv connects multiple components of two adjacent pixel drive circuits in the same row to corresponding voltage supply lines in multiple voltage supply lines Vdd. In some embodiments, the corresponding voltage supply line in the multiple voltage supply lines Vdd is connected to the voltage supply connection line Clv, for example, through the eighth via v8. The voltage supply connection line Clv is connected to the first electrodes of two adjacent light-emitting control transistors of two adjacent pixel drive circuits in the same row through the ninth via v9. The first electrodes of two adjacent light-emitting control transistors of two adjacent pixel drive circuits in the same row are part of the overall structure. The voltage supply connection line Clv is connected to the second capacitor electrodes of the first capacitors of two adjacent pixel drive circuits in the same row through different vias, respectively.

[0141] Figure 7B is a schematic diagram showing the structure of a reset signal line network in some embodiments of the present disclosure. Figure 7B In some embodiments, the array substrate includes an interconnected reset signal line network. In some embodiments, the interconnected reset signal line network includes a plurality of first reset signal lines Vint1 and a plurality of second reset signal lines Vint2 interconnected together. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the second direction DR2. Optionally, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are located in different layers. In one example, the plurality of first reset signal lines Vint1 are located in the first signal line layer, and the plurality of second reset signal lines Vint2 are located in the third gate metal layer. In some embodiments, each of the plurality of first reset signal lines Vint1 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2. In some embodiments, each of the plurality of second reset signal lines Vint2 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1, thereby forming an interconnected reset signal line network.

[0142] Reference Figure 7B In some embodiments, each of the plurality of first reset signal lines Vint1 includes a plurality of loops LP arranged in a direction substantially parallel to the first direction DR1. Each of the plurality of loops LP is connected to first electrodes of two adjacent first reset transistors of two adjacent pixel driving circuits in the same row.

[0143] Reference Figure 5A , Figure 5G , Fig.5I and Figure 5KIn some embodiments, the reset signal connection line Cli in the first signal line layer is connected to a corresponding third reset signal line in a plurality of third reset signal lines Vint3 in the third gate metal layer, and is connected to a first electrode S6 of a third reset transistor T6 in the second semiconductor material layer. Optionally, the reset signal connection line Cli is connected to first electrodes of two adjacent third reset transistors of two adjacent pixel driving circuits in the same row.

[0144] Figure 5L A via extending through the first planarization layer PLN1 is depicted in FIG.

[0145] Reference Figure 2B , Figure 5A , Figure 5M and FIG. 6A to FIG. 6D In some embodiments, the second signal line layer SD2 includes a plurality of voltage supply lines Vdd, a plurality of data lines DL and an anode connection pad ACP. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sublayers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, a plurality of voltage supply lines Vdd, a plurality of data lines DL and an anode connection pad ACP are located on the same layer.

[0146] Reference Figure 5A , Figure 5G , Figure 5K and Figure 5M In some embodiments, each of the multiple data lines DL in the second signal line layer is connected to a data connection line Cld in the first signal line layer, and the data connection line Cld is connected to a first electrode S4 of a data writing transistor T4 located in the second semiconductor material layer.

[0147] In some embodiments, each of the plurality of data lines DL includes a plurality of branches BL arranged in a direction substantially parallel to the first direction DR1. Each of the plurality of branches BL extends away from the body MB of the corresponding data line. In some embodiments, each of the plurality of branches BL is connected to a data connection line Cld in the first signal line layer. In some embodiments, the body MB of the corresponding data line extends in a direction substantially parallel to the first direction DR1, and each of the branches extends in a direction substantially parallel to the second direction DR2. The second direction DR2 is different from the first direction DR1. The second direction DR2 intersects with the first direction DR1.

[0148] Reference Figure 5A , Figure 5C , Figure 5K as well as Figure 5M In some embodiments, the anode connection pad ACP in the second signal line layer is connected to the relay electrode RE in the first signal line layer, and the relay electrode RE is connected to the second electrode of the second reset transistor T7 and the control transistor T8. The anode connection pad ACP is connected to a corresponding anode among the plurality of anodes.

[0149] Figure 5N A via extending through the second planarization layer PLN2 is depicted in FIG.

[0150] Reference Figure 5A , Fig.5O as well as FIG. 6A to FIG. 6D In some embodiments, the anode layer ADL includes a plurality of anodes AD.

[0151] Figure 7C is a schematic diagram showing the structure of a voltage supply network in some embodiments of the present disclosure. Figure 7CIn some embodiments, the array substrate includes an interconnected voltage supply network. In some embodiments, the interconnected voltage supply network includes a plurality of voltage supply lines Vdd, a plurality of second capacitor electrode lines Ce2L, and a plurality of voltage supply connection lines Clvs. Optionally, a plurality of voltage supply lines Vdd extend in a direction substantially parallel to the first direction DR1. Optionally, a plurality of second capacitor electrode lines Ce2L extend in a direction substantially parallel to the second direction DR2. Each second capacitor electrode line in the plurality of second capacitor electrode lines Ce2L includes a second capacitor electrode of a pixel driving circuit in the same row. Each voltage supply connection line in the plurality of voltage supply connection lines Clvs connects a corresponding voltage supply line in the plurality of voltage supply lines Vdd to a corresponding second capacitor electrode line in the plurality of second capacitor electrode lines Ce2L. Optionally, a plurality of voltage supply lines Vdd, a plurality of second capacitor electrode lines Ce2L, and a plurality of voltage supply connection lines Clvs are located in different layers. In one example, a plurality of second capacitor electrode lines Ce2L are located in the first gate metal layer, a plurality of voltage supply connection lines Clvs are located in the first signal line layer, and a plurality of voltage supply lines Vdd are located in the second signal line layer. In some embodiments, each of the plurality of voltage supply lines Vdd is connected to one or more second capacitor electrode lines Ce2L through one or more voltage supply connection lines Clvs, respectively. In some embodiments, each of the plurality of second capacitor electrode lines Ce2L is connected to one or more voltage supply lines Vdd through one or more voltage supply connection lines Clvs, respectively.

[0152] Reference Figure 5A In some embodiments, the array substrate includes a transmission region TR, and no conductive component of the pixel driving circuit exists in the transmission region TR. Figure 7B A corresponding loop among the plurality of loops of each first reset signal line surrounds the transmission region TR. An accessory may be installed at the transmission region TR. Examples of the accessory include a photoelectric sensor.

[0153] Reference Figure 5M , each of the plurality of data lines DL includes a body MB and a plurality of branches BL extending away from the body MB. The body MB includes a plurality of first segments SG1 and a plurality of second segments SG2 alternately connected together. Fig.7D Schematic diagram showing the structure of the second signal line layer in four adjacent pixel driving circuits in the same row in an array substrate according to some embodiments of the present disclosure. Figure 5M and Fig.7DIn some embodiments, the second segments of two adjacent data lines configured to provide data signals to two adjacent pixel driving circuits in the same row substantially surround the transmission region TR. In some embodiments, the first segment SG1 is substantially straight, and the second segment SG2 is a curved segment curved around the transmission region TR. In some embodiments, a virtual extension line of the first segment SG1 passes through the transmission region TR.

[0154] Fig. 8A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 8B It is shown Fig. 8A Schematic diagram of the arrangement of pixel driving circuits in an array substrate depicted in FIG. Figure 8C It is shown Fig. 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG. Fig.8D It is shown Fig. 8A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG. Fig. 8E It is shown Fig. 8A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG. Figure 8F It is shown Fig. 8A A schematic diagram of a via extending through a first interlayer dielectric layer in an array substrate is depicted in FIG. Figure 8G It is shown Fig. 8A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in FIG. Figure 8H It is shown Fig. 8A A schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate is depicted in FIG. Fig.8I It is shown Fig. 8A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG. Figure 8J It is shown Fig. 8A Schematic diagram of a via extending through a passivation layer in an array substrate depicted in FIG. Figure 8K It is shown Fig. 8A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 8L It is shown Fig. 8A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG. Figure 8M It is shown Fig. 8A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Figure 8N It is shown Fig. 8A Schematic diagram of a via extending through a second planarization layer in an array substrate depicted in FIG. Fig.8O It is shown Fig. 8A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0155] FIG. 8A to FIG. 8O The array substrate and FIG. 5A to FIG. 5O The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that: FIG. 8A to FIG. 8O The main body MB of each data line in the array substrate depicted in FIG. 1 extends substantially straight along a direction substantially parallel to the first direction DR1. Optionally, FIG. 8A to FIG. 8O The array substrate depicted in FIG. 1 does not include the transmissive region TR.

[0156] The inventors of the present disclosure have found that resistance-capacitance delay occurs in the relevant array substrate due to the presence of resistance and parasitic capacitance in the signal line. The resistance-capacitance delay is particularly significant when the signal transmission distance of the signal line becomes longer. The inventors of the present disclosure have found that the control signal (e.g., gate scanning signal) output from the scanning circuit to the sub-pixel row far away from the integrated circuit has a longer delay than the control signal output to the sub-pixel row closer to the integrated circuit. The inventors of the present disclosure have found that this is at least partially due to the resistance-capacitance delay in the signal line that transmits the signal (e.g., clock signal) from the integrated circuit to the multi-stage scanning circuit.

[0157] The inventors of the present disclosure have found that, in the relevant array substrate, the duration of the falling edge of the signal varies with the signal transmission distance of the signal line. When the signal transmission distance of the signal line becomes longer, the change in the duration of the falling edge becomes particularly significant. The inventors of the present disclosure have found that the gate scanning signal output from the scanning circuit to the sub-pixel far from the scanning circuit has a longer duration of the falling edge than the control signal output to the sub-pixel closer to the scanning circuit. When the scanning circuit outputs the cut-off gate scanning signal, due to the change in the duration of the falling edge, the voltage of the node N1 in the pixel driving circuit far from the scanning circuit is pulled down to a smaller extent than the voltage of the node N1 in the pixel driving circuit closer to the scanning circuit, resulting in poor display uniformity between the sub-pixel far from the scanning circuit and the sub-pixel closer to the scanning circuit.

[0158] The inventors of the present disclosure have found that surprisingly and unexpectedly, the array substrate according to the present disclosure alleviates the problem of display non-uniformity. The inventors of the present disclosure have found that the reduction of parasitic capacitance between the corresponding gate line and the N1 node can successfully eliminate the problem of display non-uniformity. Fig. 9 It is shown Figure 5A or Fig. 8A Schematic diagram of the layout of the corresponding gate lines in the array substrate relative to the first node connection line depicted in FIG. Fig. 9 The inventors of the present disclosure have found that the reduction of the parasitic capacitance between the corresponding gate lines among the plurality of gate lines GL and the first node connection line Cln1 can successfully improve the problem of display non-uniformity.

[0159] Reference Fig. 9In some embodiments, the orthographic projection of the corresponding gate line on the substrate substrate and the orthographic projection of the first node connection line Cln1 on the substrate substrate do not overlap substantially (e.g., at least 80% do not overlap, at least 90% do not overlap, at least 95% do not overlap, at least 99% do not overlap, or do not overlap at all). The parasitic capacitance between the corresponding gate line in the plurality of gate lines GL and the first node connection line Cln1 can be minimized. The first node connection line Cln1 at least partially corresponds to the node N1.

[0160] In some embodiments, the orthographic projection of the corresponding gate line on the substrate substrate is separated from the orthographic projection of the first node connection line Cln1 on the substrate substrate by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate. Optionally, the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate substrate (for example, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all), and does not substantially overlap with the orthographic projection of the first node connection line Cln1 on the substrate substrate (for example, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). By making the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate separate the orthographic projection of the corresponding gate line on the substrate substrate from the orthographic projection of the first node connection line Cln1 on the substrate substrate, the parasitic capacitance (for example, lateral parasitic capacitance) between the corresponding gate line in the plurality of gate lines GL and the node N1 can be further minimized.

[0161] In some embodiments, the orthographic projection of the corresponding gate line on the substrate substrate is separated from the orthographic projection of the third capacitor electrode Ce3 of the second capacitor C2 on the substrate substrate by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate. Optionally, the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate substrate (e.g., at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping), and does not substantially overlap with the orthographic projection of the third capacitor electrode Ce3 of the second capacitor C2 on the substrate substrate (e.g., at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping).

[0162] Comparing the array substrate according to the present disclosure with the related array substrate, the parasitic capacitance between the corresponding gate line and the node N1 is 1.33f in the array substrate according to the present disclosure and 2.72f in the related array substrate; in the related array substrate, the orthographic projection of the third capacitor electrode Ce3 on the substrate substrate separates the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate from the orthographic projection of the corresponding gate line on the substrate substrate (making the node N1 closer to the corresponding gate line). The voltage difference between the first nodes in the pixel driving circuit far away from the scanning circuit and the pixel driving circuit closer to the scanning circuit is 0.08V in the array substrate according to the present disclosure and 0.16V in the related array substrate. In the array substrate according to the present disclosure, the display non-uniformity is significantly improved.

[0163] In some embodiments, the first node connection line Cln1 is connected to the second electrode D1 of the first reset transistor T1 through the second via v2. Because the first reset transistor T1 is connected to the first node connection line Cln1, the inventors of the present disclosure have found that minimizing the parasitic capacitance between the first reset transistor T1 and the corresponding gate line further improves the display unevenness problem.

[0164] In some embodiments, the orthographic projection of the corresponding gate line on the substrate substrate does not substantially overlap with the orthographic projection of the second electrode D1 of the first reset transistor T1 on the substrate substrate (for example, at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping). Optionally, the orthographic projection of the corresponding gate line on the substrate substrate does not substantially overlap with the orthographic projection of the active layer ACT1 and the second electrode D1 of the first reset transistor T1 on the substrate substrate (for example, at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping). Optionally, the orthographic projection of the corresponding gate line on the substrate substrate does not substantially overlap with the orthographic projection of the first electrode S1, the active layer ACT1, and the second electrode D1 of the first reset transistor T1 on the substrate substrate (for example, at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping).

[0165] In some embodiments, the second electrode D1 of the first reset transistor T1 crosses the second capacitor electrode Ce2. Optionally, the orthographic projection of the second electrode D1 of the first reset transistor T1 on the substrate partially overlaps the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate.

[0166] In some embodiments, the orthographic projection of the corresponding gate line on the substrate substrate is separated from the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate by the orthographic projection of the corresponding light-emitting control signal line among the plurality of light-emitting control signal lines em on the substrate substrate. Optionally, the orthographic projection of each light-emitting control signal line em among the plurality of light-emitting control signal lines em on the substrate substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate substrate (for example, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all), and does not substantially overlap with the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate (for example, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0167] In some embodiments, the orthographic projection of the corresponding gate line on the substrate substrate is separated from the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate by the orthographic projection of the corresponding first control signal line among the plurality of first control signal lines SL1 on the substrate substrate. Optionally, the orthographic projection of each of the plurality of first control signal lines SL1 on the substrate substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate substrate (for example, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all), and does not substantially overlap with the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate substrate (for example, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0168] As previously combined Figure 7C As discussed, in some embodiments, the array substrate includes a plurality of second capacitor electrode lines Ce2L as part of an interconnected voltage supply network. The plurality of second capacitor electrode lines Ce2L extend in a direction substantially parallel to the second direction DR2. Each of the plurality of second capacitor electrode lines Ce2L includes a second capacitor electrode connected together for a pixel driving circuit in the same row.

[0169] Fig.10 It is shown Figure 5A or Fig. 8A Schematic diagram of the layout of the corresponding second capacitor electrode lines in the array substrate relative to the second node connection line depicted in FIG. Fig.10 and Figure 6B, the connection line CL connecting two adjacent second capacitor electrodes of two adjacent pixel driving circuits in the same row separates the second electrode D5 of the light emission control transistor T5 from the second electrode D6 of the third reset transistor T6, and separates the second electrode D5 of the light emission control transistor T5 from the first electrode S3 of the driving transistor T3. Because each second capacitor electrode line is located at the first gate metal layer, the second node connection line Cln2 cannot be set at the first gate metal layer.

[0170] In some embodiments, each second capacitor electrode line is located in the first gate metal layer, the second electrode D5 of the light emitting control transistor T5 and the first electrode S3 of the driving transistor T3 are located in the first semiconductor material layer, and the second electrode D6 of the third reset transistor T6 is located in the second semiconductor material layer. In some embodiments, in the pixel driving circuit, the second node connection line Cln2 is connected to the second electrode D5 of the light emitting control transistor T5 through the third via v3, connected to the first electrode S3 of the driving transistor T3 through the fourth via v4, and connected to the second electrode D6 of the third reset transistor T6 through the fifth via v5. In one example, the third via v3 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the fifth via v5 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0171] In some embodiments, the second node connection line Cln2 crosses the corresponding second capacitor electrode line. Optionally, the orthographic projection of the second node connection line Cln2 on the base substrate partially overlaps the orthographic projection of the corresponding second capacitor electrode line on the base substrate.

[0172] Reference FIG. 5A to FIG. 5O , FIG. 6A to FIG. 6D as well as FIG. 8A to FIG. 8O In some embodiments, first pixel driving circuits (eg, Figure 5B The corresponding layer of the PDC1) and the second pixel driving circuit (eg, Figure 5B The corresponding layers of PDC2 in the array substrate, for example, have substantial mirror symmetry with respect to each other about a plane perpendicular to the major surface of the array substrate and substantially parallel to the plurality of data lines.

[0173] As used herein, the term "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include an anode layer or a pixel defining layer. In some embodiments, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include a light shielding layer or a first signal line layer. In one example, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refer to at least one conductive layer of the first pixel driving circuit and a conductive layer of the second pixel driving circuit. In a specific example, the "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. In another specific example, the "corresponding layer" also includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, the "corresponding layer" includes a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, and a second signal line layer. In another specific example, the "corresponding layer" also includes a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, and a second planarization layer.

[0174] Reference FIG. 5A to FIG. 5O , FIG. 6A to FIG. 6D as well as FIG. 8A to FIG. 8O In some embodiments, the voltage supply connection line Clv connects multiple components of two adjacent pixel drive circuits in the same row to corresponding voltage supply lines in a plurality of voltage supply lines Vdd. In some embodiments, each voltage supply line in the plurality of voltage supply lines Vdd is connected to the voltage supply connection line Clv, for example, through an eighth via v8. The voltage supply connection line Clv is connected to the first electrodes of two adjacent light emitting control transistors of two adjacent pixel drive circuits in the same row through a ninth via v9. The first electrodes of two adjacent light emitting control transistors of two adjacent pixel drive circuits in the same row are part of the overall structure. The voltage supply connection line Clv is connected to the second capacitor electrodes of the first capacitors of two adjacent pixel drive circuits in the same row through different vias, respectively.

[0175] Fig.11 Schematic diagram showing the structure of voltage supply connection lines in some embodiments of the present disclosure. Fig.11In some embodiments, the voltage supply connection line includes: a main line portion MLP extending in a direction substantially parallel to the second direction DR2; a first extension portion E1, a second extension portion E2, and a third extension portion E3 extending away from the main line portion MLP. The first extension portion E1, the second extension portion E2, and the third extension portion E3 extend in directions substantially parallel to the first direction DR1, respectively. In some embodiments, each of the multiple voltage supply lines Vdd is connected to the first extension portion E1, for example, through an eighth via v8. The first extension portion E1 is connected to the first electrodes of two adjacent light-emitting control transistors of two adjacent pixel drive circuits in the same row through a ninth via v9. The second extension portion E2 is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel drive circuit, and the third extension portion E3 is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel drive circuit.

[0176] In some embodiments, the voltage supply connection line Clv has a substantial mirror symmetry with respect to a plane substantially parallel to the first direction DR1 and substantially perpendicular to the light emitting surface of the array substrate. Optionally, the plane intersects with the first extension portion. Optionally, the plane intersects with the eighth via hole v8 and the ninth via hole v9.

[0177] Fig.12 It is shown Figure 5A or Fig. 8A Schematic diagram of the layout of the voltage supply connection lines in the array substrate relative to the second semiconductor material layer as depicted in FIG. Fig.11 and Fig.12 In some embodiments, the positive projection of the voltage supply connection line Clv on the substrate substrate at least partially surrounds the positive projection of two adjacent compensation transistors of two adjacent pixel drive circuits in the same row on the substrate substrate. The main line portion MLP of the voltage supply connection line Clv crosses the active layers of two adjacent data write transistors of two adjacent pixel drive circuits in the same row. Optionally, the positive projection of the voltage supply connection line Clv on the substrate substrate partially overlaps the positive projection of the active layers of two adjacent data write transistors of two adjacent pixel drive circuits in the same row on the substrate substrate.

[0178] In some embodiments, the orthographic projection of the first extension E1 on the substrate separates the orthographic projection of the second electrode of the compensation transistor in the first adjacent pixel driving circuit from the orthographic projection of the second electrode of the compensation transistor in the second adjacent pixel driving circuit on the substrate.

[0179] In some embodiments, at least part of the orthographic projection of the second extension E2 on the substrate separates the orthographic projection of at least the active layer of the first reset transistor in the first adjacent pixel drive circuit from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel drive circuit on the substrate substrate. Because the voltage supply connection line Clv is provided with a constant voltage, this layout can effectively prevent interference between signals in the first reset transistor and the compensation transistor.

[0180] In some embodiments, at least part of the orthographic projection of the third extension E3 on the substrate separates the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel drive circuit from the orthographic projection of at least the active layer of the compensation transistor in the second adjacent pixel drive circuit on the substrate substrate. Because the voltage supply connection line Clv is provided with a constant voltage, this layout can effectively prevent interference between signals in the first reset transistor and the compensation transistor.

[0181] Fig.13 Schematic diagram showing the layout of a plurality of first reset signal lines relative to a plurality of data lines in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. Fig.13 , Figure 5K and Figure 5M In some embodiments, at least a portion of the positive projection of each of the plurality of first reset signal lines Vint1 on the substrate separates at least a portion of the positive projection of a first corresponding data line in the plurality of data lines DL on the substrate from at least a portion of the positive projection of a second corresponding data line in the plurality of data lines DL on the substrate, wherein the first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit. Optionally, at least a portion of the positive projection of each of the plurality of first reset signal lines Vint1 on the substrate separates the positive projection of a second segment of a first corresponding data line in the plurality of data lines DL on the substrate from the positive projection of a second segment of a second corresponding data line in the plurality of data lines DL on the substrate, wherein the first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit. Because each first reset signal line is supplied with a constant voltage, this layout can effectively prevent interference between data signals in two adjacent data lines among the plurality of data lines DL configured to supply data signals to two adjacent pixel driving circuits.

[0182] In some embodiments, each of the plurality of gate lines comprises a plurality of branches. FIG. 5A to FIG. 5O as well as FIG. 8A to FIG. 8O In some embodiments, each gate line includes a corresponding gate line first branch GL-1 and a corresponding gate line second branch GL-2. Optionally, the orthographic projection of the corresponding gate line first branch GL-1 on the substrate substrate overlaps at least partially with the orthographic projection of the corresponding gate line second branch GL-2 on the substrate substrate. In one example, the corresponding gate line first branch GL-1 is located in the second gate metal layer. In another example, the corresponding gate line second branch GL-2 is located in the third gate metal layer.

[0183] In some embodiments, each of the plurality of first control signal lines SL1 includes a plurality of branches. FIG. 5A to FIG. 5O as well as FIG. 8A to FIG. 8O , each first control signal line includes a corresponding first control signal line first branch SL1-1 and a corresponding first control signal line second branch SL1-2. Optionally, the orthographic projection of the corresponding first control signal line first branch SL1-1 on the substrate substrate at least partially overlaps with the orthographic projection of the corresponding first control signal line second branch SL1-2 on the substrate substrate. In one example, the corresponding first control signal line first branch SL1-1 is located in the second gate metal layer. In another example, the corresponding first control signal line second branch SL1-2 is located in the third gate metal layer.

[0184] In some embodiments, each of the plurality of third control signal lines comprises a plurality of branches. FIG. 5A to FIG. 5O as well as FIG. 8A to FIG. 8O , each third control signal line includes a corresponding third control signal line first branch SL3-1, a corresponding third control signal line second branch SL3-2, and a corresponding third control signal line third branch SL3-3. Optionally, the orthographic projection of the corresponding third control signal line first branch SL3-1 on the substrate substrate overlaps at least partially with the orthographic projection of the corresponding third control signal line second branch SL3-2 on the substrate substrate, and overlaps at least partially with the orthographic projection of the corresponding third control signal line third branch SL3-3 on the substrate substrate. Optionally, the orthographic projection of the corresponding third control signal line second branch SL3-2 on the substrate substrate overlaps at least partially with the orthographic projection of the corresponding third control signal line third branch SL3-3 on the substrate substrate. In one example, the corresponding third control signal line first branch SL3-1 is located in the first gate metal layer. In another example, the corresponding third control signal line second branch SL3-2 is located in the second gate metal layer. In another example, the corresponding third control signal line third branch SL3-3 is located in the third gate metal layer.

[0185] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0186] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of pixel drive circuits and forming a plurality of gate lines. Optionally, forming each pixel drive circuit in the plurality of pixel drive circuits includes forming a drive transistor, forming a data write transistor, forming a first reset transistor, forming a first capacitor having a first capacitor electrode and a second capacitor electrode, forming a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and forming a first node connection line. Optionally, each gate line in the plurality of gate lines is configured to provide a gate scan signal to the data write transistor in the corresponding pixel drive circuit. Optionally, the gate of the drive transistor is connected to the third capacitor electrode. Optionally, the first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode. Optionally, the positive projection of the corresponding gate line on the substrate substrate does not substantially overlap with the positive projection of the first node connection line on the substrate substrate.

[0187] For the purpose of illustration and description, the above description of the embodiment of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiment disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and changes will be obvious to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to specific examples, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate comprising a plurality of pixel driving circuits and a plurality of gate lines; in, Each of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line; Each of the plurality of gate lines is configured to provide a gate scanning signal to the data writing transistor in the corresponding pixel driving circuit; The gate of the driving transistor is connected to the third capacitor electrode; The first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode; as well as The orthographic projection of the corresponding gate line on the substrate substantially does not overlap with the orthographic projection of the first node connection line on the substrate.

2. The array substrate according to claim 1, wherein: An orthographic projection of the corresponding gate line on the base substrate is separated from an orthographic projection of the first node connection line on the base substrate by an orthographic projection of the second capacitor electrode of the first capacitor on the base substrate.

3. The array substrate according to claim 2, wherein: The orthographic projection of the second capacitor electrode of the first capacitor on the base substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the base substrate, and does not substantially overlap with the orthographic projection of the first node connection line on the base substrate.

4. The array substrate according to claim 3, wherein: The orthographic projection of the corresponding gate line on the base substrate is spaced apart from the orthographic projection of the third capacitor electrode of the second capacitor on the base substrate by the orthographic projection of the second capacitor electrode of the first capacitor on the base substrate.

5. The array substrate according to claim 4, wherein: The orthographic projection of the second capacitor electrode of the first capacitor on the base substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the base substrate, and does not substantially overlap with the orthographic projection of the third capacitor electrode of the second capacitor on the base substrate.

6. The array substrate according to any one of claims 1 to 5, wherein: An orthographic projection of the corresponding gate line on the base substrate does not substantially overlap with an orthographic projection of the active layer of the first reset transistor and the second electrode on the base substrate.

7. The array substrate according to any one of claims 1 to 6, wherein: The second electrode of the first reset transistor intersects the second capacitor electrode.

8. The array substrate according to any one of claims 1 to 7, comprising a plurality of second capacitor electrode lines extending in a direction substantially parallel to the second direction; in, Each of the plurality of second capacitor electrode lines comprises second capacitor electrodes of pixel driving circuits in the same row connected together; Wherein, each pixel driving circuit further includes a light emitting control transistor and a third reset transistor; Among them, the connecting line connecting two adjacent second capacitor electrodes of two adjacent pixel driving circuits in the same row in the corresponding second capacitor electrode line separates the second electrode of the light emitting control transistor from the second electrode of the third reset transistor, and separates the second electrode of the light emitting control transistor from the first electrode of the driving transistor.

9. The array substrate according to claim 8, wherein: Each pixel driving circuit further includes a second node connection line, the second node connection line is connected to the second electrode of the light emitting control transistor through a third via hole, connected to the first electrode of the driving transistor through a fourth via hole, and connected to the second electrode of the third reset transistor through a fifth via hole; The second electrode of the light emitting control transistor and the first electrode of the driving transistor are located in a first semiconductor material layer; The corresponding second capacitor electrode line is located in a first gate metal layer, and the first gate metal layer is located on a side of the first semiconductor material layer away from the substrate; The second electrode of the third reset transistor is located in a second semiconductor material layer, and the second semiconductor material layer is located on a side of the first gate metal layer away from the substrate; as well as The second node connection line is located in a first signal line layer, and the first signal line layer is located on a side of the second semiconductor material layer away from the base substrate.

10. The array substrate according to claim 8, wherein: The second node connection line crosses the corresponding second capacitor electrode line.

11. The array substrate according to any one of claims 1 to 7, further comprising a plurality of voltage supply lines; in, Each pixel driving circuit further includes a light emitting control transistor and a voltage supply connection line; A corresponding voltage supply line among the plurality of voltage supply lines is connected to the voltage supply connection line through an eighth via; The voltage supply connection line is connected to the first electrodes of two adjacent light emission control transistors of two adjacent pixel driving circuits in the same row through a ninth via hole; The first electrodes of two adjacent light emission control transistors of two adjacent pixel driving circuits in the same row are part of the integral structure; as well as The voltage supply connection lines are connected to the second capacitor electrodes of the first capacitors of two adjacent pixel driving circuits in the same row through different vias, respectively.

12. The array substrate according to claim 11, wherein: The voltage supply connection line comprises a main line portion extending in a direction substantially parallel to the second direction; a first extension portion, a second extension portion and a third extension portion extending away from the main line portion; The first extension portion, the second extension portion, and the third extension portion extend along directions substantially parallel to the first direction respectively; The corresponding voltage supply line among the plurality of voltage supply lines is connected to the first extension portion through the eighth via; The first extension portion is connected to the first electrodes of the two adjacent light emission control transistors of the two adjacent pixel driving circuits in the same row through the ninth via hole; The second extension is connected to a second capacitor electrode of a first capacitor of a first adjacent pixel driving circuit; as well as The third extension portion is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit.

13. The array substrate according to claim 12, wherein: The voltage supply connection line has substantial mirror symmetry relative to a plane substantially parallel to the first direction and substantially perpendicular to the light emitting surface of the array substrate.

14. The array substrate according to claim 12, wherein: Each pixel driving circuit further includes a compensation transistor; wherein the orthographic projection of the voltage supply connection line on the substrate at least partially surrounds the orthographic projections of two adjacent compensation transistors of two adjacent pixel driving circuits in the same row on the substrate; and The main line portion crosses active layers of two adjacent data writing transistors of two adjacent pixel driving circuits in the same row.

15. The array substrate according to claim 12, wherein: Each pixel driving circuit further includes a compensation transistor; wherein at least a portion of the orthographic projection of the second extension portion on the substrate separates the orthographic projection of at least the active layer of the first reset transistor in the first adjacent pixel driving circuit on the substrate from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel driving circuit on the substrate; and At least a portion of the orthographic projection of the third extension portion on the substrate separates the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel driving circuit on the substrate from the orthographic projection of at least the active layer of the compensation transistor in the second adjacent pixel driving circuit on the substrate.

16. The array substrate according to any one of claims 1 to 15, further comprising a plurality of first reset signal lines and a plurality of data lines; in, At least a portion of the orthographic projection of each first reset signal line among the multiple first reset signal lines on the substrate separates at least a portion of the orthographic projection of a first corresponding data line among the multiple data lines on the substrate from at least a portion of the orthographic projection of a second corresponding data line among the multiple data lines on the substrate, wherein the first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit.

17. The array substrate according to any one of claims 1 to 15, further comprising a plurality of first reset signal lines; in, Each of the plurality of first reset signal lines includes a plurality of loops arranged in a direction substantially parallel to the first direction; as well as Each of the plurality of loops is connected to first electrodes of two adjacent first reset transistors of two adjacent pixel driving circuits in the same row.

18. The array substrate according to any one of claims 1 to 10, further comprising an interconnection voltage supply network; in, The interconnected voltage supply network includes a plurality of voltage supply lines, a plurality of second capacitor electrode lines, and a plurality of voltage supply connection lines; the plurality of voltage supply lines extending in a direction substantially parallel to the first direction; the plurality of second capacitor electrode lines extending in a direction substantially parallel to the second direction; Each of the plurality of second capacitor electrode lines includes a second capacitor electrode of a pixel driving circuit in a same row; as well as Each of the plurality of voltage supply connection lines connects a corresponding one of the plurality of voltage supply lines with a corresponding second capacitor electrode line of the plurality of second capacitor electrode lines.

19. The array substrate according to any one of claims 1 to 14 and claims 16 to 18, wherein: Each pixel driving circuit further includes a compensation transistor and a third node connection line; wherein the third node connection line is connected to the second electrodes of the compensation transistor and the data writing transistor through a sixth via hole, and is connected to the first capacitor electrode of the first capacitor and the fourth capacitor electrode of the second capacitor through a seventh via hole; The orthographic projection of the third node connection line on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor on the substrate; and The third node connection line extends in a direction substantially parallel to an extension direction of the active layer of the compensation transistor. 20 . A display device comprising the array substrate according to claim 1 and one or more integrated circuits connected to the array substrate.

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