Gate drive circuit

Abstract

Each of a plurality of stages of the gate drive circuit according to an embodiment of the present invention comprises: a first node control unit that controls the voltage level of a first node and the voltage level of a second node; a second node control unit that controls the voltage level of a third node; and a first output section outputting a first voltage or a second voltage as a gate signal in accordance with the voltage level of the second node and the voltage level of the third node, in which the first node control section may be provided with: a single gate transistor including one gate; and a dual gate transistor including a pair of gates disposed on different layers with a semiconductor interposed therebetween.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device, and more particularly, to a gate driving circuit that outputs a gate signal and a display device including the gate driving circuit. Background Art

[0002] The display device may include, for example, a pixel unit including a plurality of pixels, a gate drive circuit, a data drive circuit, and a controller. The gate drive circuit may include a plurality of stages connected to a plurality of gate lines, respectively. The plurality of stages may provide gate signals, respectively, through the gate lines connected to the plurality of stages, in response to a signal from the controller. Summary of the invention

[0003] Technical issues

[0004] Embodiments of the present disclosure include a gate driving circuit that can stably output a gate signal and a display device including the gate driving circuit. However, these issues are merely examples and the scope of the present disclosure is not limited thereto.

[0005] Technical Solution

[0006] According to an embodiment, a gate driving circuit includes a plurality of stages. Each of the plurality of stages includes: a first node controller configured to control a voltage level of a first node and a voltage level of a second node; a second node controller configured to control a voltage level of a third node; and a first output unit connected between a first voltage input terminal to which a first voltage is input and a second voltage input terminal to which a second voltage is input, and the first output unit is configured to output the first voltage or the second voltage as a gate signal according to the voltage level of the second node and the voltage level of the third node. The first node controller includes: a first transistor connected between an input terminal to which a start signal is input and the first node, and the first transistor includes a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the first node and a third voltage input terminal to which a third voltage is input, and the second transistor includes a first gate and a second gate connected to the third node; and a third transistor connected between the first node and the second node, and the third transistor includes a gate connected to the first voltage input terminal. The first gate and the second gate of the second transistor may be arranged in different layers, and a semiconductor is arranged between the first gate and the second gate of the second transistor.

[0007] In an embodiment, a voltage level of the first voltage is greater than a voltage level of the second voltage, and a voltage level of the third voltage is less than the voltage level of the second voltage.

[0008] In an embodiment, the first transistor includes a plurality of sub-transistors connected in series to each other, and a gate of each of the plurality of sub-transistors is connected to the first clock terminal.

[0009] In an embodiment, the second transistor includes a plurality of sub-transistors connected in series to each other, and a first gate and a second gate of each of the plurality of sub-transistors are connected to the third node.

[0010] In an embodiment, each of the first transistor and the second transistor includes a pair of sub-transistors connected in series to each other, and each of the plurality of stages further includes a leakage prevention transistor including a gate connected to the first node, a first end connected to the first voltage input terminal, and a second end connected to an intermediate node of the pair of sub-transistors.

[0011] In an embodiment, the first node controller further includes: a fourth transistor connected between the second node and a second clock terminal to which a second clock signal is input, and the fourth transistor includes a gate connected to the second node; and a first capacitor connected between the second node and the fourth transistor. The first clock signal and the second clock signal may repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal may be shifted from the first clock signal by half a cycle.

[0012] In an embodiment, the second node controller includes a fourth transistor connected between the third node and the third voltage input terminal, and the fourth transistor includes a first gate connected to the first node and a second gate connected to the third voltage input terminal.

[0013] In an embodiment, the second node controller further includes: a fifth transistor connected between the first clock terminal and the fourth node, and the fifth transistor includes a gate connected to the first node; a sixth transistor connected between the first voltage input terminal and the fourth node, and the sixth transistor includes a first gate and a second gate connected to the first clock terminal; a seventh transistor connected between the fourth node and the fifth node, and the seventh transistor includes a gate connected to the first voltage input terminal; a capacitor connected between the fifth node and the sixth node; an eighth transistor connected between the second clock terminal to which the second clock signal is input and the sixth node, and the eighth transistor includes a gate connected to the fifth node; and a ninth transistor connected between the first voltage input terminal and the third node, and the ninth transistor includes a first gate and a second gate connected to the sixth node. The first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted from the first clock signal by half a cycle.

[0014] In an embodiment, the first output unit includes: a first pull-up transistor connected between the first voltage input terminal and the first output node, and the first pull-up transistor includes a gate connected to the second node; and a first pull-down transistor connected between the second voltage input terminal and the first output node, and the first pull-down transistor includes a gate connected to the third node.

[0015] In an embodiment, the first output unit includes: a first pull-up transistor connected between the first voltage input terminal and the first output node, and the first pull-up transistor includes a first gate and a second gate connected to the second node; and a first pull-down transistor connected between the second voltage input terminal and the first output node, and the first pull-down transistor includes a first gate and a second gate connected to the third node. The first gate and the second gate of each of the first pull-up transistor and the first pull-down transistor are arranged in different layers, and a semiconductor is arranged between the first gate and the second gate of each of the first pull-up transistor and the first pull-down transistor.

[0016] In an embodiment, each of the multiple stages also includes: a second output unit connected between the first voltage input terminal and the second voltage input terminal, and the second output unit is configured to output the first voltage or the second voltage as a carry signal according to the voltage level of the second node and the voltage level of the third node.

[0017] In an embodiment, the second output unit may include: a pull-up transistor connected between the first voltage input terminal and the output node, and the pull-up transistor includes a first gate and a second gate connected to the second node; and a pull-down transistor connected between the second voltage input terminal and the output node, and the pull-down transistor includes a first gate and a second gate connected to the third node. The first gate and the second gate of each of the pull-up transistor and the pull-down transistor are provided in different layers, and a semiconductor is provided between the first gate and the second gate of each of the pull-up transistor and the pull-down transistor.

[0018] In an embodiment, a start signal of a first stage among the plurality of stages is an external signal, and start signals of a second stage and subsequent stages among the plurality of stages are carry signals output from a previous stage.

[0019] In an embodiment, a turn-on time of the gate signal and a turn-on time of the carry signal are greater than a turn-on time of the external signal.

[0020] In an embodiment, the timing when the turn-on time of the start signal of the first stage starts is the same as the timing when the turn-on time of the first gate signal output from the first stage starts, and the timing when the turn-on time of the gate signal output from the second stage and each of the subsequent stages starts is delayed by a certain time from the timing when the turn-on time of the start signal of each of the second stage and the subsequent stages starts.

[0021] In an embodiment, each of the multiple stages also includes: a reset transistor connected between the first node and the second voltage input terminal, and the reset transistor is configured to reset the first node, and the reset transistor includes a first gate and a second gate connected to a reset terminal to which a reset signal is input.

[0022] According to an embodiment of the present disclosure, a gate driving circuit includes a plurality of stages, and each of the plurality of stages includes: a first node controller configured to control a voltage level of a first node and a voltage level of a second node; a second node controller configured to control a voltage level of a third node; and a first output unit connected between a first voltage input terminal to which a first voltage is input and a second voltage input terminal to which a second voltage is input, and the first output unit is configured to output the first voltage or the second voltage as a gate signal according to the voltage level of the second node and the voltage level of the third node. The first node controller includes: a first transistor including a pair of first sub-transistors connected in series to each other between an input terminal to which a start signal is input and the first node, and a gate of each of the first sub-transistors is connected to a first clock terminal to which a first clock signal is input; a second transistor including a pair of second sub-transistors connected in series to each other between the first node and a third voltage input terminal to which a third voltage is input, and a gate of each of the second sub-transistors is connected to the third node; and a third transistor connected between the first node and the second node, and the third transistor including a gate connected to the first voltage input terminal. A voltage level of the first voltage is greater than a voltage level of the second voltage, and a voltage level of the third voltage is less than the voltage level of the second voltage.

[0023] In an embodiment, each of the multiple stages further includes: a leakage prevention transistor including a gate connected to the first node, a first end connected to the first voltage input terminal, and a second end connected to an intermediate node of the first sub-transistor and an intermediate node of the second sub-transistor.

[0024] In an embodiment, the second node controller further includes: a fourth transistor connected between the first clock terminal and a fourth node, and the fourth transistor includes a gate connected to the first node; a fifth transistor connected between the first voltage input terminal and the fourth node, and the fifth transistor includes a gate connected to the first clock terminal; a sixth transistor connected between the fourth node and the fifth node, and the sixth transistor includes a gate connected to the first voltage input terminal; a capacitor connected between the fifth node and the sixth node; a seventh transistor connected between the second clock terminal to which the second clock signal is input and the sixth node, and the seventh transistor includes a gate connected to the fifth node; an eighth transistor connected between the first voltage input terminal and the third node, and the eighth transistor includes a gate connected to the sixth node; and a ninth transistor connected between the third node and the third voltage input terminal, and the ninth transistor includes a gate connected to the first node. The first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted from the first clock signal by half a cycle.

[0025] In an embodiment, each of the multiple stages also includes: a second output unit connected between the first voltage input terminal and the second voltage input terminal, and the second output unit is configured to output the first voltage or the second voltage as a carry signal according to the voltage level of the second node and the voltage level of the third node.

[0026] Beneficial Effects

[0027] According to the embodiment, a gate driving circuit that can stably output a gate signal and a display device including the gate driving circuit are provided. However, the scope of the present disclosure is not limited to these effects, and various extensions can be made without departing from the spirit of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram showing a display device according to an embodiment.

[0029] Figure 2 is a schematic diagram showing a gate driving circuit according to an embodiment.

[0030] Figure 3 is a schematic diagram showing a gate driving circuit according to an embodiment.

[0031] Figure 4 According to the embodiment Figure 3 Timing diagram of the input / output signals of the gate drive circuit.

[0032] Figure 5 It is composed Figure 3 A circuit diagram of an example of a stage of a gate drive circuit.

[0033] Figure 6a and Figure 6b It is shown Figure 5 0048 is a timing diagram of an example of the operation of the stages shown in FIG.

[0034] Figures 7 to 9 are circuit diagrams showing various modified examples of the stage circuit according to the embodiment.

[0035] Fig.10 is a schematic diagram showing a gate driving circuit according to an embodiment.

[0036] Fig.11 According to the embodiment, Fig.10 Schematic timing diagram of the gate signal output by the gate driving circuit.

[0037] Fig.12 is a schematic block diagram of a display device according to an embodiment.

[0038] Fig.13 According to the embodiment Fig.12 Circuit diagram of a pixel.

[0039] Fig.14 According to the embodiment, Fig.12 The gate drive circuit outputs to Fig.12 Schematic timing diagram of the gate signal of a pixel.

[0040] Fig.15 is a schematic block diagram of a display device according to an embodiment.

[0041] Fig.16 It is shown Fig.15 A circuit diagram of an example of a pixel.

[0042] Fig.17 According to the embodiment, Fig.15 The gate drive circuit outputs to Fig.16 Schematic timing diagram of the gate signal of a pixel.

[0043] Fig.18 is a diagram showing a method according to an embodiment of the present invention. Fig.15 A circuit diagram of an example of a pixel.

[0044] Fig.19 According to the embodiment, Fig.15 The gate drive circuit outputs to Fig.18 Schematic timing diagram of the gate signal of a pixel. DETAILED DESCRIPTION

[0045] Best Mode for Carrying Out the Invention

[0046] According to an embodiment, a gate driving circuit includes a plurality of stages. Each of the plurality of stages includes: a first node controller configured to control a voltage level of a first node and a voltage level of a second node; a second node controller configured to control a voltage level of a third node; and a first output unit connected between a first voltage input terminal to which a first voltage is input and a second voltage input terminal to which a second voltage is input, and the first output unit is configured to output a first voltage or a second voltage as a gate signal according to a voltage level of a second node and a voltage level of a third node. The first node controller includes: a first transistor connected between an input terminal to which a start signal is input and a first node, and the first transistor includes a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between a first node and a third voltage input terminal to which a third voltage is input, and the second transistor includes a first gate and a second gate connected to a third node; and a third transistor connected between a first node and a second node, and the third transistor includes a gate connected to a first voltage input terminal. The first gate and the second gate of the second transistor may be arranged in different layers and a semiconductor is arranged between the first gate and the second gate of the second transistor.

[0047] Embodiments of the present invention

[0048] Hereinafter, the embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. According to the following description in conjunction with the accompanying drawings, the features and advantages of the embodiments of the present disclosure will be more apparent. However, the present embodiments can be implemented in various forms and are not limited to the embodiments presented below.

[0049] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and these elements are not limited by these terms. Therefore, the "first" element in an embodiment may be described as the "second" element in another embodiment.

[0050] Unless the context clearly indicates otherwise, terms in the singular may include plural forms.

[0051] It will also be understood that, unless otherwise defined, the terms “comprising,” “including,” and “having” used herein specify the presence of stated elements, but do not exclude the presence or addition of other elements.

[0052] It will be understood that when a component such as a film, region, layer, etc. is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, the component may be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may also be one or more intervening components.

[0053] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0054] In the specification, expressions such as "A and / or B" may include A, B, or A and B. Expressions such as "at least one of A and B" may include A, B, or A and B.

[0055] In the following embodiments, when X and Y are connected to each other, it may include a case where X and Y are electrically connected, a case where X and Y are functionally connected, and a case where X and Y are directly connected. Here, X and Y may be objects (e.g., devices, components, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, for example, a certain connection relationship is not limited to the connection relationship described in the drawings or the detailed description, and may include connection relationships other than the connection relationships described in the drawings or the detailed description.

[0056] The case where X and Y are electrically connected to each other may include, for example, the case where one or more elements (eg, switches, transistors, capacitors, inductors, resistors, diodes, etc.) capable of achieving electrical connection between X and Y are connected between X and Y.

[0057] In the following embodiments, the term "on" used in conjunction with the device state may refer to the activation state of the device, and the term "off" may refer to the disabled state of the device. The term "on / activation (on)" used in conjunction with the signal received by the device may refer to the signal that activates the device, and the term "off / disable (off)" may refer to the signal that disables the device. The device can be activated by a high level voltage or a low level voltage. For example, a P-channel transistor is activated by a low level voltage, and an N-channel transistor is activated by a high level voltage. Therefore, it should be understood that the "on / activation (on)" voltage for P-channel transistors and N-channel transistors is in opposite (low to high) voltage levels. In the following, the voltage that turns on the transistor is referred to as the on voltage, and the voltage that turns off the transistor is referred to as the off voltage. The period during which the on voltage of the signal is maintained is referred to as the on voltage period, and the period during which the off voltage is maintained is referred to as the off voltage period.

[0058] Figure 1 is a schematic diagram showing a display device according to an embodiment.

[0059] The display device 10 according to the embodiment may be a display device such as an organic light emitting display device, an inorganic light emitting display device (eg, an inorganic electroluminescent (EL) display device), and a quantum dot light emitting display device, for example.

[0060] Reference Figure 1 The display device 10 according to the embodiment may include a pixel unit 110 (also referred to as a display panel), a gate driving circuit 130 , a data driving circuit 150 , and a controller 170 .

[0061] A plurality of pixels PX and a plurality of signal lines through which electrical signals are input to the pixels PX may be arranged in the pixel unit 110 .

[0062] The pixels PX may be repeatedly arranged in a first direction (x direction or row direction) and a second direction (y direction or column direction). The pixels PX may be arranged in various forms such as a stripe array, a PenTile array, a diamond array, and a mosaic array, and may display an image. Each of the plurality of pixels PX may include an organic light emitting diode as a display element and a pixel circuit connected to the organic light emitting diode. The pixel circuit may include a plurality of transistors and at least one capacitor.

[0063] In an embodiment, a plurality of transistors included in the pixel unit 110 may be N-type oxide thin film transistors. For example, the oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. However, this is only an example, and the N-type transistor is not limited thereto. For example, according to an embodiment, the active pattern (semiconductor layer) included in the transistor may include an inorganic material semiconductor (e.g., amorphous silicon, polycrystalline silicon) or an organic material semiconductor, etc.

[0064] The signal lines through which the electrical signals are input to the pixels PX may include a plurality of gate lines GL1 to GLn extending in the first direction and a plurality of data lines DL1 to DLm extending in the second direction, wherein n and m are positive integers. The gate lines GL1 to GLn may be spaced apart from each other in the second direction, and the gate signals may be transmitted to the pixels PX through the gate lines GL1 to GLn. The data lines DL1 to DLm may be spaced apart from each other in the first direction, and the data signals may be transmitted to the pixels PX through the data lines DL1 to DLm. Each of the plurality of pixels PX may be connected to at least one gate line corresponding thereto among the gate lines GL1 to GLn and a data line corresponding thereto among the data lines DL1 to DLm.

[0065] The gate driving circuit 130 may be connected to the gate lines GL1 to GLn, may generate a gate signal in response to a gate driving control signal GCS received from the controller 170, and may sequentially provide the generated gate signals to the gate lines GL1 to GLn, respectively. The gate lines GL1 to GLn may be connected to the gates of the transistors included in each of the plurality of pixels PX. The gate signal may be a gate control signal that controls the turning on and off of the transistors connected to the gate lines. The gate signal may be a square wave signal including an on-voltage that turns on the transistor and an off-voltage that turns off the transistor. In an embodiment, the on-voltage may be a high level voltage, and the off-voltage may be a low level voltage.

[0066] When a period during which the on-voltage of the signal is maintained is the on-time and a period during which the off-voltage of the signal is maintained is the off-time, the on-time and the off-time of the gate signal may be determined according to the function of a transistor receiving the gate signal in each of the plurality of pixels PX. The gate driving circuit 130 may include a shift register that sequentially generates gate signals and outputs the gate signals.

[0067] The data driving circuit 150 may be connected to the data lines DL1 to DLm and may provide data signals to the data lines DL1 to DLm in response to the data driving control signal DCS received from the controller 170. The data signals provided to the data lines DL1 to DLm may be provided to the pixels PX having received the gate signals.

[0068] When the display device 1 is an organic light emitting display device, the first power voltage ELVDD and the second power voltage ELVSS may be provided to the pixel PX of the pixel unit 110. The first power voltage ELVDD may be a high level voltage provided to the first electrode (pixel electrode or anode) of the organic light emitting diode included in each of the plurality of pixels PX. The second power voltage ELVSS may be a low level voltage provided to the second electrode (counter electrode or cathode) of the organic light emitting diode. The first power voltage ELVDD and the second power voltage ELVSS may be driving voltages that cause the pixel PX to emit light.

[0069] The controller 170 may generate a gate driving control signal GCS and a data driving control signal DCS based on an external input signal. The controller 170 may provide the gate driving control signal GCS to the gate driving circuit 130 and provide the data driving control signal DCS to the data driving circuit 150.

[0070] Figure 2 is a schematic diagram showing a gate driving circuit according to an embodiment.

[0071] Reference Figure 2 , the gate driving circuit 130 may include a plurality of stages ST1 to STn. The stages ST1 to STn may sequentially output gate signals GS1 to GSn to the gate lines GL1 to GLn.

[0072] Each of the stages ST1 to STn may be connected to a gate line of a corresponding row. Each of the stages ST1 to STn may receive at least one clock signal CLK and at least one voltage signal VG, generate corresponding gate signals GS1, GS2, ... GSn, and provide the generated gate signals GS1, GS2, ... GSn to the gate lines GL connected thereto. For example, the i-th stage STi may provide the i-th gate signal GSi to the gate line GL of the i-th row. In other words, each of the stages ST1 to STn may provide the corresponding gate signals GS1, GS2, ... GSn to the gate lines GL of the corresponding rows.

[0073] Each of the stages ST1 to STn may receive at least one clock signal CLK and at least one voltage signal VG and provide a carry signal CR to a previous stage or a subsequent stage. The previous stage may be a stage before at least one stage, and the subsequent stage may be a stage after at least one stage.

[0074] Figure 3 is a schematic diagram showing a gate driving circuit according to an embodiment. Figure 4 According to the embodiment Figure 3 Timing diagram of the input / output signals of the gate drive circuit.

[0075] Reference Figure 3 , the gate driving circuit 130 may include stages ST1 to STn. The number of stages provided in the gate driving circuit 130 may be variously changed according to the number of rows provided in the pixel unit 110.

[0076] The stages ST1 to STn may respectively output gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] in response to the start signal. For example, the nth stage STn may output the nth gate signal GS[n] to the nth gate line. An external signal FLM as a start signal for controlling the timing of the first gate signal GS[1] may be provided to the first stage ST1. Hereinafter, the on-voltage may represent a high-level voltage, and the off-voltage may represent a low-level voltage.

[0077] Each of the stages ST1 to STn may include an input terminal IN, first and second clock terminals CK1 and CK2 , first and second voltage input terminals V1 and V2 and V3 , a reset terminal RS, and first and second output terminals OUT1 and OUT2 .

[0078] The start signal may be input (provided) to the input terminal IN. The start signal may be an external signal FLM or a previous carry signal. In an embodiment, the external signal FLM may be input to the input terminal IN of the first stage ST1, and the carry signal (e.g., the previous carry signal) output from the previous stage may be input to the input terminal IN of each of the second stage ST2 to the nth stage STn except the first stage ST1. For example, the (n-1)th carry signal CR[n-1] output from the (n-1)th stage STn-1 may be input to the input terminal IN of the nth stage STn.

[0079] The first clock signal CLK1 or the second clock signal CLK2 can be input to the first clock terminal CK1 and the second clock terminal CK2. The first clock signal CLK1 and the second clock signal CLK2 can be alternately input to the first clock terminal CK1 of the stage ST1 to STn. The second clock signal CLK2 and the first clock signal CLK1 can be alternately input to the second clock terminal CK2 of the stage ST1 to STn. For example, the first clock signal CLK1 and the second clock signal CLK2 can be respectively input to the first clock terminal CK1 and the second clock terminal CK2 of the odd-numbered stage (ST1, ST3, ...). The second clock signal CLK2 and the first clock signal CLK1 can be respectively input to the first clock terminal CK1 and the second clock terminal CK2 of the even-numbered stage (ST2, ST4, ...).

[0080] like Figure 4As shown in, the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals that repeat the first voltage VGH of the high level and the third voltage VGL2 of the low level. The cycle of the first clock signal CLK1 and the second clock signal CLK2 may be 4 horizontal periods (4H) including one high level and one low level. The first clock signal CLK1 and the second clock signal CLK2 may be signals having the same waveform and shifted phase. For example, the second clock signal CLK2 may have the same waveform as the first clock signal CLK1, and the second clock signal CLK2 may be input with a phase shifted at a specific interval (a phase delayed at a specific interval). According to an embodiment, the second clock signal CLK2 is shifted from the first clock signal CLK1 by half a cycle, and the on-time of the second clock signal CLK2 does not overlap with the on-time of the first clock signal CLK1. The on-time of the first clock signal CLK1 and the second clock signal CLK2 may be less than about 2H or may be about 2H.

[0081] The reset signal ESR may be input to the reset terminal RS. The reset signal ESR is input as a turn-on voltage of the first voltage VGH at a specific timing, and is input as a turn-off voltage of the third voltage VGL2 at other timings. For example, when power is input to the display device (power-on), the reset signal ESR is input as the first voltage VGH to the stages ST1 to STn for a certain time, and after the certain time has passed, the reset signal ESR may be input as the second voltage VGL or the third voltage VGL2 to the stages ST1 to STn. While the stages ST1 to STn operate to generate the gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n], the reset signal ESR may be input as the second voltage VGL or the third voltage VGL2. Figure 4 An example is shown in which the reset signal ESR of the third voltage VGL2 is input during the operation of the stages ST1 to STn.

[0082] The first voltage VGH may be input to the first voltage input terminal V1, the second voltage VGL may be input to the second voltage input terminal V2, and the third voltage VGL2 may be input to the third voltage input terminal V3. The third voltage VGL2 may have a lower voltage level than the second voltage VGL. The first voltage VGH, the second voltage VGL, and the third voltage VGL2 as global signals may be input from, for example, Figure 1 Inputs such as the controller 170 and / or the power supply unit shown in .

[0083] The gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] can be output from the first output terminal OUT1. The gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] output from the first output terminal OUT1 of the stage ST1 to STn can be shifted by 2H. Each gate signal can be provided to the pixel through the corresponding output line (e.g., gate line). The on-time of the gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] can be different from the on-time of the external signal FLM as the start signal. For example, the on-time of the external signal FLM can be 8H, and the on-time of the gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] can be 10H.

[0084] The carry signal may be output from the second output terminal OUT2. The carry signals CR[1], CR[2], CR[3], CR[4], ... and CR[n] output from the second output terminal OUT2 of the stage ST1 to STn may be shifted by 2H. Each carry signal may be input to the input terminal IN of the subsequent stage. The on-time of the carry signals CR[1], CR[2], CR[3], CR[4], ... and CR[n] may be different from the on-time of the external signal FLM. For example, the on-time of the external signal FLM may be 8H, and the on-time of the carry signals CR[1], CR[2], CR[3], CR[4], ... and CR[n] may be 10H. The on-time of the carry signal outputted from each of the stages ST1 to STn and the on-time of the gate signal may be the same. The on-time of the carry signal outputted from each of the stages ST1 to STn and the on-time of the gate signal may overlap with each other.

[0085] The timing (rise time) of the start of the turn-on time of the external signal FLM input to the first stage ST1 and the rise time of the gate signal GS[1] and the carry signal CR[1] output from the first stage ST1 may be the same. The rise time of the previous carry signal input to each of the second stage ST2 to the nth stage STn and the rise time of the gate signal and the carry signal output from each of the second stage ST2 to the nth stage STn may be different from each other. The rise time of the gate signal and the carry signal output from each of the second stage ST2 to the nth stage STn may be delayed by a certain time (e.g., half a cycle of the clock signal) from the rise time of the previous carry signal input to each of the second stage ST2 to the nth stage STn. For example, the rise time of the gate signal GS[2] and the carry signal CR[2] output from the second stage ST2 may be shifted by 2H from the rise time of the previous carry signal CR[1].

[0086] According to an embodiment, at least one dummy stage may be further provided in the rear end of the nth stage STn which is the last stage among the stages ST1 to STn. A carry signal output from the second output terminal OUT2 of the nth stage may be input to an input terminal of the dummy stage. According to an embodiment, the dummy stage is not connected to the Figure 1 According to an embodiment, the dummy stage may be connected to a dummy gate line, which may be connected to a dummy pixel that does not display an image, and the dummy stage is not used to display an image. According to an embodiment, the dummy pixel may be omitted, and the dummy gate line may be provided only around the pixel unit 110.

[0087] Figure 5 It is composed Figure 3 A circuit diagram of an example of a stage of a gate drive circuit.

[0088] Each of the stages ST1 to STn has a plurality of nodes, and hereinafter, some of the plurality of nodes may be referred to as first and second output nodes ON1 and ON2 and first, second, and third nodes Q, QF, and QB.

[0089] Figure 5 The first stage STk (where k is a positive integer) is a stage corresponding to the kth row of the pixel unit 110, and may receive the (k-1)th carry signal CR[k-1] from the previous stage, output the kth gate signal GS[k] to the gate line of the kth row, and output the kth carry signal CR[k] to the subsequent stage. When k is 1, that is, in the case of the first stage ST1, the external signal FLM may be input to the input terminal IN as a start signal.

[0090] In an odd-numbered stage, the first clock terminal CK1 can receive the first clock signal CLK1, and the second clock terminal CK2 can receive the second clock signal CLK2. In an even-numbered stage, the first clock terminal CK1 can receive the second clock signal CLK2, and the second clock terminal CK2 can receive the first clock signal CLK1. For ease of explanation, the following describes a case where the stage STk is an odd-numbered stage in which a previous carry signal is received in the input terminal IN as an example.

[0091] In an embodiment, the voltage level of the turn-on voltage (turn-on voltage level) is a high level, and the voltage level of the turn-off voltage (turn-off voltage level) is a low level.

[0092] The stage STk may include a first node controller 210 (also referred to as a first node controller circuit), a second node controller 220 (also referred to as a second node controller circuit), a first output unit 230 (also referred to as a first output circuit), a second output unit 240 (also referred to as a second output circuit), a leakage control unit 250 (also referred to as a leakage control circuit), and a reset unit 260 (also referred to as a reset circuit). Each of the first node controller 210, the second node controller 220, the first output unit 230, the second output unit 240, the leakage control unit 250, and the reset unit 260 may include at least one transistor.

[0093] The at least one transistor may be an N-type transistor. The at least one transistor may be an N-type oxide semiconductor transistor. Some of the at least one transistor may each be a single-gate transistor including a gate. Some of the at least one transistor may each be a double-gate transistor including a pair of first gates and a second gate. In an embodiment, the pair of first gates and the second gate may be arranged in different layers respectively and the semiconductor is arranged between the pair of first gates and the second gate. For example, the first gate may be a top gate arranged on the top of the semiconductor, and the second gate may be a bottom gate arranged at the bottom of the semiconductor. In an embodiment, the pair of first gates and the second gate may receive the same signal. In an embodiment, the pair of first gates and the second gate may receive different signals.

[0094] The previous carry signal CR[k-1] as a start signal can be input to the input terminal IN, the first clock signal CLK1 can be input to the first clock terminal CK1, the second clock signal CLK2 can be input to the second clock terminal CK2, the first voltage VGH can be input to the first voltage input terminal V1, the second voltage VGL can be input to the second voltage input terminal V2, the third voltage VGL2 can be input to the third voltage input terminal V3, and the reset signal ESR can be input to the reset terminal RS.

[0095] The first node controller 210 may be connected between the input terminal IN and the second node QF. The first node controller 210 may control the voltage level of the first node Q and the voltage level of the second node QB based on the previous carry signal CR[k-1] and the third voltage VGL2. The first node controller 210 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first node controller 210 may also include a first capacitor C1. The first transistor T1, the third transistor T3, and the fourth transistor T4 may each be a single-gate transistor. The second transistor T2 may be a double-gate transistor.

[0096] The first transistor T1 may include a plurality of sub-transistors connected in series between the input terminal IN and the first node Q. The sub-transistors may include a pair of first-first transistors T1-1 and first-second transistors T1-2. The first-first transistors T1-1 and the first-second transistors T1-2 may each include a gate connected to the first clock terminal CK1. The first transistor T1 may be turned on when the first clock signal CLK1 is a high-level voltage, and may control the voltage level of the first node Q according to the voltage of the previous carry signal CR[k-1].

[0097] The second transistor T2 may include a plurality of sub-transistors connected in series between the first node Q and the third voltage input terminal V3. The sub-transistors may include a pair of second-first transistors T2-1 and second-second transistors T2-2. The second-first transistor T2-1 and the second-second transistor T2-2 may each include a first gate and a second gate connected to the third node QB. The second transistor T2 may be turned on when the voltage of the third node QB is a high-level voltage, and the voltage of the first node Q may be controlled to be the voltage level of the third voltage VGL2 input to the third voltage input terminal V3.

[0098] The third transistor T3 may be connected between the first node Q and the second node QF. The third transistor T3 may include a gate connected to the first voltage input terminal V1. The third transistor T3 may control the voltage level of the second node QF to the voltage level of the first node Q by electrically connecting the first node Q and the second node QF to each other. The third transistor T3 may be always turned on in response to the first voltage VGH input to the first voltage input terminal V1, and may prevent a line voltage drop between the first node Q and the second node QF, etc. Therefore, the on-voltage of the kth gate signal GS[k] may be stably output.

[0099] The fourth transistor T4 may be connected between the second clock terminal CK2 and the first capacitor C1. The fourth transistor T4 may include a gate connected to the second node QF. The fourth transistor T4 may be turned on when the voltage of the second node QF is a high level voltage, and may transmit the second clock signal CLK2 input to the second clock terminal CK2 to one end of the first capacitor C1.

[0100] The first capacitor C1 may be connected between the second node QF and the fourth transistor T4. When the second clock signal CLK2 is a high level voltage, the voltage of the second node QF may be boosted to a voltage greater than the first voltage VGH (eg, twice VGH) through the first capacitor C1 and the turned-on fourth transistor T4.

[0101] The second node controller 220 may be connected between the first node Q and the third node QB. The second node controller 220 may control the voltage of the third node QB by inverting the voltage level of the first node Q. The second node controller 220 may control the voltage of the third node QB based on the first voltage VGH and the third voltage VGL2.

[0102] The second node controller 220 may include a second-first node controller that controls the third node QB to be a low-level voltage when the voltage of the first node Q is a high-level voltage, and a second-second node controller that controls the voltage of the third node QB to be a high-level voltage when the voltage of the first node Q is a low-level voltage. The second-first node controller may include a tenth transistor T10. The second-second node controller may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2. The fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 may each be a single-gate transistor. The sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 may each be a double-gate transistor.

[0103] The fifth transistor T5 may include a plurality of sub-transistors connected in series between the first clock terminal CK1 and the fourth node SR_QB. The sub-transistors may include a pair of fifth-first transistors T5-1 and fifth-second transistors T5-2. The fifth-first transistors T5-1 and fifth-second transistors T5-2 may each include a gate connected to the first node Q. The fifth transistor T5 may be turned on when the voltage of the first node Q is a high-level voltage, and may transmit the first clock signal CLK1 input to the first clock terminal CK1 to the fourth node SR_QB.

[0104] The sixth transistor T6 may be connected between the first voltage input terminal V1 and the fourth node SR_QB. The sixth transistor T6 may include a first gate and a second gate connected to the first clock terminal CK1. The sixth transistor T6 may be turned on when the first clock signal CLK1 is a high level voltage, and may transmit the first voltage VGH input to the first voltage input terminal V1 to the fourth node SR_QB.

[0105] The seventh transistor T7 may be connected between the fourth node SR_QB and the fifth node SR_QBF. The seventh transistor T7 may include a gate connected to the first voltage input terminal V1. The seventh transistor T7 may be always turned on in response to the first voltage VGH to electrically connect the fourth node SR_QB and the fifth node SR_QBF to each other, thereby controlling the voltage level of the fifth node SR_QBF to the voltage level of the fourth node SR_QB.

[0106] The eighth transistor T8 may be connected between the second clock terminal CK2 and the sixth node QBE. The eighth transistor T8 may include a gate connected to the fifth node SR_QBF. The eighth transistor T8 may be turned on when the voltage of the fifth node SR_QBF is a high level voltage, and may transmit the second clock signal CLK2 input to the second clock terminal CK2 to the sixth node QBE.

[0107] The ninth transistor T9 may be connected between the first voltage input terminal V1 and the third node QB. The ninth transistor T9 may include a first gate and a second gate connected to the sixth node QBE. The ninth transistor T9 may be turned on when the voltage of the sixth node QBE is a high-level voltage, and may control the voltage level of the third node QB to be the first voltage VGH input to the first voltage input terminal V1.

[0108] The tenth transistor T10 may be connected between the third node QB and the third voltage input terminal V3. The tenth transistor T10 may include a first gate connected to the first node Q and a second gate connected to the third voltage input terminal V3. The tenth transistor T10 may be turned on when the first node Q is a high level voltage, and may control the voltage level of the third node QB to be the third voltage VGL2 input to the third voltage input terminal V3.

[0109] The second capacitor C2 may be connected between the fifth node SR_QBF and the sixth node QBE. When the second clock signal CLK2 is a high level voltage, the voltage of the fifth node SR_QBF may be boosted to a voltage greater than the first voltage VGH (eg, twice VGH) through the second capacitor C2 and the turned-on eighth transistor T8.

[0110] The first output unit 230 may output a gate signal of a turn-on voltage level or a gate signal of a turn-off voltage level according to the voltage levels of the second node QF and the third node QB. The first output unit 230 may transmit the first voltage VGH or the second voltage VGL to the first output terminal OUT1 connected to the first output node ON1 according to the voltage levels of the second node QF and the third node QB. A high level voltage of the first voltage VGH or a low level voltage of the second voltage VGL may be output from the first output terminal OUT1 as the kth gate signal GS[k]. The first output unit 230 may include a thirteenth transistor T13 and a fourteenth transistor T14. The first output unit 230 may further include a third capacitor C3 and a fourth capacitor C4. The thirteenth transistor T13 and the fourteenth transistor T14 may each be a double-gate transistor.

[0111] The thirteenth transistor T13 may be connected between the first voltage input terminal V1 and the first output node ON1. The thirteenth transistor T13 may include a first gate and a second gate connected to the second node QF. The thirteenth transistor T13 may be turned on or off according to the voltage level of the second node QF. The thirteenth transistor T13 may be a pull-up transistor that outputs a high-level voltage. The thirteenth transistor T13 may be turned on when the voltage of the second node QF is a high-level voltage, and may transmit the first voltage VGH from the first voltage input terminal V1 to the first output node ON1.

[0112] The fourteenth transistor T14 may be connected between the first output node ON1 and the second voltage input terminal V2. The fourteenth transistor T14 may include a first gate and a second gate connected to the third node QB. The fourteenth transistor T14 may be turned on or off according to the voltage level of the third node QB. The fourteenth transistor T14 may be a pull-down transistor that outputs a low-level voltage. The fourteenth transistor T14 may be turned on when the voltage of the third node QB is a high-level voltage, and may transmit the second voltage VGL from the second voltage input terminal V2 to the first output node ON1.

[0113] The third capacitor C3 may be connected between the second node QF and the first output node ON1. The voltage of the second node QF may be boosted by the third capacitor C3. The fourth capacitor C4 may be connected between the third node QB and the first output node ON1. The voltage of the third node QB may be boosted by the fourth capacitor C4.

[0114] The second output unit 240 may output a carry signal of a turn-on voltage level or a carry signal of a turn-off voltage level according to the voltage levels of the second node QF and the third node QB. The second output unit 240 may transmit the first voltage VGH or the third voltage VGL2 to the second output terminal OUT2 connected to the second output node ON2 according to the voltage levels of the second node QF and the third node QB. A high level voltage of the first voltage VGH or a low level voltage of the third voltage VGL2 may be output from the second output terminal OUT2 as the kth carry signal CR[k]. The second output unit 240 may include an eleventh transistor T11 and a twelfth transistor T12. The eleventh transistor T11 and the twelfth transistor T12 may be dual-gate transistors.

[0115] The eleventh transistor T11 may be connected between the first voltage input terminal V1 and the second output node ON2. The eleventh transistor T11 may include a first gate and a second gate connected to the second node QF. The eleventh transistor T11 may be turned on or off according to the voltage level of the second node QF. The eleventh transistor T11 may be a pull-up transistor that outputs a high-level voltage. The eleventh transistor T11 may be turned on when the voltage of the second node QF is a high-level voltage, and may transmit the first voltage VGH from the first voltage input terminal V1 to the second output node ON2.

[0116] The twelfth transistor T12 may be connected between the second output node ON2 and the third voltage input terminal V3. The twelfth transistor T12 may include a first gate and a second gate connected to the third node QB. The twelfth transistor T12 may be turned on or off according to the voltage level of the third node QB. The twelfth transistor T12 may be a pull-down transistor that outputs a low-level voltage. The twelfth transistor T12 may be turned on when the voltage of the third node QB is a high-level voltage, and may transmit the third voltage VGL2 from the third voltage input terminal V3 to the second output node ON2.

[0117] When the voltage of the first node Q is a high level voltage, the leakage control unit 250 can prevent leakage current from the transistors (e.g., the first transistor T1, the second transistor T2, and the sixteenth transistor T16) connected to the first node Q. The leakage control unit 250 may include a fifteenth transistor T15 (also referred to as a leakage prevention transistor), and the fifteenth transistor T15 may include a plurality of sub-transistors connected in series with each other. The sub-transistors may include a pair of a fifteenth-first transistor T15-1 and a fifteenth-second transistor T15-2. The fifteenth-first transistor T15-1 and the fifteenth-second transistor T15-2 may each be a double-gate transistor including a first gate and a second gate connected to the first node Q.

[0118] One end (e.g., the first end) of the fifteenth transistor T15 may be connected to the first voltage input terminal V1. The other end (e.g., the second end) of the fifteenth transistor T15 may be connected to the intermediate node (common electrode) between the first-first transistor T1-1 and the first-second transistor T1-2, the intermediate node (common electrode) between the second-first transistor T2-1 and the second-second transistor T2-2, and the intermediate node (common electrode) between the sixteenth-first transistor T16-1 and the sixteenth-second transistor T16-2. The fifteenth transistor T15 may be turned on when the voltage of the first node Q is a high level voltage, and the current leakage of the first node Q may be reduced by maintaining the intermediate nodes of the first transistor T1, the second transistor T2, and the sixteenth transistor T16 at a high level voltage.

[0119] The reset unit 260 can reset the first node Q based on the reset signal ESR provided to the reset terminal RS. The reset unit 260 may include a sixteenth transistor T16 (reset transistor), and the sixteenth transistor T16 may include a plurality of sub-transistors connected in series to each other between the first node Q and the second voltage input terminal V2. The sub-transistor may include a pair of the sixteenth-first transistor T16-1 and the sixteenth-second transistor T16-2. The sixteenth-first transistor T16-1 and the sixteenth-second transistor T16-2 may each be a double-gate transistor including a first gate and a second gate connected to the reset terminal RS. The sixteenth transistor T16 may be turned on when the reset signal ESR is input with a high level voltage, and the first node Q may be reset (initialized) to the third voltage VGL2. Since the reset signal ESR of the third voltage VGL2 is provided during the operation of the gate drive circuit 130, the sixteenth transistor T16 may be turned off.

[0120] When the oxide semiconductor transistor is a double-gate transistor including a pair of gates, the external light blocking effect generated by the bottom gate can be obtained while reducing the size of the transistor (e.g., channel width to channel length (W / L)). In contrast, the double-gate transistor exhibits a large threshold voltage variation compared to the single-gate transistor.

[0121] The stage according to the embodiment includes a plurality of N-type transistors including an oxide semiconductor, and some transistors (for example, at least one of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8) among the plurality of N-type transistors having a long on-bias time (high-level voltage input time) are provided as single-gate transistors, and thus a threshold voltage variation of the transistor due to repeated driving can be reduced.

[0122] In addition, the stage according to the embodiment includes some transistors with a long high-level voltage input time among N-type transistors as double-gate transistors, and the voltage level of the voltage input to the bottom gate can be different from the voltage level of the voltage input to the top gate. For example, the tenth transistor T10 can reduce the threshold voltage change of the transistor caused by repeated driving in which a high-level voltage is input to the top gate of the tenth transistor T10 by inputting a low-level voltage to the bottom gate of the tenth transistor T10.

[0123] Figure 6a and Figure 6b It is shown Figure 5 0048 is a timing diagram of an example of the operation of the stages shown in FIG. Figure 6a yes Figure 5 The stage shown in is a timing diagram of input / output signals at the first stage. Figure 6b yes Figure 5 The stages shown in are the odd-numbered stages among the second and subsequent stages. Figure 6a and Figure 6b In the embodiment of the present invention, the width of each of the plurality of time periods (P11 to P14 and P21 to P28) may be 2H. In the following description, for ease of explanation, the voltage level of the first voltage VGH is represented as a high level, and the voltage levels of the second voltage VGL and the third voltage VGL2 are represented as a low level. The high level voltage and the low level voltage may be defined as a turn-on voltage and a turn-off voltage, respectively.

[0124] Figure 6a The external signal FLM as a start signal, the first clock signal CLK1 input to the first clock terminal CK1, the second clock signal CLK2 input to the second clock terminal CK2, the node voltages of the second node QF and the third node QB, and the carry signal CR[1] and the gate signal GS[1] as output signals are shown. The operation of the first stage ST1 is described below.

[0125] In the first period P11 , the external signal FLM may be a high level voltage, the first clock signal CLK1 may be a high level voltage, and the second clock signal CLK2 may be a low level voltage.

[0126] The first transistor T1 may be turned on in response to the first clock signal CLK1 of a high level voltage, and the external signal FLM may be transmitted to the first node Q through the turned-on first transistor T1, so that the voltage of the first node Q may become a high level voltage. Through the turned-on third transistor T3, the first node Q and the second node QF are connected to each other (e.g., electrically connected to each other), and the voltage of the second node QF may become a high level voltage. Therefore, the thirteenth transistor T13 and the eleventh transistor T11 having a gate connected to the second node QF may be turned on, and the gate signal GS[1] and the carry signal CR[1] as a high level voltage may be output from the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0127] Since the voltages of the first and second nodes QF are high level voltages, the fifth and tenth transistors T5 and T10 having gates connected to the first node Q may be turned on. The third voltage VGL2 may be transmitted to the third node QB through the turned-on tenth transistor T10, so that the voltage of the third node QB may become a low level voltage.

[0128] The sixth transistor T6 may be turned on in response to the first clock signal CLK1, and the first voltage VGH may be transmitted to the fourth node SR_QB through the turned-on sixth transistor T6 and the fifth transistor T5, so that the voltage of the fourth node SR_QB may become a high level voltage. The voltage of the fifth node SR_QBF may become a high level voltage through the seventh transistor T7 turned on in response to the first voltage VGH. Since the voltage of the fifth node SR_QBF is a high level voltage, the eighth transistor T8 may be turned on, and the second clock signal CLK2 of the low level voltage is transmitted to the sixth node QBE, so that the voltage of the sixth node QBE may become a low level voltage.

[0129] In the second period P12 , the external signal FLM may be a high level voltage, the first clock signal CLK1 may be a low level voltage, and the second clock signal CLK2 may be a high level voltage.

[0130] The first transistor T1 is turned off in response to the first clock signal CLK1, so that the first node Q and the second node QF become a floating state, and the second node QF can maintain a high level state through the first capacitor C1 and the third capacitor C3 as a boost capacitor. In this state, the second node QF can maintain a higher level voltage in the first period P11 through the first capacitor C1 and the third capacitor C3. Therefore, the thirteenth transistor T13 and the eleventh transistor T11 can maintain a conductive state, and can output a gate signal GS[1] and a carry signal CR[1] as a high level voltage. The voltage of the third node QB can be maintained at a low level voltage through the turned-on tenth transistor T10.

[0131] The sixth transistor T6 is turned off in response to the first clock signal CLK1, and the low-level first clock signal CLK1 can be transmitted to the fourth node SR_QB through the turned-on fifth transistor T5, so that the voltage of the fourth node SR_QB can become a low-level voltage. Therefore, the voltage of the fifth node SR_QBF can be changed to a low-level voltage through the turned-on seventh transistor T7, so that the eighth transistor T8 is turned off, and the voltage of the sixth node QBE can be maintained at a low-level voltage.

[0132] While the external signal FLM maintains a high level voltage, the first clock signal CLK1 and the second clock signal CLK2 are alternately applied as a high level voltage and a low level voltage, and since the first period P11 and the second period P12 are repeated as described above, the gate signal GS[1] and the carry signal CR[1] as high level voltages can be output from the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0133] In the third period P13 , the external signal FLM may be converted to a low level voltage, the first clock signal CLK1 may be a high level voltage, and the second clock signal CLK2 may be a low level voltage.

[0134] The first transistor T1 and the sixth transistor T6 may be turned on in response to the first clock signal CLK1. The voltages of the first node Q and the second node QF may become a low level voltage through the turned-on first transistor T1 and the third transistor T3, and the fifth transistor T5 and the tenth transistor T10 may be turned off. Since the second node QF is in a low level state, the thirteenth transistor T13 and the eleventh transistor T11 may be turned off. The voltages of the fourth node SR_QB and the fifth node SR_QBF may become a high level voltage through the turned-on sixth transistor T6 and the seventh transistor T7. Since the fifth node SR_QBF is in a high level state, the eighth transistor T8 may be turned on, and the second clock signal CLK2 may be transmitted to the sixth node QBE, so that the sixth node QBE may be in a low level state. Since the ninth transistor T9 is turned off, the third node QB may be in a floating state and may maintain a low level state.

[0135] The first and second output nodes ON1 and ON2 may each maintain a high level state as in the second period P12 , and the gate signal GS[ 1 ] and the carry signal CR[ 1 ] as high level voltages may be output from the first and second output terminals OUT1 and OUT2 , respectively.

[0136] In the fourth period P14 , the external signal FLM may be a low level voltage, the first clock signal CLK1 may be a low level voltage, and the second clock signal CLK2 may be a high level voltage.

[0137] The first transistor T1 may be turned off in response to the first clock signal CLK1, the first node Q and the second node QF may maintain a low level state, and the thirteenth transistor T13 and the eleventh transistor T11 may be turned off. The sixth transistor T6 may be turned off in response to the first clock signal CLK1, and since the first node Q is in a low level state, the fifth transistor T5 may be turned off and the fourth node SR_QB may maintain a high level state.

[0138] Therefore, the fifth node SR_QBF may be in a high level state by the turned-on seventh transistor T7, and therefore, the eighth transistor T8 may be turned on and the voltage of the sixth node QBE may become a high level voltage by the second clock signal CLK2. In this state, due to the second capacitor C2, the fifth node SR_QBF may maintain a high level voltage higher than the high level voltage in the third period P13.

[0139] The ninth transistor T9 may be turned on, and the voltage of the third node QB may be changed to a high level voltage by the first voltage VGH. Therefore, the turned-on fourteenth transistor T14 may transmit the low level second voltage VGL to the first output node ON1, and the gate signal GS[1] of the low level voltage may be output from the first output terminal OUT1. The turned-on twelfth transistor T12 may transmit the low level third voltage VGL2 to the second output node ON2, and the carry signal CR[1] of the low level voltage may be output from the second output terminal OUT2.

[0140] Figure 6b The previous carry signal CR[k-1] as a start signal, the first clock signal CLK1 input to the first clock terminal CK1, the second clock signal CLK2 input to the second clock terminal CK2, the node voltages of the second node QF and the third node QB, and the kth carry signal CR[k] and the kth gate signal GS[k] as output signals are shown. The operation of the odd-numbered stage STk after the first stage ST1 is described below.

[0141] In the first period P21 , the previous carry signal CR[k−1] may be a low level voltage, the first clock signal CLK1 may be a high level voltage, and the second clock signal CLK2 may be a low level voltage.

[0142] The first transistor T1 can be turned on in response to the first clock signal CLK1 of the high level voltage. The previous carry signal CR[k-1] can be transmitted to the first node Q through the turned-on first transistor T1, so that the voltage of the first node Q can become a low level voltage. The voltage of the second node QF can be maintained as a low level voltage of the previous voltage level through the turned-on third transistor T3. Therefore, the fifth transistor T5 and the tenth transistor T10 having the gate connected to the first node Q can maintain the off state, and the fourth transistor T4, the eleventh transistor T11 and the thirteenth transistor T13 having the gate connected to the second node QF can maintain the off state.

[0143] The sixth transistor T6 may be turned on in response to the first clock signal CLK1 of a high level voltage, and the first voltage VGH is transmitted to the fourth node SR_QB, so that the voltage of the fourth node SR_QB may become a high level voltage. The voltage of the fifth node SR_QBF may become a high level voltage by the seventh transistor T7 turned on in response to the first voltage VGH. Since the voltage of the fifth node SR_QBF is a high level voltage, the eighth transistor T8 may be turned on, and the second clock signal CLK2 of a low level voltage is transmitted to the sixth node QBE, so that the voltage of the sixth node QBE may become a low level voltage. The ninth transistor T9 is turned off, the third node QB may be in a floating state, and the voltage of the third node QB may maintain a high level voltage as a previous voltage level.

[0144] Therefore, the fourteenth transistor T14 can transmit the low-level second voltage VGL to the first output node ON1, and the k-th gate signal GS[k] of the low-level voltage can be continuously output from the first output terminal OUT1. The twelfth transistor T12 can transmit the low-level third voltage VGL2 to the second output node ON2, and the k-th carry signal CR[k] of the low-level voltage can be continuously output from the second output terminal OUT2.

[0145] In the second period P22 , the previous carry signal CR[k−1] may be converted to a high level voltage, the first clock signal CLK1 may be a low level voltage, and the second clock signal CLK2 may be a high level voltage.

[0146] The first transistor T1 may be turned off in response to the first clock signal CLK1 of a low level voltage, the first and second nodes Q and QF may be in a floating state, and voltages of the first and second nodes Q and QF may maintain a low level voltage.

[0147] The sixth transistor T6 may be turned off in response to the first clock signal CLK1, and since the fifth transistor T5 may be turned off, the voltages of the fourth node SR_QB and the fifth node SR_QBF may be maintained at a high level voltage. The second clock signal CLK2 of the high level voltage is transmitted to the sixth node QBE through the turned-on eighth transistor T8, and thus, the voltage of the sixth node QBE may become a high level voltage. In this state, due to the second capacitor C2, the fifth node SR_QBF may have a high level voltage higher than the high level voltage in the first period P21.

[0148] Since the ninth transistor T9 having the gate connected to the sixth node QBE is turned on, the first voltage VGH can be transmitted to the third node QB, and the voltage of the third node QB can become a high level voltage. Therefore, the turned-on fourteenth transistor T14 can transmit the low-level second voltage VGL to the first output node ON1, and the k-th gate signal GS[k] of the low-level voltage can be continuously output from the first output terminal OUT1. The turned-on twelfth transistor T12 can transmit the low-level third voltage VGL2 to the second output node ON2, and the k-th carry signal CR[k] of the low-level voltage can be continuously output from the second output terminal OUT2.

[0149] In the third period P23 , the previous carry signal CR[k−1] may be a high level voltage, the first clock signal CLK1 may be a high level voltage, and the second clock signal CLK2 may be a low level voltage.

[0150] The first transistor T1 may be turned on in response to the first clock signal CLK1 of a high level voltage, the previous carry signal CR[k-1] may be transmitted to the first node Q through the turned-on first transistor T1, and the voltage of the first node Q may become a high level voltage. The first node Q and the second node QF may be connected to each other (e.g., electrically connected to each other) through the turned-on third transistor T3, and the voltage of the second node QF may become a high level voltage. Therefore, the thirteenth transistor T13 and the eleventh transistor T11 having a gate connected to the second node QF may be turned on, and the kth gate signal GS[k] and the kth carry signal CR[k] of a high level voltage may be output from the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0151] Since the voltages of the first node Q and the second node QF are high level voltages, the fifth transistor T5 and the tenth transistor T10 having the gate connected to the first node Q can be turned on. The third voltage VGL2 can be transmitted to the third node QB through the turned-on tenth transistor T10, so that the voltage of the third node QB can become a low level voltage. Therefore, the fourteenth transistor T14 and the twelfth transistor T12 can be turned off.

[0152] The sixth transistor T6 may be turned on in response to the first clock signal CLK1, and the first voltage VGH may be transmitted to the fourth node SR_QB through the turned-on sixth transistor T6 and the fifth transistor T5, so that the voltage of the fourth node SR_QB may become a high level voltage. The voltage of the fifth node SR_QBF may become a high level voltage through the seventh transistor T7 turned on in response to the first voltage VGH. Since the voltage of the fifth node SR_QBF is a high level voltage, the eighth transistor T8 may be turned on, and the second clock signal CLK2 of a low level voltage may be transmitted to the sixth node QBE, so that the voltage of the sixth node QBE may become a low level voltage.

[0153] In the fourth period P24 , the previous carry signal CR[k−1] may be a high level voltage, the first clock signal CLK1 may be a low level voltage, and the second clock signal CLK2 may be a high level voltage.

[0154] The first transistor T1 can be turned off in response to the first clock signal CLK1, so that the first node Q and the second node QF become a floating state, and the second node QF can maintain a high level state through the first capacitor C1 and the third capacitor C3 as a boost capacitor. In this state, due to the first capacitor C1 and the third capacitor C3, the second node QF can maintain a high level voltage higher than the high level voltage in the third period P23. Therefore, the thirteenth transistor T13 and the eleventh transistor T11 can maintain a conductive state, and can output the kth gate signal GS[k] and the kth carry signal CR[k] of the high level voltage. The voltage of the third node QB can be maintained at a low level voltage by the turned-on tenth transistor T10.

[0155] The sixth transistor T6 may be turned off in response to the first clock signal CLK1, and the low-level first clock signal CLK1 may be transmitted to the fourth node SR_QB through the turned-on fifth transistor T5, so that the voltage of the fourth node SR_QB may become a low-level voltage. Therefore, the voltage of the fifth node SR_QBF may become a low-level voltage through the turned-on seventh transistor T7, so that the eighth transistor T8 is turned off, and the voltage of the sixth node QBE may be maintained at a low-level voltage.

[0156] The operation of the stage STk in the fifth period P25 may be substantially the same as the operation of the stage STk in the third period P23, and the operation of the stage STk in the sixth period P26 may be substantially the same as the operation of the stage STk in the fourth period P24. Therefore, for ease of explanation, redundant descriptions thereof are omitted.

[0157] In the seventh period P27 , the previous carry signal CR[k−1] may be converted to a low level voltage, the first clock signal CLK1 may be a high level voltage, and the second clock signal CLK2 may be a low level voltage.

[0158] The first transistor T1 may be turned on in response to the first clock signal CLK1. Since the previous carry signal CR[k-1] is transmitted to the first node Q through the turned-on first transistor T1, the voltage of the first node Q may become a low level voltage, and the voltage of the second node QF may become a low level voltage through the turned-on third transistor T3. Since the voltage of the first node Q is a low level voltage, the fifth transistor T5 and the tenth transistor T10 may be turned off. Since the voltage of the second node QF is a low level voltage, the thirteenth transistor T13 and the eleventh transistor T11 may be turned off.

[0159] The sixth transistor T6 may be turned on in response to the first clock signal CLK1. The first voltage VGH is transmitted to the fourth node SR_QB through the turned-on sixth transistor T6, the voltage of the fourth node SR_QB may become a high level voltage, and the voltage of the fifth node SR_QBF may become a high level voltage through the turned-on seventh transistor T7. Since the voltage of the fifth node SR_QBF is a high level voltage, the eighth transistor T8 may be turned on, and the second clock signal CLK2 may be transmitted to the sixth node QBE, so that the voltage of the sixth node QBE may become a low level voltage. The ninth transistor T9 is turned off, the third node QB may be in a floating state, and the voltage of the third node QB may be maintained at a low level voltage.

[0160] The voltages of the first and second output nodes ON1 and ON2 may each maintain a high level voltage as in the sixth period P26, and the kth gate signal GS[k] and the kth carry signal CR[k] of the high level voltage may be output from the first and second output terminals OUT1 and OUT2, respectively.

[0161] In the eighth period P28 , the previous carry signal CR[k−1] may be a low level voltage, the first clock signal CLK1 may be a low level voltage, and the second clock signal CLK2 may be a high level voltage.

[0162] The first transistor T1 may be turned off in response to the first clock signal CLK1 , the voltages of the first and second nodes QF may maintain a low level voltage, and the thirteenth and eleventh transistors T13 and T11 may be turned off.

[0163] The sixth transistor T6 may be turned off in response to the first clock signal CLK1, the fifth transistor T5 having a gate connected to the first node Q may be turned off, and the voltage of the fourth node SR_QB may maintain a high level voltage. Therefore, the voltage of the fifth node SR_QBF may become a high level voltage by the turned-on seventh transistor T7. Therefore, the eighth transistor T8 may be turned on, and the sixth node QBE may have a high level voltage by the second clock signal CLK2. In this state, the voltage of the fifth node SR_QBF may be maintained higher than the high level voltage in the seventh period P27 due to the second capacitor C2. The ninth transistor T9 having a gate connected to the sixth node QBE may be turned on, and the voltage of the third node QB may become a high level voltage by the first voltage VGH. Therefore, the fourteenth transistor T14 may be turned on, and the low level second voltage VGL may be transmitted to the first output node ON1, so that the kth gate signal GS[k] of the low level voltage may be output from the first output terminal OUT1. The twelfth transistor T12 may be turned on and the third voltage VGL2 of a low level may be transmitted to the second output node ON2 , so that the k th carry signal CR[k] of a low level voltage may be output from the second output terminal OUT2 .

[0164] The even-numbered stages differ from the odd-numbered stages in that the second clock signal CLK2 is input to the first clock terminal CK1 and the first clock signal CLK1 is input to the second clock terminal CK2, and the other circuit configurations and operations of the even-numbered stages are the same as those described above with reference to FIG. Figure 5 The circuit configuration and operation of the odd-numbered stages described are the same.

[0165] The odd-numbered stages and the even-numbered stages may each output a gate signal and a carry signal as a high level in synchronization with a rising time of a clock signal input to the first clock terminal CK1 .

[0166] Figures 7 to 9 are circuit diagrams showing various modified examples of the stage circuit according to the embodiment.

[0167] Figure 7 The level shown in Figure 5 The stage shown in FIG. 1 differs in that the first transistor T1 and the third transistor T3 are double-gate transistors. Figure 7 In the stage shown in , the first transistor T1 may include a first-first transistor T1-1 and a first-second transistor T1-2, and the first-first transistor T1-1 and the first-second transistor T1-2 may each be a double-gate transistor having a first gate and a second gate connected to the first clock terminal CK1. The third transistor T3 may be a double-gate transistor having a first gate and a second gate connected to the first voltage input terminal V1. Figure 7Other configurations and operations of the stages shown in the Figure 5 The configuration and operation of the stages shown in are the same.

[0168] Figure 8 The level shown in Figure 5 The stage shown in FIG. 1 is different in that the thirteenth transistor T13 and the fourteenth transistor T14 are single-gate transistors. Figure 8 In the stage shown in , the thirteenth transistor T13 may be a single-gate transistor having a gate connected to the second node QF, and the fourteenth transistor T14 may be a single-gate transistor having a gate connected to the third node QB. Figure 8 Other configurations and operations of the stages shown in Figure 5 The configuration and operation of the stages shown in are the same.

[0169] Fig. 9 The level shown in Figure 5 The stage shown in FIG. 1 is different in that the first transistor T1 to the sixteenth transistor T16 are all single-gate transistors. Fig. 9 The operation of the stages shown in Figure 5 The operation of the stages shown in is the same.

[0170] Fig.10 is a schematic diagram showing a gate driving circuit according to an embodiment. Fig.11 According to the embodiment, Fig.10 Schematic timing diagram of the gate signal output by the gate driving circuit.

[0171] Fig.10 The gate driving circuit 130′ shown in FIG. 1 may include stages ST1 to STn, and Figure 3 The gate driving circuit 130 shown in FIG. 1 may be different in that each of the stages ST1 to STn outputs a pair of gate signals. The circuit configuration of each of the stages ST1 to STn may be the same as that of FIG. Figure 5 The circuit configurations of the stages shown in FIG. 1 are the same, and the gate signal output from the first output terminal OUT1 of each stage can be simultaneously provided to two rows of the pixel unit 110. For example, Fig.11 As shown in , a pair of first gate signals GS[ 1 ] and second gate signals GS[ 2 ] output from the first output terminal OUT1 of the first stage ST1 may be simultaneously provided to gate lines in a first row and a second row of the pixel unit 110 .

[0172] Fig.12 is a schematic block diagram of a display device according to an embodiment. Fig.13 According to the embodiment Fig.12 Circuit diagram of a pixel. Fig.14 According to the embodiment, Fig.12The gate drive circuit outputs to Fig.12 Schematic timing diagram of the gate signal of a pixel.

[0173] although Figure 1 It is shown that each of the plurality of pixels PX is connected to one gate line and the gate driving circuit 130 outputs a gate signal to the one gate line, but this is an example, and according to an embodiment, each of the plurality of pixels PX may be connected to one or more gate lines, and at least one gate driving circuit may output at least one gate signal to the one or more gate lines.

[0174] like Fig.12 As shown in FIG. 1 , the display device 10a according to the embodiment may include a pixel unit 110, a gate driving circuit 130a, a data driving circuit 150, and a controller 170. The gate driving circuit 130a may include a first gate driving circuit 131a, a second gate driving circuit 133a, a third gate driving circuit 135a, and a fourth gate driving circuit 137a.

[0175] The first gate driving circuit 131a may be connected to a plurality of first gate lines GWL, and may sequentially provide a first gate signal GW to the first gate lines GWL in response to a first gate driving control signal GCS1. The second gate driving circuit 133a may be connected to a plurality of second gate lines GIL, and may sequentially provide a second gate signal GI to the second gate lines GIL in response to a second gate driving control signal GCS2. The third gate driving circuit 135a may be connected to a plurality of third gate lines GRL, and may sequentially provide a third gate signal GR to the third gate lines GRL in response to a third gate driving control signal GCS3. The fourth gate driving circuit 137a may be connected to a plurality of fourth gate lines EML, and may sequentially provide a fourth gate signal EM to the fourth gate lines EML in response to a fourth gate driving control signal GCS4.

[0176] like Fig.13 As shown in , the pixel PX1 can be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, a fourth gate line EML transmitting a fourth gate signal EM, and a data line DL transmitting a data signal DATA. In addition, the pixel PX1 can be connected to a driving voltage line PL providing a first driving voltage ELVDD, an initialization voltage line VL providing an initialization voltage Vint, and a reference voltage line VRL providing a reference voltage VREF.

[0177] The pixel PX1 may include an organic light emitting diode OLED as a display element and a pixel circuit PC1 connected to the organic light emitting diode OLED. The pixel circuit PC1 may include a first transistor M1 to a fifth transistor M5, and a first capacitor Cst and a second capacitor Chold. The first transistor M1 may be a driving transistor, and the second transistor M2 to the fifth transistor M5 may be a switching transistor. The first transistor M1 to the fifth transistor M5 may be an N-type oxide semiconductor transistor. The first transistor M1 to the fifth transistor M5 may be a double-gate transistor each having a first gate and a second gate. The node to which the gate of the first transistor M1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor M1 is connected may be defined as a second node N2.

[0178] The first transistor M1 may include a first gate connected to the first node N1 and a second gate connected to the second node N2, and a first terminal connected to the fifth transistor M5 and a second terminal connected to the second node N2. The second gate of the first transistor M1 may be connected to the second terminal of the first transistor M1 and may receive a voltage applied to the second terminal of the first transistor M1, which may improve the output saturation characteristic of the first transistor M1. The first transistor M1 may receive a data signal according to a switching operation of the second transistor M2 and control the amount of driving current flowing to the organic light emitting diode OLED.

[0179] The second transistor M2 (data write transistor) may include a first gate and a second gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor M2 may be turned on in response to a first gate signal GW transmitted through the first gate line GWL to electrically connect the data line DL with the first node N1, and the second transistor M2 may transmit a data signal transmitted through the data line DL to the first node N1.

[0180] The third transistor M3 (first initialization transistor) may include a first gate and a second gate connected to the third gate line GRL, a first terminal connected to the reference voltage line VRL, and a second terminal connected to the first node N1. The third transistor M3 may be turned on in response to a third gate signal GR transmitted through the third gate line GRL, and may transmit a reference voltage VREF transmitted through the reference voltage line VRL to the first node N1.

[0181] The fourth transistor M4 (second initialization transistor) may include a first gate and a second gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the initialization voltage line VL. The fourth transistor M4 may be turned on in response to a second gate signal GI transmitted through the second gate line GIL, and may transmit an initialization voltage Vint transmitted through the initialization voltage line VL to the second node N2.

[0182] The fifth transistor M5 (emission control transistor) may include a first gate and a second gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the second terminal of the first transistor M1. The fifth transistor M5 may be turned on or off in response to a fourth gate signal EM transmitted through the fourth gate line EML. When the fifth transistor M5 is turned on, the first transistor M1 outputs a driving current, and the organic light emitting diode OLED starts to emit light, and therefore, the fourth gate signal EM may be defined as an emission control signal.

[0183] The first capacitor Cst may be connected between the first node N1 and the second node N2. A first terminal of the first capacitor Cst may be connected to the first gate of the first transistor M1, and a second terminal of the first capacitor Cst may be connected to the second gate and second terminal of the first transistor M1, a first terminal of the fourth transistor M4, and a pixel electrode of the organic light emitting diode OLED.

[0184] The second capacitor Chold may be connected between the second node N2 and the driving voltage line PL. A first terminal of the second capacitor Chold may be connected to the driving voltage line PL, and a second terminal of the second capacitor Chold may be connected to the second gate and the second terminal of the first transistor M1, the second terminal of the first capacitor Cst, the first terminal of the fourth transistor M4, and the pixel electrode of the organic light emitting diode OLED. The capacity of the first capacitor Cst may be greater than that of the second capacitor Chold.

[0185] The organic light emitting diode OLED may include a pixel electrode (anode) and an opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive the second power voltage ELVSS. The opposite electrode may be a common electrode shared by a plurality of pixels PX.

[0186] Reference Fig.14, when the second gate signal GI of a turn-on voltage level is provided through the second gate line GIL and the third gate signal GR of a turn-on voltage level is provided through the third gate line GRL, the fourth transistor M4 and the third transistor M3 can be turned on, the first gate of the first transistor M1 can be initialized to the reference voltage VREF, and the pixel electrode of the organic light emitting diode OLED can be initialized to the initialization voltage Vint.

[0187] When the third gate signal GR of the turn-on voltage level is provided through the third gate line GRL and the fourth gate signal EM of the turn-on voltage level is provided through the fourth gate line EML ( Fig.14 During the compensation period CP), the third transistor M3 and the fifth transistor M5 may be turned on, and the first capacitor Cst is charged with a voltage corresponding to the threshold voltage of the first transistor M1, so that the threshold voltage of the first transistor M1 may be compensated.

[0188] When the second transistor M2 is turned on by the first gate signal GW of the turn-on voltage level provided through the first gate line GWL, the data signal from the data line DL can be transmitted to the first gate of the first transistor M1. Therefore, the first capacitor Cst can be charged with the threshold voltage of the first transistor M1 and the voltage corresponding to the data signal.

[0189] When the fourth gate signal EM at the turn-on voltage level is provided through the fourth gate line EML ( Fig.14 During the emission period DE), the second transistor M2, the third transistor M3 and the fourth transistor M4 can be turned off in response to the first gate signal GW, the second gate signal GI and the third gate signal GR of the cut-off voltage level, the fifth transistor M5 can be turned on, and therefore, the first transistor M1 can output the driving current and the organic light emitting diode OLED can emit light with a brightness corresponding to the amount of the driving current.

[0190] After data writing and before the emission period DE, a second gate signal GI of a turn-on voltage level may be provided through the second gate line GIL so that the pixel electrode of the organic light emitting diode OLED may be initialized to the initialization voltage Vint.

[0191] According to the embodiment, the Figure 5 STk Figure 3 The gate drive circuit 130 can be applied to Fig.12 At least one of the first gate drive circuit 131a, the second gate drive circuit 133a, the third gate drive circuit 135a and the fourth gate drive circuit 137a shown in FIG. Figure 3The gate driving circuit 130 of the embodiment of the present invention may be applied to the fourth gate driving circuit 137a, and the gate signal GS as the output signal of the gate driving circuit 130 may be the fourth gate signal EM output by the fourth gate driving circuit 137a through the fourth gate line EML. The fourth gate signal EM may be provided to the compensation period CP and the emission period DE at a high level voltage.

[0192] The fourth gate driving circuit 137a can respond to the fourth gate driving control signal GCS4 according to Fig.14 The timing shown in FIG. 1 is passed through the fourth gate line EML as shown in FIG. Figure 6a and Figure 6b The input signal and the clock signal shown in generate and output the fourth gate signal EM having a high level voltage with a specific turn-on time and a low level voltage with a specific turn-off time.

[0193] Fig.15 is a schematic block diagram of a display device according to an embodiment. Fig.16 It is shown Fig.15 A circuit diagram of an example of a pixel. Fig.17 According to the embodiment, Fig.15 The gate drive circuit outputs to Fig.16 Schematic timing diagram of the gate signal of a pixel. Fig.18 It is shown Fig.15 A circuit diagram of an example of a pixel. Fig.19 According to the embodiment, Fig.15 The gate drive circuit outputs to Fig.18 For ease of description, the following mainly describes the differences from the above-described embodiment, and further description of previously described components and technical aspects may be omitted.

[0194] Fig.15 The display device 10b shown in FIG. 1 may include a pixel unit 110, a gate driving circuit 130b, a data driving circuit 150, and a controller 170. The gate driving circuit 130b may include a first gate driving circuit 131b, a second gate driving circuit 133b, a third gate driving circuit 135b, a fourth gate driving circuit 137b, and a fifth gate driving circuit 139b.

[0195] The first gate driving circuit 131b may be connected to a plurality of first gate lines GWL, and may sequentially provide a first gate signal GW to the first gate lines GWL in response to a first gate driving control signal GCS1. The second gate driving circuit 133b may be connected to a plurality of second gate lines GIL, and may sequentially provide a second gate signal GI through the second gate lines GIL in response to a second gate driving control signal GCS2. The third gate driving circuit 135b may be connected to a plurality of third gate lines GRL, and may sequentially provide a third gate signal GR through the third gate lines GRL in response to a third gate driving control signal GCS3. The fourth gate driving circuit 137b may be connected to a plurality of fourth gate lines EML, and may sequentially provide a fourth gate signal EM through the fourth gate line EML in response to a fourth gate driving control signal GCS4. The fifth gate driving circuit 139b may be connected to a plurality of fifth gate lines EMBL, and may sequentially provide a fifth gate signal EMB through the fifth gate line EMBL in response to a fifth gate driving control signal GCS5.

[0196] Fig.16 The pixel circuit PC2 of the pixel PX2 shown in FIG. Fig.13 The pixel circuit PC1 of the pixel PX1 shown in FIG. 1 is different in that a sixth transistor M6 is added between the second node N2 and the pixel electrode of the organic light emitting diode OLED, and a first terminal of the fourth transistor M4 is connected to a third node N3 to which the sixth transistor M6 and the organic light emitting diode OLED are connected.

[0197] The fourth transistor M4 may be a single-gate transistor including a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL.

[0198] The sixth transistor M6 (second emission control transistor) may be a single-gate transistor including a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The sixth transistor M6 may be turned on or off in response to a fifth gate signal EMB transmitted through the fifth gate line EMBL. When the fifth transistor M5 and the sixth transistor M6 are turned on at the same time, the first transistor M1 may output a driving current, and the organic light emitting diode OLED begins to emit light, and therefore, the fourth gate signal EM and the fifth gate signal EMB may be defined as emission control signals.

[0199] Reference Fig.17, the fifth gate signal EMB may be provided to the pixel PX2 at the off voltage level in the compensation period CP, and provided to the pixel PX2 at the on voltage level in the emission period DE. In addition, the fifth gate signal EMB may be provided at the on voltage level by partially overlapping the second gate signal GI at the on voltage level.

[0200] When the sixth transistor M6 is turned off in the compensation period CP, Fig.16 The pixel PX2 shown in FIG. 1 can block the electrical connection between the first transistor M1 and the organic light emitting diode OLED in the compensation period CP. Therefore, since a compensation deviation caused by a capacitor charging deviation of the organic light emitting diode OLED is not generated in the compensation period CP, a brightness deviation can be reduced.

[0201] According to the embodiment, the Figure 5 STk Figure 3 The gate drive circuit 130 can be applied to Fig.15 At least one of the first gate drive circuit 131b, the second gate drive circuit 133b, the third gate drive circuit 135b, the fourth gate drive circuit 137b and the fifth gate drive circuit 139b shown in FIG. For example, Figure 3 The gate driving circuit 130 can be applied to the fourth gate driving circuit 137b and / or the fifth gate driving circuit 139b, and the gate signal GS as the output signal of the gate driving circuit 130 can be the fourth gate signal EM output by the fourth gate driving circuit 137b through the fourth gate line EML and / or the fifth gate signal EMB output by the fifth gate driving circuit 139b through the fifth gate line EMBL.

[0202] The fourth gate driving circuit 137b can respond to the fourth gate driving control signal GCS4 according to Fig.17 The timing shown in FIG. 1 is passed through the fourth gate line EML as shown in FIG. Figure 6a and Figure 6b The input signal and the clock signal shown in generate and output the fourth gate signal EM having a high level voltage with a specific turn-on time and a low level voltage with a specific turn-off time.

[0203] The fifth gate driving circuit 139b may respond to the fifth gate driving control signal GCS5 according to Fig.17 The timing shown in FIG. 1 is passed through the fifth gate line EMBL as shown in FIG. Figure 6a and Figure 6b The input signal and the clock signal shown in generate and output the fifth gate signal EMB having a high level voltage with a specific turn-on time and a low level voltage with a specific turn-off time.

[0204] Fig.18The pixel circuit PC3 of the pixel PX3 shown in FIG. Fig.13 The difference of the pixel circuit PC1 of the pixel PX1 shown in FIG. 1 is that a sixth transistor M6 connected between the second node N2 and the pixel electrode of the organic light emitting diode OLED and a seventh transistor M7 connected between the third node N3 to which the sixth transistor M6 and the organic light emitting diode OLED are connected and the second initialization voltage line VL2 are added.

[0205] The fourth transistor M4 may be a single-gate transistor including a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the initialization voltage line VL.

[0206] The sixth transistor M6 may be a single-gate transistor including a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The sixth transistor M6 may be turned on or off in response to a fifth gate signal EMB transmitted through the fifth gate line EMBL. Fig.19 , the fifth gate signal EMB may be provided at a turn-on voltage level in the emission period DE.

[0207] The seventh transistor M7 may be a single-gate transistor including a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the second initialization voltage line VL2. The seventh transistor M7 may be turned on in response to a second gate signal GI transmitted through the second gate line GIL, and may transmit a second initialization voltage Vaint transmitted through the second initialization voltage line VL2 to the third node N3. The second initialization voltage Vaint may be different from the initialization voltage Vint. The voltage level of the second initialization voltage Vaint may be greater than the voltage level of the first initialization voltage Vint.

[0208] The fourth gate driving circuit 137b can respond to the fourth gate driving control signal GCS4 according to Fig.19 The timing shown in FIG. 1 is passed through the fourth gate line EML as shown in FIG. Figure 6a and Figure 6b The input signal and the clock signal shown in generate and output the fourth gate signal EM having a high level voltage with a specific turn-on time and a low level voltage with a specific turn-off time.

[0209] The fifth gate driving circuit 139b may respond to the fifth gate driving control signal GCS5 according to Fig.19 The timing shown in FIG. 1 is passed through the fifth gate line EMBL as shown in FIG. Figure 6a and Figure 6bThe input signal and the clock signal shown in generate and output the fifth gate signal EMB having a high level voltage with a specific on-time and a low level voltage with a specific off-time. In an embodiment, as Fig.13 Like the pixel PX1 shown in Fig.16 The first to sixth transistors of the pixel circuit PC2 of the pixel PX2 shown in FIG. Fig.18 The first to seventh transistors of the pixel circuit PC3 of the pixel PX3 shown in FIG. 8 are double-gate transistors including a first gate and a second gate.

[0210] The gate driving circuit according to the embodiment may include N-type oxide semiconductor transistors, and some of the N-type oxide semiconductor transistors may be implemented as single-gate transistors and some of the N-type oxide semiconductor transistors may be implemented as double-gate transistors in consideration of characteristic degradation of the transistors according to bias stress, blocking of external light, and the size of the transistors. A pair of gates of the double-gate transistor may receive the same signal or different signals.

[0211] The gate driving circuit according to the embodiment can adjust the timing of the start signal and the clock signal to output a high level voltage or a low level voltage as a gate signal according to the timing determined by the pixel driving. The gate signal output by the gate driving circuit according to the embodiment can be input to the transistor (for example, Fig.13 The fifth transistor M5, and Fig.16 and Fig.18 The emission control signal is used to control the emission timing of the pixel.

[0212] As is customary in the field of the present disclosure, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or similar elements, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions.

[0213] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A gate drive circuit, the gate drive circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first node controller configured to control a voltage level of the first node and a voltage level of the second node; a second node controller configured to control a voltage level of a third node; and a first output unit connected between a first voltage input terminal to which a first voltage is input and a second voltage input terminal to which a second voltage is input, and configured to output the first voltage or the second voltage as a gate signal according to the voltage level of the second node and the voltage level of the third node, Wherein, the first node controller includes: a first transistor connected between an input terminal to which a start signal is input and the first node, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the first node and a third voltage input terminal to which a third voltage is input, and the second transistor includes a first gate and a second gate connected to the third node; and a third transistor connected between the first node and the second node, and the third transistor includes a gate connected to the first voltage input terminal, The first gate and the second gate of the second transistor are arranged in different layers, and a semiconductor is arranged between the first gate and the second gate of the second transistor.

2. The gate drive circuit according to claim 1, wherein: The voltage level of the first voltage is greater than the voltage level of the second voltage, and A voltage level of the third voltage is lower than the voltage level of the second voltage.

3. The gate driving circuit according to claim 1, wherein: The first transistor includes a plurality of sub-transistors connected in series with each other, and A gate of each of the plurality of sub-transistors is connected to the first clock terminal.

4. The gate driving circuit according to claim 1, wherein: The second transistor includes a plurality of sub-transistors connected in series with each other, and The first gate and the second gate of each of the plurality of sub-transistors are connected to the third node.

5. The gate driving circuit according to claim 1, wherein: Each of the first transistor and the second transistor includes a pair of sub-transistors connected in series with each other, and Each of the plurality of stages further includes a leakage prevention transistor including a gate connected to the first node, a first end connected to the first voltage input terminal, and a second end connected to an intermediate node of the pair of sub-transistors.

6. The gate driving circuit according to claim 1, wherein: The first node controller also includes: a fourth transistor connected between the second node and a second clock terminal to which a second clock signal is input, and including a gate connected to the second node; and a first capacitor connected between the second node and the fourth transistor, The first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted from the first clock signal by half a cycle.

7. The gate driving circuit according to claim 1, wherein: The second node controller comprises: A fourth transistor is connected between the third node and the third voltage input terminal, and includes a first gate connected to the first node and a second gate connected to the third voltage input terminal.

8. The gate driving circuit according to claim 7, wherein: The second node controller also includes: a fifth transistor connected between the first clock terminal and a fourth node, and including a gate connected to the first node; a sixth transistor connected between the first voltage input terminal and the fourth node, and including a first gate and a second gate connected to the first clock terminal; a seventh transistor connected between the fourth node and the fifth node, and including a gate connected to the first voltage input terminal; a capacitor connected between the fifth node and the sixth node; an eighth transistor connected between a second clock terminal to which a second clock signal is input and the sixth node, and including a gate connected to the fifth node; and a ninth transistor connected between the first voltage input terminal and the third node, and including a first gate and a second gate connected to the sixth node, The first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted from the first clock signal by half a cycle.

9. The gate driving circuit according to claim 1, wherein: The first output unit comprises: a first pull-up transistor connected between the first voltage input terminal and a first output node, and the first pull-up transistor includes a gate connected to the second node; and A first pull-down transistor is connected between the second voltage input terminal and the first output node, and the first pull-down transistor includes a gate connected to the third node.

10. The gate driving circuit according to claim 1, wherein: The first output unit comprises: a first pull-up transistor connected between the first voltage input terminal and a first output node, and the first pull-up transistor includes a first gate and a second gate connected to the second node; and a first pull-down transistor connected between the second voltage input terminal and the first output node, and the first pull-down transistor includes a first gate and a second gate connected to the third node, The first gate and the second gate of each of the first pull-up transistor and the first pull-down transistor are disposed in different layers, and a semiconductor is disposed between the first gate and the second gate of each of the first pull-up transistor and the first pull-down transistor.

11. The gate driving circuit according to claim 1, wherein: Each of the plurality of stages further comprises: A second output unit is connected between the first voltage input terminal and the second voltage input terminal, and the second output unit is configured to output the first voltage or the second voltage as a carry signal according to the voltage level of the second node and the voltage level of the third node.

12. The gate driving circuit according to claim 11, wherein: The second output unit comprises: a pull-up transistor connected between the first voltage input terminal and an output node, the pull-up transistor including a first gate and a second gate connected to the second node; and a pull-down transistor connected between the second voltage input terminal and the output node, and the pull-down transistor includes a first gate and a second gate connected to the third node, The first gate and the second gate of each of the pull-up transistor and the pull-down transistor are disposed in different layers, and a semiconductor is disposed between the first gate and the second gate of each of the pull-up transistor and the pull-down transistor.

13. The gate driving circuit according to claim 11, wherein: A start signal of a first stage among the plurality of stages is an external signal, and a start signal of a second stage and subsequent stages among the plurality of stages is a carry signal output from a previous stage.

14. The gate driving circuit according to claim 13, wherein: A turn-on time of the gate signal and a turn-on time of the carry signal are greater than a turn-on time of the external signal.

15. The gate driving circuit according to claim 13, wherein: The timing when the on-time of the start signal of the first stage starts is the same as the timing when the on-time of the first gate signal output from the first stage starts, and The timing when the turn-on time of the gate signal output from each of the second stage and the subsequent stage starts is delayed by a certain time from the timing when the turn-on time of the start signal of each of the second stage and the subsequent stage starts.

16. The gate driving circuit according to claim 1, wherein: Each of the plurality of stages further comprises: a reset transistor connected between the first node and the second voltage input terminal, and the reset transistor is configured to reset the first node, The reset transistor includes a first gate and a second gate connected to a reset terminal to which a reset signal is input.

17. A gate drive circuit, the gate drive circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first node controller configured to control a voltage level of the first node and a voltage level of the second node; a second node controller configured to control a voltage level of a third node; and a first output unit connected between a first voltage input terminal to which a first voltage is input and a second voltage input terminal to which a second voltage is input, and configured to output the first voltage or the second voltage as a gate signal according to the voltage level of the second node and the voltage level of the third node, Wherein, the first node controller includes: a first transistor including a pair of first sub-transistors connected in series with each other between an input terminal to which a start signal is input and the first node, a gate of each of the first sub-transistors being connected to a first clock terminal to which a first clock signal is input; a second transistor including a pair of second sub-transistors connected in series with each other between the first node and a third voltage input terminal to which a third voltage is input, a gate of each of the second sub-transistors being connected to the third node; and a third transistor connected between the first node and the second node, and the third transistor includes a gate connected to the first voltage input terminal, wherein the voltage level of the first voltage is greater than the voltage level of the second voltage, and A voltage level of the third voltage is lower than the voltage level of the second voltage.

18. The gate driving circuit according to claim 17, wherein: Each of the plurality of stages further comprises: A leakage prevention transistor includes a gate connected to the first node, a first end connected to the first voltage input terminal, and a second end connected to an intermediate node of the first sub-transistor and an intermediate node of the second sub-transistor.

19. The gate driving circuit according to claim 17, wherein: The second node controller comprises: a fourth transistor connected between the first clock terminal and a fourth node, and including a gate connected to the first node; a fifth transistor connected between the first voltage input terminal and the fourth node, and including a gate connected to the first clock terminal; a sixth transistor connected between the fourth node and the fifth node, and including a gate connected to the first voltage input terminal; a capacitor connected between the fifth node and the sixth node; a seventh transistor connected between a second clock terminal to which a second clock signal is input and the sixth node, and including a gate connected to the fifth node; an eighth transistor connected between the first voltage input terminal and the third node, and including a gate connected to the sixth node; and a ninth transistor connected between the third node and the third voltage input terminal, and including a gate connected to the first node, The first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted from the first clock signal by half a cycle.

20. The gate driving circuit according to claim 17, wherein: Each of the plurality of stages further comprises: A second output unit is connected between the first voltage input terminal and the second voltage input terminal, and the second output unit is configured to output the first voltage or the second voltage as a carry signal according to the voltage level of the second node and the voltage level of the third node.

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