Remote upgrading method and device for prototype verification board card, equipment and medium

Abstract

The invention discloses a remote upgrading method, device, equipment and medium for a prototype verification board card, relates to the field of industrial design, is applied to a main equipment programmable logic device, and comprises the following steps: obtaining data information after serial-parallel conversion sent by a local signal analysis board card through a first preset link layer protocol interface, after an upgrade file is determined based on the data information after serial-parallel conversion, the upgrade file is stored in a preset external storage device; reading corresponding update data from an upgrade file in a preset external storage device by using a first preset bus transmission protocol, and determining a target to-be-updated memory chip based on a remote upgrade command sent by a preset programmable logic device; and performing gating control on the update data based on the remote upgrade command, and controlling a preset data flow controller to write the gated update data into the target to-be-updated memory chip so as to perform remote upgrade on the prototype verification board card. Therefore, remote upgrading of the prototype verification board card can be realized.

Description

Technical Field

[0001] The present invention relates to the field of industrial design technology, and in particular to a remote upgrade method, device, equipment and medium for a prototype verification board. Background Art

[0002] Currently, the prototype verification board is arranged in the laboratory or computer room, and the prototype verification version needs to be frequently changed for iteration. If the prototype verification board needs to be upgraded, it needs to be updated in the laboratory or computer room, which will waste a certain amount of manpower and time.

[0003] It can be seen that how to remotely update the prototype verification board is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a remote upgrade method, device, equipment and medium for a prototype verification board, which can solve the problem of remote updating of the prototype verification board.

[0005] In a first aspect, the present invention provides a remote upgrade method for a prototype verification board, which is applied to a programmable logic device of a master device, comprising:

[0006] Obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, storing the upgrade file in a preset external storage device;

[0007] Reading corresponding update data from an upgrade file in a preset external storage device using a first preset bus transmission protocol, and determining a target memory chip to be updated based on a remote upgrade command sent by a preset programmable logic device;

[0008] Based on the remote upgrade command, the update data is gated and controlled, and a preset data flow controller is controlled to write the gated update data into a target memory chip to be updated, so as to remotely upgrade the prototype verification board.

[0009] Optionally, obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, storing the upgrade file in a preset external storage device includes:

[0010] Obtaining serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface; the serial-to-parallel converted data information is information obtained after the first preset link layer protocol interface performs a serial-to-parallel conversion operation on the initial upgrade file;

[0011] Performing a sequence alignment operation on the serial-to-parallel converted data information based on a preset alignment sequence symbol to obtain target data information;

[0012] After the upgrade file is extracted from the target data information, the upgrade file is stored in a preset external storage device.

[0013] Optionally, before obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, the method further includes:

[0014] The network protocol sent by the remote network device is obtained through the local signal analysis board; the network protocol includes the serial number information of the target memory chip to be updated and the update action instruction;

[0015] Parse the number information and update action instructions in the network protocol through the local signal parsing board to extract the command information;

[0016] The command information is sent to the preset programmable logic device through the local signal analysis board, and a corresponding command sending completion signal is generated; so that the preset programmable logic device can generate a remote upgrade command after parsing the command information;

[0017] The command sending completion signal is sent to the remote network device through the local signal analysis board, so that the remote network device sends the initial upgrade file to the local signal analysis board based on the command sending completion signal.

[0018] Optionally, controlling the preset data flow controller to write the selected update data into the target memory chip to be updated includes:

[0019] Controlling the preset data flow controller to connect with the first preset communication protocol of the slave device programmable logic device based on the remote upgrade command, so as to send the selected update data to the slave device programmable logic device through the first preset communication protocol and the second preset link layer protocol interface;

[0020] In the slave device programmable logic device, the update data is connected to the preset memory controller through the second preset communication protocol and the second preset bus transmission protocol, and the preset memory controller is used to write the update data into the target memory chip to be updated.

[0021] Optionally, controlling the preset data flow controller to write the selected update data into the target memory chip to be updated includes:

[0022] Based on the remote upgrade command, the preset data flow controller is controlled to access the update data to the preset memory controller through the third preset bus transmission protocol, and the preset memory controller is used to write the update data into the target memory chip to be updated.

[0023] Optionally, after controlling the preset data flow controller to write the selected update data into the target memory chip to be updated to remotely upgrade the prototype verification board, the method further includes:

[0024] Performing a frequency division operation on the base frequency generated by the local preset phase locking loop to obtain a heartbeat signal;

[0025] The heartbeat signal is sent to a preset programmable logic device through a preset data decoder, so that after the preset programmable logic device determines a readback flag based on the heartbeat signal, the readback flag is sent to a local signal analysis board through a preset serial port;

[0026] Sending a readback flag to a remote network device through a local signal analysis board to start a readback operation, so as to read the readback data through the remote network device, and determine whether the readback data and the updated data match, and if they do not match, sending a backup start instruction to a preset programmable logic device through the remote network device;

[0027] Controlling the startup of the preset backup memory based on the backup startup instruction and the preset data decoder through the preset programmable logic device;

[0028] After the preset backup memory is successfully started, the preset backup memory is connected to the local through the preset signal line through the preset programmable logic device, so as to remotely upgrade the prototype verification board again.

[0029] Optionally, after controlling the preset data flow controller to write the selected update data into the target memory chip to be updated so as to remotely upgrade the prototype verification board, the method further includes:

[0030] The preset programmable logic device uses a preset data decoder to control the local memory chip and the memory chip of the slave device programmable logic device to restart.

[0031] In a second aspect, the present invention discloses a remote upgrade device for a prototype verification board, which is applied to a programmable logic device of a main device, comprising:

[0032] An upgrade file storage module, used to obtain the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, store the upgrade file in a preset external storage device;

[0033] A target chip determination module, configured to read corresponding update data from an upgrade file in a preset external storage device using a first preset bus transmission protocol, and determine a target memory chip to be updated based on a remote upgrade command sent by a preset programmable logic device;

[0034] The prototype verification board upgrade module is used to perform gating control on the update data based on the remote upgrade command, and control the preset data flow controller to write the gated update data into the target memory chip to be updated so as to remotely upgrade the prototype verification board.

[0035] In a third aspect, the present invention provides an electronic device, comprising:

[0036] Memory for storing computer programs;

[0037] The processor is used to execute a computer program to implement the remote upgrade method of the aforementioned prototype verification board.

[0038] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the remote upgrade method of the aforementioned prototype verification board.

[0039] In the present invention, the serial-to-parallel converted data information sent by the local signal analysis board is obtained through the first preset link layer protocol interface, and after the upgrade file is determined based on the serial-to-parallel converted data information, the upgrade file is stored in a preset external storage device; the corresponding update data is read from the upgrade file in the preset external storage device using the first preset bus transmission protocol, and the target memory chip to be updated is determined based on the remote upgrade command sent by the preset programmable logic device; the update data is selected based on the remote upgrade command, and the preset data flow controller is controlled to write the selected update data to the target memory chip to be updated, so as to remotely upgrade the prototype verification board.

[0040] It can be seen from the above technical solution that by using the preset protocol interface to transmit upgrade commands and upgrade files, and using the preset data flow controller to write the update data to the target memory chip to be updated to realize remote upgrading of the prototype verification board, the manpower and time required for local updates can be saved, thereby improving the efficiency of the prototype verification board upgrade. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A flow chart of a remote upgrade method of a prototype verification board provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of an update data flow structure provided by an embodiment of the present invention;

[0044] Figure 3 A flow chart of a method for remotely upgrading a prototype verification board provided by an embodiment of the present invention;

[0045] Figure 4 A data decoder control schematic diagram provided by an embodiment of the present invention;

[0046] Figure 5 A flowchart of a remote upgrade method for a specific prototype verification board provided by an embodiment of the present invention;

[0047] Figure 6 A specific CPLD timing control diagram provided by an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of a remote control supporting host computer software provided by an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of the structure of a remote upgrade device for a prototype verification board provided by an embodiment of the present invention;

[0050] Fig. 9 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0053] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0054] FPGA (Field Programmable Gate Array) is currently widely used in industrial design, chip prototype verification, communication, data acquisition, etc. However, as the requirements for FPGA logic resources in chip verification and other aspects are getting higher and higher, single-chip FPGA can no longer meet the needs of chip verification; secondly, because the location where the FPGA device is deployed may be in a remote computer room or other places where the equipment cannot be upgraded on site. Therefore, this application will specifically introduce a remote upgrade method for a prototype verification board to solve the above problems.

[0055] See also Figure 1 As shown, the embodiment of the present application discloses a remote upgrade method of a prototype verification board, which is applied to a main device programmable logic device, including:

[0056] Step S11: obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, storing the upgrade file in a preset external storage device.

[0057] In this embodiment, after obtaining the serial-to-parallel converted data information sent by the local signal parsing board through the first preset link layer protocol interface, and determining the upgrade file based on the serial-to-parallel converted data information, the upgrade file is stored in a preset external storage device, including: obtaining the serial-to-parallel converted data information sent by the local signal parsing board through the first preset link layer protocol interface; the serial-to-parallel converted data information is the information obtained after the first preset link layer protocol interface performs a serial-to-parallel conversion operation on the initial upgrade file; performing a sequence alignment operation on the serial-to-parallel converted data information based on a preset alignment sequence symbol to obtain target data information; after extracting the upgrade file from the target data information, the upgrade file is stored in a preset external storage device. Specifically, the main device programmable logic device (hereinafter referred to as the main FPGA) receives the signal from the local signal analysis board through the first preset link layer protocol interface, which is the Aurora interface (Aurora is a scalable lightweight link layer protocol for moving data between point-to-point serial links) in the present invention. The Aurora interface protocol has its own serial-to-parallel conversion. The main FPGA aligns the comma code (K code, which is a special sequence) according to the data after the serial-to-parallel conversion, and then extracts the data therein and stores the data in a preset external storage device. In the present invention, the preset external storage device uses DDR (Double Data Rate, i.e., double-rate synchronous dynamic random access memory) for subsequent FLASH updates.

[0058] It should be noted that in this embodiment, the present invention can remotely update the startup FLASH (FlashMemory, a non-volatile memory device) and the test case FLASH in the prototype verification board; wherein the instructions of the prototype verification board come from the remote computer. Therefore, before obtaining the serial-to-parallel converted data information sent by the local signal parsing board through the first preset link layer protocol interface, it also includes: obtaining the network protocol sent by the remote network device through the local signal parsing board; the network protocol includes the numbering information and update action instructions of the target memory chip to be updated; the numbering information and update action instructions in the network protocol are parsed by the local signal parsing board to extract the command information; the command information is sent to the preset programmable logic device through the local signal parsing board, and a corresponding command sending completion signal is generated; so that the preset programmable logic device generates a remote upgrade command after parsing the command information; the command sending completion signal is sent to the remote network device through the local signal parsing board, so that the remote network device sends the initial upgrade file to the local signal parsing board based on the command sending completion signal. Specifically, the information transmitted through the network will first be parsed by the local signal parsing board. The command information is first transmitted in the protocol transmission, which includes which FPGA to upgrade. In the present invention, each FPGA is numbered, and it is also indicated whether the upgrade startup FLASH or the test case FLASH. The coding table is shown in Table 1 below:

[0059] Table 1

[0060]

[0061] The local signal parsing board parses the network protocol, extracts command information from it, and sends the command information to a preset programmable logic device through a serial port. The preset programmable logic device in the present invention refers to a CPLD (Complex Programmable Logic Device). After the sending is completed, a command sending completion signal, that is, a done signal (indicating that the FPGA has successfully completed configuration and initialization, and the FPGA is ready to receive data and start processing) is returned to the remote terminal. After receiving the done signal, the remote terminal will send an upgrade file for the prototype verification board; the local signal parsing board will store it in an external memory and then pass it to the main FPGA through the Aurora interface.

[0062] Step S12: reading corresponding update data from an upgrade file in a preset external storage device using a first preset bus transmission protocol, and determining a target memory chip to be updated based on a remote upgrade command sent by a preset programmable logic device.

[0063] In this embodiment, the data sent from the remote computer is analyzed by the local signal analysis board and the main FPGA and then stored in the external storage device DDR of the main FPGA. The data needs to be read out through the AXI bus (Advanced eXtensible Interface, a bus protocol). According to the command information transmitted by the CPLD, it is decided whether to upgrade the related FLASH chip of the main FPGA or the FLASH chip of the SLAVE FPGA (slave programmable logic device).

[0064] Step S13: Based on the remote upgrade command, the update data is gated and controlled, and the preset data flow controller is controlled to write the gated update data into the target memory chip to be updated, so as to remotely upgrade the prototype verification board.

[0065] In this embodiment, the first preset communication protocol is used to connect to the device programmable logic device to complete the writing of the updated data. The first preset communication protocol used here is the C2C protocol (Consumer to Consumer). It should be noted that C2c is a high-speed interconnection protocol between FPGA chips, which can be connected to the Aurora interface to achieve high-throughput data transmission. C2C is a master-slave structure design. The master FPGA needs to be set to the Master (master node) end, and the SLAVE FPGA is set to the Slave (slave node) end. From the command flow analysis, the command can only flow from the master end to the Slave end; from the data flow analysis, the Master can read data from the Slave and write data to the Slave.

[0066] Furthermore, in a specific embodiment, when the target memory chip to be updated is the FLASH chip of the SLAVE FPGA, the preset data flow controller is controlled to write the selected update data to the target memory chip to be updated, including: based on the remote upgrade command, the preset data flow controller is controlled to connect with the first preset communication protocol of the slave device programmable logic device to send the selected update data to the slave device programmable logic device through the first preset communication protocol and the second preset link layer protocol interface; in the slave device programmable logic device, the update data is connected to the preset memory controller through the second preset communication protocol and the second preset bus transmission protocol, and the preset memory controller is used to write the update data to the target memory chip to be updated. Figure 2As shown, data is first read from DDR, and then under the data flow controller controlled by CPLD signals, the AXI SLAVE (Advanced eXtensible Interface Slave) of the C2C protocol is connected, and then converted to the C2C protocol through the Aurora interface. At this time, the AXI interface becomes an AXI MASTER (Advanced eXtensible Interface Master), which can be directly connected to the AXI2AHB interface, and finally the data is written to the external FLASH through the FLASH controller.

[0067] In a specific embodiment, when the target memory chip to be updated is a FLASH chip related to the upgrade main FPGA, controlling the preset data flow controller to write the selected update data to the target memory chip to be updated includes: based on the remote upgrade command, controlling the preset data flow controller to connect the update data to the preset memory controller through the third preset bus transmission protocol, and using the preset memory controller to write the update data to the target memory chip to be updated. Figure 2 As shown, AXI MASTER, as the data initiator, first reads data from DDR, and then connects the data stream to the FLASH controller through the AXI2AHB module under the data flow controller controlled by the CPLD signal.

[0068] In this embodiment, after controlling the preset data flow controller to write the selected update data into the target memory chip to be updated to remotely upgrade the prototype verification board, it also includes: performing a frequency division operation on the base frequency generated by the local preset phase lock latch loop to obtain a heartbeat signal; sending the heartbeat signal to the preset programmable logic device through the preset data decoder, so that the preset programmable logic device determines the readback flag based on the heartbeat signal, and then sends the readback flag to the local signal analysis board through the preset serial port; sending the readback flag to the remote network device through the local signal analysis board to start the readback operation, so as to read the readback data through the remote network device, and determine whether the readback data and the update data match, if not, sending a backup startup instruction to the preset programmable logic device through the remote network device; controlling the startup of the preset backup memory based on the backup startup instruction and the preset data decoder through the preset programmable logic device; after the preset backup memory is successfully started, the preset backup memory is connected to the local through the preset signal line through the preset programmable logic device to remotely upgrade the prototype verification board again. Specifically, when the FLASH remote update is completed, in order to facilitate the remote host to initiate the process of reading back the FLASH data, the main FPGA and SLAVE FPGA generate a heartbeat signal. The heartbeat signal frequency of each FPGA is different. The heartbeat signal is transmitted to the CPLD, and the CPLD combines the FPGA's init and done signals as a sign that it can be read back; the heartbeat signal is generated by the PLL (Phase Locked Loop) inside the FPGA. The base frequency is obtained by dividing the base frequency. The main FPGA and SLAVE FPGA are set to 1hz, 5hz, 10hz, and 20hz respectively, and sent to the CPLD. The CPLD needs to pass the read-back flag to the local signal analysis board through the serial port, and then the local signal analysis board passes it to the remote computer, and then initiates the read-back process. When the remote computer reads back the data and finds that the data does not match the original data, it will send a backup startup command to the CPLD, and the CPLD will start the backup FLASH. For example Figure 3As shown, at the same time, CPLD needs to control the startup FLASH of the main FPGA. In order to prevent the whole system from collapsing after the update fails, a backup FLASH is added. The backup FLASH stores the basic version. When the remote readback data verification fails, the backup FLASH will be started. After the backup FLASH is successfully started, the signal line will be connected to the original FLASH again through CPLD to upgrade again. In order to save the time of signal update, a backup FLASH can be started while upgrading, and the data can be written to the backup FLASH at the same time using the same data update method. For example, when upgrading the relevant FLASH chip of the main FPGA, the backup FLASH chip can be updated while updating the relevant FLASH chip; when the remote readback data verification fails after the update, the signal line can be directly connected to the backup FLASH through CPLD to complete the upgrade of the prototype verification board. If the remote readback data verification succeeds after the update, the backup FLASH can be discarded. In this way, the step of starting the backup FLASH when the remote read-back data verification fails and connecting the signal line to the original FLASH through the CPLD again after the backup FLASH is successfully started can be omitted, which saves a certain amount of time cost and speeds up the remote update rate.

[0069] In this embodiment, after controlling the preset data flow controller to write the selected update data to the target memory chip to be updated to remotely upgrade the prototype verification board, it also includes: using the preset data decoder to control the local memory chip and the memory chip of the slave device programmable logic device to restart. Specifically, Figure 4 As shown, CPLD controls the data decoder to realize the control of single FPGA or multiple FPGAs. When the FPGA board is upgraded, a single FPGA is controlled. When the upgrade is completed and needs to be restarted, multiple FPGAs need to be controlled.

[0070] Combination Figure 5The present invention is specifically described. The present invention can remotely update the startup FLASH and test case FLASH in the prototype verification board; wherein the instructions of the prototype verification board come from the remote computer, and are transmitted to the local signal analysis board through the network; the main function of the local signal analysis board is to analyze the commands and data from the remote computer, and pass the data to the CPLD through the serial port, and pass it to the main FPGA through the optical fiber Aurora interface. Among them, the CPLD is the downstream of the local signal analysis board, and its function 1 is to analyze the command information transmitted from the upstream, and its function 2 is to pass the command information to the main FPGA, and the command information will be used as the basis for board selection, and its function 3 is to receive the feedback signal sent by the prototype verification board, and the feedback signal will be used as the startup signal for the remote computer to start verifying the data in the FLASH, and its function 4 is to control which FPGA starts to upgrade, and its function 5 is to control the data decoder through the remote command information to realize the control of a single or multiple FPGAs and the judgment of the return signal. It should be noted here that, Figure 6 As shown, in the present invention, CPLD mainly exists as a control module. First, it receives the command information of the local signal analysis board and transfers the command information to the main FPGA after parsing; secondly, it controls the loading signal PROG (a configuration signal) of the FPGA. When the main FPGA writes the update file to the FLASH to be written, the CPLD will pull the PROG signal low and then high, and the corresponding FPGA will reload the bit stream file; finally, it controls the external decoding chip according to the command information to realize signal monitoring and control. The main FPGA is the "brain" of the prototype verification board. Its function 1 is to receive the remotely updated bin file (binary file) through the Aurora interface and store it in the DDR memory. Its function 2 is to parse the command sent by the CPLD and control the data read from the DDR. Its function 3 is to have a FLASH controller in the memory, which can update the startup FLASH and the test case FLASH. Its function 4 is to control the GPIO management to generate a heartbeat signal after the bit stream is reloaded. The heartbeat signal will be fed back to the CPLD. Its function 5 is the Master with internal integrated C2C, which can communicate with the SLAVE FPGA and then update the startup FLASH and the test case FLASH of the SLAVE FPGA. It should be noted here that because there are many modules in the prototype verification and the resources are large, one FPGA cannot meet the demand. Therefore, this application adds 3 SLAVE FPGAs to verify the prototype verification module. The SLAVE FPGA is a branch of the main FPGA and can verify modules other than the main FPGA. Its function 1 is to receive the instructions and data of the main FPGA through the Aurora interface, and operate the corresponding modules after parsing the instructions. Its function 2 is to generate a heartbeat signal and feed it back to the CPLD. In addition, the present invention also provides a host computer software interface, such as Figure 7As shown, the main functions include remote update, command sending, FLASH readback and other functions. Relevant commands can be sent through the host computer software interface for upgrading.

[0071] In the present invention, the serial-to-parallel converted data information sent by the local signal analysis board is obtained through the first preset link layer protocol interface, and after the upgrade file is determined based on the serial-to-parallel converted data information, the upgrade file is stored in a preset external storage device; the corresponding update data is read from the upgrade file in the preset external storage device using the first preset bus transmission protocol, and the target memory chip to be updated is determined based on the remote upgrade command sent by the preset programmable logic device; the update data is selected based on the remote upgrade command, and the preset data flow controller is controlled to write the selected update data to the target memory chip to be updated, so as to remotely upgrade the prototype verification board.

[0072] It can be seen from the above technical solution that by using the preset protocol interface to transmit upgrade commands and upgrade files, and using the preset data flow controller to write the update data to the target memory chip to be updated to realize remote upgrading of the prototype verification board, the manpower and time required for local updates can be saved, thereby improving the efficiency of the prototype verification board upgrade.

[0073] refer to Figure 8 The embodiment of the present application also discloses a remote upgrade device for a prototype verification board, which is applied to a main device programmable logic device, including:

[0074] The upgrade file storage module 11 is used to obtain the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, store the upgrade file in a preset external storage device;

[0075] A target chip determination module 12, configured to read corresponding update data from an upgrade file in a preset external storage device using a first preset bus transmission protocol, and determine a target memory chip to be updated based on a remote upgrade command sent by a preset programmable logic device;

[0076] The prototype verification board upgrade module 13 is used to perform gating control on the update data based on the remote upgrade command, and control the preset data flow controller to write the gating update data into the target memory chip to be updated to remotely upgrade the prototype verification board.

[0077] In this embodiment, it can be seen from the above technical scheme that by utilizing a preset protocol interface to transmit upgrade commands and upgrade files, and utilizing a preset data flow controller to write update data to the target memory chip to be updated to achieve remote upgrade of the prototype verification board, the manpower and time required for local updates can be saved, thereby improving the efficiency of the prototype verification board upgrade.

[0078] Furthermore, the present application also discloses an electronic device. Fig. 9 It is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the remote upgrade method of the prototype verification board disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0079] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0080] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0081] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the remote upgrade method of the prototype verification board executed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0082] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the remote upgrade method of the prototype verification board disclosed above is implemented. The specific steps of the method can refer to the corresponding contents disclosed in the above embodiments, and will not be repeated here.

[0083] Furthermore, the present application also discloses a computer program product, including a computer program / instruction; wherein the computer program / instruction, when executed by a processor, implements the aforementioned disclosed alarm aggregation method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0084] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0085] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0086] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0087] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0088] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A remote upgrade method for a prototype verification board, characterized in that: Applicable to master device programmable logic devices, including: Obtaining serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, storing the upgrade file in a preset external storage device; Reading corresponding update data from the upgrade file in the preset external storage device using a first preset bus transmission protocol, and determining a target memory chip to be updated based on a remote upgrade command sent by a preset programmable logic device; The update data is gated based on the remote upgrade command, and a preset data flow controller is controlled to write the gated update data into the target memory chip to be updated, so as to remotely upgrade the prototype verification board.

2. The remote upgrade method of the prototype verification board according to claim 1, characterized in that: The method of obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, storing the upgrade file in a preset external storage device includes: Obtaining serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface; the serial-to-parallel converted data information is information obtained after the first preset link layer protocol interface performs a serial-to-parallel conversion operation on the initial upgrade file; Performing a sequence alignment operation on the serial-to-parallel converted data information based on a preset alignment sequence symbol to obtain target data information; After the upgrade file is extracted from the target data information, the upgrade file is stored in a preset external storage device.

3. The remote upgrade method of the prototype verification board according to claim 2, characterized in that: Before obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, the method further includes: Acquire the network protocol sent by the remote network device through the local signal analysis board; the network protocol includes the serial number information of the target memory chip to be updated and the update action instruction; Parsing the numbering information and the update action instruction in the network protocol through the local signal parsing board to extract command information; The command information is sent to the preset programmable logic device through the local signal analysis board, and a corresponding command sending completion signal is generated; so that the preset programmable logic device generates the remote upgrade command after parsing the command information; The command sending completion signal is sent to the remote network device through the local signal parsing board, so that the remote network device sends the initial upgrade file to the local signal parsing board based on the command sending completion signal.

4. The remote upgrade method of the prototype verification board according to claim 1, characterized in that: The control preset data flow controller writes the selected update data into the target memory chip to be updated, including: Controlling a preset data flow controller to connect with a first preset communication protocol of a slave device programmable logic device based on the remote upgrade command, so as to send the selected update data to the slave device programmable logic device through the first preset communication protocol and the second preset link layer protocol interface; In the slave device programmable logic device, the update data is connected to a preset memory controller through a second preset communication protocol and a second preset bus transmission protocol, and the preset memory controller is used to write the update data into the target memory chip to be updated.

5. The remote upgrade method of the prototype verification board according to claim 1, characterized in that: The control preset data flow controller writes the selected update data into the target memory chip to be updated, including: Based on the remote upgrade command, a preset data flow controller is controlled to connect the update data to a preset memory controller through a third preset bus transmission protocol, and the preset memory controller is used to write the update data into the target memory chip to be updated.

6. The remote upgrade method of the prototype verification board according to claim 1, characterized in that: After the preset data flow controller is controlled to write the selected update data into the target memory chip to be updated so as to remotely upgrade the prototype verification board, the method further includes: Performing a frequency division operation on the base frequency generated by the local preset phase locking loop to obtain a heartbeat signal; The heartbeat signal is sent to the preset programmable logic device through a preset data decoder, so that after the preset programmable logic device determines a readback flag based on the heartbeat signal, the readback flag is sent to the local signal analysis board through a preset serial port; Sending the readback flag to the remote network device through the local signal analysis board to start a readback operation, so as to read the readback data through the remote network device, and determine whether the readback data matches the update data, and if they do not match, sending a backup startup instruction to the preset programmable logic device through the remote network device; Controlling the startup of the preset backup memory based on the backup startup instruction and the preset data decoder by the preset programmable logic device; After the preset backup memory is successfully started, the preset backup memory is connected to the local through a preset signal line through the preset programmable logic device, so as to remotely upgrade the prototype verification board again.

7. The remote upgrade method of the prototype verification board according to claim 6, characterized in that: After the preset data flow controller is controlled to write the selected update data into the target memory chip to be updated so as to remotely upgrade the prototype verification board, the method further includes: The preset programmable logic device uses the preset data decoder to control the local memory chip and the memory chip of the slave device programmable logic device to restart.

8. A remote upgrade device for a prototype verification board, characterized in that: Applicable to master device programmable logic devices, including: An upgrade file storage module, used for obtaining the serial-to-parallel converted data information sent by the local signal analysis board through the first preset link layer protocol interface, and after determining the upgrade file based on the serial-to-parallel converted data information, storing the upgrade file in a preset external storage device; a target chip determination module, configured to read corresponding update data from an upgrade file in the preset external storage device using a first preset bus transmission protocol, and determine a target memory chip to be updated based on a remote upgrade command sent by a preset programmable logic device; The prototype verification board upgrade module is used to perform gating control on the update data based on the remote upgrade command, and control the preset data flow controller to write the gating update data into the target memory chip to be updated to remotely upgrade the prototype verification board.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program to implement the steps of the remote upgrade method of the prototype verification board as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the remote upgrade method of the prototype verification board as claimed in any one of claims 1 to 7 are implemented.

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