Bus expansion device and data processing method

Abstract

The invention relates to the technical field of electronic information, and particularly discloses a bus expansion device and a data processing method, and the bus expansion device comprises a bus expansion module which is configured to be connected with a target bus; the bus expansion module is configured to interact a data signal with a first width with a target bus, and generate a first target data signal based on the data signal with the first width, or generate the data signal with the first width based on an acquired second target data signal; wherein the data width of the first target data signal is a first target width, and the data width of the second target data signal is a second target width; the first target width is equal to or greater than the first width and the second target width is greater than or equal to the first width. Based on the bus expansion module, the width of the target bus can be expanded, control over the data bus module with the data width larger than the first width is achieved, the problem of application limitation is solved, and the technical effect of flexible application is achieved.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a bus expansion device and a data processing method. Background Art

[0002] The Low Pin Count (LPC) bus is a low-pin parallel bus consisting of 13 signal lines, including 7 mandatory signals and 6 optional signals. Only 7 mandatory signals are needed to implement LPC communication, so the implementation method is relatively flexible. However, due to the data width limitation of the LPC bus or other similar buses, only device operations with corresponding data width can be implemented, resulting in application limitations. Summary of the invention

[0003] The present application provides a bus expansion device and a data processing method to at least solve the problem of bus application limitations caused by data width in the related art.

[0004] According to a first aspect, the present application provides a bus extension device, which is configured on a server; the bus extension device includes:

[0005] A bus extension module, configured to connect to a target bus; the bus extension module is configured to exchange a data signal having a first width with the target bus, and generate a first target data signal based on the data signal having the first width, or generate the data signal having the first width based on the acquired second target data signal;

[0006] Among them, the data width of the first target data signal is a first target width, and the data width of the second target data signal is a second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width.

[0007] According to a second aspect, the present application provides a data processing method, which is performed based on the bus expansion device provided in the first aspect, and the data processing method includes:

[0008] Acquire a data signal with a first width transmitted by the target bus;

[0009] generating a first target data signal based on the data signal having the first width, wherein the data width of the first target data signal is a first target width, and the first target width is equal to or greater than the first width;

[0010] or,

[0011] acquiring a second target data signal;

[0012] A data signal having a first width is generated based on the second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is greater than or equal to the first width.

[0013] According to the present application, a bus extension module connected to a target bus is provided in a bus extension device. The bus extension module interacts with the target bus and has a data signal having a first width, and can generate a first target data signal based on the data signal having the first width, wherein the data width of the first target data signal is greater than or equal to the first width, or generate a data signal having the first width based on an acquired second target data signal, wherein the data width of the second target data signal is greater than or equal to the first width. Thus, based on the bus extension module, the width of the target bus can be extended, and control of a module of a data bus having a data width greater than the first width is achieved, thereby improving the problem of application limitations and achieving a technical effect of flexible application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is an LPC interface solution in the related art;

[0015] Figure 2 The application architecture of a bus extension device according to an embodiment of the present application is shown in FIG. Figure 1 ;

[0016] Figure 3 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 1 ;

[0017] Figure 4 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 2 ;

[0018] Figure 5 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 3 ;

[0019] Figure 6 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 4 ;

[0020] Figure 7 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 5 ;

[0021] Figure 8 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 6 ;

[0022] Fig. 9A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 7 ;

[0023] Fig.10 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 8 ;

[0024] Fig.11 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 9 ;

[0025] Fig.12 A schematic diagram of a state transition flow of an algorithm state machine of a bus extension device according to an embodiment of the present application;

[0026] Fig.13 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 10 ;

[0027] Fig.14 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 10 one;

[0028] Fig.15 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 10 two;

[0029] Fig.16 The application architecture of a bus extension device according to an embodiment of the present application is shown in FIG. Figure 2 ;

[0030] Fig.17 A data processing method according to an embodiment of the present application is shown in FIG. Figure 1 ;

[0031] Fig.18 A data processing method according to an embodiment of the present application is shown in FIG. Figure 2 ;

[0032] Fig.19 A data processing method according to an embodiment of the present application is shown in FIG. Figure 3 . DETAILED DESCRIPTION

[0033] The core improvement of the present application is to provide a bus expansion device and a data processing method for expanding the data width of the data signal of the target bus, and realizing the control of the module of the data bus whose data signal width is greater than the data width of the target bus, so as to improve the application flexibility.

[0034] In some implementations, clock multiplication can be used to control a module with a high-speed clock signal using a low-speed target bus to increase the speed of data processing.

[0035] In some implementations, a password control module may also be provided to enhance security during data communication.

[0036] In some implementations, the bus extension device may be provided based on a programmable logic device, which is flexible to deploy and easy to implement.

[0037] The following is a clear and complete description of the technical solutions provided by the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] Figure 1 It is an LPC interface solution in the related technology. Figure 1 As shown, the LPC bus is located under the south bridge chip (PCH) of the server / computer (CPU); modules with LPC interfaces such as TPM (Trusted Platform Module) / TCM (Trusted Cryptography Module) can be used as LPC devices and inserted into the LPC slot on the motherboard to communicate with the south bridge chip (PCH). Since the LPC bus has only a 4-bit data bus, the server / computer can only control LPC devices (such as TPM / TCM) with a 4-bit data width through the LPC bus, but cannot control IO (Input Output) devices / modules with a data width exceeding 4 bits, such as 16-bit, 32-bit, 64-bit IO devices / modules, etc., which leads to application limitations.

[0039] In view of this, the embodiments of the present application propose a bus expansion device and a data processing method, which break the application limitations based on the expansion of data width. The above only takes the LPC bus as an example to illustrate the application limitations caused by data width. The application limitations of other buses due to data width can also be improved by using the technical solutions provided in the embodiments of the present application, which are not limited here.

[0040] For example, Figure 2 The application architecture of a bus extension device according to an embodiment of the present application is shown in FIG. Figure 1 .like Figure 2As shown, the bus extension device 100 provided in the embodiment of the present application is configured in the server 10. For example, the bus extension device 100 can be connected between the target bus 01 and the server 10, or the bus extension device 100 can be set in the server 10 (such as Figure 2 ), which is not limited here. One end of the bus extension device 100 is connected to the host computer 20 through the target bus 01, and the other end can be connected to the password module 30. Among them, the host computer 20 may include upper-layer application software operated by the user end. The user can set keys, registers, data to be calculated, etc. based on the operation on the host computer 20, and send them to the bus extension device 100 through the target bus 01, and can receive the data returned by the bus extension device 100. The bus extension device 100 expands the data transmitted from the target bus 01 into data of the corresponding width of the password module 30, and transmits it to the password module 30. The password module 30 calculates the received data and returns the calculated data to the bus extension device 100. The bus extension device 100 performs data conversion on the received calculated data, outputs data with a data width that meets the data transmission width of the target bus 01, and returns the calculated data to the host computer 20 through the target bus 01.

[0041] For example, Figure 3 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 1 .like Figure 3 As shown, the bus extension device 100 provided in the embodiment of the present application may include: a bus extension module 110, configured to connect to the target bus 01; the bus extension module 110 is configured to interact with the target bus 01 with a data signal having a first width, and generate a first target data signal based on the data signal having the first width, or generate a data signal having the first width based on the acquired second target data signal; wherein the data width of the first target data signal is the first target width, and the data width of the second target data signal is the second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width.

[0042] The target bus 01 may be a bidirectional data / address bus with a certain data width, and the certain data width may be represented as a first width. It is understandable that the first width is relatively small, and based on the bus expansion device 100, the data width of the data signal transmitted by the target bus 01 is expanded, so that the control of the module / device with a data width of a large number of bits can be realized. Exemplarily, the target bus 01 may be an LPC bus or other bus with a low data width, which is not limited here.

[0043] The bus extension module 110 is connected to the target bus 01, and can receive a data signal with a first width transmitted by the target bus 01, or output a data signal with a first width to the target bus 01. Further, the bus extension module 110 can perform data expansion based on the received data signal with the first width, and generate a first target data signal with a first target width to achieve control of the module / device with the first target width. Alternatively, the bus extension module 110 can obtain a second target data signal with a second target width transmitted by a module / device with a second target width, and convert the second target data signal into at least one data signal with a first width, and transmit it through the target bus 01, thereby achieving control of the module / device with the second target width through the target bus 01.

[0044] The first target width and the second target width may be the same or different, which is not limited here. When the second target width and the first target width are the same, the module / device controlled based on the target bus may be the same module / device, which is not limited here.

[0045] In some implementations, when the first target width and the second target width are both equal to the first width, control of a module / device having the first width can be implemented based on the target bus, so that the setting of the bus extension device 100 does not affect the control of the module / device having the first width.

[0046] In some implementations, when the first target width is greater than the first width and the second target width is greater than the first width, control of modules / devices with larger data widths can be achieved based on the target bus and the bus extension device 100, thereby breaking the application limitations of the target bus.

[0047] The bus extension device 100 provided in the embodiment of the present application includes a bus extension module 110, which is capable of receiving a data signal with a first width transmitted by a target bus 01 and generating a first target data signal with a first target width; or obtaining a second target data signal, and generating a data signal with a first width, and transmitting it via the target bus 01; wherein the first target width is greater than or equal to the first width, and the second target width is greater than or equal to the first width, thereby achieving the expansion of the data width transmitted by the target bus 01, breaking the application limitation of the target bus 01 caused by the data width limitation, and improving the application flexibility of the target bus 01.

[0048] In some implementations, Figure 4 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 2 , which shows a specific structure of the bus expansion module 110. Figure 4As shown, in the bus extension device 100 provided in the embodiment of the present application, the bus extension module 110 may include a control module 111, a counting module 112 and a first data buffer area 113, and the counting module 112 and the first data buffer area 113 are respectively connected to the control module 111; the counting module 112 is configured to count the data cycle of the target bus and transmit the count value to the control module 111; the first data buffer area 113 is configured to store a data signal of at least one data cycle transmitted by the target bus; the control module 111 is configured to generate a first target data signal based on the data signal of at least one data cycle stored in the first data buffer area 113 based on the count value reaching the target count value, and output a cycle valid signal of the first target data signal.

[0049] Among them, the input end of the counting module 112 is connected to the bus cycle signal LFRAME of the target bus 01, and the output end of the counting module 112 is connected to the control module 111. The bus cycle signal LFRAME is the start signal of the data cycle of the target bus 01, and the bus cycle signal LFRAME is valid at a low level. Based on this, when the bus cycle signal LFRAME switches to a low level, it indicates the start of a data cycle; the period when the bus cycle signal LFRAME is at a low level corresponds to a data cycle. The counting module 112 can count the data cycles of the target bus, and in each data cycle, a valid data signal LAD[3..0] is transmitted on the target bus.

[0050] Exemplarily, the count value may be n (n=1, 2, ..., N), that is, n is a positive integer. The target count value may be set by the user based on the data width requirement of the target data signal, that is, based on the data expansion requirement, and its specific value is not limited here. When the count value reaches the target count value, the control module 111 outputs a cycle valid signal of the first target data signal, that is, generates an extended bus cycle signal, Figure 4 The extended bus cycle signal is shown as FRAME in FIG.

[0051] Exemplarily, when the first width is 4 bits and the first target width is 16 bits, the target count value is 16 bits / 4 bits, that is, the target count value is 4. Based on this, when the count value is accumulated from 1 to 4, the target bus transmits 4 data signals LAD[3..0] with the first width, that is, after satisfying 4×4 bits=16 bits, the control module 111 generates an extended bus cycle signal FRAME. Exemplarily, the extended bus cycle signal FRAME is low level valid.

[0052] The first data buffer area 113 is used to temporarily store the data signals corresponding to the target count value transmitted on the target bus. Exemplarily, the first data buffer area 113 can be a volatile storage unit, such as a random access memory (RAM) or other components with storage functions, which are not limited here.

[0053] The capacity of the first data buffer area 113 can be set according to the need of data width expansion. In different application scenarios, the capacity of the first data buffer area 113 can be changed. Exemplarily, the capacity of the first data buffer area 113 can be set to an integer multiple of the first width to store the data signal LAD[3..0] transmitted by the target bus. Exemplarily, the first width is 4 bits, and the capacity of the first data buffer area 113 can be 4N bits, where N represents the target count value.

[0054] The control module 111 can receive the count value of the counting module 112, and output the extended bus cycle signal FRAME based on the count value reaching the target count value; and output the first target data signal DATA[4n-1..0] (n=1, 2, ..., N) after data splicing according to the data stored in the first data buffer area 113. Exemplarily, when the first target width is 16 bits, the target count value N=4, and the first target data signal can be DATA[15..0].

[0055] In the bus extension device 100 provided in the embodiment of the present application, the bus extension module 110 is configured to include a control module 111, a counting module 112 and a first data buffer area 113. The counting module 112 can count the data cycle of the target bus and transmit the count value to the control module 111; the first data buffer area 113 can store a data signal of at least one data cycle transmitted by the target bus; the control module 111 can generate a first target data signal based on the data signal of at least one data cycle stored in the first data buffer area 113 when the count value reaches a target count value, and output a cycle valid signal of the first target data signal, thereby realizing data width expansion.

[0056] In some implementations, Figure 5 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 3 , which shows a specific structure of the counter. Figure 5 As shown, in the bus extension device provided in the embodiment of the present application, the counting module 112 may include an accumulator ADD; the accumulator ADD counts the data cycle based on the cycle start signal (ie, the bus cycle signal LFRAME) transmitted by the target bus.

[0057] Among them, when the bus cycle signal LFRAME is at a low level, the count is increased by 1, and the output terminal Q of the D flip-flop DR_FF_1 with reset generates a periodic count value cnt[5..0]. Taking the count range of 1 to 32 as an example, when the count value cnt=32, it will return to 0 and re-counting is valid, and the accumulator ADD counts by 1. Exemplarily, when the bus cycle signal is at a low level, the accumulator ADD counts by 1, and the output terminal Q of the D flip-flop DR_FF_1 with reset generates a periodic count value cnt[5..0]. Exemplarily, if the target count value is 32, the count range is 1 to 32, and when the count value reaches 32, the accumulator ADD will return to 0 and re-count.

[0058] In the bus extension device 100 provided in the embodiment of the present application, by setting the counting module 112 to include an accumulator ADD, the counting function can be implemented based on a simple hardware circuit structure, and the hardware structure is simple.

[0059] It should be noted that, in other implementations, the counting module 112 may also be implemented based on other structural components with counting functions, which will not be elaborated or limited here.

[0060] In some implementations, Figure 6 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 4 , which shows a specific structure of the first data buffer area 113. Figure 6 As shown, in the bus extension device provided in the embodiment of the present application, the first data cache area 113 includes at least one first storage unit 1131; the capacity of the first storage unit 1131 matches the first width and is configured to store a data signal of at least one data cycle.

[0061] The first data buffer area 113 may include a first storage unit 1131, which may store a data signal with a first width transmitted by the target bus, so that the bus extension device 100 can control the module / device with the first width. Alternatively, the first data buffer area 113 may include two or more first storage units 1131, each of which may store a data signal with a first width transmitted by the target bus, so as to achieve splicing and expansion of the data signal. The capacity of the first storage unit 1131 may be equal to the first width, so as to store the data signal with the first width.

[0062] Exemplarily, if the first width is 4 bits, the capacity of the first storage unit may be 4 bits. If the target count value is N, the number of first storage units 1131 may be N, and the data stored in each first storage unit 1131 may be D[4n-1, 4n-4] (n=1, 2, ..., N), so as to achieve N-fold expansion of the data signal transmitted by the target bus.

[0063] In the bus extension device 100 provided in the embodiment of the present application, the first data cache area 113 may include a number of first storage units 1131 matching the number of target count values, and each first storage unit 1131 may store a data signal within a data cycle transmitted by the target bus, so as to splice and output the data signal within at least one data cycle stored in the first data cache area 113, thereby realizing data expansion and improving the flexibility of bus application.

[0064] In some implementations, see Figure 5 In the bus extension device provided in the embodiment of the present application, the control module 111 includes an RS trigger RS_FF and a first inverter. Exemplarily, the first inverter is shown as a first NOT gate NOT_14; the data input terminal D of the RS trigger RS_F is connected to the first level, the carry terminal C of the RS trigger RS_F is connected to the second level, the set terminal S and the clear terminal R of the RS trigger RS_F are connected to the counting module 112, and the output terminal of the RS trigger RS_F is connected to the output terminal of the control module 111 through the first inverter; the RS trigger RS_F outputs a period valid signal of the first target data signal based on the count value reaching the target count value, that is, the expanded bus cycle signal.

[0065] The first level is a high level, and the second level is a low level. The set terminal S of the RS flip-flop RS_FF is connected to the output terminal of the AND gate AND_2, and the clear terminal R is connected to the output terminal of the OR gate OR. The specific connection is as follows: Figure 5As shown, the output terminal Q of RS_FF is connected to the output terminal of the control module through the NOT gate NOT_14. Among them, the data input terminal D of the RS flip-flop RS_FF is connected to a high level, so that the value output by the output terminal Q outputs '0' or '1' according to the values ​​of the set terminal S and the clear terminal R; specifically, when R = '1', Q = '0'; when S = '1' and R = '0', Q = '1'. The carry terminal C of the RS flip-flop RS_FF is connected to a low level, so that the value of the output terminal Q is not affected by the carry signal of the carry terminal C. The set terminal S of the RS flip-flop RS_FF is connected to the output terminal of the AND gate AND_2, and the clear terminal R is connected to the output terminal of the OR gate OR; when the system is reset (LRESET = '0'), the reset signal LRESET transmitted by the target bus becomes '1' through the NOT gate NOT_7, and is input to the OR gate OR, so that the OR gate OR outputs '1'. At this time, the clear terminal R of the RS flip-flop RS_FF is '1', so that the value output by the output terminal Q is '0'; when the system is in a non-reset state ( When LRESET='1'), and the output of the D flip-flop DR_FF_1 with reset is cnt[5..0]="100000" (100000 is a binary number, corresponding to the decimal number 32), the lower 5 bits of cnt[4..0]="00000" become "11111" after passing through NOT gates NOT_9~NOT12, and then output a high level '1' after passing through AND gate AND_2, so the set terminal S of the RS flip-flop RS_FF='1 '; The highest bit cnt[5]='1' of cnt becomes '0' after passing through the NOT gate NOT_8 and is input to the OR gate OR. When in the non-reset state, LRESET='1' passes through the NOT gate NOT_7 and becomes '0' and is also input to the OR gate OR. At this time, the OR gate OR outputs '0', so the value of the reset terminal R of the RS flip-flop RS_FF is '0', and the output terminal Q of the RS flip-flop RS_FF is '1'; when cnt is 1-31, since the highest bit cnt[5]='0', it becomes '1' after passing through the NOT gate NOT_8, making the OR gate OR output '1', and the reset terminal R of the RS flip-flop RS_FF is '1', and the output terminal Q is '0'; the output terminal Q of the RS flip-flop RS_FF is connected to the output terminal FRAME through the NOT gate NOT_14. Therefore, whenever the count value cnt reaches 32, the extended bus cycle signal FRAME generates a low level, and in other cases, the extended bus cycle signal FRAME is a high level.

[0066] Therefore, when the count value reaches the target count value, such as 32, the output end of the control module outputs the expanded bus cycle signal FRAME as a valid signal, such as generating a low level; in other cases, the expanded bus cycle signal FRAME is an ineffective signal, such as outputting a high level signal.

[0067] In the bus extension device 100 provided in the embodiment of the present application, by setting the control module 111 to include an RS trigger RS_FF and a first inverter, the function of outputting an extended bus cycle signal based on the count value reaching the target count value can be realized based on a simple hardware circuit structure, and the hardware structure is simple.

[0068] It should be noted that, in other implementations, the control module 111 may also be implemented based on other structural components, which will not be elaborated or limited here.

[0069] In some implementations, Figure 7 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 5 , which shows another specific structure of the control module 111. Figure 7 As shown, in the bus extension device provided in the embodiment of the present application, the control module 111 also includes a second inverter and a first D flip-flop D_FF_2. Exemplarily, the second inverter is shown as a second NOT gate NOT_15; the clock end of the first D flip-flop D_FF_2 is connected to the cycle start signal of the target bus through the second inverter, the input end of the first D flip-flop D_FF_2 is connected to the data signal of the target bus, and the output end Q of the first D flip-flop D_FF_2 is connected to the first data buffer area 113; the first D flip-flop D_FF_2 stores the data signal of the target bus in the first data buffer area 113 based on the cycle start signal being a valid signal, and based on the difference in the count value, transfers the data in the first storage unit 1131 corresponding to the first data buffer area 113 to the position corresponding to the first target data signal.

[0070] The control module 111 can read the data transmitted on the target bus, store the data in the first data buffer 113, and output the data in the first data buffer 113 to the data port DATA[127..0].

[0071] Figure 7In the embodiment, the bus cycle signal LFRAME is connected to the clock terminal of the first D flip-flop D_FF_2 through the second NOT gate NOT_15. When the bus cycle signal LFRAME is a valid signal (low level), the data signal LAD[3..0] having the first width is sequentially stored in the first storage unit 1131 of the first data buffer area 113 through the output terminal Q of the first D flip-flop D_FF_2; and according to different count values, the data corresponding to different first storage units 1131 are transferred to the position corresponding to the first target data signal. Exemplarily, the first target data signal is shown as DATA[127..0]. When the count value is 1, the data of the first first storage unit 1131 in the first data buffer area 113 is transferred to the lower 4 bits DATA[3..0] of the first target data signal DATA[127..0], and so on.

[0072] In the bus extension device 100 provided in the embodiment of the present application, by setting the control module 111 to also include a second inverter and a first D flip-flop D_FF_2, it is possible to achieve data splicing between different first storage units 1131 in the first data cache area 113 based on the counting order, thereby achieving data width expansion and improving the application flexibility of the target bus.

[0073] It should be noted that, in other implementations, the control module 111 may also be implemented based on other structural components, which will not be elaborated or limited here.

[0074] In some implementations, Figure 8 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 6 , which shows another specific structure of the bus expansion module 110. Figure 8 As shown, in the bus extension device provided in the embodiment of the present application, the bus extension module 110 further includes a clock module 114, and the clock module 114 is connected to the control module 111; the clock module 114 is configured to multiply the clock signal LCLK transmitted by the target bus under the control of the control module 111 to generate a target clock signal CLK. Specifically, the control module 111 can control the clock module 114 to adjust the clock coefficient and output the multiplied target clock signal.

[0075] The input end of the clock module 114 is connected to the clock signal LCLK transmitted by the target bus. Taking the target bus as the LPC bus as an example, the frequency of the clock signal is 33 MHz.

[0076] In the bus extension device 100 provided in the embodiment of the present application, the bus extension module 110 also includes a clock module 114. Under the control of the control module 111, the clock module 114 can multiply the clock signal LCLK transmitted by the target bus, so as to achieve data width expansion while controlling the module / device of the high-speed clock signal by using the low-speed target bus.

[0077] In some implementations, see Figure 5 In the bus extension device provided in the embodiment of the present application, the clock module 114 may include a phase-locked loop PLL; the input end of the phase-locked loop PLL is connected to the clock signal LCLK of the target bus, and the phase-locked loop PLL is configured to multiply the clock signal LCLK transmitted by the target bus to generate a target clock signal.

[0078] A phase-locked loop (PLL) may be used as the clock module 114 to increase the clock frequency.

[0079] For example, the multiplication factor of the phase-locked loop PLL can be 2, which increases the 33 MHz frequency of the clock signal LCLK transmitted by the target bus to the 66 MHz frequency of the target clock signal, and outputs it to the clock terminal CLK as the clock signal of the controlled module, such as the password module. Figure 5 As shown, the multiplication factor of the phase-locked loop PLL can be 4, and the input 33 MHz clock signal is multiplied by 4 to output a 132 MHz target clock signal.

[0080] In other implementations, the multiplication coefficient of the phase-locked loop PLL can also be set to other values, which can be set according to the frequency multiplication requirements and are not limited here. Specifically, the control module 111 can control the phase-locked loop PLL to adjust the multiplication coefficient and output a target clock signal that meets the frequency requirements.

[0081] In some implementations, the parameters of the phase-locked loop PLL may be adjusted according to the clock frequency of the controlled module, such as the cryptographic module, to achieve synchronization between the clock signal LCLK transmitted by the target bus and the clock of the cryptographic module.

[0082] In some implementations, the multiplication factor of the phase-locked loop PLL may also be set to 1, so that the clock frequency remains unchanged, that is, the clock terminal CLK still outputs a target clock signal of 33 MHz.

[0083] In the bus extension device 100 provided in the embodiment of the present application, the clock module 114 may include a phase-locked loop PLL, and the multiplication coefficient of the phase-locked loop PLL is set, so as to meet the matching requirements of different clock frequencies, and the hardware circuit structure is simple and easy to implement.

[0084] In some implementations, continue to refer to Figure 5In the bus extension device provided in the embodiment of the present application, the control module 111 further includes a second D flip-flop D_FF_1; the clock end of the second D flip-flop D_FF_1 is connected to the clock signal of the target bus, and the data input end of the second D flip-flop D_FF_1 is connected to the reset signal of the target bus; the second D flip-flop D_FF_1 is configured to output a new reset signal RESET corresponding to the first target data signal after controlling the effective time of the reset based on the reset signal LRESET of the target bus. Exemplarily, the reset signal can be a low-level effective signal.

[0085] Specifically, the reset signal LRESET of the target bus is delayed by one clock cycle through the second D flip-flop D_FF_1 to form a new reset signal RESET, which is output to the reset terminal of the bus extension module 110 .

[0086] In the bus extension device 100 provided in the embodiment of the present application, the control module 111 can also receive the reset signal LRESET transmitted by the target bus and perform control, such as adjusting or keeping the effective time of the reset unchanged, and then outputting a new reset signal RESET to meet the reset requirements of the controlled device.

[0087] It should be noted that Figure 5 The clock signal ( Figure 5 LCLK in the figure), reset signal ( Figure 5 LRESET) and the data cycle signal ( Figure 5 ), generating an extended clock signal ( Figure 5 CLK), reset signal ( Figure 5 RESET) and the data cycle signal ( Figure 5 FRAME in FIG. 1 ), the circuit structure may include a phase-locked loop ( Figure 5 PLL), 1 D flip-flop ( Figure 5 1 D flip-flop with reset terminal ( Figure 5 DR_FF_1 in the figure), 1 RS flip-flop ( Figure 5 RS_FF), 2 two-choice data selectors ( Figure 5 MUX_1 to MUX_2), a 6-bit accumulator ( Figure 5 ADD in the figure), 2 AND gates ( Figure 5 AND_1 to AND_2), 1 OR gate ( Figure 5 ), 14 NOT gates ( Figure 5 The connection relationship between the structures is shown as NOT_1 to NOT_14. Figure 5 In other implementations, the bus extension module may also be implemented using other circuit structures that can implement the above-mentioned extension functions, without limitation.

[0088] In some implementations, Fig. 9 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 7 , which shows another specific structure of the bus extension device. Fig. 9 As shown, the bus extension device 100 provided in the embodiment of the present application may also include a password control module 120, which is connected to the bus extension module 110, and the password control module 120 is also configured to connect to the target password module 300; the password control module 120 is configured to generate a password control signal based on the first target data signal, and the password control signal is configured to control the target password module 300.

[0089] The first target data signal is an extended signal based on the data signal transmitted by the target bus 01. The password control module 120 is connected to the bus extension module 110, and can receive the first target data signal and generate a password control signal to control the target password module 300 connected to the password control module 120. The password control signal can also be understood as a password algorithm control signal, which can control the target password module 300. The data width of the first target data signal matches the data width of the target password module 300 to control the target password module 300.

[0090] The bus extension device 100 provided in the embodiment of the present application includes a bus extension module 110 and a password control module 120. The bus extension module 110 can realize the width expansion of the data signal transmitted by the target bus, thereby improving the application flexibility of the target bus; and the password control module 120 can control the target password module 300 to improve the security of the data.

[0091] In some embodiments, when the bus expansion module 110 expands the width of the data signal by a multiple of 1, that is, the first target data signal has the same data width as the data signal transmitted by the target bus, the target cryptographic module 300 may be a TCM or a TPM. In other embodiments, when the bus expansion module 110 expands the width of the data signal by a multiple greater than 1, that is, the data width of the first target data signal is greater than the data width of the data signal transmitted by the target bus, the target cryptographic module 300 may be a cryptographic module with a corresponding data width, such as an SM4 cryptographic module, which is not limited herein.

[0092] In some implementations, Fig.10 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 8, which shows a specific structure of the password control module 120. Fig.10 As shown, in the bus extension device provided in the embodiment of the present application, the password control module 120 includes an algorithm state machine 121 and a second data buffer 122, and the second data buffer 122 is connected to the algorithm state machine 121; the algorithm state machine 121 is configured to transmit the first target data signal to the second data buffer 122 based on the periodic valid signal of the first target data signal; the second data buffer 122 is configured to store at least one first target data signal in the second data buffer 122 based on the control of the algorithm state machine 121, and interact with the target password module 300. Exemplarily, the second data buffer 122 can be a volatile storage unit, such as a random access memory (RAM) or other components with storage functions, which are not limited here.

[0093] Among them, the algorithm state machine 121 can control the data transmission between the first data buffer area 113 and the second data buffer area 122, and control the target password module 300. Specifically, when the extended bus cycle signal FRAME is valid, the cycle valid signal corresponding to the first target data signal, at this time, the algorithm state machine 121 transmits the first target data signal to the second data buffer area 122. At least one first target data signal can be temporarily stored in the second data buffer area 122, and a control signal for the target password module 300 can be generated based on the stored at least one first target data signal, thereby realizing the control of the target password module 300.

[0094] In the bus extension device 100 provided in the embodiment of the present application, by setting the password control module 120 to include an algorithm state machine 121 and a second data buffer area 122 connected to the bus extension module 110, the first target data signal formed by splicing and expanding the data stored in the first data buffer area 113 can be transmitted to the second data buffer area 122 based on the effective period signal of the first target data signal, and further transmitted to the target password module 300, thereby realizing control of the target password module 300.

[0095] In some implementations, Fig.11 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 9 , which shows another specific structure of the password control module 120. Fig.11As shown, in the bus extension device provided in the embodiment of the present application, the cryptographic control module 120 also includes a function register 123, the input end of the function register 123 is connected to the algorithm state machine 121, and the output end of the function register 123 is connected to the target cryptographic module 300; the function register 123 is configured to output the target operation instruction to the target cryptographic module 300 based on the control of the algorithm state machine 121, and the target operation instruction includes at least one of an operation instruction for writing a key to the target cryptographic module 300, an operation instruction for writing a data packet length to the target cryptographic module 300, and an operation instruction for data encryption and decryption.

[0096] Exemplarily, the function register 123 may be a register composed of 3 bits, which is used to represent different operation commands of the algorithm state machine 121 to the target cryptographic module 300, and different operation instructions may be output to the target cryptographic module 300 through the command port OP[2..0]. The functions of each bit are as follows: OP[0]: The initial value of this bit is '0', which is set by the algorithm state machine 121. When it is set to '1', it indicates an operation instruction to write a key to the target cryptographic module. Exemplarily, the key may be represented as KEY[4n-1..0]; OP[1]: The initial value of this bit is '0', which is set by the algorithm state machine 121. When it is set to '1', it indicates an operation instruction to write a data packet length to the target cryptographic module. Exemplarily, the data packet length may be represented as LEN[4n-1..0]; OP[2]: This bit is set by the user in the upper computer software. When it is set to '1', it indicates an operation instruction to encrypt data, and when it is set to '0', it indicates an operation instruction to decrypt data.

[0097] In the bus extension device 100 provided in the embodiment of the present application, by setting the password control module 120 to include a function register 123, different operations on the target password module 300 can be implemented based on operation instruction control, while ensuring data security and simplifying the control method.

[0098] In some implementations, Fig.12 FIG. 1 is a schematic diagram of a state transition process of an algorithm state machine of a bus extension device according to an embodiment of the present application, showing a state transition process step of the algorithm state machine 121. Fig.12 As shown, the algorithm state machine 121 includes the following states: IDLE, START, WR_KEY, WR_LEN, WR_DATA, WAIT, RD_DATA, FINISH. Exemplarily, when the bus extension device 100 is implemented based on a programmable device, such as a field programmable gate array (FPGA), the algorithm state machine 121 can be implemented by VHDL programming of the FPGA, which is not limited here.

[0099] like Fig.12 As shown, the conversion / transition relationship between different states may include the following steps:

[0100] After the system is reset (eg, RESET = "0"), it enters the IDLE state. When the reset is completed and the target bus transmits a cycle start signal (eg, FRAME = '0'), the algorithm state machine 121 enters the START state.

[0101] In the START state, the algorithm state machine 121 sets the function register 123 to write a key to the target cryptographic module 300, that is, the algorithm state machine 121 sets OP[0]='1' of the function register 123, and then enters the write key WR_KEY state;

[0102] In the write key WR_KEY state, the algorithm state machine 121 sends the key data in the second data buffer area 122, such as KEY[127..0], to the target cryptographic module 300; and sets the function register 123 to write the length to the target cryptographic module 300, that is, sets OP[1]='1' of the function register 123, and then enters the write length WR_LEN state;

[0103] In the write length WR_LEN state, the algorithm state machine 121 sends the length data in the second data buffer area 122, such as LEN[127..0], to the target cryptographic module 300, and then enters the write data WR_DATA state;

[0104] In the write data WR_DATA state, the algorithm state machine 121 sends the password data stored in at least one second storage unit 1221 in the second data buffer area 122 to the target password module 300 according to the password length value LEN in the length data, and then enters the wait WAIT state;

[0105] In the WAIT state, the algorithm state machine 121 waits for the target cryptographic module 300 to complete the operation, and enters the RD_DATA state based on the completion of the operation (eg, DONE='1');

[0106] In the data reading RD_DATA state, the algorithm state machine 121 reads the data ciphertext or data plaintext after the target cryptographic module 300 completes the operation, and stores it in at least one second storage unit 1221 in the second data buffer area 122; then enters the end FINISH state;

[0107] At the end of the FINISH state, the algorithm state machine 121 clears the flag bit of the function register 123, that is, clears the OP[0] bit and the OP[1] bit of the function register 123, and then returns to the IDLE state.

[0108] So far, one data processing process of controlling the target password module 300 is completed, and the above steps will be repeated for the next data processing.

[0109] In some implementations, Fig.13 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 10 , which shows a specific structure of the second data buffer area 122. Fig.13 As shown, in the bus extension device provided in the embodiment of the present application, the second data cache area 122 includes a key data storage unit 1222, a length data storage unit 1223 and at least one second storage unit 1221; the key data storage unit 1222 is configured to store key data, the length data storage unit 1223 is configured to store length data, and the second storage unit 1221 is configured to store cryptographic data of different data groups, and a group of cryptographic data includes a first target data signal.

[0110] For example, when the first data width is 4 bits, the first target width of the first target data signal is 4n bits, and the capacity of each second storage unit 1221 can be 4n bits. Similar to the first data cache area, the storage capacity of the entire second data cache area 122 can be set by the user according to data storage requirements, or dynamically changed based on different reference scenarios, which is not limited here.

[0111] For example, Fig.13 Taking the orientation of the second data cache area 122 shown as an example, in order from bottom to top, the first storage unit may be a key data storage unit 1222, used to store key data KEY[4n-1..0]; the second storage unit may be a length data storage unit 1223, used to store length data LEN[4n-1..0], indicating the number of data packets to be encrypted / decrypted, that is, LEN=M (M≥1), indicating that there are M data packets to be encrypted / decrypted, and the corresponding data width is M×4n bit; the 3rd to M+2nd storage units may be second storage units 1221, all used to store the first target data signal; the first target data signal DATA[4n-1..0] may be stored in the 3rd to M+2nd second storage units 1221 in sequence.

[0112] In the bus extension device 100 provided in the embodiment of the present application, the algorithm state machine 121 also controls the key data KEY[4n-1..0] in the second data buffer area 122 to be transmitted to the key port of the target cryptographic module 300 through the key output terminal KEY; the length data LEN[4n-1..0] is transmitted to the length port of the target cryptographic module 300 through the length output terminal LEN; the data packets DATA_1~DATA_M are sequentially transmitted to the data input port of the target cryptographic module 300 through the data output terminal DATA_OUT[4n-1..0]; the command port OP[2..0] is connected to the command control port of the target cryptographic module 300 to realize the transmission of operation instructions and realize the control of the target cryptographic module 300 based on the operation instructions.

[0113] In some implementations, Fig.14 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 10 1, which shows another specific structure of the bus extension device. Fig.14 As shown, in the bus extension device provided in the embodiment of the present application, the algorithm state machine 121 and the second data cache area 122 are also respectively connected to the control module 111 in the bus extension module 110; the algorithm state machine 121 is also configured to send a ready completion signal to the control module 111 based on receiving the data packets completed by the target cryptographic module 300 and transmitting the data packets to different second storage units 1221 in the second data cache area 122; the control module 111 is also configured to read the second target data signal in the target second storage unit 1221 in the second data cache area 122 based on the ready completion signal, and store the second target data signal in the first storage unit 1131 in the first data cache area 113 in the bus extension module 110 in a first width format.

[0114] Specifically, the algorithm state machine 121 can also receive the operation completion signal DONE of the target cryptographic module 300. When DONE = '1', the data packet of the target cryptographic module 300 operation completion is received through the data input port DATA_IN[4n-1..0], that is, the encrypted data ciphertext or the decrypted data plaintext, and the data packet is sequentially transmitted to the second data buffer area 122; after the data transmission is completed, the output terminal READY changes to a high level '1'. Correspondingly, the control module 111 receives the READY signal of the algorithm state machine 121. When READY = '1', the data in the second data buffer area 122 is read through the data exchange port DATA, and the data is the second target data signal, and the read data is sequentially stored in the first data buffer area 113 in the format of the first width, such as 4 bits, so that the data can be transmitted through the target bus.

[0115] In some implementations, Fig.15 A schematic diagram of a bus expansion device according to an embodiment of the present application Figure 10 2. The bus expansion module 110 reads data DATA[127..0], stores it in the first data buffer 113, and then transmits it to the target bus. Take the first width as 4 bits and the second target width as 128 bits as an example. In the figure, the control module 111 includes a three-state buffer Tri, a multiplexer SEL, and 32 comparators CMP_1 to CMP_32. The control end of the three-state buffer Tri is connected to the READY signal. When READY = '1', the three-state buffer Tri is turned on, and the data DATA[127..0] can be output through the three-state gate, and connected to the corresponding input end d of the multiplexer SEL after being split into 4 bits; one input end of the comparator CMP_1~CMP_32 is connected to the count value cnt, and the other input end is the comparison value, which is set to 1~32 respectively; the output ends of CMP_1~CMP_32 are respectively connected to the selection control end e of the multiplexer SEL, and the output end of the multiplexer SEL is connected to the first data buffer area 113; the multiplexer SEL can select the corresponding data for output according to the output results of each comparator. For example, when the count value cnt = 1, the first CMP_1 outputs a high level, and the other comparators output a low level. At this time, the data DATA[3..0] is output to the first data buffer area 113 through the multiplexer SEL, and so on. After the data is transmitted to the first data buffer area 113, it is transmitted to the target bus.

[0116] In some implementations, the target bus includes an LPC bus; the bus extension device is implemented based on a programmable logic device, and the first target width and the second target width are both integer multiples of the first width.

[0117] The bus extension device 100 provided in the embodiment of the present application can extend the LPC bus based on a programmable logic device, such as an FPGA, to achieve control of a module / device having a data bus width greater than 4 bits, specifically an integer multiple of 4 bits. At the same time, frequency multiplication can be performed based on a clock module to achieve control of a module / device having a high-speed clock signal (e.g., an integer multiple of 33MHz) using a low-speed LPC bus, thereby increasing the speed of data processing. At the same time, a password control module can be used to improve security during data communication. In addition, the use of this solution does not affect the function of the existing system, that is, when the multiple is 1, the data width relative to the LPC bus remains unchanged, maintaining the function of the existing system, and is flexible to deploy and easy to implement.

[0118] Specifically, the bus extension device 100 provided in the embodiment of the present application can realize the expansion of the LPC bus based on FPGA, and can be applied to the field of electronic information and data security. Specifically, by setting the bus extension module including the control module based on FPGA, the processing of the LPC bus data signal and the control signal can be realized, so that the device with the LPC interface can control the module / device / data bus with a width of 4nbit (n=1, 2, ..., N), that is, a multiple of 4bit, such as 16bit, 32bit, 64bit, etc., thereby realizing the expansion of the data bus and improving the application flexibility. On this basis, the clock module is used to multiply the clock signal of the LPC bus, and the algorithm state machine of the password control module is used to control the target password module, which can improve the data transmission speed and security. Therefore, the embodiment of the present application can use the limited data width and clock signal of the LPC bus to realize the control of the module / device with a high-speed clock signal and a data bus with a multiple of 4bit, which has scalability and security, does not affect the function of the existing system, and is flexible to deploy and easy to implement. In addition, by controlling the target cryptographic module, the overall security of the system can be improved and the requirements for data security processing in the information security field can be met.

[0119] In some implementations, Fig.16 The application architecture of a bus extension device according to an embodiment of the present application is shown in FIG. Figure 2 , taking the SM4 cryptographic algorithm module as an example, an application method of the bus extension device is shown. The target cryptographic module based on the bus extension device to control other data widths is similar to it, and will not be repeated here. Among them, the SM4 cryptographic algorithm is a national secret symmetric cryptographic algorithm module, whose key width is 128 bits and data width is 128 bits; the SM4 cryptographic algorithm uses 128 bits as a data group, and processes one data group at a time until all data groups are processed to generate encrypted ciphertext or decrypted plaintext.

[0120] The signals and their corresponding functions of the SM4 cryptographic algorithm module shown in the figure are explained. Among them, clk represents the clock signal, and the specific value can be input from an external clock source. The higher the frequency, the faster the operation speed of the SM4 cryptographic algorithm module. In this embodiment, the clock signal can use a clock frequency of 132MHz; reset represents the reset signal; Data_in[127..0] represents the data input signal, and the data width is 128bit; Key[127..0] represents the key signal, and the data width is 128bit;

[0121] Len[127..0] represents the length signal, indicating the number of data packets; op[2..0] represents the command control signal; done represents the output signal after the data operation is completed; Data_out[127..0] represents the data output signal, and the data width is 128 bits.

[0122] like Fig.16 As shown, the bus extension device 100 can be connected to the host computer software 200 via the LPC bus, and connected to the SM4 cryptographic algorithm module 3 via another bus.

[0123] Among them, the host computer software 200 is the upper-level application software operated by the user end, which may include a driver, an application software interface, etc. The user sets the key, register, data to be calculated, etc. through the host computer software, and sends them to the bus extension module 110 through the LPC bus; and receives the data calculated by the SM4 cryptographic algorithm module 3 returned by the bus extension module 110 through the LPC bus.

[0124] The bus extension module 110 can adopt any of the bus extension modules provided in the above-mentioned embodiments. Exemplarily, in the bus extension module 110, by setting the phase-locked loop PLL multiplication coefficient of the clock module 114 to 4, the control module 111 multiplies the clock signal LCLK input by the LPC bus by 4, and outputs the target clock signal CLK=33×4=132 (MHz) as the clock signal of the SM4 cryptographic algorithm module. Since the data width of the SM4 cryptographic algorithm module is 128 bits, the count value n of the counting module 112 is 128 bits / 4 bits=32; the data signal output by the bus extension module is DATA[127..0].

[0125] The password control module 120 may adopt any of the password control modules provided in the above embodiments. Exemplarily, in the password control module 120, the capacity of the storage unit of the second data buffer area 122 is 128 bits; accordingly, the width of the interactive ports, including the key output terminal KEY, the length output terminal LEN, the data output terminal DATA_OUT, and the data input terminal DATA_IN, is also 128 bits.

[0126] In some implementations, the bus extension device 100, such as an FPGA, may also be provided with a power module and a JTAG / AS interface. The power module can provide operating voltages for various modules of the FPGA, such as 1.5V, 3.3V, etc., which are not limited here. The JTAG / AS interface is a debugging / downloading interface of the FPGA, which is used for debugging the FPGA and downloading programs.

[0127] In an embodiment of the present application, the expansion of the LPC bus and the multiplication of the clock frequency are implemented based on FPGA, so that it can control the SM4 cryptographic algorithm module with a data bus width of 32 times that of 4 bits; in addition, the SM4 cryptographic algorithm module is controlled by an algorithm state machine in the FPGA to improve the speed and security of data processing.

[0128] Based on the same inventive concept, an embodiment of the present application also provides a data processing method, which is executed based on any bus expansion device provided in the embodiment of the present application and has corresponding beneficial effects. The same or similar points can be understood by referring to the above and will not be repeated here.

[0129] For example, Fig.17 A data processing method according to an embodiment of the present application is shown in FIG. Figure 1 .like Fig.17 As shown, the data processing method may include:

[0130] S510: Acquire a data signal with a first width transmitted by a target bus.

[0131] Exemplarily, the bus extension device may acquire a data signal having a first width transmitted by the target bus.

[0132] S520 , generating a first target data signal based on a data signal having a first width, wherein the data width of the first target data signal is a first target width, and the first target width is equal to or greater than the first width.

[0133] Exemplarily, the bus extension device may perform data expansion on a data signal having a first width to generate a first target data signal having a first target width, wherein the first target width may be equal to the first width so as not to affect the control of a module / device having a data signal having the first width; or the first target width may be greater than the first width so as to achieve control of a module / device having a data signal greater than the first width.

[0134] In the data processing method provided in the embodiment of the present application, by expanding the width of the data signal transmitted by the target bus, the module / device with a data width equal to or greater than the first width can be controlled, thereby improving the application flexibility of the target bus.

[0135] For example, Fig.18 A data processing method according to an embodiment of the present application is shown in FIG. Figure 2 .like Fig.18 As shown, the data processing method may include:

[0136] S610: Acquire a second target data signal.

[0137] Exemplarily, the control module in the bus extension device may obtain a second target data signal having a second target width.

[0138] S620 . Generate a data signal having a first width based on a second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is greater than or equal to the first width.

[0139] Exemplarily, the control module in the bus extension device may split the second target data signal having the second target width according to the format of the first width, and further store it in the first storage unit in the first data buffer area for transmission based on the target bus having the first width.

[0140] In the data processing method provided in the embodiment of the present application, by performing data width conversion on the second target data signal, a data signal with a first width that can be transmitted by the target bus is generated, and control of modules / devices with other data widths can be achieved based on the target bus, thereby improving the application flexibility of the target bus.

[0141] In some implementations, the bus extension module may include a control module, a counting module, and a first data buffer area.

[0142] Based on this, generating the first target data signal based on the data signal having the first width may specifically include:

[0143] The counting module counts the data cycles of the target bus and transmits the count value to the control module;

[0144] The first data buffer area stores a data signal of at least one data cycle transmitted by the target bus;

[0145] The control module generates a first target data signal based on at least one data cycle of data signals stored in the first data buffer area, and outputs a cycle valid signal of the first target data signal, based on the count value reaching the target count value.

[0146] In the data processing method provided in the embodiment of the present application, a bus extension module is set up to include a control module, a counting module and a first data buffer area. The counting module can count the data cycle of the target bus and transmit the count value to the control module; the first data buffer area can store the data signal of at least one data cycle transmitted by the target bus; the control module can generate a first target data signal based on the data signal of at least one data cycle stored in the first data buffer area based on the count value reaching the target count value, and output a period valid signal of the first target data signal, thereby realizing data width expansion.

[0147] In some implementations, the bus expansion module also includes a clock module.

[0148] Based on this, the data processing method may further include: the clock module, under the control of the control module, multiplies the frequency of the clock signal transmitted by the target bus to generate a target clock signal.

[0149] In the data processing method provided in the embodiment of the present application, the bus extension module is configured to also include a clock module. The clock module can multiply the frequency of the clock signal transmitted by the target bus under the control of the control module, thereby achieving data width expansion while being able to use the low-speed target bus to control the module / device of the high-speed clock signal.

[0150] In some implementations, the bus extension device further includes a password control module.

[0151] Based on this, the data processing method may further include: the password control module generates a password control signal based on the first target data signal, and the password control signal is configured to control the target password module.

[0152] In the data processing method provided in the embodiment of the present application, the width of the data signal transmitted by the target bus can be expanded based on the bus expansion module, thereby improving the application flexibility of the target bus; and the target password module can be controlled based on the password control module to improve the security of the data.

[0153] In some implementations, the cryptographic control module includes an algorithm state machine and a second data buffer.

[0154] Based on this, generating a password control signal based on the first target data signal may specifically include:

[0155] The algorithm state machine transmits the first target data signal to the second data buffer area based on the periodic valid signal of the first target data signal;

[0156] The second data buffer area stores at least one first target data signal in the second data buffer area based on the control of the algorithm state machine, and interacts with the target password module.

[0157] In the data processing method provided in the embodiment of the present application, by setting up a password control module including an algorithm state machine connected to a bus expansion module and a second data cache area, the first target data signal formed by splicing and expanding the data stored in the first data cache area can be transmitted to the second data cache area based on the effective period signal of the first target data signal, and further transmitted to the target password module, thereby realizing control of the target password module.

[0158] In some implementations, interacting with a target cryptographic module may specifically include:

[0159] The algorithm state machine sends the key data, length data and cipher data of different data groups in the second data buffer area to the target cipher module;

[0160] The algorithm state machine completes the processing of the password data based on the target password module, reads the data processed by the target password module, and stores it in the second storage unit in the second data buffer area.

[0161] In this way, data is transmitted to the target cryptographic module and data is read from the target cryptographic module, thereby realizing the interaction between the algorithm state machine and the target cryptographic module, and further realizing the control of the target cryptographic module.

[0162] In some implementations, generating a data signal having a first width based on the second target data signal may specifically include:

[0163] The control module reads the second target data signal in the target second storage unit in the second data buffer area, and stores the second target data signal in the first storage unit in the first data buffer area according to the format of the first width; the data in the first data buffer area is read by the host computer connected to the target bus.

[0164] In this way, data width conversion is achieved based on the control module, the second data buffer area and the first data buffer area, which facilitates the conversion of the second target data signal of the second target width into a data signal with the first width, facilitates the transmission of data signals with a larger data width based on the target bus, and improves the application flexibility of the target bus.

[0165] In some implementations, Fig.19 A data processing method according to an embodiment of the present application is shown in FIG. Figure 3 , which shows the overall process of data processing. Fig.19 As shown, the data processing method may include:

[0166] S710, the user sets the key, packet length, data to be operated, and the value of the function register OP[2] bit through the host computer software. OP[2]='1' indicates data encryption operation, and '0' indicates decryption operation.

[0167] S720: Data is transmitted to the first data buffer area through the target bus.

[0168] S730: After the data is converted by the bus expansion module, it is stored in the second data buffer area in a format of the first target width.

[0169] S740: The algorithm state machine sends the data in the second data buffer area to the target cryptographic module.

[0170] S750. The target cryptographic module obtains the key, the block length, and the data to be operated; and performs encryption or decryption operation on the data according to the value of OP[2].

[0171] S760: The algorithm state machine is in a waiting state.

[0172] During this step, wait for all data groups to be processed. It can be determined whether all data groups are processed, for example, whether DONE = '1'; when the determination result is no, it indicates that the processing is not completed, and return to S750; when the determination result is yes, it indicates that the processing is completed, and the subsequent S770 is executed.

[0173] S770, when DONE = '1', the algorithm state machine reads the ciphertext data or plaintext data after the operation is completed, and stores it in the second data buffer area. After all the data after the operation is read, the signal READY = '1'.

[0174] During this step, it is determined whether the reading is completed, for example, whether READY='1'; when the determination result is no, it indicates that the reading is not completed, and the read action is returned to be executed; when the determination result is yes, it indicates that the reading is completed, and the subsequent S780 is executed.

[0175] S780: The bus extension module reads the data in the second data buffer area, and stores the data in the first data buffer area in sequence according to a format of the first width.

[0176] S790: The host computer reads data in the first data buffer area through the target bus.

[0177] At this point, a data processing process is completed.

[0178] In other implementations, if it is necessary to change the key, change the data and packet length, etc., just repeat the above steps.

[0179] The data processing method provided in the embodiment of the present application can realize the control of the target cryptographic module with the first target width based on the target bus through data width expansion, thereby improving the application flexibility of the target bus and ensuring the security of data processing.

[0180] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0181] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bus expansion device, characterized in that: Configured on the server; The bus expansion device comprises: A bus extension module, configured to connect to a target bus; the bus extension module is configured to exchange a data signal having a first width with the target bus, and generate a first target data signal based on the data signal having the first width, or generate the data signal having the first width based on the acquired second target data signal; Among them, the data width of the first target data signal is a first target width, and the data width of the second target data signal is a second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width.

2. The bus expansion device according to claim 1, characterized in that: The bus extension module includes a control module, a counting module and a first data buffer area, wherein the counting module and the first data buffer area are respectively connected to the control module; the counting module is configured to count the data cycles of the target bus and transmit the count value to the control module; the first data buffer area is configured to store the data signal of at least one data cycle transmitted by the target bus; The control module is configured to generate the first target data signal based on the data signal of the at least one data cycle stored in the first data buffer area based on the count value reaching the target count value, and output a cycle valid signal of the first target data signal.

3. The bus expansion device according to claim 2, characterized in that: The counting module includes an accumulator; The accumulator counts the data cycle based on a cycle start signal of the target bus transfer.

4. The bus expansion device according to claim 2, characterized in that: The first data cache area includes at least one first storage unit; The capacity of the first storage unit matches the first width, and is configured to store the data signal of at least one of the data cycles.

5. The bus expansion device according to claim 2, characterized in that: The control module includes an RS trigger and a first inverter; the data input end of the RS trigger is connected to a first level, the carry end of the RS trigger is connected to a second level, the set end and the clear end of the RS trigger are connected to the counting module, and the output end of the RS trigger is connected to the output end of the control module through the first inverter; The RS trigger outputs a periodic valid signal of the first target data signal based on the count value reaching the target count value; The control module further includes a second inverter and a first D flip-flop; a clock end of the first D flip-flop is connected to a cycle start signal of the target bus through the second inverter, an input end of the first D flip-flop is connected to a data signal of the target bus, and an output end of the first D flip-flop is connected to the first data buffer area; The first D flip-flop stores the data signal of the target bus in the first data buffer based on the cycle start signal being a valid signal, and transfers the data in the first storage unit corresponding to the first data buffer to the position corresponding to the first target data signal based on the difference in the count value.

6. The bus expansion device according to claim 2, characterized in that: The bus extension module also includes a clock module, and the clock module is connected to the control module; The clock module is configured to multiply the frequency of the clock signal transmitted by the target bus under the control of the control module to generate a target clock signal.

7. The bus expansion device according to claim 6, characterized in that: The clock module includes a phase-locked loop; The input end of the phase-locked loop is connected to the clock signal of the target bus, and the phase-locked loop is configured to multiply the frequency of the clock signal transmitted by the target bus to generate a target clock signal.

8. The bus expansion device according to claim 6, characterized in that: The control module also includes a second D flip-flop; the clock end of the second D flip-flop is connected to the clock signal of the target bus, and the data input end of the second D flip-flop is connected to the reset signal of the target bus; the second D flip-flop is configured to control the effective time of the reset based on the reset signal of the target bus and then output a new reset signal corresponding to the first target data signal.

9. The bus extension device according to any one of claims 1 to 8, characterized in that: It also includes a password control module, which is connected to the bus expansion module and is also configured to connect to a target password module; the password control module is configured to generate a password control signal based on the first target data signal, and the password control signal is configured to control the target password module.

10. The bus expansion device according to claim 9, characterized in that: The password control module includes an algorithm state machine and a second data buffer area, and the second data buffer area is connected to the algorithm state machine; The algorithm state machine is configured to transmit the first target data signal to the second data buffer area based on a periodic valid signal of the first target data signal; The second data buffer is configured to store at least one of the first target data signals in the second data buffer based on the control of the algorithm state machine, and to interact with the target cryptographic module.

11. The bus expansion device according to claim 9, characterized in that: The password control module also includes a function register, an input end of the function register is connected to the algorithm state machine, and an output end of the function register is connected to the target password module; The function register is configured to output target operation instructions to the target cryptographic module based on the control of the algorithm state machine, and the target operation instructions include at least one of an operation instruction to write a key to the target cryptographic module, an operation instruction to write a data packet length to the target cryptographic module, and an operation instruction for data encryption and decryption.

12. The bus extension device according to claim 11, characterized in that: The algorithm state machine includes the following states: idle, start, write key, write length, write data, wait, read data, end; The transition between the different states includes the following steps: After the system is reset, it enters an idle state. When the reset is completed and the target bus transmits a cycle start signal, the algorithm state machine enters a start state. In the start state, the algorithm state machine sets the function register to write a key to the target cryptographic module, and then enters a key writing state; In the write key state, the algorithm state machine sends the key data in the second data buffer area to the target cryptographic module; and sets the function register to write the length to the target cryptographic module, and then enters the write length state; in the write length state, the algorithm state machine sends the length data in the second data buffer area to the target cryptographic module, and then enters the write data state; In the data writing state, the algorithm state machine sends the password data stored in at least one of the second storage units in the second data buffer area to the target password module according to the password length value in the length data, and then enters the waiting state; In the waiting state, the algorithm state machine waits for the target cryptographic module to complete operation, and enters the data reading state based on the completion of the operation; In the data reading state, the algorithm state machine reads the data ciphertext or data plaintext after the target cryptographic module completes the operation, and stores it in at least one of the second storage units in the second data buffer area; then enters the end state; In the end state, the algorithm state machine clears the flag bit of the function register and then returns to the idle state.

13. The bus expansion device according to claim 9, characterized in that: The second data buffer area includes a key data storage unit, a length data storage unit and at least one second storage unit; The key data storage unit is configured to store key data, the length data storage unit is configured to store length data, and the second storage unit is configured to store cipher data of different data groups, a group of the cipher data includes one first target data signal.

14. The bus extension device according to claim 13, characterized in that: The algorithm state machine and the second data buffer area are also respectively connected to the control module in the bus extension module; The algorithm state machine is further configured to send a preparation completion signal to the control module based on receiving data packets completed by operation of the target cryptographic module and transmitting the data packets to different second storage units in the second data buffer area; The control module is also configured to read the second target data signal in the target second storage unit in the second data buffer area based on the preparation completion signal, and store the second target data signal in the first storage unit in the first data buffer area in the bus expansion module in the format of the first width.

15. The bus expansion device according to claim 1, characterized in that: The target bus includes an LPC bus; the bus extension device is implemented based on a programmable logic device, and the first target width and the second target width are both integer multiples of the first width.

16. A data processing method, characterized in that: Based on the bus extension device according to any one of claims 1 to 15, the data processing method comprises: Acquire a data signal with a first width transmitted by the target bus; generating a first target data signal based on the data signal having the first width, wherein the data width of the first target data signal is a first target width, and the first target width is equal to or greater than the first width; or, acquiring a second target data signal; A data signal having a first width is generated based on the second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is greater than or equal to the first width.

17. The data processing method according to claim 16, characterized in that: The bus extension module includes a control module, a counting module and a first data buffer area; the generating a first target data signal based on the data signal with the first width includes: The counting module counts the data cycles of the target bus and transmits the count value to the control module; The first data buffer area stores the data signal of at least one data cycle transmitted by the target bus; The control module generates the first target data signal based on the data signal of the at least one data cycle stored in the first data buffer area, and outputs a cycle valid signal of the first target data signal based on the count value reaching the target count value.

18. The data processing method according to claim 17, characterized in that: The bus expansion module also includes a clock module; the data processing method also includes: Under the control of the control module, the clock module multiplies the frequency of the clock signal transmitted by the target bus to generate a target clock signal.

19. The data processing method according to claim 17, characterized in that: The bus expansion device also includes a password control module; the data processing method also includes: The cryptographic control module generates a cryptographic control signal based on the first target data signal, wherein the cryptographic control signal is configured to control the target cryptographic module.

20. The data processing method according to claim 19, characterized in that: The password control module includes an algorithm state machine and a second data buffer area; the generating of the password control signal based on the first target data signal includes: The algorithm state machine transmits the first target data signal to the second data buffer area based on the periodic valid signal of the first target data signal; The second data buffer stores at least one of the first target data signals into the second data buffer based on the control of the algorithm state machine, and interacts with the target cryptographic module; Wherein, the interacting with the target password module includes: The algorithm state machine sends the key data, length data and cryptographic data of different data groups in the second data buffer area to the target cryptographic module; The algorithm state machine completes the processing of the password data based on the target password module, reads the data processed by the target password module, and stores it in the second storage unit in the second data buffer area; The step of generating a data signal having a first width based on the second target data signal comprises: The control module reads the second target data signal in the target second storage unit in the second data cache area, and stores the second target data signal in the first storage unit in the first data cache area according to the format of the first width; the data in the first data cache area is read by the host computer connected to the target bus.

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