Display panel, preparation method thereof and display device

Abstract

The application discloses a display panel and a preparation method thereof, and a display device, and relates to the technical field of display. The display panel comprises a substrate, a pixel definition layer, a first pixel isolation column, a plurality of light emitting units, an electrode patterning layer and a third electrode pattern. The third electrode pattern and a first edge part of the second electrode pattern exposed by the electrode patterning layer are overlapped and connected with the first pixel isolation column, so that the first pixel isolation column serves as a cathode auxiliary electrode of the light emitting unit. Meanwhile, since the second electrode pattern of the light emitting unit is connected with the first pixel isolation column through the third electrode pattern, the second electrode pattern of the light emitting unit can receive a cathode signal through the first pixel isolation column, and the reliability of cathode signal receiving is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] With the rapid development of the information age, OLED (Organic Light-Emitting Diode) display technology has gradually become an indispensable part of display technology due to its advantages such as self-illumination, wide viewing angle, thinness, low energy consumption, and flexibility.

[0003] In related technologies, to reduce the production cost of display panels, OLED display panels are fabricated using photolithography. When fabricating OLED display panels using photolithography, the light-emitting patterns of the light-emitting units do not need to be formed by fine metal mask (FMM) evaporation. Instead, they are obtained by coating the entire surface with a light-emitting thin film and then performing photolithography on the film. Furthermore, the cathode patterns of each light-emitting unit in the display panel are independently set, thereby achieving independent encapsulation of each light-emitting unit. Summary of the Invention

[0004] This application provides a display panel, a method for manufacturing the same, and a display device. The technical solution is as follows:

[0005] On one hand, a display panel is provided, the display panel comprising:

[0006] A substrate, the substrate including a display area;

[0007] A pixel defining layer, the pixel defining layer being located on one side of the substrate, and the pixel defining layer including a plurality of pixel openings located in the display area;

[0008] The first pixel isolation pillar is located on the side of the pixel defining layer away from the substrate.

[0009] The plurality of light-emitting units corresponding to the plurality of pixel openings, each light-emitting unit including a first electrode pattern, a light-emitting pattern, and a second electrode pattern, wherein the first electrode pattern is located on the side of the pixel defining layer close to the substrate, the pixel opening exposes at least a portion of the first electrode pattern corresponding to the light-emitting unit, the light-emitting pattern is located within the pixel opening and connected to the first electrode pattern, and the second electrode pattern is located on the side of the light-emitting pattern away from the substrate and connected to the light-emitting pattern;

[0010] An electrode patterning layer includes a first patterned portion located within the pixel opening. The orthographic projection of the first patterned portion on the substrate is located within the orthographic projection of the second electrode pattern on the substrate. The second electrode pattern includes a first edge portion, which is an edge portion of the second electrode pattern that does not overlap with the first patterned portion.

[0011] In addition, a third electrode pattern, wherein the third electrode pattern is electrically connected to the first edge portion of the second electrode pattern, and the third electrode pattern is electrically connected to the first pixel isolation pillar.

[0012] Optionally, the third electrode pattern and the electrode patterning layer do not overlap.

[0013] Optionally, the orthographic projection of the first pixel isolation pillar on the substrate and the orthographic projection of the pixel opening on the substrate do not overlap. The first pixel isolation pillar includes: a first isolation portion and a second isolation portion stacked along a direction away from the pixel defining layer. The material of the first isolation portion includes a conductive material. The orthographic projection of the first isolation portion on the substrate is located inside the orthographic projection of the second isolation portion on the substrate.

[0014] The third electrode pattern is electrically connected to the first isolation section.

[0015] Optionally, the second isolation portion includes a portion located on the side of the first isolation portion away from the substrate, and a protrusion extending beyond the edge of the first isolation portion in a plane parallel to the substrate.

[0016] The orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the protrusion on the substrate overlap, and the third electrode pattern and the first isolation portion are electrically connected in contact.

[0017] Optionally, the orthographic projection of the second electrode pattern on the substrate covers the orthographic projection of the light-emitting pattern on the substrate; the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the light-emitting pattern on the substrate do not overlap.

[0018] The distance between the orthographic projection of the boundary of the second electrode pattern on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate is greater than the distance between the orthographic projection of the boundary of the first patterned portion on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate.

[0019] The distance between the orthographic projection of the boundary of the second electrode pattern on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate is greater than the distance between the orthographic projection of the boundary of the third electrode pattern on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate.

[0020] Optionally, the orthographic projection of the first pixel isolation pillar on the substrate surrounds the orthographic projection of the light-emitting unit on the substrate;

[0021] The third electrode pattern and at least a portion of the first isolation portion surrounding the first pixel isolation pillar of the light-emitting unit are electrically connected.

[0022] Optionally, the shape of the first pixel isolation pillar surrounding each of the light-emitting units on the substrate is a closed pattern.

[0023] Optionally, at least a portion of the first pixel isolation pillars surrounding two adjacent light-emitting units are shared.

[0024] Optionally, the plurality of light-emitting units include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit emit different colors; any one of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit is arranged adjacent to at least one of the other two light-emitting units.

[0025] The orthographic projection of the first pixel isolation pillar on the substrate surrounds the orthographic projection of the first light-emitting unit on the substrate, surrounds the orthographic projection of the second light-emitting unit on the substrate, and surrounds the orthographic projection of the third light-emitting unit on the substrate.

[0026] Optionally, any one of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit is arranged adjacent to the other two light-emitting units;

[0027] The portion of the first pixel isolation pillar surrounding the first light-emitting unit that is close to the second light-emitting unit, and the portion of the first pixel isolation pillar surrounding the second light-emitting unit that is close to the first light-emitting unit, are shared.

[0028] The portion of the first pixel isolation pillar surrounding the first light-emitting unit that is close to the third light-emitting unit, and the portion of the first pixel isolation pillar surrounding the third light-emitting unit that is close to the first light-emitting unit, are shared.

[0029] The portion of the first pixel isolation pillar surrounding the second light-emitting unit that is close to the third light-emitting unit is shared with the portion of the first pixel isolation pillar surrounding the third light-emitting unit that is close to the second light-emitting unit; or, there is a gap between the first pixel isolation pillar surrounding the second light-emitting unit and the first pixel isolation pillar surrounding the third light-emitting unit, the gap being located in the arrangement direction of the second light-emitting unit and the third light-emitting unit.

[0030] Optionally, the orthographic projections of the first pixel isolation pillars surrounding any two adjacent light-emitting units on the substrate are spaced apart.

[0031] Optionally, the second isolation portion of the first pixel isolation pillar, in a plane parallel to the substrate, protruding beyond the edge of the first isolation portion, includes: a first portion on the side closer to the light-emitting unit, and a second portion on the side farther from the light-emitting unit;

[0032] The width of the orthographic projection of the first part on the substrate is greater than the width of the orthographic projection of the second part on the substrate.

[0033] Optionally, the distance between the orthographic projections of the first isolation portion of the first pixel isolation pillar surrounding two adjacent light-emitting units on the substrate away from the substrate is greater than the width of the orthographic projection of the first portion on the substrate and greater than the width of the orthographic projection of the second portion on the substrate.

[0034] Optionally, the pixel opening includes a plurality of pixel sub-openings, the plurality of pixel sub-openings exposing at least a portion of the first electrode pattern of the same light-emitting unit; the display panel further includes: a second pixel isolation pillar, the orthographic projection of the second pixel isolation pillar on the substrate and the orthographic projection of the pixel sub-opening on the substrate do not overlap, and the orthographic projection of the second pixel isolation pillar on the substrate is located between the orthographic projections of adjacent pixel sub-openings on the substrate.

[0035] The second pixel isolation pillar includes a third isolation portion and a fourth isolation portion stacked in a direction away from the substrate, wherein the orthographic projection of the third isolation portion on the substrate is located inside the orthographic projection of the fourth isolation portion on the substrate;

[0036] The light-emitting unit includes a plurality of light-emitting sub-patterns spaced apart and a plurality of first cathode sub-patterns spaced apart. The light-emitting sub-patterns and the first cathode sub-patterns are all located within the corresponding pixel sub-openings. The third electrode pattern is also electrically connected to the third isolation part.

[0037] Optionally, the first electrode pattern of the light-emitting unit is an integral structure, with each pixel sub-opening exposing a portion of the first electrode pattern; or, the first electrode pattern of the light-emitting unit includes a plurality of anode sub-patterns spaced apart and corresponding to the plurality of pixel sub-openings, with each pixel sub-opening exposing at least a portion of the corresponding first electrode pattern.

[0038] Optionally, adjacent pixel sub-openings have a plurality of second pixel isolation pillars between their orthogonal projections on the substrate.

[0039] Optionally, the display panel further includes: a plurality of light-emitting circuits corresponding to the plurality of light-emitting units, wherein the light-emitting circuits are connected to the corresponding light-emitting units to form light-emitting pixels; the display panel further includes: a plurality of signal lines, wherein the signal lines are connected to the light-emitting circuits and are used to provide driving signals to the light-emitting circuits;

[0040] Wherein, at least a portion of the orthographic projections of at least a portion of the plurality of signal lines on the substrate are located between the orthographic projections of the adjacent pixel sub-openings on the substrate.

[0041] Optionally, the substrate further includes a peripheral region surrounding the display area; the display panel further includes: power traces, signal switching patterns, a fourth electrode pattern and a fifth electrode pattern located at least partially in the peripheral region, wherein the signal switching pattern and the first electrode pattern are located on the same layer, the fourth electrode pattern and the second electrode pattern are located on the same layer, and the fifth electrode pattern and the third electrode pattern are located on the same layer.

[0042] The signal conversion pattern is connected to the power supply trace, the fourth electrode pattern is connected to the signal conversion pattern, the fourth electrode pattern is also electrically connected to the first isolation section, and the fifth electrode pattern is electrically connected to the fourth electrode pattern.

[0043] Optionally, the electrode patterning layer further includes a second patterned portion located on the side of the fourth electrode pattern away from the substrate, the fourth electrode pattern including a second edge portion, the second edge portion being an edge portion of the fourth electrode pattern that does not overlap with the second patterned portion;

[0044] The fifth electrode pattern is electrically connected to the second edge portion.

[0045] Optionally, the angle between the side of the second patterned portion away from the display area and the surface of the second patterned portion near the substrate is an acute angle.

[0046] On the other hand, a method for manufacturing a display panel is provided, the method comprising:

[0047] Obtain a substrate, the substrate including a display area;

[0048] A first electrode pattern of multiple light-emitting units is formed on one side of the substrate.

[0049] A pixel defining layer is formed on the side of the first electrode pattern of the plurality of light-emitting units away from the substrate. The pixel defining layer includes a plurality of pixel openings located in the display area. The plurality of pixel openings correspond to the plurality of light-emitting units, and the pixel openings expose at least a portion of the first electrode pattern of the corresponding light-emitting unit.

[0050] A first pixel isolation pillar is formed on the side of the pixel defining layer away from the substrate, and the first pixel isolation pillar is located on the side of the pixel defining layer away from the substrate.

[0051] A light-emitting pattern of multiple light-emitting units is formed within the plurality of pixel openings, and the light-emitting pattern is connected to the first electrode pattern;

[0052] A second electrode pattern for the plurality of light-emitting units is formed on the side of the light-emitting pattern away from the substrate, and the second electrode pattern is connected to the light-emitting pattern;

[0053] An electrode patterning layer is formed on the side of the second electrode pattern away from the substrate. The electrode patterning layer includes a first patterned portion located within the pixel opening. The orthographic projection of the first patterned portion on the substrate is located within the orthographic projection of the second electrode pattern on the substrate. The second electrode pattern includes a first edge portion, which is an edge portion of the second electrode pattern that does not overlap with the first patterned portion.

[0054] A third electrode pattern is formed, wherein the third electrode pattern and the first edge portion of the second electrode pattern are electrically connected, and the third electrode pattern and the first isolation portion are electrically connected.

[0055] In another aspect, a display device is provided, the display device comprising: a power supply component and a display panel as described above;

[0056] The power supply component is connected to the display panel and is used to supply power to the display panel.

[0057] The beneficial effects of the technical solution provided in this application include at least the following:

[0058] This application provides a display panel, a method for fabricating the same, and a display device. The display panel includes a substrate, a pixel defining layer, a first pixel isolation pillar, a plurality of light-emitting units, an electrode patterning layer, and a third electrode pattern. The third electrode pattern overlaps with the first edge of the exposed second electrode pattern of the electrode patterning layer and is connected to the first pixel isolation pillar, thereby enabling the first pixel isolation pillar to serve as the cathode auxiliary electrode of the light-emitting unit. Simultaneously, since the second electrode pattern of the light-emitting unit is connected to the first pixel isolation pillar through the third electrode pattern, the second electrode pattern of the light-emitting unit can receive cathode signals through the first pixel isolation pillar, improving the reliability of cathode signal reception. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0061] Figure 2 This is a top view of a substrate provided in an embodiment of this application;

[0062] Figure 3 This is a partial top view of a display panel provided in an embodiment of this application;

[0063] Figure 4 This is a flowchart illustrating the fabrication process of a display panel's light-emitting pattern and encapsulation film layer, as provided in an embodiment of this application.

[0064] Figure 5 This is a partial top view of another display panel provided in an embodiment of this application;

[0065] Figure 6 This is a partial cross-sectional schematic diagram of another display panel provided in an embodiment of this application;

[0066] Figure 7 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application;

[0067] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0068] Figure 9 This is a top view of a light-emitting unit, including a first pixel isolation pillar and a second pixel isolation pillar, provided in an embodiment of this application.

[0069] Figure 10 This is a top view of another light-emitting unit provided in this application embodiment, including the first pixel isolation pillar and the second pixel isolation pillar;

[0070] Figure 11 This is a partial top view of a light-emitting unit and a data signal line provided in an embodiment of this application;

[0071] Figure 12 This is a partial cross-sectional schematic diagram of the peripheral area of ​​a display panel provided in an embodiment of this application;

[0072] Figure 13 This is a top view of a first mask opening, a second mask opening, and a third mask opening provided in an embodiment of this application;

[0073] Figure 14 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0074] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0076] In related technologies, each light-emitting unit in the display panel is independently packaged, resulting in poor reliability of the cathode pattern of each light-emitting unit receiving cathode signals.

[0077] Figure 1 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of this application. (Reference) Figure 1 The display panel 100 includes: a substrate 101, a pixel defining layer 102, a first pixel isolation pillar 103, a plurality of light-emitting units 104, an electrode patterned material (CPM) 105, and a third electrode pattern 106.

[0078] refer to Figure 2 The substrate 101 includes a display area 101a. The substrate 101 can serve to support multiple light-emitting units 104, and the material of the substrate 101 can be plastic or glass, etc.

[0079] A pixel defining layer 102 is located on one side of the substrate 101, and includes a plurality of pixel openings 102a located in the display area 101a. The pixel defining layer 102 is used to define the positions of the plurality of light-emitting units 104 on the substrate 101. The plurality of pixel openings 102a can be evenly distributed in the pixel defining layer 102, and the shape of the pixel openings 102a can be circular, rectangular, hexagonal, rhomboid, etc. This embodiment does not limit the shape of the pixel openings 102a.

[0080] The first pixel isolation pillar 103 is located on the side of the pixel defining layer 102 away from the substrate 101. In order to avoid the first pixel isolation pillar 103 affecting the light-emitting unit 104, the orthographic projection of the first pixel isolation pillar 103 on the substrate 101 and the orthographic projection of the pixel opening 102a on the substrate 101 can be made not to overlap.

[0081] Optional, see reference Figure 1 The first pixel isolation pillar 103 includes a first isolation portion 1031 and a second isolation portion 1032 stacked along a direction away from the pixel defining layer 102. The material of the first isolation portion 1031 includes a conductive material, and the orthographic projection of the first isolation portion 1031 on the substrate 101 is located inside the orthographic projection of the second isolation portion 1032 on the substrate 101. The material of the second isolation portion 1032 may also include a conductive material or may not include a conductive material; this embodiment does not limit this.

[0082] The function of the first pixel isolation pillar 103 is to cause the light-emitting functional layer (for obtaining the light-emitting pattern 1042) and the first cathode layer (for obtaining the second electrode pattern 1043) of the multiple light-emitting units 104 to break at the boundary of the first pixel isolation pillar 103, thereby obtaining multiple independent light-emitting patterns 1042 and multiple independent second electrode patterns 1043.

[0083] refer to Figure 1 Although the light-emitting functional layer and the first cathode layer break at the boundary of the first pixel isolation pillar 103, since both layers are integrally vapor-deposited, the surface of the first pixel isolation pillar 103 away from the substrate 101 can also have the materials of the light-emitting functional layer and the cathode layer. Of course, the materials of the light-emitting functional layer and the cathode layer on the surface of the first pixel isolation pillar 103 away from the substrate 101 can also be removed by photolithography; this application does not limit this. For example... Figure 1 The surface of the first pixel isolation pillar 103 away from the substrate 101 may be provided with only the material of the light-emitting functional layer, without the material of the cathode layer.

[0084] Multiple light-emitting units 104 correspond to multiple pixel openings 102a. Each light-emitting unit 104 includes a first electrode pattern 1041, a light-emitting pattern 1042, and a second electrode pattern 1043. The first electrode pattern 1041 is located on the side of the pixel defining layer 102 closest to the substrate 101. The pixel opening 102a exposes at least a portion of the first electrode pattern 1041 corresponding to the light-emitting unit 104. The light-emitting pattern 1042 is located within the pixel opening 102a and is connected to the first electrode pattern 1041. The second electrode pattern 1043 is located on the side of the light-emitting pattern 1042 away from the substrate 101 and is connected to the light-emitting pattern 1042. The light-emitting patterns 1042 of the multiple light-emitting units 104 are independently arranged, and the second electrode patterns 1043 of the multiple light-emitting units 104 are independently arranged. The material of the second electrode pattern 1043 can be a metal or a metal alloy. For example, the material of the second electrode pattern 1043 includes at least one of magnesium (Mg) and silver (Ag). Taking into account resistance and transmittance in the wavelength range of 300 nm to 1100 nm, the thickness of the second electrode pattern 1043 can be less than or equal to 20 nm. The second electrode pattern 1043 can function as a microcavity for the light-emitting unit 104.

[0085] The electrode patterning layer 105 includes a first patterned portion 1051 located within the pixel opening 102a. The orthographic projection of the first patterned portion 1051 onto the substrate 101 lies within the orthographic projection of the second electrode pattern 1043 onto the substrate 101. The second electrode pattern 1043 includes a first edge portion 10431, which is an edge portion of the second electrode pattern 1043 that does not overlap with the first patterned portion 1051. Further, refer to... Figure 1 The electrode patterning layer 105 also includes a third patterned portion 1053 located on the side of the first pixel isolation pillar 103 away from the substrate 101.

[0086] The third electrode pattern 106 is electrically connected to the first edge portion 10431, and the third electrode pattern 106 is electrically connected to the first pixel isolation pillar 103. For example, the third electrode pattern 106 is electrically connected to the first isolation portion 1031 of the first pixel isolation pillar 103.

[0087] Optionally, the light-emitting unit 104 may have a light-emitting region 104a, which may be an area where the light-emitting pattern 1042, the first electrode pattern 1041, and the second electrode pattern 1043 of the light-emitting unit 104 are all in contact with each other to achieve light emission. The area between adjacent light-emitting units 104 may be a non-light-emitting region 104a. The non-light-emitting region 104a must contain a third electrode pattern 106. Due to the size of the light-emitting unit 104 and the technical difficulty of the photolithography process itself, the third electrode pattern 106 is located on at least one side of the light-emitting region 104a of the light-emitting unit 104, so as to overlap with at least one side of the first pixel isolation pillar 103.

[0088] In this embodiment, the first edge 10431 of the third electrode pattern 106 and the second electrode pattern 1043 overlaps and is connected to the first isolation portion 1031 of the first pixel isolation pillar 103. The first pixel isolation pillar 103 can serve as the cathode auxiliary electrode of the light-emitting unit 104. Furthermore, by providing the third electrode pattern 106, it can be ensured that the first isolation portion 1031 can connect to the second electrode pattern 1043, allowing the first isolation portion 1031 to function as a cathode auxiliary electrode. Simultaneously, since the second electrode pattern 1043 of the light-emitting unit 104 is connected to the first isolation portion 1031 through the third electrode pattern 106, the second electrode pattern 1043 can receive signals through the first isolation portion 1031, improving the reliability of signal reception.

[0089] According to the resistance formula, the resistance R satisfies: R = ρ * L / S. Where ρ is the resistivity, L is the length of the resistor, and S is the area through which the current flows. By setting the third electrode pattern 106, the third electrode pattern 106 can overlap with the second electrode pattern 1043 of the light-emitting unit 104 in the non-light-emitting area 104a, thereby enabling the first isolation portion 1031 of the first pixel isolation pillar 103 to function as a cathode auxiliary electrode, effectively increasing the cathode area. According to the above formula, with a fixed resistivity and resistor length, an increase in area S reduces the resistance R. That is, by designing the third electrode pattern 106 to make the first pixel isolation pillar 103 act as a cathode auxiliary electrode, the cathode resistance can be effectively reduced.

[0090] In this embodiment, the electrode patterning layer 105 can be made of a material capable of patterning the cathode material within a wavelength range of 300 nm to 1100 nm. The reason for designing the electrode patterning layer 105 is that multiple patterned second electrode patterns 1043 need to be obtained based on the mutual repulsion between the cathode material and the electrode patterning layer. If a fine metal mask (FMM) is used to fabricate multiple patterned second electrode patterns 1043, the material of the second electrode patterns 1043 (such as an alloy material like silver) has a relatively high temperature, which can easily cause the FMM to deform, hindering mass production.

[0091] Optionally, the material of the electrode patterning layer 105 may be a high-fluorine compound, which has poor compatibility with the cathode material. The electrode patterning layer 105 exposes the first edge portion 10431 of the second electrode pattern 1043, so that when the second cathode layer is formed after the electrode patterning layer 105, the second cathode layer can be formed above the first edge portion 10431 of the second electrode pattern 1043 (i.e., the third electrode pattern 106 is obtained), thereby allowing the third electrode pattern 106 formed after the electrode patterning layer 105 to overlap with the first edge portion 10431 of the second electrode pattern 1043.

[0092] When fabricating the display panel 100, a first electrode pattern 1041 of multiple light-emitting units 104 needs to be fabricated on a substrate 101. Then, a pixel defining layer 102 is formed on the side of the first electrode pattern 1041 of the multiple light-emitting units 104 away from the substrate 101, and multiple pixel openings 102a of the pixel defining layer 102 expose the first electrode pattern 1041 of the multiple light-emitting units 104. Next, a first pixel isolation pillar 103 is formed on the side of the pixel defining layer 102 away from the substrate 101. Based on the isolation effect of the first pixel isolation pillar 103, the light-emitting pattern 1042 of the multiple light-emitting units 104 and the second electrode pattern 1043 of the multiple light-emitting units 104 are obtained. Then, an electrode patterning layer 105 can be formed by vapor deposition, such that the first patterned portion 1051 of the electrode patterning layer 105 located in the pixel opening 102a exposes the first edge portion 10431 of the second electrode pattern 1043.

[0093] After the electrode patterning layer 105 is formed, the cathode material of the second cathode layer can be deposited on the side of the electrode patterning layer 105 away from the pixel defining layer 102. Since the compatibility between the cathode material and the material of the electrode patterning layer 105 is very poor, it is difficult for the cathode material to adhere to the material of the electrode patterning layer 105. Therefore, the cathode material can be attached to the first edge portion 10431 of the first patterned portion 1051 that exposes the second electrode pattern 1043. Furthermore, the cathode material can be attached to the first isolation portion 1031 of the first pixel isolation pillar 103 by controlling the deposition angle, so that the formed third electrode pattern 106 connects the first isolation portion 1031 and the second electrode pattern 1043.

[0094] This configuration allows the third electrode pattern 106 to connect the first isolation portion 1031 and the second electrode pattern 1043, enabling the first pixel isolation pillar 103 to function as a cathode auxiliary electrode. Simultaneously, a large portion of the second electrode pattern 1043 on the side furthest from the substrate 101 is comprised of an electrode patterning layer 105. Since the transmittance of the electrode patterning layer 105 is higher than that of the cathode material, this structure also avoids placing the third electrode pattern 106 above the second electrode pattern 1043, which would affect the transmittance of the display panel.

[0095] Since it is difficult for cathode material to adhere to the electrode patterning layer 105, the electrode patterning layer 105 may be completely devoid of cathode material or may have only a small amount of cathode material attached. In either case, since the electrode patterning layer 105 has high transmittance and there is very little or no cathode material on the electrode patterning layer 105, this structure avoids affecting the transmittance of the display panel 100 due to the setting of the cathode auxiliary electrode.

[0096] In summary, this application provides a display panel including a substrate, a pixel defining layer, a first pixel isolation pillar, a plurality of light-emitting units, an electrode patterning layer, and a third electrode pattern. The third electrode pattern overlaps with the first edge of the exposed second electrode pattern of the electrode patterning layer and is connected to the first pixel isolation pillar, thereby enabling the first pixel isolation pillar to serve as the cathode auxiliary electrode of the light-emitting unit. Furthermore, since the second electrode pattern of the light-emitting unit is connected to the first pixel isolation pillar through the third electrode pattern, the second electrode pattern of the light-emitting unit can receive cathode signals through the first pixel isolation pillar, improving the reliability of cathode signal reception.

[0097] In this embodiment, because the material of the electrode patterning layer 105 and the cathode material of the third electrode pattern 106 have poor compatibility, it is difficult for the cathode material of the third electrode pattern 106 to adhere to the electrode patterning layer 105 during the fabrication of the third electrode pattern 106. That is, the third electrode pattern 106 and the electrode patterning layer 105 do not overlap.

[0098] The fact that the third electrode pattern 106 and the electrode patterning layer 105 do not overlap can mean that the third electrode pattern 106 and the electrode patterning layer 105 will not overlap due to direct contact, but their orthogonal projections may overlap when they are not in contact.

[0099] refer to Figure 1 The second isolation portion 1032 includes a portion 10321 located on one side of the first isolation portion 1031, and a protrusion 10322 extending beyond the edge of the first isolation portion 1031 in a plane parallel to the substrate 101. That is, the first pixel isolation pillar 103 can be an incised structure. This facilitates the breaking of the light-emitting functional layer and the first cathode layer at the edge of the second isolation portion 1032 in the first pixel isolation pillar 103, ensuring the formation of multiple independent light-emitting patterns 1042 and multiple independent second electrode patterns 1043.

[0100] Optionally, in order to make the third electrode pattern 106 and the first isolation portion 1031 of the first pixel isolation pillar 103 make contact and electrical connection, the orthographic projection of the third electrode pattern 106 on the substrate 101 and the orthographic projection of the protrusion 10322 of the second isolation portion 1032 that extends beyond the first isolation portion 1031 on the substrate 101 can overlap. For example Figure 1 In the middle, the third electrode pattern 106 and the side wall of the first isolation part 1031 are electrically connected.

[0101] refer to Figure 1 The sidewall of the first isolation portion 1031 can be an arc-shaped sidewall, and the third electrode pattern 106 can contact the arc-shaped sidewall of the first isolation portion 1031. Of course, the sidewall of the first isolation portion 1031 can also be other shapes, and this embodiment does not limit this.

[0102] Optional, see reference Figure 1 The dimension a1 of the first isolation portion 1031 on the side closer to the substrate 101 is larger than the dimension a2 of the first isolation portion 1031 on the side farther from the substrate 101. Among the two sides of the first isolation portion 1031 that are closer to and farther from the substrate 101, at least the orthographic projection of the side farther from the substrate 101 on the substrate 101 is located inside the orthographic projection of the second isolation portion 1032 on the substrate 101.

[0103] In this embodiment, since the second electrode pattern 1043 functions as a microcavity for the light-emitting unit 104, the orthogonal projection of the second electrode pattern 1043 onto the substrate 101 overlaps with the orthogonal projection of the light-emitting pattern 1042 onto the substrate 101. Furthermore, since the third electrode pattern 106 is used to electrically connect the second electrode pattern 1043 and the first isolation portion 1031, to avoid the third electrode pattern 106 affecting the light-emitting region 104a, the orthogonal projections of the third electrode pattern 106 and the light-emitting pattern 1042 onto the substrate 101 can be made to not overlap.

[0104] Furthermore, the orthographic projection of the first patterned portion 1051 of the electrode patterning layer 105 onto the substrate 101 covers the orthographic projection of the light-emitting pattern 1042 onto the substrate 101. Since the third electrode pattern 106 is not formed on the first patterned portion 1051, the orthographic projection of the third electrode pattern 106 onto the substrate 101 and the orthographic projection of the light-emitting pattern 1042 onto the substrate 101 can be avoided from overlapping. In this case, the orthographic projection of the boundary of the first patterned portion 1051 onto the substrate 101 can be located on the side of the orthographic projection of the boundary of the light-emitting pattern 1042 onto the substrate 101 closer to the first pixel isolation pillar 103.

[0105] Optionally, to ensure that the third electrode pattern 106 can connect with the second electrode pattern 1043, the first patterned portion 1051 of the electrode patterning layer 105 needs to expose the first edge portion 10431 of the second electrode pattern 1043. Therefore, referring to... Figure 1The distance b1 between the orthographic projection of the boundary of the second electrode pattern 1043 away from the light-emitting region 104a on the substrate 101 and the orthographic projection of the boundary of the light-emitting pattern 1042 away from the light-emitting region 104a on the substrate 101 is greater than the distance b2 between the orthographic projection of the boundary of the first patterned portion 1051 away from the light-emitting region 104a on the substrate 101 and the orthographic projection of the boundary of the light-emitting pattern 1042 away from the light-emitting region 104a on the substrate 101. The distance b1 between the orthographic projection b1 of the boundary of the second electrode pattern 1043 away from the light-emitting region 104a on the substrate 101 and the orthographic projection b3 of the boundary of the light-emitting pattern 1042 away from the light-emitting region 104a on the substrate 101 is greater than the distance b3 between the orthographic projection b6 of the third electrode pattern 106 near the light-emitting region 104a on the substrate 101 and the orthographic projection b3 of the boundary of the light-emitting pattern 1042 away from the light-emitting region 104a on the substrate 101. That is, the boundary of the second electrode pattern 1043 away from the light-emitting region 104a is farther from the boundary of the light-emitting pattern 1042 away from the light-emitting region 104a than the boundary of the first patterned portion 1051 away from the light-emitting region 104a, and the boundary of the second electrode pattern 1043 away from the light-emitting region 104a is farther from the boundary of the third electrode pattern 106 near the light-emitting region 104a than the boundary of the light-emitting pattern 1042 away from the light-emitting region 104a.

[0106] Optionally, the boundary of the first patterned portion 1051 away from the light-emitting region 104a and the boundary of the third electrode pattern 106 near the light-emitting region 104a may overlap or be spaced apart; this embodiment does not limit this. When the boundary of the first patterned portion 1051 away from the light-emitting region 104a and the boundary of the third electrode pattern 106 near the light-emitting region 104a overlap, b2 may be equal to b3.

[0107] Figure 3 This is a partial top view of a display panel provided in an embodiment of this application. (Reference) Figure 3 The orthographic projection of the first pixel isolation pillar 103 on the substrate 101 surrounds the orthographic projection of the light-emitting unit 104 on the substrate 101. Correspondingly, the orthographic projections of the first isolation portion 1031 and the second isolation portion 1032 of the first pixel isolation pillar 103 on the substrate 101 both surround the orthographic projection of the light-emitting unit 104 on the substrate 101. That is, the first pixel isolation pillar 103 can separate adjacent light-emitting units 104, thereby preventing crosstalk between the light from adjacent light-emitting units 104 and improving the display effect of the display panel 100.

[0108] Optional, see reference Figure 3The shape of the orthographic projection of the first pixel isolation pillar 103 surrounding each light-emitting unit 104 onto the substrate 101 is a closed pattern. For example, it is annular; that is, for each light-emitting unit 104, the first pixel isolation pillar 103 surrounding the light-emitting unit 104 can be annular isolation pillars. Therefore, the third electrode pattern 106 can be electrically connected to at least a portion of the first isolation portion 1031 of the first pixel isolation pillar 103. For example, Figure 3 In this embodiment, the orthographic projection of the first pixel isolation pillar 103 surrounding the light-emitting unit 104 onto the substrate 101 is hexagonal. Alternatively, the orthographic projection of the first pixel isolation pillar 103 surrounding the light-emitting unit 104 onto the substrate 101 may be of other shapes, which are not limited in this application.

[0109] In the embodiments of this application, reference is made to Figure 3 The plurality of light-emitting units 104 include a first light-emitting unit 104a, a second light-emitting unit 104b, and a third light-emitting unit 104c. The light-emitting colors of the first light-emitting unit 104a, the second light-emitting unit 104b, and the third light-emitting unit 104c are different from each other. Any one of the first light-emitting units 104a, the second light-emitting unit 104b, and the third light-emitting unit 104c is arranged adjacent to at least one of the other two light-emitting units 104. Figure 3 The light-emitting area of ​​the light-emitting unit is used to represent the light-emitting unit.

[0110] The orthographic projection of the first pixel isolation pillar 103 on the substrate 101 surrounds the orthographic projection of the first light-emitting unit 104a on the substrate 101, the orthographic projection of the second light-emitting unit 104b on the substrate 101, and the orthographic projection of the third light-emitting unit 104c on the substrate 101. That is, the first pixel isolation pillar 103 can be located around any light-emitting unit 104 to separate adjacent light-emitting units 104 and avoid light crosstalk between adjacent light-emitting units 104.

[0111] For example, the first light-emitting unit 104a is blue (blue, B) light-emitting unit 104-B, and the light-emitting color of the first light-emitting unit 104a is blue; the second light-emitting unit 104b is red (red, R) light-emitting unit 104-R, and the light-emitting color of the second light-emitting unit 104b is red; the third light-emitting unit 104c is green (green, G) light-emitting unit 104-G, and the light-emitting color of the third light-emitting unit 104c is green.

[0112] In this embodiment, the plurality of light-emitting units 104 may include a plurality of first light-emitting units 104a, a plurality of second light-emitting units 104b, and a plurality of third light-emitting units 104c. (See reference...) Figure 3Two first light-emitting units 104a, two second light-emitting units 104b, and two third light-emitting units 104c are shown.

[0113] In this configuration, any one of the following light-emitting units 104 (at least one first light-emitting unit 104a, at least one second light-emitting unit 104b, and at least one third light-emitting unit 104c) and the other two light-emitting units 104 are arranged adjacent to each other.

[0114] Optionally, the portion of the first pixel isolation pillar 103 surrounding the first light-emitting unit 104a that is close to the second light-emitting unit 104b, and the portion of the first pixel isolation pillar 103 surrounding the second light-emitting unit 104b that is close to the first light-emitting unit 104a are shared.

[0115] The portion of the first pixel isolation pillar 103 surrounding the first light-emitting unit 104a that is close to the third light-emitting unit 104c, and the portion of the first pixel isolation pillar 103 surrounding the third light-emitting unit 104c that is close to the first light-emitting unit 104a are shared.

[0116] The portion of the first pixel isolation pillar 103 surrounding the second light-emitting unit 104b that is near the third light-emitting unit 104c is shared with the portion of the first pixel isolation pillar 103 surrounding the third light-emitting unit 104c that is near the second light-emitting unit 104b. Alternatively, there is a gap G between the first pixel isolation pillar 103 surrounding the second light-emitting unit 104b and the first pixel isolation pillar 103 surrounding the third light-emitting unit 104c. The gap G is located in the arrangement direction of the second light-emitting unit 104b and the third light-emitting unit 104c.

[0117] That is, the first pixel isolation pillar 103 surrounding the first light-emitting unit 104a can be shared with the first pixel isolation pillar 103 of the adjacent light-emitting unit 104. The first pixel isolation pillar 103 surrounding the second light-emitting unit 104b can be shared with the first pixel isolation pillar 103 of the adjacent light-emitting unit 104, or not. The first pixel isolation pillar 103 surrounding the third light-emitting unit 104c can be shared with the first pixel isolation pillar 103 of the adjacent light-emitting unit 104, or not.

[0118] In this embodiment, the light-emitting pattern 1042 of the light-emitting unit 104 may include a functional layer pattern and a light-emitting layer pattern. The functional layer pattern may be the portion of the light-emitting functional layer located in the light-emitting region 104a after the boundary of the first pixel isolation pillar 103 breaks. The light-emitting layer pattern may be prepared using different light-emitting materials. For example, the material of the light-emitting layer pattern of the blue light-emitting unit 104-B may be a material used to emit blue light, the material of the light-emitting layer pattern of the red light-emitting unit 104-R may be a material used to emit red light, and the material of the light-emitting layer pattern of the green light-emitting unit 104-G may be a material used to emit green light.

[0119] Optionally, the functional layer patterns of light-emitting units 104 of different colors can be fabricated together, and the light-emitting layer patterns of light-emitting units 104 of different colors can be fabricated in a certain order. For example, refer to... Figure 4 The light-emitting layer pattern of the first light-emitting unit 104a can be formed by vapor deposition on the entire surface. Then, the light-emitting layer pattern of the area where the second light-emitting unit 104b and the third light-emitting unit 104c are located is removed by photolithography (photoresist coating, exposure, development and photoresist removal). Then, the light-emitting layer pattern of the second light-emitting unit 104b and the light-emitting layer pattern of the third light-emitting unit 104c are formed by vapor deposition and photolithography on the entire surface. Figure 4 The diagram is used to illustrate the fabrication of the light-emitting layer pattern and the encapsulation film layer 111, but does not illustrate the second electrode pattern 1041, the electrode patterning layer 105, or the third electrode pattern 106.

[0120] Since no other film layers are prepared using photolithography after the formation of the first pixel isolation pillar 103 and before the formation of the light-emitting layer pattern of the first light-emitting unit 104a, the integrity of the first pixel isolation pillar 103 can be guaranteed, thereby ensuring the reliable overlap of the third electrode pattern 106 and the first isolation portion 1031 of the first pixel isolation pillar 103. However, if other film layers are prepared using photolithography before the formation of the light-emitting layer pattern of the second light-emitting unit 104b or before the formation of the light-emitting layer pattern of the third light-emitting unit 104c, the morphology of the first pixel isolation pillar 103 may be incomplete. Therefore, the first pixel isolation pillar 103 surrounding the second light-emitting unit 104b can be spaced apart from the first pixel isolation pillar 103 of the adjacent light-emitting unit 104, and the first pixel isolation pillar 103 surrounding the third light-emitting unit 104c can be spaced apart from the first pixel isolation pillar 103 of the adjacent light-emitting unit 104. Alternatively, it can be understood that the first pixel isolation pillar 103 surrounding the second light-emitting unit 104b and the first pixel isolation pillar 103 of the adjacent light-emitting unit 104 can be used independently. The first pixel isolation pillar 103 surrounding the third light-emitting unit 104c and the first pixel isolation pillar 103 of the adjacent light-emitting unit 104 can be used independently.

[0121] Figure 5 This is a partial top view of another display panel provided in an embodiment of this application. (Reference) Figure 5 The orthographic projections of the first pixel isolation pillars 103 surrounding any two adjacent light-emitting units 104 on the substrate 101 are spaced apart. That is, the first pixel isolation pillars 103 surrounding each light-emitting unit 104 are independently configured, allowing the second electrode pattern 1043 of each light-emitting unit 104 to be electrically connected to the first isolation portion 1031 of the surrounding first pixel isolation pillars 103 via the third electrode pattern 106. For each light-emitting unit 104, the first isolation portion 1031 surrounding the first pixel isolation pillars 103 can serve as the cathode auxiliary electrode of that light-emitting unit 104, and the cathode auxiliary electrodes of different light-emitting units 104 are independently configured. This allows for individual control based on the data driving voltage required for different light-emitting units 104 to emit light, thereby reducing power consumption. Figure 5 The diagram shows two first light-emitting units 104a, two second light-emitting units 104b, and one third light-emitting unit 104c. Figure 5 The light-emitting area of ​​the light-emitting unit is used to represent the light-emitting unit.

[0122] In this embodiment, the light-emitting unit 104 can be a single-layer light-emitting device or a tandem light-emitting device. A single-layer light-emitting device may include a single layer of light-emitting pattern, while a tandem light-emitting device may include multiple layers of light-emitting pattern. Compared to a single-layer light-emitting device, a dual-layer light-emitting device offers improvements in brightness, luminous efficiency, and lifespan.

[0123] Referring to Table 1, if the display panel 100 includes multiple light-emitting units 104 that are single-layer light-emitting devices, the luminance of the red light-emitting unit 104-R is in the range of 0.01 nits to 3000 nits, and the required data driving voltage (Vdata) for the red light-emitting unit 104-R is in the range of 1.7V to 5.17V. The luminance of the green light-emitting unit 104-G is in the range of 0.01 nits to 3000 nits, and the required data driving voltage for the green light-emitting unit 104-G is in the range of 2.22V to 5.06V. The luminance of the blue light-emitting unit 104-B is in the range of 0.01 nits to 3000 nits, and the required data driving voltage for the blue light-emitting unit 104-B is in the range of 0.92V to 4.87V.

[0124] Table 1

[0125] Red light-emitting unit 1.7V to 5.17V Green light-emitting unit 2.22V to 5.06V Blue light-emitting unit 0.92V to 4.87V

[0126] Referring to Table 2, if the display panel 100 includes multiple light-emitting units 104 that are stacked and connected in series, when the luminance of the red light-emitting unit 104-R is 2000 nits, the required data driving voltage for the red light-emitting unit 104-R is 2.27V. When the luminance of the red light-emitting unit 104-R is 1600 nits, the required data driving voltage for the red light-emitting unit 104-R is 2.38V. When the luminance of the red light-emitting unit 104-R is 1400 nits, the required data driving voltage for the red light-emitting unit 104-R is 2.49V.

[0127] When the luminance of the green emitting unit 104-G is 2000 nits, the data driving voltage required for the red emitting unit 104-R is 2.05V. When the luminance of the green emitting unit 104-G is 1600 nits, the data driving voltage required for the red emitting unit 104-R is 2.24V. When the luminance of the green emitting unit 104-G is 1400 nits, the data driving voltage required for the red emitting unit 104-R is 2.34V.

[0128] When the luminance of the blue light-emitting unit 104-B is 2000 nits, the data driving voltage required for the red light-emitting unit 104-R is 1.05V. When the luminance of the blue light-emitting unit 104-B is 1600 nits, the data driving voltage required for the red light-emitting unit 104-R is 1.30V. When the luminance of the blue light-emitting unit 104-B is 1400 nits, the data driving voltage required for the red light-emitting unit 104-R is 1.44V.

[0129] Table 2

[0130]

[0131] As can be seen from the above analysis, the data driving voltage of light-emitting units 104 with different emitting colors is different under the same emitting brightness. Therefore, the first pixel isolation pillars 103 around different light-emitting units 104 are set independently to realize the independent setting of the cathodes of different light-emitting units 104. This can be controlled based on the data driving voltage required by different light-emitting units 104. This can avoid the need to provide a high data driving voltage for all light-emitting units 104 because the data driving voltage of some light-emitting units 104 is high. In addition, it can avoid the overheating phenomenon of thin film transistors (TFTs) in the light-emitting circuit that provides light emission signals to light-emitting units 104, and can effectively reduce power consumption.

[0132] Figure 6 This is a partial cross-sectional schematic diagram of another display panel provided in an embodiment of this application. (Reference) Figure 6The protrusion 10322 of the second isolation portion 1032 of the first pixel isolation pillar 103 extending beyond the first isolation portion 1031 includes: a first portion 103221 on the side closer to the light-emitting unit 104, and a second portion 103222 on the side farther from the light-emitting unit 104. The width c1 of the orthographic projection of the first portion 103221 onto the substrate 101 is greater than the width c2 of the orthographic projection of the second portion 103222 onto the substrate 101.

[0133] Since the first pixel isolation pillars 103 around different light-emitting units 104 are independently set, each first pixel isolation pillar 103 only needs to be connected to the third electrode pattern 106 on the side closest to the corresponding light-emitting unit 104, while the side away from the corresponding light-emitting unit 104 does not require special design. Therefore, the width c1 of the first portion 103221 of the second isolation portion 1032 directly determines the overlap area between the first pixel isolation pillar 103 and the third electrode pattern 106. The larger the width c1 of the first portion 103221 of the second isolation portion 1032, the larger the overlap area between the first pixel isolation pillar 103 and the third electrode pattern 106; the smaller the width c1 of the first portion 103221 of the second isolation portion 1032, the smaller the overlap area between the first pixel isolation pillar 103 and the third electrode pattern 106.

[0134] To improve the overlap effect and reduce the cathode resistance, the overlap area between the first pixel isolation pillar 103 and the third electrode pattern 106 should be as large as possible. This allows the width of the second isolation portion 1032 extending relative to the first isolation portion 1031 on the side closer to the light-emitting unit 104 (i.e., the width of the first portion 103221) to be greater than the width of the second isolation portion 1032 extending relative to the first isolation portion 1031 on the side farther from the light-emitting unit 104 (i.e., the width c2 of the second portion 103222).

[0135] In addition, since the side of the first pixel isolation pillar 103 away from the corresponding light-emitting unit 104 only serves as a barrier and does not serve as the connection point of the cathode auxiliary electrode, the width c2 of the second part 103222 of the second isolation part 1032 should be designed to be as small as possible.

[0136] refer to Figure 6 Since there is a gap between the first pixel isolation pillars 103 surrounding adjacent light-emitting units 104, the gap between the first pixel isolation pillars 103 surrounding adjacent light-emitting units 104 can contain the material of both the light-emitting functional layer and the first cathode layer during the full-layer evaporation of the light-emitting functional layer and the first cathode layer. Of course, the material of the light-emitting functional layer and the material of the first cathode layer in the gap between the first pixel isolation pillars 103 surrounding adjacent light-emitting units 104 can also be removed by photolithography; this embodiment does not limit this process. For example... Figure 6Materials with only a light-emitting layer in the middle, but without a cathode layer. Further, refer to... Figure 6 The electrode patterning layer 105 also includes a fourth patterned portion 1054 located on the side of the first pixel isolation pillar 103 away from the substrate 101, thereby avoiding the cathode material from being attached to the gap between the first pixel isolation pillars 103 around the adjacent light-emitting unit 104 and affecting the transmittance of the display panel 100 when the third electrode pattern 106 is formed.

[0137] Considering the independent arrangement and manufacturing process of the first pixel isolation pillar 103, the spacing between adjacent first pixel isolation pillars 103 needs to be limited. Optionally, the distance d1 between the orthographic projections d1 of the first isolation portions 1031 of the first pixel isolation pillars 103 surrounding two adjacent light-emitting units 104 on the substrate 101 away from the substrate 101 is greater than the width c1 of the orthographic projection of the first portion 103221 on the substrate 101, and greater than the width c2 of the orthographic projection of the second portion 103222 on the substrate 101. This avoids the difficulty in fabricating adjacent first pixel isolation pillars 103 due to excessively small distances.

[0138] In this embodiment, the design of the first pixel isolation pillar 103 is not limited by the arrangement of the multiple light-emitting units 104. For example, the multiple light-emitting units 104 can be arranged in a diamond-like pattern, a real RGB pattern, an RGBW pattern, or an RGBY pattern. In the case of an RGBW pattern, the multiple light-emitting units 104 may include a red light-emitting unit 104-R, a green light-emitting unit 104-G, a blue light-emitting unit 104-B, and a white light-emitting unit 104-W. In the case of an RGBY pattern, the multiple light-emitting units 104 may include a red light-emitting unit 104-R, a green light-emitting unit 104-G, a blue light-emitting unit 104-B, and a yellow light-emitting unit 104-Y.

[0139] However, if the pixel pitch of adjacent light-emitting units 104 is too large, the effect of the first pixel isolation pillar 103 in preventing light crosstalk will be poor, thereby affecting the yield and display quality of the display panel 100. If the size of the orthographic projection of the light-emitting unit 104 on the substrate 101 differs too much in one direction from the size in other directions (e.g., the shape is elongated), it will be difficult for the first pixel isolation pillar 103 surrounding the light-emitting unit 104 to overlap with the second electrode pattern 1043 of the light-emitting unit 104 through the third electrode pattern 106 (overlapping is difficult).

[0140] Therefore, to avoid the aforementioned problems, the pixel pitch of adjacent light-emitting units 104 can be made small, and / or the dimensional differences of the orthographic projections of the light-emitting units 104 on the substrate 101 in different directions can be small. For example, the pixel pitch of adjacent light-emitting units 104 is less than or equal to 50 μm. Alternatively, the aspect ratio of the orthographic projections of the light-emitting units 104 on the substrate 101 is close to 1:1. Or, the pixel pitch of adjacent light-emitting units 104 is less than or equal to 50 μm, and the aspect ratio of the orthographic projections of the light-emitting units 104 on the substrate 101 is close to 1:1.

[0141] In this embodiment, if the pixel pitch of adjacent light-emitting units 104 is large, such as greater than 50 μm, or if the aspect ratio of the orthographic projection of the light-emitting unit 104 on the substrate 101 is significantly different from 1:1, the light-emitting unit 104 can be divided into multiple sub-light-emitting units by using a second pixel isolation pillar 107 disposed inside the light-emitting unit 104.

[0142] Optional, see reference Figures 7 to 8 The pixel opening 102a includes a plurality of pixel sub-openings 102a1, which can expose at least a portion of the first electrode pattern 1041 of the same light-emitting unit 104. In this case, refer to Figure 9 and Figure 10 The light-emitting area 104a of the light-emitting unit 104 may include multiple sub-light-emitting areas 104a1 corresponding to multiple pixel sub-openings 102a1, or it can be understood that the light-emitting area 104a of the light-emitting unit 104 includes multiple sub-light-emitting areas 104a1 of multiple sub-light-emitting units. The display panel 100 also includes a second pixel isolation pillar 107. The orthographic projection of the second pixel isolation pillar 107 on the substrate 101 and the orthographic projection of the pixel sub-opening 102a1 on the substrate 101 do not overlap, so as to avoid the second pixel isolation pillar 107 affecting the light emission at the position of the pixel sub-opening 102a1. Figure 9 The diagram illustrates four sub-light-emitting regions 104a1, and the second pixel isolation pillar 107 can be located between any two adjacent sub-light-emitting regions 104a1. Figure 10 The diagram illustrates two sub-light-emitting regions 104a1, and the second pixel isolation pillar 107 can be located between two adjacent sub-light-emitting regions 104a1.

[0143] refer to Figures 7 to 8The second pixel isolation pillar 107 includes a third isolation portion 1071 and a fourth isolation portion 1072 stacked in a direction away from the substrate 101. The orthographic projection of the third isolation portion 1071 on the substrate 101 is located inside the orthographic projection of the fourth isolation portion 1072 on the substrate 101.

[0144] Optionally, when a second pixel isolation pillar 107 is provided internally, the light-emitting unit 104 may include a plurality of light-emitting sub-patterns 10421 and a plurality of first sub-electrode patterns 10431 spaced apart. The main function of the second pixel isolation pillar 107 is to cause the light-emitting functional layer and the cathode layer to break at the boundary of the second pixel isolation pillar 107 during the formation of the light-emitting functional layer and the cathode layer, thereby obtaining at least some of the light-emitting units 104 including the plurality of light-emitting sub-patterns 10421 and the plurality of first sub-electrode patterns 10431.

[0145] The light-emitting unit 104 includes multiple light-emitting sub-patterns 10421 and multiple first sub-electrode patterns 10431, each corresponding to a multiple pixel sub-openings 102a1. The light-emitting sub-patterns 10421 and the first sub-electrode patterns 10431 are all located within their respective pixel sub-openings 102a1. To enable the second pixel isolation pillar 107 to also serve as the cathode auxiliary electrode of the light-emitting unit 104, the third electrode pattern 106 can be electrically connected to the third isolation portion 1071 of the second pixel isolation pillar 107.

[0146] Since the light-emitting unit 104 is divided into multiple sub-light-emitting units, the multiple sub-light-emitting regions 104a1 of the multiple sub-light-emitting units will not affect each other, and the light emission of other sub-light-emitting units will not be affected by black spots or dark spots in a certain sub-light-emitting unit, thereby improving the reliability of the light-emitting unit 104.

[0147] Optional, see reference Figure 7 The first sub-electrode pattern 10431 within adjacent pixel sub-openings 102a1 can be electrically connected to the third isolation portion 1071 of the same second pixel isolation pillar 107 via the third electrode pattern 106. This allows multiple first sub-electrode patterns 10431 of the light-emitting unit 104 to be electrically connected, providing a cathode signal to multiple first sub-electrode patterns 10431 together. Alternatively, refer to... Figure 8 One of the first sub-electrode patterns 10431 in adjacent pixel sub-openings 102a1 can be electrically connected to the third isolation portion 1071 of the third electrode pattern 106 and the second pixel isolation pillar 107, while the other first sub-electrode pattern 10431 is not electrically connected to the third isolation portion 1071 of the second pixel isolation pillar 107, so that cathode signals can be provided to multiple first sub-electrode patterns 10431 respectively.

[0148] refer to Figure 7The first electrode pattern 1041 of the light-emitting unit 104 can be a single, integral structure, with each pixel sub-opening 102a1 exposing a portion of the first electrode pattern 1041. That is, although the light-emitting unit 104 is divided into multiple sub-light-emitting units, only the light-emitting pattern 1042 and the second electrode pattern 1043 of the light-emitting unit 104 can be divided, while the first electrode pattern 1041 of the light-emitting unit 104 does not need to be divided. Alternatively, refer to... Figure 8 The first electrode pattern 1041 of the light-emitting unit 104 includes a plurality of anode sub-patterns 10411 that are spaced apart and correspond to a plurality of pixel sub-openings 102a1, with each pixel sub-opening 102a1 exposing at least a portion of the corresponding first electrode pattern 1041.

[0149] In the embodiments of this application, reference is made to Figure 7 A second pixel isolation pillar 107 is provided between the orthographic projections of adjacent pixel sub-openings 102a1 onto the substrate 101. Alternatively, refer to... Figure 8 Each adjacent pixel sub-opening 102a1 has a plurality of second pixel isolation pillars 107 (e.g., two) between its orthogonal projection on the substrate 101. This application embodiment does not limit this.

[0150] When there are multiple second pixel isolation pillars 107 between the orthographic projections of adjacent pixel sub-openings 102a1 on the substrate 101, it can be ensured that the fourth isolation portion 1072 on the side of the second pixel isolation pillar 107 near the pixel sub-opening 102a1 extends a larger length than the third isolation portion 1071. As a result, the first sub-electrode pattern 10431 is electrically connected to the third isolation portion 1071 through the third electrode pattern 106, thereby improving the reliability of the overlap.

[0151] Optional, see reference Figures 7 to 8 The first pixel isolation pillar 103 may further include a fifth isolation portion 1033 located on the side of the first isolation portion 1031 closest to the substrate 101. The material of the fifth isolation portion 1033 may be the same as the material of the second isolation portion 1032. In this case, the etching rate of the material of the first isolation portion 1031 is greater than the etching rate of the material of the second isolation portion 1032, thereby allowing the first isolation portion 1031 to be recessed relative to the second isolation portion 1032 and the fifth isolation portion 1033 during the etching process, resulting in an undercut isolation pillar.

[0152] refer to Figure 7 and Figure 8The second pixel isolation pillar 107 may further include a sixth isolation portion 1073 located on the side of the third isolation portion 1071 closest to the substrate 101. The material of the sixth isolation portion 1073 may be the same as the material of the fourth isolation portion 1072. In this case, the etching rate of the material of the third isolation portion 1071 is greater than the etching rate of the material of the fourth isolation portion 1072, thereby allowing the third isolation portion 1071 to be recessed relative to the fourth isolation portion 1072 and the sixth isolation portion 1073 during the etching process, resulting in an undercut isolation pillar.

[0153] Optionally, the fifth isolation portion 1033 of the first pixel isolation pillar 103 and the sixth isolation portion 1073 of the second pixel isolation pillar 107 are located on the same layer. The first pixel isolation pillar 103 may not include the fifth isolation portion 1033, and the second pixel isolation pillar 107 may not include the sixth isolation portion 1073. The fifth isolation portion 1033 and the sixth isolation portion 1073 do not necessarily exist simultaneously or both are absent. For example, if the first pixel isolation pillar 103 includes the fifth isolation portion 1033, the second pixel isolation pillar 107 may not include the sixth isolation portion 1073.

[0154] In addition, the first isolation portion 1031 of the first pixel isolation pillar 103 and the third isolation portion 1071 of the second pixel isolation pillar 107 are located on the same layer, and the second isolation portion 1032 of the first pixel isolation pillar 103 and the fourth isolation portion 1072 of the second pixel isolation pillar 107 are located on the same layer.

[0155] Optionally, if there is no pixel defining layer 102 on the side of the second pixel isolation pillar 107 closest to the substrate 101, the second pixel isolation pillar 107 may not need to include a sixth isolation portion 1073. This is because the sixth isolation portion 1073 has poor conductivity and is difficult to etch.

[0156] In this embodiment of the application, when the light-emitting unit 104 is divided into multiple sub-light-emitting units, the multiple sub-light-emitting units may emit light together or not emit light together. That is, although the light-emitting unit 104 is divided, it does not affect the light emission of the light-emitting unit 104.

[0157] Optionally, the first pixel isolation pillar 103 is used to isolate light-emitting units 104 of different emission colors to prevent crosstalk between different light-emitting units 104. Because crosstalk is prevented, the distance between the side of the first pixel isolation pillar 103 furthest from the substrate 101 and the substrate 101 is relatively large. Different sub-light-emitting units of the same light-emitting unit 104 emit the same emission color, so there is no crosstalk problem. The second pixel isolation pillar 107 is mainly used to improve the overlap effect. Because the second pixel isolation pillar 107 does not need to prevent crosstalk, the distance between the side of the second pixel isolation pillar 107 furthest from the substrate 101 and the substrate 101 can be smaller.

[0158] Optionally, the distance h1 between the side of the first pixel isolation pillar 103 away from the substrate 101 and the substrate 101 is greater than the distance h2 between the side of the second pixel isolation pillar 107 away from the substrate 101 and the substrate 101. For example, when pixel defining layers 102 are provided on the sides of both the first pixel isolation pillar 103 and the second pixel isolation pillar 107 near the substrate 101, the first pixel isolation pillar 103 and the second pixel isolation pillar 107 are approximately formed on the same plane. In this case, the thickness of the second pixel isolation pillar 107 can be less than the thickness of the first pixel isolation pillar 103, so that the distance h2 between the side of the second pixel isolation pillar 107 away from the substrate 101 and the substrate 101 is less than the distance h1 between the side of the first pixel isolation pillar 103 away from the substrate 101 and the substrate 101. Further, the thickness of the third isolation portion 1071 included in the second pixel isolation pillar 107 can be less than the thickness of the first isolation portion 1031 included in the first pixel isolation pillar 103.

[0159] In this embodiment, the display panel 100 further includes: a plurality of light-emitting circuits corresponding to the plurality of light-emitting units 104, wherein the light-emitting circuits and the corresponding light-emitting units 104 are connected to form light-emitting pixels. The display panel also includes: a plurality of signal lines connected to the light-emitting circuits for providing driving signals to the light-emitting circuits. Optionally, the light-emitting circuits may include a plurality of thin-film transistors and at least one storage capacitor.

[0160] In this configuration, the orthographic projection of the signal line on the substrate 101 and the orthographic projection of the light-emitting region 104a of the light-emitting unit 104 on the substrate 101 do not overlap, thus avoiding any interference from the signal line with the normal light emission of the light-emitting region 104a. Optionally, when the light-emitting unit 104 is divided into multiple sub-light-emitting units, the area between adjacent sub-light-emitting units can also be a non-light-emitting region 104a. Therefore, at least a portion of the orthographic projections of at least a portion of the signal lines on the substrate 101 lie between the orthographic projections of adjacent pixel sub-openings 102a1 on the substrate 101.

[0161] Optional, see reference Figure 11 The plurality of light-emitting units 104 may include a plurality of first light-emitting units 104a, a plurality of second light-emitting units 104b, and a plurality of third light-emitting units 104c. The plurality of light-emitting units 104 includes a plurality of first light-emitting unit groups Z1 and a plurality of second light-emitting unit groups Z2 arranged along a first direction X. The first light-emitting unit group Z1 includes a plurality of second light-emitting units 104b and a plurality of third light-emitting units 104c arranged alternately along a second direction Y. The second light-emitting unit group Z2 includes a plurality of first light-emitting units 104a along the second direction Y. The second light-emitting units 104b and third light-emitting units 104c are not divided; each first light-emitting unit 104a can be divided into two first sub-light-emitting units 104a1 arranged along the first direction X. Figure 11 The light-emitting area is used to represent the light-emitting unit.

[0162] Figure 11 The multiple signal lines shown can all be data signal lines (data). These multiple data signal lines (data) are arranged along the first direction X and extend along the second direction Y. Each first light-emitting unit group Z1 can be provided with two data signal lines (Data1 and Data2). One data signal line can be connected to multiple second light-emitting units 104b included in the first light-emitting unit group Z1 to provide data signals to the multiple second light-emitting units 104b; the other data line can be connected to multiple third light-emitting units 104c included in the first light-emitting unit group Z1 to provide data signals to the multiple third light-emitting units 104c. Each second light-emitting unit group Z2 can be provided with one data signal line (Data3), the orthographic projection of which is located on the substrate 101 between the orthographic projections of the two first sub-light-emitting units 104a1 arranged along the first direction X on the substrate 101.

[0163] In the embodiments of this application, reference is made to Figure 2 The substrate 101 also includes a peripheral region 101b surrounding the display region 101a. (See reference) Figure 12 The display panel 100 also includes: power traces at least partially located in the peripheral area 101b. Figure 12 (Not shown), signal transfer pattern 108, fourth electrode pattern 109 and fifth electrode pattern 110. Among them, signal transfer pattern 108 and first electrode pattern 1041 are located on the same layer, fourth electrode pattern 109 and second electrode pattern 1043 are located on the same layer, and fifth electrode pattern 110 and third electrode pattern 106 are located on the same layer.

[0164] Optionally, the signal switching pattern 108 and the first electrode pattern 1041 can be made of the same material and fabricated using a single process. The fourth electrode pattern 109 and the second electrode pattern 1043 can be made of the same material and fabricated using a single process; for ease of description, the fourth electrode pattern 109 and the second electrode pattern 1043 will be referred to as the first cathode layer in the following text. The fifth electrode pattern 110 and the third electrode pattern 106 can be made of the same material and fabricated using a single process; for ease of description, the fifth electrode pattern 110 and the third electrode pattern 106 will be referred to as the second cathode layer in the following text.

[0165] Optionally, the thickness of the first cathode layer is less than or equal to 20 nm. The first cathode layer may include a first sublayer and a second sublayer. The material of the first sublayer may be ytterbium (Yb). The material of the second sublayer may be a metal or a metal alloy, for example, the material of the second sublayer may include at least one of magnesium (Mg) and silver (Ag). Optionally, the ratio of magnesium to silver in the material of the second sublayer may be greater than 0 and less than 1. It should be noted that the first sublayer may also be omitted, and this application does not limit this.

[0166] Optionally, since both the third electrode pattern 106 and the fifth electrode pattern 110 in the second cathode layer are used for signal transmission, the conductivity of the second cathode layer is greater than or equal to the conductivity of the first cathode layer. The material of the second cathode layer is a metal or a metal alloy. To ensure the conductivity of the second cathode layer, the material of the second cathode layer includes at least silver (Ag), and may also include other metals or metal alloys; this embodiment does not limit this. Furthermore, since neither the third electrode pattern 106 nor the fifth electrode pattern 110 in the second cathode layer affects the display, the thickness of the second cathode layer can be greater than or equal to 20 nm. The second cathode layer can be transparent or opaque. It includes at least one of magnesium (Mg) and other metals.

[0167] Optionally, the materials of the first cathode layer and the second cathode layer can be the same or different materials, and this application embodiment does not limit this.

[0168] In this embodiment, the signal conversion pattern 108 can be connected to the power supply trace, the fourth electrode pattern 109 is connected to the signal conversion pattern 108, the fourth electrode pattern 109 is also electrically connected to the first isolation section 1031, and the fifth electrode pattern 110 is electrically connected to the fourth electrode pattern 109. Since the first isolation section 1031 is connected to the second electrode pattern 1043 of the light-emitting unit 104 through the third electrode pattern 106, the power supply trace can be sequentially connected to the second electrode pattern 1043 of the light-emitting unit 104 through the signal conversion pattern 108, the fourth electrode pattern 109, the first isolation section 1031, and the third electrode pattern 106. This allows the power supply trace to transmit the power signal received from the external circuit to the second electrode pattern 1043, enabling the light-emitting unit 104 to emit light. Optionally, the power supply trace can be a negative power supply trace, or it can also be called a VSS trace.

[0169] Optionally, since the display panel 100 also includes a fifth electrode pattern 110 connected to the fourth electrode pattern 109, the fifth electrode pattern 110 can reduce the cathode resistance.

[0170] refer to Figure 12 As can be seen, the electrode patterning layer 105 also includes a second patterned portion 1052 located on the side of the fourth electrode pattern 109 away from the substrate 101. The fourth electrode pattern 109 includes a second edge portion 1091, which is an edge portion of the fourth electrode pattern 109 that does not overlap with the second patterned portion 1052. The fifth electrode pattern 110 is connected to the second edge portion 1091.

[0171] Since the material of the electrode patterning layer 105 and the cathode material are mutually repulsive, the second patterned portion 1052 exposes the second edge portion 1091 of the fourth electrode pattern 109, so that when the cathode material layer is formed after the electrode patterning layer 105, the cathode material layer can be formed above the second edge portion 1091 of the fourth electrode pattern 109 (i.e., the fifth electrode pattern 110 is obtained), thereby allowing the fifth electrode pattern 110 formed after the electrode patterning layer 105 to overlap with the second edge portion 1091 of the fourth electrode pattern 109.

[0172] In this embodiment, the second electrode pattern 1043 and the fourth electrode pattern 109 can be fabricated together using an open mask, which can be referred to as the first open mask. The electrode patterning layer 105 is fabricated using an open mask, which can be referred to as the second open mask. The third electrode pattern 106 and the fifth electrode pattern 110 can be fabricated together using an open mask, which can be referred to as the third open mask.

[0173] The first open mask has a first mask opening that covers the display area 101a and a portion of the surrounding area adjacent to the display area 101a. The second open mask has a second mask opening that covers the display area 101a and a portion of the surrounding area adjacent to the display area 101a. The third open mask has a third mask opening that covers the display area 101a.

[0174] To ensure the effectiveness of the overlap, the size of the third mask opening can be greater than or equal to the size of the first mask opening, and the size of the first mask opening can be greater than the size of the second mask opening. Furthermore, refer to... Figure 13 During the fabrication process, the orthographic projection of the third mask opening on the substrate 101 covers the orthographic projection of the first mask opening on the substrate 101, and the orthographic projection of the first mask opening on the substrate 101 covers the orthographic projection of the second mask opening on the substrate 101.

[0175] Optionally, the design relationship between the fourth electrode pattern 109, the second patterned portion 1052, and the fifth electrode pattern 110 can be measured by the distance between the fourth electrode pattern 109 and the boundary of the pixel defining layer 102 away from the display area 101a. For example, the distance e1 between the fourth electrode pattern 109 and the boundary of the pixel defining layer 102 away from the display area 101a is greater than the distance e2 between the second patterned portion 1052 and the boundary of the pixel defining layer 102 away from the display area 101a, and the distance e2 between the second patterned portion 1052 and the boundary of the pixel defining layer 102 away from the display area 101a is less than the distance e3 between the fifth electrode pattern 110 and the boundary of the pixel defining layer 102 away from the display area 101a. Furthermore, the distance e1 between the fourth electrode pattern 109 and the boundary of the display area 101a and the pixel defining layer 102 and the boundary of the display area 101a can be greater than the distance e3 between the fifth electrode pattern 110 and the boundary of the display area 101a and the boundary of the pixel defining layer 102. Of course, the distance e1 between the fourth electrode pattern 109 and the boundary of the display area 101a and the boundary of the pixel defining layer 102 and the boundary of the display area 101a can also be less than or equal to the distance e3 between the fifth electrode pattern 110 and the boundary of the pixel defining layer 102 and the boundary of the display area 101a; this embodiment does not limit this.

[0176] To ensure that the fifth electrode pattern 110 can connect with the second edge 1091 of the fourth electrode pattern 109, the distance between the fifth electrode pattern 110 and the boundary of the display area 101a, and the distance between the second patterned portion 1052 and the boundary of the display area 101a, must be greater than or equal to the alignment accuracy of the open mask. Optionally, assuming the alignment accuracy of the open mask is 50 μm, the distance between the fifth electrode pattern 110 and the boundary of the display area 101a, and the distance between the second patterned portion 1052 and the boundary of the display area 101a, must be greater than or equal to 50 μm.

[0177] Optionally, the thickness of the fourth electrode pattern 109 may be less than the thickness of the second patterned portion 1052, and the thickness of the second patterned portion 1052 may be less than the thickness of the fifth electrode pattern 110.

[0178] Since the fourth electrode pattern 109 and the second electrode pattern 1043 are located in the same layer, the thickness of the fourth electrode pattern 109 is affected by the second electrode pattern 1043. The second electrode pattern 1043 is designed to adjust the microcavity of the light-emitting unit 104, which requires high transmittance, so the thickness of the second electrode pattern 1043 needs to be designed to be thinner. Correspondingly, the thickness of the fourth electrode pattern 109 is also thinner.

[0179] Furthermore, since the fifth electrode pattern 110 and the third electrode pattern 106 are located in the same layer, the thickness of the fifth electrode pattern 110 is affected by the thickness of the third electrode pattern 106. The third electrode pattern 106 is designed to reduce resistance, so its thickness is relatively thick. Correspondingly, the thickness of the fifth electrode pattern 110 is also relatively thick.

[0180] Additionally, the thickness of the second patterned portion 1052 can be between the thickness of the fourth electrode pattern 109 and the thickness of the fifth electrode pattern 110.

[0181] Furthermore, because the fifth electrode pattern 110 needs to slope up the boundary of the second patterned portion 1052 away from the display area 101a, the angle between the side of the second patterned portion 1052 away from the display area 101a and the surface of the second patterned portion 1052 near the substrate 101 can be an acute angle, i.e., less than 90°. The angle between the side of the second patterned portion 1052 away from the display area 101a and the surface of the fifth electrode pattern 110 near the substrate 101 can be complementary to the angle between the side of the second patterned portion 1052 away from the display area 101a and the surface of the second patterned portion 1052 near the substrate 101.

[0182] In this embodiment, if the first pixel isolation pillars 103 surrounding the plurality of light-emitting units 104 are not used individually, the plurality of light-emitting units 104 can share a common cathode signal. In this case, the plurality of light-emitting units 104 do not need to be segmented, or at least some of the plurality of light-emitting units 104 can be segmented into a plurality of sub-light-emitting units. Of course, if the first pixel isolation pillars 103 surrounding the plurality of light-emitting units 104 are used individually, the plurality of light-emitting units 104 can independently obtain a cathode signal. In this case, the plurality of light-emitting units 104 do not need to be segmented, or at least some of the plurality of light-emitting units 104 can be segmented into a plurality of sub-light-emitting units.

[0183] In the embodiments of this application, reference is made to Figure 4 The display panel 100 also includes an encapsulation film layer 111. The encapsulation film layer 111 may be located on the side of the plurality of light-emitting units 104 away from the substrate 101. Optionally, the encapsulation film layer 111 includes a first encapsulation layer 1111, a second encapsulation layer 1112, and a third encapsulation layer 1113.

[0184] The first encapsulation layer 1111 may include multiple encapsulation portions corresponding to multiple light-emitting units 104, each encapsulation portion covering the corresponding light-emitting unit 104 for encapsulating the light-emitting unit 104. The second encapsulation layer 1112 and the third encapsulation layer 1113 may both cover multiple light-emitting units 104.

[0185] Optionally, the first encapsulation layer 1111 and the third encapsulation layer 1113 can be made of inorganic materials, while the second encapsulation layer 1112 can be made of organic materials. For example, the first encapsulation layer 1111 and the third encapsulation layer 1113 can be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The second encapsulation layer 1112 can be made of a resin material. The resin can be a thermoplastic resin or a thermosetting resin; the thermoplastic resin can include acrylic (PMMA) resin, and the thermosetting resin can include epoxy resin.

[0186] In this embodiment, the second encapsulation layer 1112 can be fabricated using inkjet printing (IJP). The first encapsulation layer 1111 and the third encapsulation layer 1113 can be fabricated using chemical vapor deposition (CVD).

[0187] In summary, this application provides a display panel comprising a substrate, a pixel defining layer, a first pixel isolation pillar, a plurality of light-emitting units, an electrode patterning layer, and a third electrode pattern. The third electrode pattern overlaps with the first edge of the exposed second electrode pattern of the electrode patterning layer and is connected to the first pixel isolation pillar, thereby enabling the first pixel isolation pillar to serve as the cathode auxiliary electrode of the light-emitting unit. Furthermore, since the second electrode pattern of the light-emitting unit is connected to the first pixel isolation pillar through the third electrode pattern, the second electrode pattern of the light-emitting unit can receive cathode signals through the first pixel isolation pillar, improving the reliability of cathode signal reception.

[0188] Figure 14 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. (Reference) Figure 14 The method includes:

[0189] Step S101: Obtain the substrate.

[0190] The substrate 101 includes a display area 101a. The substrate 101 can support multiple light-emitting units 104, and the material of the substrate 101 can be plastic or glass, etc.

[0191] Step S102: Form a first electrode pattern of multiple light-emitting units on one side of the substrate.

[0192] The first electrode patterns 1041 of the plurality of light-emitting units 104 can be arranged at intervals. Optionally, some of the first electrode patterns 1041 of the plurality of light-emitting units 104 may include a plurality of anode sub-patterns 10411 arranged at intervals.

[0193] Step S103: A pixel defining layer is formed on the side of the first electrode pattern of the multiple light-emitting units away from the substrate.

[0194] The pixel defining layer 102 includes a plurality of pixel openings 102a located in the display area 101a, and the plurality of pixel openings 102a correspond to a plurality of light-emitting units 104. The pixel openings 102a expose at least a portion of the first electrode pattern 1041 of the corresponding light-emitting unit 104.

[0195] Step S104: Form a first pixel isolation pillar on the side of the pixel defining layer away from the substrate.

[0196] In this embodiment of the application, in order to avoid the first pixel isolation pillar 103 affecting the light-emitting unit 104, the orthographic projection of the first pixel isolation pillar 103 on the substrate 101 and the orthographic projection of the pixel opening 102a on the substrate 101 can be made not to overlap.

[0197] The first pixel isolation pillar 103 includes a first isolation portion 1031 and a second isolation portion 1032 stacked along a direction away from the pixel defining layer 102. The material of the first isolation portion 1031 may include a conductive material. The orthographic projection of the first isolation portion 1031 on the substrate 101 is located inside the orthographic projection of the second isolation portion 1032 on the substrate 101.

[0198] Optionally, the first isolation portion 1031 and the second isolation portion 1032 can be formed using a single etching process. The etching rate of the material of the first isolation portion 1031 is greater than that of the material of the second isolation portion 1032, thereby allowing the first pixel isolation pillar 103 to have an incised structure. This avoids breakage of the subsequent light-emitting functional layer and cathode layer at the edge of the second isolation portion 1032 in the first pixel isolation pillar 103, ensuring the formation of multiple independent light-emitting patterns 1042 and multiple independent second electrode patterns 1043.

[0199] Step S105: Form a light-emitting pattern of multiple light-emitting units within multiple pixel openings.

[0200] In this embodiment, the light-emitting pattern 1042 can be connected to the first electrode pattern 1041. The light-emitting pattern 1042 may include a functional layer pattern and a light-emitting layer pattern. The functional layer pattern may be the portion of the light-emitting functional layer located in the light-emitting region 104a after the boundary of the first pixel isolation pillar 103 breaks. The light-emitting layer pattern may be prepared using different light-emitting materials. For example, the material of the light-emitting layer pattern of the blue light-emitting unit 104-B may be a material used to emit blue light, the material of the light-emitting layer pattern of the red light-emitting unit 104-R may be a material used to emit red light, and the material of the light-emitting layer pattern of the green light-emitting unit 104-G may be a material used to emit green light.

[0201] Optionally, the functional layer patterns of light-emitting units 104 of different colors can be prepared together, and the light-emitting layer patterns of light-emitting units 104 of different colors can be prepared in a certain order.

[0202] Step S106: Form a second electrode pattern of multiple light-emitting units on the side of the light-emitting pattern away from the substrate.

[0203] In this embodiment, the second electrode pattern 1043 can be connected to the light-emitting pattern 1042 to enable the light-emitting unit 104 to emit light. The second electrode pattern 1043 can function as a microcavity for the light-emitting unit 104. Optionally, the orthogonal projection of the second electrode pattern 1043 on the substrate 101 can cover the orthogonal projection of the light-emitting unit 104 on the substrate 101.

[0204] Step S107: An electrode patterning layer is formed on the side of the first cathode layer away from the substrate.

[0205] In this embodiment, the material of the electrode patterning layer 105 has poor compatibility with the cathode material. The electrode patterning layer 105 includes a first patterned portion 1051 located within the pixel opening 102a. The orthographic projection of the first patterned portion 1051 on the substrate 101 lies within the orthographic projection of the second electrode pattern 1043 on the substrate 101, and the first patterned portion 1051 exposes the first edge portion 10431 of the second electrode pattern 1043.

[0206] Since the first patterned portion 1051 exposes the first edge portion 10431 of the second electrode pattern 1043, when the electrode patterned layer 105 is subsequently formed, the cathode material can be attached above the first edge portion 10431 of the second electrode pattern 1043.

[0207] Step S108: Form the third electrode pattern.

[0208] In this embodiment, since the first patterned portion 1051 exposes the first edge portion 10431 of the second electrode pattern 1043, a cathode material layer is formed after the electrode patterning layer 105, so that the cathode material layer can be formed above the first edge portion 10431 of the second electrode pattern 1043 (i.e., the third electrode pattern 106 is obtained), thereby enabling the third electrode pattern 106 formed after the electrode patterning layer 105 to overlap with the first edge portion 10431 of the second electrode pattern 1043.

[0209] This configuration allows the third electrode pattern 106 to connect the first isolation portion 1031 and the second electrode pattern 1043, enabling the first pixel isolation pillar 103 to function as a cathode auxiliary electrode. Simultaneously, a large portion of the second electrode pattern 1043 on the side furthest from the substrate 101 is comprised of an electrode patterning layer 105. Since the transmittance of the electrode patterning layer 105 is higher than that of the cathode material, this structure also avoids placing the third electrode pattern 106 above the second electrode pattern 1043, which would affect the transmittance of the display panel.

[0210] Since it is difficult for cathode material to adhere to the electrode patterning layer 105, the electrode patterning layer 105 may be completely devoid of cathode material or may have only a small amount of cathode material attached. In either case, since the electrode patterning layer 105 has high transmittance and there is very little or no cathode material on the electrode patterning layer 105, this structure avoids affecting the transmittance of the display panel due to the setting of the cathode auxiliary electrode.

[0211] In this embodiment, if the light-emitting unit 104 is divided into multiple sub-light-emitting units, the display panel may further include a second pixel isolation pillar 107 located between the multiple sub-light-emitting units. The second pixel isolation pillar 107 may be fabricated using the same process as the first pixel isolation pillar 103.

[0212] Optionally, the signal transfer pattern 108 included in the display panel 100 can be fabricated in the same process as the first electrode pattern 1041 of the plurality of light-emitting units 104. The fourth electrode pattern 109 included in the display panel can be fabricated in the same process as the second electrode pattern 1043 of the plurality of light-emitting units 104. The fifth electrode pattern 110 included in the display panel can be fabricated in the same process as the third electrode pattern 106.

[0213] In summary, this application provides a method for fabricating a display panel. The display panel fabricated by this method includes a substrate, a pixel defining layer, a first pixel isolation pillar, a plurality of light-emitting units, an electrode patterning layer, and a third electrode pattern. The first edge of the third electrode pattern overlaps with the exposed second electrode pattern of the electrode patterning layer and is connected to the first pixel isolation pillar, thereby enabling the first pixel isolation pillar to serve as the cathode auxiliary electrode of the light-emitting unit. Simultaneously, since the second electrode pattern of the light-emitting unit is connected to the first pixel isolation pillar through the third electrode pattern, the second electrode pattern of the light-emitting unit can receive cathode signals through the first pixel isolation pillar, improving the reliability of cathode signal reception.

[0214] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 15 The display device includes a power supply component 200 and a display panel 100 as described in the above embodiments. The power supply component 200 is connected to the display panel 100 and is used to supply power to the display panel 100.

[0215] Optionally, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, car navigation systems, and e-readers, as well as any product or component with display functionality.

[0216] Since the display device can have essentially the same technical effects as the display panel described in the previous embodiments, for the sake of brevity, the technical effects of the display device will not be described again here.

[0217] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0218] The Description of Embodiments section of this application describes several embodiments; however, this description is exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0219] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0220] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0221] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Furthermore, the drawings schematically illustrate ideal examples, and this application is not limited to the shapes or numerical values ​​shown in the drawings.

[0222] The ordinal numbers "first," "second," and "third" used in this specification are for the purpose of avoiding confusion among the constituent elements, not for limiting the quantity. The term "multiple" in this application refers to two or more quantities.

[0223] The thickness range of the film layer in this specification is A to B, which means that the thickness is between A and B, including the two endpoints of A and B.

[0224] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0225] In this specification, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this application according to the specific circumstances.

[0226] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode (drain terminal, drain region, or drain), and a source electrode (source terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0227] In this specification, the first terminal of a transistor can be the drain electrode and the second terminal of a transistor can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0228] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0229] In this application, "thickness" and "height" refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer closer to the substrate.

[0230] In this specification, circles, rectangles, hexagons, or rhombuses are not strictly defined; they can be approximate circles, rectangles, hexagons, or rhombuses. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0231] In this application, "about" means a value that is not strictly limited and allows for process and measurement errors.

[0232] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: A substrate, the substrate including a display area; A pixel defining layer, the pixel defining layer being located on one side of the substrate, and the pixel defining layer including a plurality of pixel openings located in the display area; The first pixel isolation pillar is located on the side of the pixel defining layer away from the substrate. The plurality of light-emitting units corresponding to the plurality of pixel openings, each light-emitting unit including a first electrode pattern, a light-emitting pattern, and a second electrode pattern, wherein the first electrode pattern is located on the side of the pixel defining layer close to the substrate, the pixel opening exposes at least a portion of the first electrode pattern corresponding to the light-emitting unit, the light-emitting pattern is located within the pixel opening and connected to the first electrode pattern, and the second electrode pattern is located on the side of the light-emitting pattern away from the substrate and connected to the light-emitting pattern; An electrode patterning layer includes a first patterned portion located within the pixel opening. The orthographic projection of the first patterned portion on the substrate is located within the orthographic projection of the second electrode pattern on the substrate. The second electrode pattern includes a first edge portion, which is an edge portion of the second electrode pattern that does not overlap with the first patterned portion. In addition, a third electrode pattern is electrically connected to the first edge portion of the second electrode pattern, and the third electrode pattern is electrically connected to the first pixel isolation pillar; the third electrode pattern and the electrode patterning layer do not overlap.

2. The display panel according to claim 1, characterized in that, The orthogonal projection of the first pixel isolation pillar on the substrate and the orthogonal projection of the pixel opening on the substrate do not overlap. The first pixel isolation pillar includes: a first isolation portion and a second isolation portion stacked along a direction away from the pixel defining layer. The material of the first isolation portion includes a conductive material. The orthogonal projection of the first isolation portion on the substrate is located inside the orthogonal projection of the second isolation portion on the substrate. The third electrode pattern is electrically connected to the first isolation section.

3. The display panel according to claim 2, characterized in that, The second isolation portion includes a portion located on the side of the first isolation portion away from the substrate, and a protrusion extending beyond the edge of the first isolation portion in a plane parallel to the substrate. The orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the protrusion on the substrate overlap, and the third electrode pattern and the first isolation portion are electrically connected in contact.

4. The display panel according to claim 1, characterized in that, The orthographic projection of the second electrode pattern on the substrate covers the orthographic projection of the light-emitting pattern on the substrate; The orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the light-emitting pattern on the substrate do not overlap; The distance between the orthographic projection of the boundary of the second electrode pattern on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate is greater than the distance between the orthographic projection of the boundary of the first patterned portion on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate. The distance between the orthographic projection of the boundary of the second electrode pattern on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate is greater than the distance between the orthographic projection of the boundary of the third electrode pattern on the substrate and the orthographic projection of the boundary of the light-emitting pattern on the substrate.

5. The display panel according to claim 1, characterized in that, The orthographic projection of the first pixel isolation pillar on the substrate surrounds the orthographic projection of the light-emitting unit on the substrate; The third electrode pattern and at least a portion of the first isolation portion surrounding the first pixel isolation pillar of the light-emitting unit are electrically connected.

6. The display panel according to claim 5, characterized in that, The first pixel isolation pillar surrounding each of the light-emitting units has a closed shape on the substrate.

7. The display panel according to claim 6, characterized in that, At least a portion of the first pixel isolation pillars surrounding two adjacent light-emitting units are shared.

8. The display panel according to claim 5, characterized in that, The plurality of light-emitting units include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit emit different colors; any one of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit is arranged adjacent to at least one of the other two light-emitting units. The orthographic projection of the first pixel isolation pillar on the substrate surrounds the orthographic projection of the first light-emitting unit on the substrate, surrounds the orthographic projection of the second light-emitting unit on the substrate, and surrounds the orthographic projection of the third light-emitting unit on the substrate.

9. The display panel according to claim 8, characterized in that, The first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are arranged adjacent to the other two light-emitting units; The portion of the first pixel isolation pillar surrounding the first light-emitting unit that is close to the second light-emitting unit, and the portion of the first pixel isolation pillar surrounding the second light-emitting unit that is close to the first light-emitting unit, are shared. The portion of the first pixel isolation pillar surrounding the first light-emitting unit that is close to the third light-emitting unit, and the portion of the first pixel isolation pillar surrounding the third light-emitting unit that is close to the first light-emitting unit, are shared. The portion of the first pixel isolation pillar surrounding the second light-emitting unit that is close to the third light-emitting unit is shared with the portion of the first pixel isolation pillar surrounding the third light-emitting unit that is close to the second light-emitting unit; or, there is a gap between the first pixel isolation pillar surrounding the second light-emitting unit and the first pixel isolation pillar surrounding the third light-emitting unit, the gap being located in the arrangement direction of the second light-emitting unit and the third light-emitting unit.

10. The display panel according to claim 5, characterized in that, The orthographic projections of the first pixel isolation pillars surrounding any two adjacent light-emitting units on the substrate are spaced apart.

11. The display panel according to claim 10, characterized in that, The second isolation portion of the first pixel isolation pillar, protruding beyond the edge of the first isolation portion in a plane parallel to the substrate, includes: a first portion on the side closer to the light-emitting unit, and a second portion on the side farther from the light-emitting unit; The width of the orthographic projection of the first part on the substrate is greater than the width of the orthographic projection of the second part on the substrate.

12. The display panel according to claim 11, characterized in that, The distance between the orthographic projections of the first isolation portion of the first pixel isolation pillar surrounding two adjacent light-emitting units on the substrate away from the substrate is greater than the width of the orthographic projection of the first portion on the substrate and greater than the width of the orthographic projection of the second portion on the substrate.

13. The display panel according to any one of claims 1 to 12, characterized in that, The pixel opening includes a plurality of pixel sub-openings, and the plurality of pixel sub-openings expose at least a portion of the first electrode pattern of the same light-emitting unit; The display panel further includes: a second pixel isolation pillar, wherein the orthographic projection of the second pixel isolation pillar on the substrate and the orthographic projection of the pixel sub-opening on the substrate do not overlap, and the orthographic projection of the second pixel isolation pillar on the substrate is located between the orthographic projections of adjacent pixel sub-openings on the substrate. The second pixel isolation pillar includes a third isolation portion and a fourth isolation portion stacked in a direction away from the substrate, wherein the orthographic projection of the third isolation portion on the substrate is located inside the orthographic projection of the fourth isolation portion on the substrate; The light-emitting unit includes a plurality of light-emitting sub-patterns spaced apart and a plurality of first cathode sub-patterns spaced apart. The light-emitting sub-patterns and the first cathode sub-patterns are all located within the corresponding pixel sub-openings. The third electrode pattern is also electrically connected to the third isolation part.

14. The display panel according to claim 13, characterized in that, The first electrode pattern of the light-emitting unit is an integral structure, and each pixel sub-opening exposes a portion of the first electrode pattern; or, the first electrode pattern of the light-emitting unit includes a plurality of anode sub-patterns spaced apart and corresponding to the plurality of pixel sub-openings, and each pixel sub-opening exposes at least a portion of the corresponding first electrode pattern.

15. The display panel according to claim 13, characterized in that, The adjacent pixel sub-openings have a plurality of second pixel isolation pillars between their orthogonal projections on the substrate.

16. The display panel according to claim 13, characterized in that, The display panel further includes: a plurality of light-emitting circuits corresponding to the plurality of light-emitting units, wherein the light-emitting circuits and the corresponding light-emitting units are connected to form light-emitting pixels; the display panel further includes: a plurality of signal lines, wherein the signal lines are connected to the light-emitting circuits and are used to provide driving signals to the light-emitting circuits; Wherein, at least a portion of the orthographic projections of at least a portion of the plurality of signal lines on the substrate are located between the orthographic projections of the adjacent pixel sub-openings on the substrate.

17. The display panel according to claim 2, characterized in that, The substrate further includes a peripheral region surrounding the display area; the display panel further includes: power traces, signal switching patterns, a fourth electrode pattern and a fifth electrode pattern located at least partially in the peripheral region, wherein the signal switching pattern and the first electrode pattern are located on the same layer, the fourth electrode pattern and the second electrode pattern are located on the same layer, and the fifth electrode pattern and the third electrode pattern are located on the same layer. The signal conversion pattern is connected to the power supply trace, the fourth electrode pattern is connected to the signal conversion pattern, the fourth electrode pattern is also electrically connected to the first isolation section, and the fifth electrode pattern is electrically connected to the fourth electrode pattern.

18. The display panel according to claim 17, characterized in that, The electrode patterning layer further includes a second patterned portion located on the side of the fourth electrode pattern away from the substrate, the fourth electrode pattern including a second edge portion, the second edge portion being an edge portion of the fourth electrode pattern that does not overlap with the second patterned portion; The fifth electrode pattern is electrically connected to the second edge portion.

19. The display panel according to claim 18, characterized in that, The angle between the side of the second patterned portion away from the display area and the surface of the second patterned portion near the substrate is an acute angle.

20. A method for manufacturing a display panel, characterized in that, The method includes: Obtain a substrate, the substrate including a display area; A first electrode pattern of multiple light-emitting units is formed on one side of the substrate. A pixel defining layer is formed on the side of the first electrode pattern of the plurality of light-emitting units away from the substrate. The pixel defining layer includes a plurality of pixel openings located in the display area. The plurality of pixel openings correspond to the plurality of light-emitting units, and the pixel openings expose at least a portion of the first electrode pattern of the corresponding light-emitting unit. A first pixel isolation pillar is formed on the side of the pixel defining layer away from the substrate, and the first pixel isolation pillar is located on the side of the pixel defining layer away from the substrate. A light-emitting pattern of multiple light-emitting units is formed within the plurality of pixel openings, and the light-emitting pattern is connected to the first electrode pattern; A second electrode pattern for the plurality of light-emitting units is formed on the side of the light-emitting pattern away from the substrate, and the second electrode pattern is connected to the light-emitting pattern; An electrode patterning layer is formed on the side of the second electrode pattern away from the substrate. The electrode patterning layer includes a first patterned portion located within the pixel opening. The orthographic projection of the first patterned portion on the substrate is located within the orthographic projection of the second electrode pattern on the substrate. The second electrode pattern includes a first edge portion, which is an edge portion of the second electrode pattern that does not overlap with the first patterned portion. A third electrode pattern is formed, wherein the third electrode pattern is electrically connected to the first edge portion of the second electrode pattern, and the third electrode pattern is electrically connected to the first pixel isolation pillar, and the third electrode pattern and the electrode patterning layer do not overlap.

21. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in any one of claims 1 to 19; The power supply component is connected to the display panel and is used to supply power to the display panel.

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