Array substrate, manufacturing method of array substrate, display panel and manufacturing method of display panel

Abstract

The invention discloses an array substrate, a manufacturing method of the array substrate, a display panel and a manufacturing method of the display panel. The first conducting layer is arranged on one side of the substrate, the first conducting layer comprises a plurality of data signal lines, touch signal lines and fixed voltage signal lines, the data signal lines, the touch signal lines and the fixed voltage signal lines extend in the second direction and are arranged in the first direction, and the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines; the first direction intersects with the second direction. By means of the structure, the display and touch performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof. Background Art

[0002] OLED (Organic Light-Emitting Diode) display screen has become the current mainstream display trend with its self-luminescence, wide viewing angle, high contrast, fast response speed, etc. However, existing products can no longer meet the needs of users. Summary of the invention

[0003] The main technical problem solved by the present application is to provide an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof, so as to isolate data signal lines and touch lines through baselines, thereby reducing electrical signal interference between display signals and touch signals and improving display and touch performance.

[0004] In order to solve the above problems, the first technical solution provided by the present application is: to provide an array substrate, the array substrate comprising:

[0005] substrate;

[0006] a first conductive layer disposed on one side of the substrate, the first conductive layer comprising a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, the fixed voltage signal lines being disposed between the data signal lines and the touch signal lines;

[0007] The first direction intersects the second direction.

[0008] Preferably, the fixed voltage signal line is located between the adjacent data signal lines and the touch signal lines, and is used to form signal shielding between the data signal lines and the touch signal lines.

[0009] Preferably, the first conductive layer further comprises a plurality of power supply voltage signal lines extending along the second direction and arranged along the first direction, wherein the power supply voltage signal lines comprise a first power supply voltage signal line and a second power supply voltage signal line;

[0010] And / or, the data signal line includes a first data signal line, a second data signal line and a third data signal line;

[0011] And / or, the touch signal line includes a first touch signal line and a second touch signal line;

[0012] Preferably, the first data signal line and the second data signal line are located between the first power supply voltage signal line and the second power supply voltage signal line;

[0013] Preferably, the first power supply voltage signal line, the first data signal line, the second data signal line, and the second power supply voltage signal line are arranged in sequence along the first direction;

[0014] Preferably, the first touch signal line, the fixed voltage signal line, and the third data signal line are sequentially arranged on a side of the first power voltage signal line away from the second power voltage signal line;

[0015] Preferably, the first touch signal line is located between the fixed voltage signal line and the first power supply voltage signal line;

[0016] and / or,

[0017] The third data signal line, the fixed voltage signal line, and the second touch signal line are sequentially arranged on a side of the second power supply voltage signal line away from the first power supply voltage signal line;

[0018] Preferably, the third data signal line is located between the fixed voltage signal line and the second power supply voltage signal line;

[0019] Preferably, the second touch signal line, the fixed voltage signal line, and the third data signal line are sequentially arranged on a side of the first power supply voltage signal line away from the second power supply voltage signal line;

[0020] Preferably, the second touch signal line is located between the fixed voltage signal line and the first power supply voltage signal line;

[0021] and / or,

[0022] Preferably, the third data signal line, the fixed voltage signal line, and the first touch signal line are sequentially arranged on a side of the second power supply voltage signal line away from the first power supply voltage signal line;

[0023] Preferably, the third data signal line is located between the fixed voltage signal line and the second power supply voltage signal line.

[0024] Preferably, a pixel circuit layer is provided between the substrate and the first conductive layer, and the pixel circuit layer includes a first pixel circuit structure, a second pixel circuit structure and a third pixel circuit structure;

[0025] Preferably, the first pixel circuit structure, the second pixel circuit structure, and the third pixel circuit structure are arranged in sequence along the first direction;

[0026] Preferably, the second pixel circuit structure is symmetrically arranged with the first pixel circuit structure along the second direction; the third pixel circuit structure is symmetrically arranged with the second pixel circuit structure along the second direction, and is arranged the same as the first pixel circuit structure.

[0027] Preferably, a pixel circuit layer is provided between the substrate and the first conductive layer, and the pixel circuit layer includes a first pixel circuit structure, a second pixel circuit structure and a third pixel circuit structure;

[0028] The first pixel circuit structure is electrically connected to the first data signal line, the second pixel circuit structure is electrically connected to the second data signal line, and the third pixel circuit structure is electrically connected to the third data signal line;

[0029] Preferably, the first pixel circuit structure, the second pixel circuit structure, and the third pixel circuit structure are arranged in sequence along the first direction;

[0030] Preferably, the second pixel circuit structure is symmetrically arranged with the first pixel circuit structure along the second direction; the third pixel circuit structure is symmetrically arranged with the second pixel circuit structure along the second direction, and is arranged in the same manner as the first pixel circuit structure;

[0031] Preferably, the orthographic projection of the first power supply voltage signal line on the substrate at least partially covers the orthographic projection of the first pixel circuit structure on the substrate;

[0032] and / or,

[0033] The orthographic projection of the second power supply voltage signal line on the substrate at least partially covers the orthographic projection of the second pixel circuit structure on the substrate and the orthographic projection of the third pixel circuit structure on the substrate.

[0034] Preferably, an anode layer is provided on a side of the first conductive layer away from the substrate, and the anode layer includes a first anode, a second anode and a third anode;

[0035] Preferably, the first anode and the second anode are arranged along the second direction, and the third anode, the first anode and the second anode are arranged along the first direction;

[0036] Preferably, an orthographic projection of at least one of the first anode and the second anode on the substrate overlaps with an orthographic projection of the first power supply voltage signal line on the substrate, an orthographic projection of the first data signal line on the substrate, an orthographic projection of the second data signal line on the substrate, and an orthographic projection of the second power supply voltage signal line on the substrate;

[0037] Preferably, an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is equal to an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate;

[0038] Preferably, an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is equal to an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate;

[0039] Preferably, the symmetry axis of the orthographic projection of the first anode on the substrate along the second direction coincides with the symmetry axis of the orthographic projection of the second anode on the substrate along the second direction;

[0040] Preferably, the orthographic projection of the second power supply voltage signal line on the substrate covers the orthographic projection of the third anode on the substrate;

[0041] Preferably, the width of the second power supply voltage signal line is greater than the width of the first power supply voltage signal line.

[0042] Preferably, an anode layer is provided on a side of the first conductive layer away from the substrate, and the anode layer includes a first anode, a second anode and a third anode;

[0043] The first anode is electrically connected to the first pixel circuit structure, the second anode is electrically connected to the second pixel circuit structure, and the third anode is electrically connected to the third pixel circuit structure;

[0044] Preferably, the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of the first power supply voltage signal line on the substrate, the orthographic projection of the first data signal line on the substrate, the orthographic projection of the second data signal line on the substrate, and the orthographic projection of the second power supply voltage signal line on the substrate;

[0045] Preferably, an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is equal to an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate;

[0046] Preferably, the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the first power supply voltage signal line on the substrate, the orthographic projection of the first data signal line on the substrate, the orthographic projection of the second data signal line on the substrate, and the orthographic projection of the second power supply voltage signal line on the substrate;

[0047] Preferably, an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is the same as an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate;

[0048] Preferably, the orthographic projection of the second power supply voltage signal line on the substrate covers the orthographic projection of the third anode on the substrate;

[0049] Preferably, the symmetry axis of the orthographic projection of the first anode on the substrate along the second direction, the symmetry axis of the orthographic projection of the second anode on the substrate along the second direction, and the symmetry axis between the orthographic projection of the first data signal line on the substrate and the orthographic projection of the second data signal line on the substrate coincide with each other;

[0050] Preferably, the width of the second power supply voltage signal line is greater than the width of the first power supply voltage signal line.

[0051] In order to solve the above problem, the second technical solution provided by the present application is: to provide a display panel, the display panel comprising:

[0052] The array substrate as described in any embodiment of the first aspect above;

[0053] A pixel unit layer, disposed on one side of the array substrate, the pixel unit layer comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a first sub-pixel, a second sub-pixel and a third sub-pixel;

[0054] The first sub-pixel corresponds to the first anode, the second sub-pixel corresponds to the second anode, and the third sub-pixel corresponds to the third anode.

[0055] Preferably, the first sub-pixel and the second sub-pixel are arranged along the second direction, and the third sub-pixel, the first sub-pixel and the second sub-pixel are arranged along the first direction;

[0056] Preferably, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0057] Preferably, the array substrate comprises a touch signal line, and an orthographic projection of the touch signal line on the substrate is located between orthographic projections of two adjacent pixel units along the first direction on the substrate;

[0058] Preferably, the touch signal line comprises a first touch signal line and a second touch signal line, and an orthographic projection of the first touch signal line on the substrate and an orthographic projection of the second touch signal line on the substrate are arranged alternately.

[0059] Preferably, the pixel unit layer comprises:

[0060] A pixel definition layer is disposed on a side of the anode layer away from the first conductive layer and covers a portion of the surface of the anode layer;

[0061] A second conductive layer is disposed on a surface of the pixel definition layer away from the anode layer, the second conductive layer comprising a first partition structure and a second partition structure, the first partition structure is insulated from the second partition structure;

[0062] Preferably, the first partition structure is used to transmit a touch signal, and the second partition structure is used to transmit a cathode voltage signal.

[0063] Preferably, the first partition structure comprises a first touch electrode arranged along a first direction and a second touch electrode arranged along a second direction, and the first touch electrode is electrically connected to the second touch electrode;

[0064] Preferably, the orthographic projection of the second touch electrode on the substrate at least partially covers the orthographic projection of the touch signal line on the substrate;

[0065] Preferably, the orthographic projection of the second touch electrode on the substrate does not overlap with the orthographic projection of the data signal line on the substrate;

[0066] Preferably, the orthographic projection of the first touch electrode on the substrate overlaps with the orthographic projections of the first power supply voltage signal line, the first data signal line, the second data signal line, the second power supply voltage signal line, the third data signal line and the fixed voltage signal line on the substrate in sequence.

[0067] Preferably, the second partition structure comprises a first cathode voltage signal line and a second cathode voltage signal line, and the first cathode voltage signal line is electrically connected to the second cathode voltage signal line;

[0068] Preferably, the first cathode voltage signal line is arranged around the pixel unit and around the first sub-pixel, the second sub-pixel and the third sub-pixel in the pixel unit, and the second cathode voltage signal line is electrically connected to two adjacent first cathode voltage signal lines along the first direction;

[0069] Preferably, the first partition structure is disposed around the first cathode voltage signal line, wherein the second touch electrode is partitioned by the second cathode voltage signal line.

[0070] In order to solve the above problems, the third technical solution provided by the present application is to provide a method for manufacturing an array substrate, wherein the manufacturing method comprises:

[0071] providing a substrate;

[0072] A patterned first conductive layer is made on one side of the substrate; wherein the first conductive layer includes a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, and the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines; the first direction intersects with the second direction.

[0073] In order to solve the above problems, the fourth technical solution provided by the present application is to provide a method for manufacturing a display panel, wherein the manufacturing method comprises:

[0074] providing a substrate;

[0075] A patterned first conductive layer is formed on one side of the substrate; wherein the first conductive layer comprises a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines; the first direction intersects with the second direction;

[0076] A patterned pixel unit layer is fabricated on a side of the first conductive layer away from the substrate; wherein the pixel unit layer comprises a plurality of pixel units arranged in an array, and each of the pixel units comprises a first sub-pixel, a second sub-pixel and a third sub-pixel.

[0077] The beneficial effects of the present application are: in the In Cell touch architecture, the space occupied by the pixel driving circuit is compressed, the touch line is placed between two pixel units, and the signal crosstalk between the touch line and the data signal line is isolated by a baseline, which can reduce the electrical signal interference between the display signal and the touch signal, thereby improving the display performance and touch performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0079] Figure 1 A schematic structural diagram of an embodiment of an array substrate provided in the present application;

[0080] Figure 2 A schematic diagram of the structure of the first conductive layer provided in this application;

[0081] Figure 3 This is a schematic structural diagram of an embodiment of a first conductive layer in a pixel unit of the present application;

[0082] Figure 4 A schematic structural diagram of a patterned shielding layer provided in the present application;

[0083] Figure 5 A schematic diagram of the structure of a patterned active layer provided in this application;

[0084] Figure 6 A schematic diagram of the structure of the patterned first metal layer provided in the present application;

[0085] Figure 7 A schematic diagram of the structure of the patterned second metal layer provided in the present application;

[0086] Figure 8 A schematic diagram of the structure of the patterned third metal layer provided in this application;

[0087] Fig. 9 A schematic diagram of the first stacked structure provided in this application;

[0088] Fig.10 A schematic diagram of a second stacked structure provided in this application;

[0089] Fig.11 This is a schematic structural diagram of an embodiment of an anode layer of the present application;

[0090] Fig.12 This is a schematic structural diagram of a specific embodiment of the anode layer of the present application;

[0091] Fig.13 This is a schematic diagram of a cross-sectional structure of an embodiment of a display panel of the present application;

[0092] Fig.14 This is a schematic diagram of a top view of a display panel according to an embodiment of the present application;

[0093] Fig.15 A schematic diagram of a top view of the structure of an embodiment of a second conductive layer provided in the present application;

[0094] Fig.16 A schematic diagram of a process flow of an embodiment of a method for manufacturing an array substrate provided in the present application;

[0095] Fig.17 A schematic diagram of a process flow of an embodiment of a method for manufacturing a display panel provided in the present application. DETAILED DESCRIPTION

[0096] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0097] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0098] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0099] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0100] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0101] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0102] The present application provides an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof, and the following will be combined with the accompanying drawings Figures 1 to 17 Various embodiments of a display panel and a display device are described.

[0103] Figure 1 This is a schematic diagram of the structure of an embodiment of an array substrate provided in this application. Figure 1As shown, the array substrate 1000 includes a substrate 110 and a patterned first conductive layer 200 disposed on one side of the substrate 110 .

[0104] For further information, see Figure 2 , Figure 2 This is a schematic diagram of the structure of the first conductive layer provided in this application. Figure 2 As shown, the first conductive layer 200 includes a plurality of data signal lines data, touch signal lines TP and fixed voltage signal lines Vref extending along the second direction and arranged along the first direction. The fixed voltage signal lines Vref are arranged between the data signal lines data and the touch signal lines TP. The first direction X intersects with the second direction Y, and can be arranged vertically, which is not limited here.

[0105] In this embodiment, the fixed voltage signal line Vref is located between the adjacent data signal line data and the touch signal line TP, and is used to form a signal shield between the data signal line data and the touch signal line TP, thereby effectively avoiding signal crosstalk between the data signal line data and the touch signal line TP, and improving the display and touch performances, respectively. For details, please refer to Figure 2 The dotted line frame shows the location of the fixed voltage signal line Vref. The fixed voltage signal line Vref is arranged between two adjacent data signal lines data and the touch signal line TP.

[0106] It should be noted that the signal on the fixed voltage signal line Vref is a fixed, non-jumping signal, and the fixed voltage signal line Vref can effectively shield the signal interference between the data signal line data and the touch signal line TP. The fixed voltage signal line Vref can be a reference signal line or a zero potential signal line, which is not limited here.

[0107] The first conductive layer 200 includes signal lines such as a first data signal line data1, a second data signal line data2, a third data signal line data3, a first high signal line VDD1, a second high signal line VDD2, a touch line TP, and a reference line Vref, etc. The signal lines are repeatedly arranged along the arrangement direction of the pixel units.

[0108] Among them, the first data signal line data1, the second data signal line data2 and the third data signal line data3 provide data signals for the first sub-pixel, the second sub-pixel and the third sub-pixel in each pixel unit 30 respectively, so that each sub-pixel in the pixel unit 30 emits light of different gray levels, which is not limited here.

[0109] like Figure 2As shown, the first conductive layer 200 includes a plurality of power supply voltage signal lines VDD extending along the second direction and arranged along the first direction. In a repeating unit, the power supply voltage signal line VDD includes a first power supply voltage signal line VDD1 and a second power supply voltage signal line VDD2; and / or, the data signal line data includes a first data signal line data1, a second data signal line data2 and a third data signal line data3; and / or, the touch signal line TP includes a first touch signal line TP1 and a second touch signal line TP2.

[0110] The first data signal line data1 and the second data signal line data2 are located between the first power supply voltage signal line VDD1 and the second power supply voltage signal line VDD2. The first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2 and the second power supply voltage signal line VDD2 are arranged in sequence along the first direction.

[0111] Specifically, Figure 2 The first high potential signal line VDD1 and the second high potential signal line VDD2 in the left pixel unit are used as references.

[0112] The first touch signal line TP1, the fixed voltage signal line Vref, and the third data signal line data3 are sequentially arranged on the side of the first power supply voltage signal line VDD1 away from the second power supply voltage signal line VDD2. Preferably, the first touch signal line TP1 is located between the fixed voltage signal line Vref and the first power supply voltage signal line VDD1. The third data signal line data3 is a data signal line in the previous pixel unit, which is not limited here.

[0113] And / or, a third data signal line data3, a fixed voltage signal line Vref, and a second touch signal line TP2 are sequentially arranged on the side of the second power supply voltage signal line VDD2 away from the first power supply voltage signal line VDD1. Preferably, the third data signal line data3 is located between the fixed voltage signal line Vref and the second power supply voltage signal line VDD2.

[0114] Further, Figure 2 The first high potential signal line VDD1 and the second high potential signal line VDD2 in the pixel unit on the right are used as references.

[0115] A second touch signal line TP2, a fixed voltage signal line Vref, and a third data signal line data3 are sequentially arranged on the side of the first power voltage signal line VDD1 away from the second power voltage signal line VDD2. Preferably, the second touch signal line TP2 is located between the fixed voltage signal line Vref and the first power voltage signal line VDD1. The third data signal line data3 is a data signal line in the left pixel unit, which is not limited here.

[0116] And / or, a third data signal line data3, a fixed voltage signal line Vref, and a first touch signal line TP1 are sequentially arranged on a side of the second power supply voltage signal line VDD2 away from the first power supply voltage signal line VDD1. Preferably, the third data signal line data3 is located between the fixed voltage signal line Vref and the second power supply voltage signal line VDD2.

[0117] The above-mentioned repeating units are used for repeated wiring, which will not be described in detail here.

[0118] In this embodiment, compared with the solution in the prior art that a power supply voltage signal line VDD is arranged on the same side of each data signal line data (that is, a power supply voltage signal line VDD is arranged between each two adjacent data signal lines data), the present application arranges the first data signal line data1 and the second data signal line data2 adjacent to each other, moves the power supply voltage signal line VDD between the first data signal line data1 and the second data signal line data2 to the right side of the second data signal line data2, and merges the power supply voltage signal line VDD adjacent to the third data signal line data3 into one power supply voltage signal line, thereby reducing the number of power supply voltage signal lines in each pixel unit. At the same time, it is convenient to arrange the touch signal line and the fixed voltage signal line between the two pixel units.

[0119] Further, each pixel unit is described as a repeating unit, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the structure of an embodiment of a first conductive layer in a pixel unit of the present application. Figure 3 As shown, each pixel unit 30 further includes a first touch signal line TP1 and / or a second touch signal line TP2, wherein the first touch signal line TP1 is arranged on a side of the first power voltage signal line VDD1 away from the first data signal line data1, and / or the second touch signal line TP2 is arranged on a side of the third data signal line data3 away from the second power voltage signal line VDD2. The touch signal in the pixel unit 30 can be transmitted by the first touch signal line TP1 located on a side of the first power voltage signal line VDD1 away from the first data signal line data1; or by the second touch signal line TP2 located on a side of the third data signal line data3 away from the second power voltage signal line VDD2, that is, the touch signal line TP and the fixed voltage signal line Vref are both located between two adjacent pixel units 30, and the pixel unit 30 can transmit the touch signal by the touch signal line TP located on its left side, or by the touch signal line TP located on its right side, which is not specifically limited here.

[0120] Furthermore, each pixel unit 30 also includes a fixed voltage signal line Vref, wherein the fixed voltage signal line Vref includes a line disposed on a side of the touch signal line TP away from the first power supply voltage signal line VDD1, and a line disposed on a side of the third data signal line data3 away from the second power supply voltage signal line VDD, and located between the third data signal line data3 and the touch signal line TP. The fixed voltage signal line Vref disposed between the third data signal line data3 and the touch signal line TP can isolate the third data signal line data3 from the touch signal line TP, and avoid signal crosstalk between the third data signal line data3 and the touch signal line TP. That is, the fixed voltage signal line Vref is also located between two adjacent pixel units 30, and is disposed between the third data signal line data3 and the touch signal line TP.

[0121] It should be noted that the first data signal line data1, the second data signal line data2, the third data signal line data3, the first power supply voltage signal line VDD1, the second power supply voltage signal line VDD2, the touch signal line TP, and the fixed voltage signal line Vref are arranged in parallel and at intervals along the second direction Y, so that each signal is transmitted independently, but if two adjacent signal lines transmit different signals, they may interfere with each other. In particular, in the In cell touch architecture, the touch signal line TP is arranged in the thin film encapsulation layer and is easily affected by the data signal on the adjacent data signal line. Therefore, according to the arrangement of the first data signal line data1, the second data signal line data2, the third data signal line data3, the first power supply voltage signal line VDD1, the second power supply voltage signal line VDD2, the touch signal line TP, and the fixed voltage signal line Vref in the first conductive layer 200 of the present case, the electrical signal interference between the display signal and the touch signal can be effectively reduced, and the display and touch performance can be improved.

[0122] The touch signal line TP includes a first touch signal line TP1 disposed on a side of the first power voltage signal line VDD1 away from the first data signal line data1 and a second touch signal line TP2 disposed on a side of the third data signal line data3 away from the second power voltage signal line VDD2. In a specific embodiment, the first touch signal line TP1 is used to sense the touch signal of the current pixel unit 30, and the second touch signal line TP2 is used to sense the touch signal of the next pixel unit 30. In another specific embodiment, the touch signal of the pixel unit 30 of the current column can also be sensed by the second touch signal line TP2, and the first touch signal line TP1 is used to sense the touch signal of the pixel unit 30 of the previous column, which is not limited here. Among them, the next pixel unit 30 is adjacent to the current pixel unit 30 in the first direction X, and the first direction X is perpendicular to the second direction Y.

[0123] In a specific embodiment, the second direction Y is the column direction, and the first direction X is the row direction; the first touch signal line TP1 senses the touch signal of the pixel unit 30 of the current column, and the second touch signal line TP2 is used to sense the touch signal of the pixel unit 30 of the next column. In another specific embodiment, the second direction Y is the row direction, and the first direction X is the column direction; the first touch signal line TP1 senses the pixel unit 30 of the current row, and the second touch signal line TP2 senses the touch signal of the pixel unit 30 of the next row. The second direction and the first direction are not specifically defined herein.

[0124] That is, the touch signal line TP is disposed between two adjacent pixel units 30. The fixed voltage signal line Vref is also disposed between two adjacent pixel units 30, and the fixed voltage signal line Vref is disposed between the touch signal line TP and the data signal line data of the adjacent pixel unit 30.

[0125] Furthermore, the fixed voltage signal line Vref includes a first fixed voltage signal line Vref1 disposed on a side of the touch signal line TP away from the first power voltage signal line VDD1, and a second fixed voltage signal line Vref2 disposed on a side of the third data signal line data3 away from the second power voltage signal line VDD and located between the third data signal line data3 and the touch signal line TP. The first fixed voltage signal line Vref1 is used to separate the touch signal line TP1 of the current pixel unit 30 from the data signal line of the previous pixel unit 30; the second fixed voltage signal line Vref2 is used to separate the data signal line data of the current pixel unit 30 from the touch signal line TP2 in the next pixel unit 30, and so on.

[0126] Furthermore, the array substrate 1000 further includes a pixel circuit layer 120 disposed between the substrate 110 and the first conductive layer 200. For details, please refer to Figures 4 to 10 .

[0127] Specifically, the pixel circuit layer 120 includes a plurality of first pixel circuit structures 121 , a second pixel circuit structure 122 and a third pixel circuit structure 123 .

[0128] Furthermore, the first pixel circuit structure 121 is electrically connected to the first data signal line data1 , the second pixel circuit structure 122 is electrically connected to the second data signal line data2 , and the third pixel circuit structure 123 is electrically connected to the third data signal line data3 .

[0129] The first pixel circuit structure 121 is used to provide a driving signal to the first sub-pixel in each pixel unit 30, the second pixel circuit structure 122 is used to provide a driving signal to the second sub-pixel in each pixel unit 30, and the third pixel circuit structure 123 is used to provide a driving signal to the third sub-pixel in each pixel unit 30.

[0130] Preferably, the first pixel circuit structure 121 , the second pixel circuit structure 122 and the third pixel circuit structure 123 are arranged along the first direction X.

[0131] Preferably, the first pixel circuit structure 121 and the second pixel circuit structure 122 are symmetrically arranged along the second direction Y; the third pixel circuit structure 123 and the second pixel circuit structure 122 are symmetrically arranged along the second direction Y, and are arranged the same as the first pixel circuit structure 121.

[0132] Specifically, the pixel circuit layer 120 specifically includes: a patterned shielding layer M0, a patterned active layer psi, a patterned first metal layer M1, a patterned second metal layer M2, and a patterned third metal layer M3.

[0133] It should be noted that the first conductive layer 200 in the present application is a patterned fourth metal layer M4, and the first conductive layer 200 is disposed between the third metal layer M3 and away from the substrate 110. The above metal layers are all disposed at intervals, and are spaced by spacer layers. The shielding layer M0 is also called a shielding metal layer.

[0134] Figure 4 A schematic diagram of the structure of the patterned shielding layer provided in this application, such as Figure 4 As shown, the shielding layer M0 of the first pixel circuit structure 121 is symmetrically arranged with the shielding layer M0 of the second pixel circuit structure 122 along the second direction Y (Y axis). The shielding layer M0 of the third pixel circuit structure 123 is arranged in the same manner as the shielding layer M0 of the first pixel circuit structure 121, and is symmetrically arranged with the shielding layer M0 of the second pixel circuit structure 122 along the second direction Y (Y axis). Among them, the shielding layer M0 serves as a shielding layer.

[0135] Figure 5 The schematic diagram of the structure of the patterned active layer provided in this application is as follows: Figure 5 As shown, the active layer psi of the first pixel circuit structure 121 is symmetrically arranged with the active layer psi of the second pixel circuit structure 122 along the second direction Y. The active layer psi of the third pixel circuit structure 123 is arranged the same as the active layer psi of the first pixel circuit structure 121, and is symmetrically arranged with the active layer psi of the second pixel circuit structure 122 along the second direction Y. Among them, the active layer psi, also called the P-silicon layer, serves as the channel layer of the TFT (thin film transistor).

[0136] Figure 6 The schematic diagram of the structure of the patterned first metal layer provided in this application is as follows: Figure 6 As shown, the first metal layer M1 of the first pixel circuit structure 121 and the first metal layer M1 of the second pixel circuit structure 122 are symmetrically arranged along the second direction Y. The first metal layer M1 of the third pixel circuit structure 123 is arranged the same as the first metal layer M1 of the first pixel circuit structure 121, and is symmetrically arranged with the first metal layer M1 of the second pixel circuit structure 122 along the second direction Y. Among them, the patterned first metal layer M1 is formed into a gate layer of a TFT (thin film transistor), a scanning signal line, and a plate of a storage capacitor, etc.

[0137] Figure 7 The schematic diagram of the structure of the patterned second metal layer provided in this application is as follows: Figure 7 As shown, the second metal layer M2 of the first pixel circuit structure 121 and the second metal layer M2 of the second pixel circuit structure 122 are symmetrically arranged along the second direction Y. The second metal layer M2 of the third pixel circuit structure 123 is arranged in the same manner as the second metal layer M2 of the first pixel circuit structure 121, and is symmetrically arranged along the second direction Y with the second metal layer M2 of the second pixel circuit structure 122. Among them, the second metal layer M2 includes another plate of the storage capacitor, and a horizontal power supply voltage signal line and a horizontal fixed voltage signal line. Among them, the horizontal power supply voltage signal line and the horizontal fixed voltage signal line can be connected to the longitudinal power supply voltage signal line VDD and the fixed voltage signal line Vref of the first conductive layer 200 through vias.

[0138] Figure 8 A schematic diagram of the structure of the patterned third metal layer provided in this application, such as Figure 8 As shown, the third metal layer M3 of the first pixel circuit structure 121 is symmetrically arranged with the third metal layer M3 of the second pixel circuit structure 122 along the second direction Y. The third metal layer M3 of the third pixel circuit structure 123 is arranged in the same manner as the third metal layer M3 of the first pixel circuit structure 121, and is symmetrically arranged with the third metal layer M3 of the second pixel circuit structure 122 along the second direction Y. Among them, the third metal layer M3 includes a source electrode and a drain electrode forming a TFT, and forms a Scan signal line, etc. Among them, the third metal layer M3 is connected to other metal layers through a via hole. Specifically, the source electrode and the drain electrode forming the TFT are connected to the active layer psi layer through a via hole, which can be referred to. Figure 1 .

[0139] For further information, see Fig. 9 , Fig. 9 This is a schematic diagram of the first stacked structure provided in this application.

[0140] Fig. 9 It is a stacked structure of M0-M3. Fig. 9 As shown, since the metal layers of the first pixel circuit structure 121 and the metal layers of the second pixel circuit structure 122 located below the first conductive layer 200 are symmetrically arranged, the first pixel circuit structure 121 and the second pixel circuit structure 122 are symmetrically arranged along the second direction Y. Similarly, since the metal layers forming the third pixel circuit structure 123 are arranged in the same manner as the metal layers of the first pixel circuit structure 121 and are symmetrically arranged along the second direction Y with the metal layers of the second pixel circuit structure 122, the third pixel circuit structure 123 is arranged in the same manner as the first pixel circuit structure 121 and is symmetrically arranged along the second direction Y with the second pixel circuit structure 122.

[0141] For further information, see Fig.10 , Fig.10 This is a schematic diagram of the second stacked structure provided in this application. Fig.10 The stacked structure includes metal layers M0-M3 and a first conductive layer 200. Fig.10 As shown, the first pixel circuit structure 121 is located directly below the first power supply voltage signal line VDD1 and the first data signal line data1 of the first conductive layer 200, the second pixel circuit structure 122 is located directly below the second power supply voltage signal line VDD2 and the second data signal line data2, and the third pixel circuit structure 123 is located directly below the second power supply voltage signal line VDD2 and the third data signal line data3. In other words, the orthographic projection of the first power supply voltage signal line VDD1 on the substrate 110 at least partially covers the first pixel circuit structure 121. Furthermore, the orthographic projection of the second power supply voltage signal line VDD2 on the substrate 110 at least partially covers the orthographic projection of the second pixel circuit structure 122 on the substrate 110 and the orthographic projection of the third pixel circuit structure 123 on the substrate 110.

[0142] Furthermore, an anode layer 310 is provided on a side of the first conductive layer 200 away from the substrate 110. For details, please refer to Fig.11 , Fig.11 Schematic diagram of the structure of an embodiment of the anode layer of the present application. Fig.11 As shown, the anode layer 310 includes a first anode 301, a second anode 302 and a third anode 303. The region of each pixel unit 30 includes the first anode 301, the second anode 302 and the third anode 303 arranged at intervals. It can be understood that the first anode 301, the second anode 302 and the third anode 303 are the light-emitting regions of the first sub-pixel, the second sub-pixel and the third sub-pixel respectively.

[0143] Preferably, the first anode 301 and the second anode 302 are arranged along the second direction Y, and the third anode 303 and the first anode 301 and the second anode 302 are arranged along the first direction X. Preferably, the upper edge of the third sub-pixel is aligned with the upper edge of the first sub-pixel, and the lower edge is aligned with the lower edge of the second sub-pixel, so that each pixel unit can be arranged in a regular shape.

[0144] Preferably, in the direction of the orthographic projection plane perpendicular to the substrate, the orthographic projections of the first anode 301 and the second anode 302 on the substrate 110 sequentially cover the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2, and the second power supply voltage signal line VDD2. In other words, the orthographic projection of the first anode 301 on the substrate 110 overlaps with the orthographic projections of the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2, and the second power supply voltage signal line VDD2 on the substrate 110; the orthographic projection of the second anode 302 on the substrate 110 overlaps with the orthographic projections of the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2, and the second power supply voltage signal line VDD2 on the substrate 110. Preferably, in the direction along the orthographic projection plane perpendicular to the substrate, the third anode 303 is entirely projected onto the second power supply voltage signal line VDD2, wherein the area of ​​the second power supply voltage signal line VDD2 projected onto the substrate 110 is larger than the area of ​​the third anode 303 projected onto the substrate 110, that is, the orthographic projection of the second power supply voltage signal line VDD2 on the substrate 110 covers the orthographic projection of the third anode 303 on the substrate 110.

[0145] Preferably, on the orthographic projection plane perpendicular to the substrate, the overlapping area between the first anode 301 and the first power supply voltage signal line VDD1 is equal to the overlapping area between the first anode 301 and the second power supply voltage signal line VDD2; the overlapping area between the second anode 302 and the first power supply voltage signal line VDD1 is equal to the overlapping area between the second anode 302 and the second power supply voltage signal line VDD2. That is, the overlapping area of ​​the orthographic projection of the first anode 301 on the substrate and the orthographic projection of the first power supply voltage signal line VDD1 on the substrate (which can be defined as the first overlapping area) and the overlapping area of ​​the orthographic projection of the first anode 301 on the substrate and the orthographic projection of the second power supply voltage signal line VDD2 on the substrate (which can be defined as the second overlapping area) are equal; the overlapping area of ​​the orthographic projection of the second anode 302 on the substrate and the orthographic projection of the first power supply voltage signal line VDD1 on the substrate (which can be defined as the third overlapping area) and the overlapping area of ​​the orthographic projection of the second anode 302 on the substrate and the orthographic projection of the second power supply voltage signal line VDD2 on the substrate (which can be defined as the fourth overlapping area) are equal. Thereby, the first anode 301 is symmetrically arranged along the second direction Y based on the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2 and the second power supply voltage signal line VDD2 of the first conductive layer 200; the second anode 302 is also symmetrically arranged along the second direction Y based on the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2 and the second power supply voltage signal line VDD2 of the first conductive layer 200, thereby improving the display effect of the first sub-pixel and the second sub-pixel and improving color deviation.

[0146] Furthermore, the orthographic projection of the third anode 303 on the substrate 110 is completely located within the orthographic projection of the second power supply voltage signal line VDD2 of the first conductive layer 200 on the substrate 110, which effectively improves display abnormality.

[0147] Preferably, the symmetry axis of the orthographic projection of the first anode 301 on the substrate 110 along the second direction Y coincides with the symmetry axis of the orthographic projection of the second anode 302 on the substrate along the second direction Y. This further improves the color deviation of the first sub-pixel and the second sub-pixel when the display is melted.

[0148] Preferably, the symmetry axis of the orthographic projection of the first anode 301 on the substrate 110 along the second direction Y, the symmetry axis of the orthographic projection of the second anode 302 on the substrate 110 along the second direction Y, and the symmetry axis between the orthographic projection of the first data signal line data1 on the substrate 110 and the orthographic projection of the second data signal line data2 on the substrate 110 coincide with each other. It should be noted that the orthographic projection of the first data signal line data1 on the substrate 110 and the orthographic projection of the second data signal line data2 on the substrate 110 are symmetrical along the second direction Y, and their symmetry axes are located between the first data signal line data1 and the second data signal line data2. That is to say, in the top view projection plane (or perpendicular to the orthographic projection plane), the symmetry axis of the first anode 301, the symmetry axis of the second anode 302, and the symmetry axis between the first data signal line data1 and the second data signal line data2 coincide with each other (three axes coincide with each other).

[0149] Furthermore, the first anode 301 is electrically connected to the first pixel circuit structure 121 located below the first conductive layer 200, the second anode 302 is electrically connected to the second pixel circuit structure 122 located below the first conductive layer 200, and the third anode 303 is electrically connected to the third pixel circuit structure 123 located below the first conductive layer 200.

[0150] Furthermore, the anode layer 310 further includes a first anode wiring 311 connected to the first anode 301, a second anode wiring 312 connected to the second anode 302, and a third anode wiring 313 connected to the third anode 303. Fig.12 , Fig.12 It is a structural schematic diagram of a specific embodiment of the anode layer of the present application.

[0151] Preferably, the first anode wiring 311 is projected on the first power supply voltage signal line VDD1, and is electrically connected to the first pixel circuit structure 121 located below the first power supply voltage signal line VDD1 through a first via hole. Preferably, the positive projection of the first anode 301 on the substrate 110 sequentially covers the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2, and the second power supply voltage signal line VDD2. And the area of ​​the first anode 301 projected on the first power supply voltage signal line VDD1 is equal to the area projected on the second power supply voltage signal line VDD2.

[0152] Preferably, the second anode wiring 312 is projected on the second power supply voltage signal line VDD2, and is electrically connected to the second pixel circuit structure 122 located below the second power supply voltage signal line VDD2 through a second via hole. Preferably, the positive projection of the second anode 302 on the substrate 110 sequentially covers the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2, and the second power supply voltage signal line VDD2. And the area of ​​the second anode 302 projected on the first power supply voltage signal line VDD1 is equal to the area projected on the second power supply voltage signal line VDD2.

[0153] Preferably, along the projection plane direction perpendicular to the substrate, the third anode wiring 313 is projected on the second power supply voltage signal line VDD2, and is electrically connected to the third pixel circuit structure 123 located below the second power supply voltage signal line VDD2 through a third via hole. Preferably, the orthographic projection of the second power supply voltage signal line VDD2 on the substrate 110 covers the orthographic projection of the third anode 303 on the substrate 110.

[0154] Preferably, the materials of the first anode wiring 311 , the second anode wiring 312 and the third anode wiring 313 may be the same as or different from those of the first anode 301 , the second anode 302 and the third anode 303 , which is not limited herein.

[0155] Further, the first via hole, the second via hole, and the third via hole are arranged along the first direction X and are located on the same straight line. This is because the first pixel circuit structure 121, the second pixel circuit structure 122, and the third pixel circuit structure 123 are arranged along the first direction X and are symmetrical along the second direction Y, so that each via hole is also at a corresponding (symmetrical) position in each pixel circuit structure, that is, each via hole is also symmetrically arranged in the second direction Y. Preferably, the first via hole, the second via hole, and the third via hole are located in the non-luminous area of ​​the pixel unit.

[0156] Preferably, the width of the second power supply voltage signal line VDD2 is greater than the width of the first power supply voltage signal line VDD1.

[0157] In this embodiment, the touch signal line is placed after the occupied space of the pixel circuit structure is compressed, so that the touch signal line TP is located between two pixel units, and the data signal line and the touch signal line between two adjacent pixel units are isolated by a fixed voltage signal line Vref, thereby effectively avoiding crosstalk between the data signal line and the touch signal line. Compressing the space of the pixel circuit structure refers to reducing the occupied space of the pixel circuit structure on the substrate plane (that is, the projection plane).

[0158] Furthermore, in the same pixel unit, the first pixel circuit structure and the second pixel circuit structure are designed symmetrically along the Y axis, and the light-emitting areas of the first sub-pixel and the second sub-pixel are symmetrically arranged based on the first pixel circuit structure and the second pixel circuit structure or symmetrically arranged along the Y axis, which can improve the display quality and improve the color deviation. In the same pixel unit, the third pixel circuit structure and the second pixel circuit structure are designed symmetrically along the Y axis, which is consistent with the design of the first pixel circuit structure, and the light-emitting area of ​​the third sub-pixel is symmetrically arranged based on the third pixel circuit structure or symmetrically arranged along the Y axis, which can further improve the display quality and improve the color deviation.

[0159] Furthermore, the present application also provides a display panel, for details, please refer to Fig.13 , Fig.13 FIG. 1 is a schematic diagram of a cross-sectional structure of an embodiment of a display panel of the present application. Fig.13 As shown, the display panel includes: an array substrate 1000, and a pixel unit layer 300 disposed on one side of the array substrate 1000. The array substrate 1000 is the array substrate described in any of the above embodiments.

[0160] The pixel unit layer 300 includes a plurality of pixel units arranged in an array, each pixel unit including a first sub-pixel, a second sub-pixel and a third sub-pixel (not shown in the figure). The first sub-pixel corresponds to the first anode 301, the second sub-pixel corresponds to the second anode 302, and the third sub-pixel corresponds to the third anode. It can be understood that the first sub-pixel includes the first anode 301, the first light-emitting layer, the first cathode and the encapsulation layer stacked in sequence; the second sub-pixel includes the second anode 302, the second light-emitting layer and the second cathode and the encapsulation layer stacked in sequence; the third sub-pixel includes the third anode 303, the third light-emitting layer and the third cathode and the encapsulation layer stacked in sequence, which are not specifically limited here.

[0161] Please refer to Fig.14 , Fig.14 It is a schematic diagram of a top view structure of an embodiment of a display panel of the present application, specifically including a schematic diagram of a top view structure of a pixel unit layer in the display panel.

[0162] The pixel unit layer 300 further includes a pixel definition layer PDL, which covers a portion of the surface of the anode layer 310 and exposes a portion of the surface of the anode layer 310 to form a first anode 301, a second anode 302, and a third anode 303. The first anode 301 is a light-emitting area of ​​a first sub-pixel, the second anode 302 is a light-emitting area of ​​a second sub-pixel, and the third anode 303 is a light-emitting area of ​​a third sub-pixel.

[0163] Preferably, the first anode 301 and the second anode 302 are arranged in parallel and spaced apart along the second direction, and the third anode 303 is arranged in parallel and spaced apart along the first direction with the first anode 301 and the second anode 302 .

[0164] Preferably, the second anode 302 is arranged in alignment with the first anode 301 in the second direction Y, and the third anode 303 is arranged in alignment with the first anode 301 and the second anode 302 in the first direction X. Specifically, the upper edge of the third anode 303 is aligned with the upper edge of the first anode 301, and the lower edge is aligned with the lower edge of the second anode 302, so that each pixel unit can be arranged in a regular shape.

[0165] like Fig.14 As shown, on the vertical projection plane in the stacking direction, the first anode 301 and the second anode 302 are projected on the first data signal line data1, the second data signal line data2, and part of the first power supply voltage signal line VDD1 and part of the second power supply voltage signal line VDD2. The third anode 303 is fully projected on the second power supply voltage signal line VDD2.

[0166] Preferably, the projection area of ​​the first anode 301 and the second anode 302 projected on the first power supply voltage signal line VDD1 is symmetrical with the projection area projected on the second power supply voltage signal line VDD2 along the second direction Y. That is to say, the projection area of ​​the first anode 301 projected on the first power supply voltage signal line VDD1 is the same as the projection area projected on the second power supply voltage signal line VDD2, and the projection area of ​​the second anode 302 projected on the first power supply voltage signal line VDD1 is the same as the projection area projected on the second power supply voltage signal line VDD2. Moreover, the widths of the first data signal line data1 and the second data signal line data2 are also set in the same way, so that the light emission center of the first anode 301 and the second anode 302 can be located between the first data signal line data1 and the second data signal line data2. In addition, the first anode 301 and the second anode 302 are symmetrically arranged along the second direction Y, which can improve the display quality and improve the display color deviation.

[0167] In this embodiment, the third anode 303 is entirely located on the second power supply voltage signal line VDD2. Therefore, the third anode 303 is also symmetrically arranged based on the second power supply voltage signal line VDD2 or symmetrically arranged along the Y axis, thereby improving the display quality of the third sub-pixel and improving the display color deviation.

[0168] In this embodiment, preferably, the width of the second power supply voltage signal line VDD2 in the first direction X is greater than the width of the first power supply voltage signal line VDD1 in the first direction X. Thus, the third anode 303 and part of the first anode 301 and the second anode 302 can be projected onto the second power supply voltage signal line VDD2.

[0169] Preferably, the first sub-pixel is a red sub-pixel R, the second sub-pixel is a green sub-pixel G, and the third sub-pixel is a blue sub-pixel B.

[0170] See also Fig.15 , Fig.15 This is a schematic diagram of a top view of an embodiment of the second conductive layer provided in this application. Fig.15 As shown, the pixel unit layer 300 includes a pixel definition layer PDL, and a second conductive layer 320 arranged on a side of the pixel definition layer PDL away from the anode layer 310. The second conductive layer 320 includes a first partition structure TP-s and a second partition structure VSS. The first partition structure TP-s and the second partition structure VSS are insulated. Preferably, on the top projection plane, the first partition structure TP-s and the second partition structure VSS are spaced apart.

[0171] The first partition structure TP-s is used for transmitting touch signals or sensing touch signals, and the second partition structure VSS is used for transmitting cathode voltage signals.

[0172] Preferably, the first partition structure TP-s and the second partition structure VSS have the same cross-sectional shape, such as Fig.13 In other embodiments, the configuration may be different and is not limited here.

[0173] The first partition structure TP-s includes a first touch electrode TP-s1 arranged along a first direction X and a second touch electrode TP-s2 arranged along a second direction Y. The first touch electrode TP-s1 and the second touch electrode TP-s2 are electrically connected to each other to form a touch electrode block whose touch range covers (or encompasses) a plurality of pixel units.

[0174] Preferably, the orthographic projection of the second touch electrode TP-s2 on the substrate at least covers a portion of the orthographic projection of the touch signal line TP on the substrate, that is, the orthographic projection of the second touch electrode TP-s2 on the substrate at least partially overlaps with the orthographic projection of the touch signal line TP on the substrate. Thus, the second touch electrode TP-s2 located in the second conductive layer 320 and the touch signal line TP located in the first conductive layer 200 can be connected to the touch signal through the vertical via hole for transmitting the touch signal.

[0175] Preferably, the orthographic projection of the second touch electrode TP-s2 on the substrate can also extend in the direction of the orthographic projection of the fixed voltage signal line Vref and the power voltage signal line VDD adjacent to the touch signal line TP on the substrate, and partially overlap with the orthographic projection of the fixed voltage signal line Vref and the power voltage signal line VDD on the substrate, that is, the second touch electrode TP-s2 can extend along the first direction X, thereby expanding the width of the second touch electrode TP-s2 in the first direction X, and also expanding the touch coverage of the first partition structure TP-s. It should be noted that, in order to further avoid signal crosstalk between the data signal line data and the touch signal line TP, preferably, the orthographic projection of the second touch electrode TP-s2 on the substrate does not overlap with the orthographic projection of the data signal line data on the substrate.

[0176] Preferably, the orthographic projection of the first touch electrode TP-s1 on the substrate 110 overlaps with the orthographic projections of the first power supply voltage signal line VDD1, the first data signal line data1, the second data signal line data2, the second power supply voltage signal line VDD2, the third data signal line data3 and the fixed voltage signal line Vref on the substrate 110 in sequence. Compared with the prior art, the first touch electrode TP-s1 only needs to cross two power supply voltage signal lines, while in the prior art, the first touch electrode TP-s1 needs to cross three power supply voltage signal lines.

[0177] The second partition structure VSS is also disposed on the surface of the pixel definition layer PDL away from the anode layer 310 . The second partition structure VSS includes a first cathode voltage signal line VSS1 and a second cathode voltage signal line VSS2 .

[0178] Preferably, the first partition structure TP-s is arranged on the surface of the pixel definition layer PDL, and is located in the same layer as the second partition structure VSS and is arranged at intervals. The first partition structure TP-s is arranged on the side of the second partition structure VSS away from the pixel unit. The pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel, that is, arranged around the outer periphery of the pixel unit.

[0179] Furthermore, the first cathode voltage signal line VSS1 surrounds each pixel unit and surrounds the first sub-pixel, the second sub-pixel and the third sub-pixel in each pixel unit. The second cathode voltage signal line VSS2 extends along the first direction X and connects the first cathode voltage signal lines VSS1 in two adjacent pixel units arranged along the first direction X.

[0180] Preferably, the first isolation structure TP-s is arranged around the first cathode voltage signal line VSS1. The second touch electrode TP-s2 arranged along the second direction Y is isolated by the second cathode voltage signal line VSS2 arranged along the first direction X, that is, the second touch electrode TP-s2 is disconnected at a position close to the second auxiliary cathode VSS2, so that the first isolation structure TP-s and the second isolation structure VDD are insulated and arranged for transmitting different signals. Preferably, the first isolation structure TP-s and the second isolation structure VDD are filled with an insulating packaging layer to achieve insulation, which is not limited here. Furthermore, the second touch electrode TP-s2 isolated by the second cathode voltage signal line VSS2 can achieve signal connection through the touch signal line TP located in the first conductive layer 200, thereby realizing touch signal connection between multiple pixel units included in the same touch electrode block.

[0181] Preferably, the partition structure (the first partition structure and / or the second partition structure) includes a first metal layer and a second metal layer, and the second metal layer is arranged on the surface of the first metal layer and has a larger area than the first metal layer, thereby forming a partition structure.

[0182] The partition structure is described in patents 202311222756.6, 202311451935.7, 202311110881.8, and 202311596673.3 for reference.

[0183] The cathode of the pixel can be connected through the side wall of the first metal layer of the second partition structure, and the pixel cathodes in two adjacent sub-pixels or two adjacent pixel units are connected through the first metal layer of the second partition structure, thereby realizing the connection of the entire cathode surface, which is not limited here. In this embodiment, at least the pixel cathodes of the pixel units in the same row are connected through the second partition structure. Specifically, part of the second partition structure can also pass through the second touch electrode TP-s2, and the second touch electrode TP-s2 can be disconnected here, so as to realize the connection of the pixel cathodes of the pixel units in two adjacent columns, thereby realizing the connection of the entire surface of the pixel cathode, which is not limited here.

[0184] It should be noted that the touch electrode TP-s may be a self-capacitive capacitive touch electrode.

[0185] The present application also provides a method for manufacturing an array substrate, and the array substrate in any of the above embodiments is manufactured using the method. Fig.16 , Fig.16 This is a flow chart of an embodiment of a method for manufacturing an array substrate provided in the present application. The method comprises:

[0186] Step S11: providing a substrate.

[0187] Step S12: forming a patterned first conductive layer on one side of the substrate.

[0188] The first conductive layer includes a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, and the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines. The first direction intersects the second direction. Figure 2 .

[0189] The present application also provides a method for manufacturing a display panel, and the display panel in any of the above embodiments is manufactured using the manufacturing method. Fig.17 , Fig.17 This is a flow chart of an embodiment of a method for manufacturing a display panel provided in the present application. The method comprises:

[0190] Step S21: providing a substrate.

[0191] Step S22: forming a patterned first conductive layer on one side of the substrate.

[0192] The first conductive layer includes a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, and the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines. The first direction intersects the second direction. Figure 2 .

[0193] Step S23: forming a patterned pixel unit layer on a side of the first conductive layer away from the substrate.

[0194] The pixel unit layer includes a plurality of pixel units arranged in an array, and each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel.

[0195] The beneficial effects of the present application are as follows: in the In Cell touch architecture, the space occupied by the pixel circuit structure on the substrate plane is reduced, the touch signal line is placed between two pixel units, and the signal crosstalk between the touch signal line and the data signal line is isolated by a fixed voltage signal line, which can reduce the electrical signal interference between the display signal and the touch signal, thereby improving the display performance and touch performance of the display panel. In the second aspect, in the same pixel, the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel are designed symmetrically along the Y axis, and the light-emitting areas of the first sub-pixel and the second sub-pixel are symmetrically arranged based on the pixel driving circuit or symmetrically arranged along the Y axis, which can effectively improve the color deviation and improve the display quality. In the third aspect, in the same pixel, the pixel driving circuit of the third sub-pixel and the pixel driving circuit of the second sub-pixel are symmetrically designed along the Y axis, which is consistent with the pixel circuit structure design of the first sub-pixel, and the light-emitting area of ​​the third sub-pixel is symmetrically arranged based on the pixel driving circuit of the third sub-pixel or symmetrically arranged along the Y axis, which improves the color deviation and improves the display quality.

[0196] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; a first conductive layer disposed on one side of the substrate, the first conductive layer comprising a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, the fixed voltage signal lines being disposed between the data signal lines and the touch signal lines; The first direction intersects the second direction.

2. The array substrate according to claim 1, characterized in that: The fixed voltage signal line is located between the adjacent data signal line and the touch signal line, and is used to form a signal shield between the data signal line and the touch signal line.

3. The array substrate according to claim 1, characterized in that: The first conductive layer further comprises a plurality of power supply voltage signal lines extending along the second direction and arranged along the first direction, wherein the power supply voltage signal lines comprise a first power supply voltage signal line and a second power supply voltage signal line; And / or, the data signal line includes a first data signal line, a second data signal line and a third data signal line; And / or, the touch signal line includes a first touch signal line and a second touch signal line; Preferably, the first data signal line and the second data signal line are located between the first power supply voltage signal line and the second power supply voltage signal line; Preferably, the first power supply voltage signal line, the first data signal line, the second data signal line, and the second power supply voltage signal line are arranged in sequence along the first direction; Preferably, the first touch signal line, the fixed voltage signal line, and the third data signal line are sequentially arranged on a side of the first power voltage signal line away from the second power voltage signal line; Preferably, the first touch signal line is located between the fixed voltage signal line and the first power supply voltage signal line; and / or, The third data signal line, the fixed voltage signal line, and the second touch signal line are sequentially arranged on a side of the second power supply voltage signal line away from the first power supply voltage signal line; Preferably, the third data signal line is located between the fixed voltage signal line and the second power supply voltage signal line; Preferably, the second touch signal line, the fixed voltage signal line, and the third data signal line are sequentially arranged on a side of the first power supply voltage signal line away from the second power supply voltage signal line; Preferably, the second touch signal line is located between the fixed voltage signal line and the first power supply voltage signal line; and / or, Preferably, the third data signal line, the fixed voltage signal line, and the first touch signal line are sequentially arranged on a side of the second power supply voltage signal line away from the first power supply voltage signal line; Preferably, the third data signal line is located between the fixed voltage signal line and the second power supply voltage signal line.

4. The array substrate according to claim 1, characterized in that: A pixel circuit layer is provided between the substrate and the first conductive layer, and the pixel circuit layer includes a first pixel circuit structure, a second pixel circuit structure and a third pixel circuit structure; Preferably, the first pixel circuit structure, the second pixel circuit structure, and the third pixel circuit structure are arranged in sequence along the first direction; Preferably, the second pixel circuit structure is symmetrically arranged with the first pixel circuit structure along the second direction; the third pixel circuit structure is symmetrically arranged with the second pixel circuit structure along the second direction, and is arranged the same as the first pixel circuit structure.

5. The array substrate according to claim 3, characterized in that: A pixel circuit layer is provided between the substrate and the first conductive layer, and the pixel circuit layer includes a first pixel circuit structure, a second pixel circuit structure and a third pixel circuit structure; The first pixel circuit structure is electrically connected to the first data signal line, the second pixel circuit structure is electrically connected to the second data signal line, and the third pixel circuit structure is electrically connected to the third data signal line; Preferably, the first pixel circuit structure, the second pixel circuit structure, and the third pixel circuit structure are arranged in sequence along the first direction; Preferably, the second pixel circuit structure is symmetrically arranged with the first pixel circuit structure along the second direction; the third pixel circuit structure is symmetrically arranged with the second pixel circuit structure along the second direction, and is arranged in the same manner as the first pixel circuit structure; Preferably, the orthographic projection of the first power supply voltage signal line on the substrate at least partially covers the orthographic projection of the first pixel circuit structure on the substrate; and / or, The orthographic projection of the second power supply voltage signal line on the substrate at least partially covers the orthographic projection of the second pixel circuit structure on the substrate and the orthographic projection of the third pixel circuit structure on the substrate.

6. The array substrate according to claim 3, characterized in that: An anode layer is provided on a side of the first conductive layer away from the substrate, and the anode layer includes a first anode, a second anode and a third anode; Preferably, the first anode and the second anode are arranged along the second direction, and the third anode, the first anode and the second anode are arranged along the first direction; Preferably, an orthographic projection of at least one of the first anode and the second anode on the substrate overlaps with an orthographic projection of the first power supply voltage signal line on the substrate, an orthographic projection of the first data signal line on the substrate, an orthographic projection of the second data signal line on the substrate, and an orthographic projection of the second power supply voltage signal line on the substrate; Preferably, an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is equal to an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate; Preferably, an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is equal to an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate; Preferably, the symmetry axis of the orthographic projection of the first anode on the substrate along the second direction coincides with the symmetry axis of the orthographic projection of the second anode on the substrate along the second direction; Preferably, the orthographic projection of the second power supply voltage signal line on the substrate covers the orthographic projection of the third anode on the substrate; Preferably, the width of the second power supply voltage signal line is greater than the width of the first power supply voltage signal line.

7. The array substrate according to claim 5, characterized in that: An anode layer is provided on a side of the first conductive layer away from the substrate, and the anode layer includes a first anode, a second anode and a third anode; The first anode is electrically connected to the first pixel circuit structure, the second anode is electrically connected to the second pixel circuit structure, and the third anode is electrically connected to the third pixel circuit structure; Preferably, the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of the first power supply voltage signal line on the substrate, the orthographic projection of the first data signal line on the substrate, the orthographic projection of the second data signal line on the substrate, and the orthographic projection of the second power supply voltage signal line on the substrate; Preferably, an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is equal to an overlapping area of ​​an orthographic projection of the first anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate; Preferably, the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the first power supply voltage signal line on the substrate, the orthographic projection of the first data signal line on the substrate, the orthographic projection of the second data signal line on the substrate, and the orthographic projection of the second power supply voltage signal line on the substrate; Preferably, an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the first power supply voltage signal line on the substrate is the same as an overlapping area of ​​an orthographic projection of the second anode on the substrate and an orthographic projection of the second power supply voltage signal line on the substrate; Preferably, the orthographic projection of the second power supply voltage signal line on the substrate covers the orthographic projection of the third anode on the substrate; Preferably, the symmetry axis of the orthographic projection of the first anode on the substrate along the second direction, the symmetry axis of the orthographic projection of the second anode on the substrate along the second direction, and the symmetry axis between the orthographic projection of the first data signal line on the substrate and the orthographic projection of the second data signal line on the substrate coincide with each other; Preferably, the width of the second power supply voltage signal line is greater than the width of the first power supply voltage signal line.

8. A display panel, characterized in that: The display panel comprises: The array substrate according to any one of claims 1 to 7; A pixel unit layer, disposed on one side of the array substrate, the pixel unit layer comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a first sub-pixel, a second sub-pixel and a third sub-pixel; The first sub-pixel corresponds to the first anode, the second sub-pixel corresponds to the second anode, and the third sub-pixel corresponds to the third anode.

9. The display panel according to claim 8, characterized in that: The first sub-pixel and the second sub-pixel are arranged along the second direction, and the third sub-pixel, the first sub-pixel and the second sub-pixel are arranged along the first direction; Preferably, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

10. The display panel according to claim 8, characterized in that: The array substrate comprises a touch signal line, wherein an orthographic projection of the touch signal line on the substrate is located between orthographic projections of two adjacent pixel units on the substrate along a first direction; Preferably, the touch signal line comprises a first touch signal line and a second touch signal line, and an orthographic projection of the first touch signal line on the substrate and an orthographic projection of the second touch signal line on the substrate are arranged alternately.

11. The display panel according to claim 8, characterized in that: The pixel unit layer comprises: A pixel definition layer is disposed on a side of the anode layer away from the first conductive layer and covers a portion of the surface of the anode layer; A second conductive layer is disposed on a surface of the pixel definition layer away from the anode layer, the second conductive layer comprising a first partition structure and a second partition structure, the first partition structure is insulated from the second partition structure; Preferably, the first partition structure is used to transmit a touch signal, and the second partition structure is used to transmit a cathode voltage signal.

12. The display panel according to claim 11, characterized in that: The first partition structure includes a first touch electrode arranged along a first direction and a second touch electrode arranged along a second direction, and the first touch electrode is electrically connected to the second touch electrode; Preferably, the orthographic projection of the second touch electrode on the substrate at least covers a portion of the orthographic projection of the touch signal line on the substrate; Preferably, the orthographic projection of the second touch electrode on the substrate does not overlap with the orthographic projection of the data signal line on the substrate; Preferably, the orthographic projection of the first touch electrode on the substrate overlaps with the orthographic projections of the first power supply voltage signal line, the first data signal line, the second data signal line, the second power supply voltage signal line, the third data signal line and the fixed voltage signal line on the substrate in sequence.

13. The display panel according to claim 12, characterized in that: The second partition structure includes a first cathode voltage signal line and a second cathode voltage signal line, and the first cathode voltage signal line is electrically connected to the second cathode voltage signal line; Preferably, the first cathode voltage signal line is arranged around the pixel unit and around the first sub-pixel, the second sub-pixel and the third sub-pixel in the pixel unit, and the second cathode voltage signal line is electrically connected to two adjacent first cathode voltage signal lines along the first direction; Preferably, the first partition structure is disposed around the first cathode voltage signal line, wherein the second touch electrode is partitioned by the second cathode voltage signal line.

14. A method for manufacturing an array substrate, characterized in that: The production method comprises: providing a substrate; A patterned first conductive layer is made on one side of the substrate; wherein the first conductive layer includes a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, and the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines; the first direction intersects with the second direction.

15. A method for manufacturing a display panel, characterized in that: The production method comprises: providing a substrate; A patterned first conductive layer is formed on one side of the substrate; wherein the first conductive layer comprises a plurality of data signal lines, touch signal lines and fixed voltage signal lines extending along the second direction and arranged along the first direction, the fixed voltage signal lines are arranged between the data signal lines and the touch signal lines; the first direction intersects with the second direction; Fabricating a patterned pixel unit layer on a side of the first conductive layer away from the substrate; The pixel unit layer includes a plurality of pixel units arranged in an array, and each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel.

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