Storage device, media interface device of storage device, and operating method of media interface device

Abstract

There is provided a memory device including: a plurality of non-volatile memory devices; a host interface device configured to communicate with an external host device through the interface channel; and at least one media interface device connected between the host interface device and the plurality of non-volatile memory devices, the at least one media interface device configured to control the plurality of non-volatile memory devices, the at least one media interface device is further configured to perform an operation offloaded from the host interface device and perform serial communication with the host interface device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0147152 filed on October 30, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments relate to a storage device, and more particularly, to a storage device, a media interface device of the storage device, and an operating method of the media interface device. Background Art

[0003] Semiconductor memories are classified into volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM), which lose stored data when power is cut off, and nonvolatile memory devices such as flash memory devices, phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM), which retain stored data even when power is cut off. The memory controller of the memory device may include a media interface having a multi-channel structure, and pad limitations may occur as semiconductors become more integrated and miniaturized. Summary of the invention

[0004] One or more embodiments provide a media interface device in which some functions of a storage controller are offloaded, an operating method of the media interface device, and a storage device including the media interface device.

[0005] According to one aspect of the embodiment, there is provided a storage device, comprising: a plurality of non-volatile storage devices; a host interface device configured to communicate with an external host device through an interface channel; and at least one media interface device connected between the host interface device and the plurality of non-volatile storage devices, the at least one media interface device being configured to control the plurality of non-volatile storage devices, wherein the at least one media interface device is further configured to perform operations unloaded from the host interface device and to perform serial communications with the host interface device.

[0006] According to another aspect of the embodiment, a system is provided, comprising a plurality of non-volatile memory devices and a media interface device, the media interface device comprising: a first interface circuit configured to connect to an external host interface device to operate as a storage device; a second interface circuit configured to connect to the plurality of non-volatile memory devices; and a processing circuit configured to perform operations unloaded from the host interface device, wherein the first interface circuit is also configured to perform serial communication with the host interface device.

[0007] According to another aspect of the embodiment, there is provided an operating method of a media interface device, wherein the media interface device is connected between a host interface device and a plurality of non-volatile memory devices, the host interface device being configured to communicate with an external host device, and the media interface device being configured to control the plurality of non-volatile memory devices, the operating method comprising: receiving a first command from the host interface device, wherein a plurality of host commands of the external host device are serialized; deserializing the first command to generate a plurality of second commands; performing an operation of unloading from the host interface device on the plurality of second commands to generate a plurality of third commands; and transmitting the plurality of third commands to the plurality of non-volatile memory devices, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating a host-storage system according to an embodiment;

[0010] Figure 2 is a block diagram illustrating a host-storage system according to a related example;

[0011] Figure 3 is a block diagram showing a substrate of a storage controller according to a related example;

[0012] Figure 4 is a block diagram showing a substrate of a storage device according to a related example;

[0013] Figure 5 is a block diagram showing a substrate of a storage device according to an embodiment;

[0014] Figure 6 It shows Figure 1 Detailed block diagram of the host-storage system;

[0015] Figure 7 is a block diagram showing a SerDes according to an embodiment;

[0016] Fig. 8A It shows Figure 6 A detailed block diagram of the Error Correction Code (ECC) engine;

[0017] Figure 8B It shows Figure 6 A detailed block diagram of the Advanced Encryption Standard (AES) engine;

[0018] Fig. 9 is a block diagram showing a storage device according to an embodiment;

[0019] Fig.10is a flowchart illustrating an operating method of a host-storage system according to an embodiment;

[0020] Fig.11 is a flow chart illustrating a method of operating a media interface device according to an embodiment;

[0021] Fig. 12A and Fig. 12B is a block diagram showing a packaging form of a media interface device according to an embodiment;

[0022] Fig.13 is a block diagram illustrating a system including a storage device according to an embodiment;

[0023] Fig.14 is a block diagram illustrating a data center including a storage device according to an embodiment; and

[0024] Fig.15 is a cross-sectional view showing a BVNAND structure applicable to a memory device according to an embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto.

[0026] It will be understood that although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and / or parts (collectively referred to as "elements"), these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, a first element described in the specification section may be referred to as a second element in the claims section, and vice versa.

[0027] It will be understood that when an element or layer is referred to as being "on," "over," "up," "below," "under," "below," "connected to," or "coupled to" another element or layer, it can be directly on, over, over, under, under, below, directly connected to or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "over," "up," "below," "under," "below," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0028] As used herein, the expression "at least one of..." follows a list of elements and modifies the entire list of elements rather than the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0029] Figure 1 is a block diagram showing a host-storage system 10 according to an embodiment.

[0030] Reference Figure 1 , the host-storage system 10 may include a host 100 and a storage device 300. The storage device 300 may include a host interface device 310, at least one media interface device 320 and 330, and a non-volatile memory (NVM) device 340. The storage device 300 may include a storage medium for storing data according to a request from the host 100. Figure 2 Detailed operations of the host 100 and the storage device 300 are described in detail.

[0031] The host interface device 310 and at least one media interface device 320 and 330 may perform a storage controller operation of the storage device. The storage controller may be provided inside the storage device 300, and may perform a series of processes for storing data according to a request received by the storage device from the host 100. For example, the host interface portion inside the storage controller may be configured as the host interface device 310, and the media interface portion inside the storage controller may be configured as at least one media interface device 320 and 330, respectively. Figure 1 An example in which two media interface devices are provided is shown, but the embodiment is not limited thereto. Although the NVM device 340 is shown as a single block, a plurality of NVM devices 340 may be provided. At least one media interface device 320 and 330 may be connected to a plurality of NVM devices. Figure 5 and Figure 6 A storage device including a host interface device 310 and media interface devices 320 and 330 is described in detail.

[0032] Figure 2 is a block diagram showing a host-storage system 10 according to a related example.

[0033] The host-storage system 10 may include a host 100 and a storage device 200. In addition, the storage device 200 may include a storage controller 210 and an NVM 220. In addition, according to an embodiment, the host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory for temporarily storing data to be transmitted to or from the storage device 200.

[0034] The storage device 200 may include a storage medium for storing data according to a request from the host 100. As an example, the storage device 200 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device that complies with the non-volatile memory express (NVMe) standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the universal flash memory (UFS) or embedded multimedia card (eMMC) standard. The host 100 and the storage device 200 may each generate and transmit data packets according to the adopted standard protocol.

[0035] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of non-volatile memory. For example, the storage device 200 may include MRAM, spin transfer torque MRAM, conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), PRAM, RRAM, and various other types of memory.

[0036] According to an embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. According to another embodiment, in some embodiments, the host controller 110 and the host memory 120 may be integrated into the same semiconductor chip. As an example, the host controller 110 may be one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory provided in the application processor, or may be an NVM or a memory module located outside the application processor.

[0037] The host controller 110 may manage an operation of storing data of the buffer (eg, write data) in the NVM 220 or storing data of the NVM 220 (eg, read data) in the buffer.

[0038] The storage controller 210 may include a host interface (I / F) 211, a memory I / F 212, and a central processing unit (CPU) 213. In addition, the storage controller 210 may further include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) 218. The storage controller 210 may also include a working memory loaded with the FTL 214, and may control data write and read operations to the NVM 220 when the CPU 213 executes the FTL 214.

[0039] The host I / F 211 may transmit and receive data packets to and from the host 100. The data packets transmitted from the host 100 to the host I / F 211 may include commands or data to be written to the NVM 220, and the data packets transmitted from the host I / F 211 to the host 100 may include responses to commands or data read from the NVM 220. The memory I / F 212 may transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory I / F 212 may be implemented to comply with a standard protocol such as Toggle or ONFI.

[0040] The FTL 214 may perform several operations such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of changing a logical address received from the host 100 to a physical address for storing data in the NVM 220. Wear leveling is a technique for preventing excessive damage to a particular block by ensuring that the blocks in the NVM 220 are uniformly used, and may be implemented by, for example, a firmware technique that balances the erase counts of physical blocks. Garbage collection is a technique for ensuring available capacity in the NVM 220 by copying valid data of a block to a new block and then erasing the existing block.

[0041] The packet manager 215 may generate a packet according to the protocol of the I / F negotiated with the host 100, or parse various information in a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be written to or read from the NVM 220. The buffer memory 216 may be provided in the storage controller 210, or may be located outside the storage controller 210.

[0042] The ECC engine 217 may perform error detection and correction operations on the read data read from the NVM 220. For example, the ECC engine 217 may generate parity bits for the write data to be written to the NVM 220, and store the generated parity bits together with the write data in the NVM 220. When reading data from the NVM 220, the ECC engine 217 may use the parity bits read from the NVM 220 together with the read data to correct errors in the read data, and output the error-corrected read data.

[0043] The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 210 using a symmetric key algorithm.

[0044] Figure 3 is a block diagram showing a memory controller substrate 500 according to a related example.

[0045] Reference Figure 3 , the storage controller substrate 500 may include a host physical layer (PHY) 510 at the edge, a buffer PHY 520, and a plurality of media PHYs 531, 532, 533, 534, 535, 536, 537, and 538. The storage controller substrate 500 may represent a substrate on which the above-mentioned Figure 2 The storage controller 210 of the substrate. Each PHY is a physical layer and can be connected to an external device as a physical connection terminal. For example, the host PHY 510 can be connected to an external host device, and the buffer PHY 520 can be connected to various elements such as an external DRAM and PRAM. Figure 3 In the storage controller substrate 500 of FIG. 5 , the central circuit wiring is omitted to focus on the pads at the edge of the substrate, but multiple wirings may be located in the center, and the PHY of the pad portion may be arranged in a different manner. Figure 3 , eight media PHYs 531 to 538 are shown, but this is exemplary and a different number of media PHYs may be formed on the pads.

[0046] The memory controller substrate 500 is a substrate created during the physical manufacturing of semiconductor devices, and as semiconductor structures become more integrated and miniaturized, the size of the memory controller substrate 500 can be made smaller. Therefore, the pad area present at the edge of the memory controller substrate 500 can also be reduced. The PHY used for physical connection may have limitations in reducing its size. Therefore, Figure 3The pads of the memory controller substrate 500 shown may be saturated, thus reaching the pad limit. Therefore, the additional PHY may not be located on the pads of the memory controller substrate 500. When the PHY for physical connection is located in the center of the substrate, the PHY may need to be sufficiently fixed on the pad because electrical connection cannot be made on a plane.

[0047] Figure 4 is a block diagram illustrating a substrate of a storage device 600 according to a related example.

[0048] For example, Figure 4 Shows Figure 3 The storage controller substrate 500 of FIG. 5 is connected to a plurality of NVM devices 610 to form an example of a storage device 600. The plurality of NVM devices 610 may correspond to the NVM devices 610 described above. Figure 2 The NVM device 220 described in the above description may also be referred to as a storage device, a medium, etc. Reference is omitted. Figure 3 Redundant description about the storage controller substrate 500.

[0049] The storage controller substrate 500 located inside the storage device 600 may be electrically connected to the media PHYs 531 , 532 , 533 , 534 , 535 , 536 , 537 , and 538 , and the NVM device 610 . Figure 4 The connection form shown is an example, and the number of PHYs and the number of NVM devices 610 are not limited thereto.

[0050] For example, the first group of NVM devices 531_1 to 531_4 may be electrically connected to the first media PHY 531, and the eighth group of NVM devices 538_1 to 538_4 may be electrically connected to the eighth media PHY 538. Each of the media PHYs 531 to 538 may be connected to a specific number of NVM devices. The storage controller substrate 500 may transmit data corresponding to a command received from an external host to the NVM device 610 through the media PHYs 531 to 538.

[0051] Figure 5 is a block diagram illustrating a substrate of a storage device 700 according to an embodiment.

[0052] Reference Figure 5 The storage device 700 may include a host I / F circuit substrate 710, a first media I / F circuit substrate 720, a second media I / F circuit substrate 730, and a plurality of NVM devices 740. The host I / F circuit substrate 710, the first media I / F circuit substrate 720, and the second media I / F circuit substrate 730 may represent the above-mentioned circuit substrates manufactured thereon. Figure 1The plurality of NVM devices 740 may represent a host I / F device 310 and a substrate of at least one media I / F device 320 and 330. Figure 1 NVM device 340 or Figure 4 NVM device 610. Reference is omitted Figure 1 and Figure 4 A redundant description of storage device 700.

[0053] The host I / F circuit substrate 710 may include a host PHY 711, a buffer PHY 712, and a host serializer-deserializer (SerDes) PHY 713. The host PHY 711 and the buffer PHY 712 may correspond to Figure 3 The host PHY 510 and the buffer PHY 520 of the first media I / F circuit substrate 720 may include a first media SerDes PHY 721 and a plurality of media PHYs 722 to 725. Similarly, the second media I / F circuit substrate 730 may include a second SerDes PHY 731 and a plurality of media PHYs 732 to 735. The media PHYs 722 to 725 and 732 to 735 may correspond to Figure 3 The host SerDes PHY 713 can configure the SerDes with the first media SerDes PHY 721 and the second media SerDes PHY 731 to transmit data. Details of the SerDes will be described below. Figure 7 Detailed description.

[0054] The host I / F circuit substrate 710, the first media I / F circuit substrate 720, and the second media I / F circuit substrate 730 communicate via a SerDes connection, and can be generally viewed as Figure 3 For example, Figure 1 The host I / F device 310 and at least one media I / F device 320 and 330 may perform Figure 2 The media PHYs 722 to 725 and 732 to 735 may be connected to the NVM device 740, and reference to the NVM device 740 is omitted. Figure 4 Redundant description of this aspect.

[0055] To solve Figure 3 and Figure 4 The pad limitation problem of the memory controller 500 can be configured separately Figure 5The host I / F circuit substrate 710, the first media I / F circuit substrate 720, and the second media I / F circuit substrate 730 are provided. Data can be transmitted through the SerDes connection between the host I / F circuit substrate 710, the first media I / F circuit substrate 720, and the second media I / F circuit substrate 730, but the media PHY (a portion requiring multiple PHYs) is located in the media I / F circuit substrates 720 and 730, thereby solving the pad limitation problem of the substrate. In addition, the number of I / F circuit substrates and the number of media PHYs can be flexible, and since the pad limitation is eliminated, flexible circuit design can be achieved.

[0056] Since the host I / F circuit board 710 processes commands from the host and executes the above reference Figure 2 The various operations described above may therefore require relatively high-speed data processing, and for this purpose, the host I / F circuit substrate may need to be produced by an advanced process. In contrast, the media I / F circuit substrates 720 and 730 that mainly perform operations of exchanging data with the NVM device 700 may not require relatively high-speed data processing, and it may be effective to produce the media I / F circuit substrates 720 and 730 by a cost-effective mature process. Therefore, according to the above-mentioned embodiment, by reflecting the fineness of the processes required for the host I / F device and the media I / F device, respectively, the yield of circuit manufacturing can be improved and the production cost can be reduced.

[0057] Figure 6 is shown in more detail Figure 1 A block diagram of a host-storage system 10 is shown.

[0058] Reference Figure 6 , the host-storage system 10 may include a host 100 and a storage device 300. The storage device 300 may include a host interface device 310, at least one media interface device 320 and 330, and an NVM device 340. Reference is omitted Figure 1 and Figure 2 A redundant description of the host-storage system 10.

[0059] The host I / F device 310 may include a host I / F 311, a host SerDes I / F 312, a packet manager 315, and a CPU 313. The host I / F 311 may communicate with the host 100 to exchange data, and the host SerDes I / F 312 may be connected to the first media SerDes I / F 321 and the second media SerDes I / F 331 in a SerDes manner to exchange data. Figure 5 and Figure 7 Redundant description of SerDes.

[0060] The first media I / F device 320 may include a first media SerDes I / F 321 and a first memory I / F 322, and the second media I / F device 330 may include a second media SerDes I / F 331 and a second memory I / F 332. The first memory I / F 322 and the second memory I / F 332 may communicate with the NVM device 340 to exchange data.

[0061] The first memory I / F 322 and the second memory I / F 332 may communicate through a frequency boosting I / F (FBI) method. For example, the first memory I / F 322 and the second memory I / F 332 may include FBI. The FBI method may increase the signal transmission rate by reducing the capacitance effect of the input / output port of the NVM device. For example, the FBI method may electrically separate the input / output port of each NVM device using a switching circuit unit (such as a multiplexer). Therefore, by reducing the capacitance effect of the input / output port of the NVM device, the signal transmission rate may be increased.

[0062] In some cases, the host I / F device 310 may further include an FTL 314, buffer memories 324 and 334, an ECC engine 317, and an AES engine 318. The FTL 314, the buffer memory 316, the ECC engine 317, and the AES engine 318 may correspond to the FTL 214, the buffer memories 324 and 334, the ECC engine 217, and the AES engine 218.

[0063] In addition, the first media I / F device 320 may further include an FTL 323, a buffer memory 324, an ECC engine 325, and an AES engine 326 in some cases, and the second media I / F device 330 may further include an FTL 333, a buffer memory 334, an ECC engine 335, and an AES engine 336 in some cases. The FTLs 323 and 333, the buffer memories 324 and 334, the ECC engines 325 and 335, and the AES engines 326 and 336 may correspond to the FTL 214, the buffer memory 216, the ECC engine 217, and the AES engine 218.

[0064] The first media I / F device 320 and the second media I / F device 330 may perform an operation of uninstalling from the host I / F device 310 on behalf of the host I / F device 310. Figure 2Unlike the storage controller 210 of the host I / F device 310, the FTL, the buffer memory, the ECC engine, and the AES engine can be respectively performed by the host I / F device 310 and the media I / F devices 320 and 330. For example, the host I / F device 310 may include the FTL 314, the buffer memories 324 and 334, and the AES engine 318, and the first media I / F device 320 and the second media I / F device 330 may include the ECC engines 325 and 335. The offloading does not necessarily have to be selectively present in only one location, and the host I / F device 310, the first media I / F device 320, and the second media I / F device 330 can all perform the operation. For example, the host I / F device 310, the first media I / F device 320, and the second media I / F device 330 can all include the buffer memories 316, 324, and 334.

[0065] The first media I / F device 320 and the second media I / F device 330 may provide an operation to resolve the pad limitation by performing an operation offloaded from the host I / F device 310 on behalf of the host I / F device 310. Fig. 12A and Fig. 12B As described above, the first media I / F device 320 and the second media I / F device 330 may be appropriately packaged together with a peripheral chip to be used, or may form an independent chip or chiplet structure.

[0066] Figure 7 is a block diagram illustrating a SerDes 800 according to an embodiment.

[0067] Reference Figure 5 and Figure 7 , the host SerDes I / F 312 , the first media SerDes I / F 321 , and the second media SerDes I / F 331 may each include at least a portion of the SerDes 800 .

[0068] The SerDes 800 may be an I / F that supports communication between one device and another device. The SerDes 800 may convert parallel data into serial data, or convert serial data into parallel data. The SerDes 800 in this specification may be a transceiver. The parallel data may be data including a deserialization bit, and the serial data may be data including a serialization bit.

[0069] In an embodiment, the SerDes 800 may include a serializer 810 and a deserializer 820 .

[0070] The serializer 810 may transmit data (or signals) to the deserializer 820. The pins of the integrated circuit implementing the serializer 810 may increase the cost required to implement the SerDes 800. In order to reduce the implementation cost, the serializer 810 may transmit data including serialized bits. The serializer 810 may receive parallel data and output serial data. The serializer 810 may use, for example, single-ended signaling to transmit signals. For another example, the serializer 810 may use dual-ended signaling or differential signaling to transmit a pair of signals. The serializer 810 in this specification may be referred to as a transmitter or TX.

[0071] The deserializer 820 may receive data (or signals) transmitted from the serializer 810. The deserializer 820 may receive serial data and output parallel data. The deserializer 820 may include an amplifier and an equalizer to restore a transmission signal or compensate for channel loss.

[0072] The SerDes 800 may also include a channel. The channel may be a path that physically or electrically connects the serializer 810 to the deserializer 820. The channel may be formed between the serializer 810 and the deserializer 820. The channel may be implemented using a printed circuit board (PCB) trace or a coaxial cable. The channel may degrade the high-frequency components of the signal due to skin effect, dielectric loss, etc. When the signal is transmitted through the channel, channel loss may occur in the deserializer 820. Impedance discontinuities may occur due to connectors and other physical I / Fs between the substrate and the cable in the channel. The impedance discontinuity of the channel may appear as a notch in the frequency response of the channel. Due to the impedance discontinuity of the channel, reflection noise may occur in the deserializer 820. Due to channel loss or bandwidth limitations, each data bit passing through the channel may interfere with the next bit, and as adjacent symbols overlap, the bit error rate (BER) may increase. The SerDes 800 can generally be manufactured based on a SerDes model modeled on a computer.

[0073] In an embodiment, the host SerDes I / F 312 may include a SerDes 800. The host SerDes I / F 312 may include a serializer 810 and a deserializer 820. The serializer 810 of the host SerDes I / F 312 may serialize a command or data to be transmitted to at least one media I / F device 320 and 330. The serializer 810 of the host SerDes I / F 312 may serialize a parallel signal and output a serial signal. The serializer 810 of the host SerDes I / F 312 may transmit a serial signal to at least one media I / F device 320 and 330. The deserializer 820 of the host SerDes I / F 312 may parallelize a serial signal. The deserializer 820 of the host SerDes I / F 312 may parallelize a serial signal received from at least one media I / F device 320 and 330 and output a parallel signal.

[0074] The first media SerDes I / F 321 may include a SerDes 800. The first media SerDes I / F 321 may include a serializer 810 and a deserializer 820. The serializer 810 of the first media SerDes I / F 321 may serialize a parallel signal and output a serial signal. The serializer 810 of the first media SerDes I / F 321 may transmit the serial signal to the host I / F device 310. The deserializer 820 of the first media SerDes I / F 321 may parallelize the serial signal. The deserializer 820 of the first media SerDes I / F 321 may parallelize the serial signal received from the host I / F device 310 and output a parallel signal.

[0075] The second media SerDes I / F 331 may include a SerDes 800. The first media SerDes I / F 321 may include a serializer 810 and a deserializer 820. The serializer 810 of the second media SerDes I / F 331 may serialize a parallel signal and output a serial signal. The serializer 810 of the second media SerDes I / F 331 may transmit the serial signal to the host I / F device 310. The deserializer 820 of the second media SerDes I / F 331 may parallelize the serial signal. The deserializer 820 of the second media SerDes I / F 331 may parallelize the serial signal received from the host I / F device 310 and output a parallel signal.

[0076] Fig. 8A is shown in more detail Figure 6 A block diagram of the ECC engines 325 and 335 is shown.

[0077] Reference Figure 6and Fig. 8A , the media I / F devices 320 and 330 may include ECC engines 325 and 335, respectively. The ECC engines 325 and 335 may include an ECC encoding circuit 610 and an ECC decoding circuit 620. In response to the ECC control signal ECC_CON, the ECC encoding circuit 610 may generate a parity bit ECCP[0:7] for write data WData[0:63] to write it into a memory cell of the second block 110B of the memory cell array. The parity bit ECCP[0:7] may be stored in the ECC cell array 120. According to an embodiment, in response to the ECC control signal ECC_CON, the ECC encoding circuit 610 may generate a parity bit ECCP[0:7] for write data WData[0:63] to write it into a memory cell including a defective cell of the second block 110B.

[0078] In response to the ECC control signal ECC_CON, the ECC decoding circuit 620 may correct the error bit data using the read data RData[0:63] read from the memory cells of the second block 110B of the memory cell array and the parity bits ECCP[0:7] read from the ECC cell array 120, and output the error-corrected data Data[0:63]. According to an embodiment, the ECC decoding circuit 620 may correct the error bit data using the read data RData[0:63] read from the memory cells of the second block 110B including the defective cells and the parity bits ECCP[0:7] read from the ECC cell array 120, and output the error-corrected data Data[0:63].

[0079] In an embodiment, the ECC engines 325 and 335 of the respective media I / F devices 320 and 330 may perform an ECC operation. Each of the media I / F devices 320 and 330 may perform an ECC operation on behalf of the host I / F device 310. For example, the first media I / F device 320 may receive write data from the host I / F device 310 via serial communication. The ECC engine 325 may perform an encoding operation. The ECC engine 325 may generate a parity bit for the write data. The ECC engine 325 may transmit the write data and the parity bit to the first memory I / F 322.

[0080] The ECC engine 325 may receive the read data and the parity bit from the first memory I / F 322. The ECC engine 325 may perform an error correction operation. The ECC engine 325 may perform error correction on the read data based on the parity bit. The ECC engine 325 may transmit the error-corrected data to the first media SerDes I / F 321. The first media I / F device 320 may transmit the error-corrected data to the host I / F device 310 through serial communication.

[0081] Figure 8B is shown in more detail Figure 6 Block diagram of the AES engine.

[0082] Reference Figure 6 and Figure 8B , the media I / F devices 320 and 330 may include AES engines 326 and 336, respectively. The AES engines 326 and 336 may perform encryption and decryption on data using an AES algorithm, and may include an encryption module 218a and a decryption module 218b. Figure 8B The encryption module 218a and the decryption module 218b are shown implemented as separate modules, but the embodiment is not limited thereto, and a single module capable of performing both encryption and decryption may also be implemented in the AES engines 326 and 336. The buffer memory 216 may be a volatile memory used as a buffer, or may be an NVM. Figure 6 The buffer memories 324 and 334 in FIG. 2 may represent the buffer memory 216 as an example.

[0083] The AES engines 326 and 336 may receive the first data transmitted from the buffer memory 216. The encryption module 218a may generate second data by encrypting the first data transmitted from the buffer memory 216 using the encryption key. The second data may be transmitted from the AES engines 326 and 336 to the buffer memory 216 and stored in the buffer memory 216.

[0084] In addition, the AES engines 326 and 336 may receive third data transmitted from the buffer memory 216. The third data may be data encrypted using the same encryption key as the encryption key used to encrypt the first data. The decryption module 218b may generate fourth data by decrypting the third data transmitted from the buffer memory 216 using the same encryption key as the encryption key used to encrypt the first data. The fourth data may be transmitted from the AES engines 326 and 336 to the buffer memory 216 and stored in the buffer memory 216.

[0085] Fig. 9 is a block diagram showing a storage device 100 according to an embodiment.

[0086] like Fig. 9As shown, the memory device 100 may include a memory cell array 110 , a row decoder 120 , an input / output circuit 130 , a voltage generator 140 , and a control logic 150 . Figure 6 The storage device 340 may be an example of the storage device 100 .

[0087] The memory cell array 110 may include a plurality of memory cells and may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. For example, the memory cell array 110 may be connected to the row decoder 120 through word lines WL or selection lines SSL and GSL, and may be connected to the input / output circuit 130 through bit lines BL.

[0088] The memory cell array 110 may include a plurality of memory blocks BL1 to BLKi. The memory blocks BLK1 to BLKi may include at least one of a single-level cell block including a single-level cell, a multi-level cell block including a multi-level cell, and a three-level cell block including a three-level cell. Some memory blocks included in the memory cell array 110 may be single-level cell blocks, and other blocks may be multi-level cell blocks or three-level cell blocks.

[0089] In an embodiment, each memory block may have a three-dimensional structure (or a vertical structure). For example, each memory block may include a plurality of memory strings extending in a direction perpendicular to the substrate. However, the embodiment is not limited thereto, and each memory block may have a two-dimensional structure.

[0090] When an erase voltage is applied to the memory cell array 110, the memory cell may be in an erase state; and when a program voltage is applied to the memory cell array 110, the memory cell may be in a program state. In this case, each memory cell may have an erase state E and at least one program state classified according to a threshold voltage Vth.

[0091] In an embodiment, when the memory cell is a single level cell, the memory cell may have an erase state and a program state. In another embodiment, when the memory cell is a multi-level cell, the memory cell may have an erase state and at least three program states.

[0092] The row decoder 120 may select some word lines WL in response to the row address X-ADDR. The row decoder 120 transmits the word line voltage to the word line. During a programming operation, the row decoder 120 may apply a programming voltage and a verification voltage to the selected word line, and apply a programming inhibition voltage to an unselected word line. The programming inhibition voltage may be a high voltage. The high voltage may be a voltage having a level higher than a power supply voltage, which is generated by pumping the power supply voltage. The programming voltage may be a high voltage having a level higher than the programming inhibition voltage. During a read operation, the row decoder 120 may apply a read voltage to the selected word line, and apply a read inhibition voltage to an unselected word line. In addition, the row decoder 120 may select some string selection lines SSL or some ground selection lines GSL in response to the row address X-ARRD.

[0093] The input / output circuit 130 may receive data from an external source (e.g., a controller) and store the input data in the memory cell array 110. In addition, the input / output circuit 130 may read data from the memory cell array 110 and output the read data to an external device or the control logic 150. The input / output circuit 130 may include a page buffer corresponding to the bit line BL. In addition, the input / output circuit 130 may include components such as a column selection gate, a data buffer, a write driver, and a sense amplifier. The page buffer may be connected to the memory cell array 110 through the bit line BL, and may select some of the bit lines BL in response to the column address Y-ADDR received from the control logic 150. During a programming operation, the page buffer may be used as a write driver to program the data DATA to be stored in the memory cell array 110.

[0094] The voltage generator 140 may generate various types of voltages based on the voltage control signal CTRL_vol to perform programming, reading and erasing operations on the memory cell array 110. For example, the voltage generator 140 may generate a word line voltage, such as a programming voltage (or a write voltage), a read voltage, a pass voltage (or a word line non-selection voltage), or a verification voltage. The voltage generator 140 may generate a bit line voltage, such as a bit line force voltage, an inhibition voltage, etc. In addition, the voltage generator 140 may also generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_vol. In an embodiment, the voltage generator 140 may generate a programming pulse and a verification voltage based on the voltage control signal CTRL_vol, and the levels of the programming pulse and the verification voltage vary as the number of programming loops increases. When performing a programming loop, the programming method according to the embodiment may be performed in an incremental step pulse programming (ISPP) manner, and the voltage generator 140 may generate a programming pulse each time a programming loop is performed, and the level of the programming pulse gradually increases to be higher than the level of the previous programming voltage.

[0095] The control logic 150 may output various control signals for writing data to or reading data from the memory cell array 110 based on the command CMD, the address ADDR, and the control signal CTRL received from the controller. Thus, the control logic 150 may generally control various operations within the memory device 100. In addition, the control logic 150 may control the voltage generator 140 to generate at least one verification voltage and at least one program pulse in each program loop.

[0096] Various control signals output from the control logic 150 may be provided to the voltage generator 140, the row decoder 120, and the input / output circuit 130. For example, the control logic 150 may provide a voltage control signal CTRL_vol to the voltage generator 140, a row address X-ADDR to the row decoder 120, and a column address Y-ADDR to the input / output circuit 130. However, the embodiment is not limited thereto, and the control logic 150 may also provide other control signals to the voltage generator 140, the row decoder 120, and the input / output circuit 130. In addition, the control logic 150 may control the overall operation performed by the overall storage device 100 based on the command received from the controller, and the control logic 150 may perform the operation performed by the program controller. The program controller within the control logic 150 may be implemented as a hardware component, or may be implemented as a firmware component.

[0097] Fig.10 is a flowchart illustrating an operating method of a host-storage system according to an embodiment.

[0098] Reference Fig.10 , the host device 910, the host I / F device 920, the media I / F device 930, and the NVM device 940 may be connected to adjacent devices to exchange data. The host device 910, the host I / F device 920, the media I / F device 930, and the NVM device 940 may correspond to, for example Figure 6 The host device 100, the host I / F device 310, the media I / F device 320 or 330, and the NVM device 340 are described, and the redundant description given above is omitted.

[0099] The host-storage system 10 may operate by performing a plurality of operations S110 to S170. In operation S110, the host device 910, the host I / F device 920, and the media I / F device 930 may be reset (or powered on). After the host device 910, the host I / F device 920, and the media I / F device 930 are reset, the host I / F device 920 may receive a plurality of host commands from the host device 910 in operation S120. In operation S130, the host I / F device 920 may serialize the host commands to generate a first command.

[0100] In operation S140, the media I / F device 930 may receive the serialized first command. In operation S150, the media I / F device 930 may deserialize the first command to generate a plurality of second commands. The result of performing operations S130 to S150 may correspond to a SerDes type of data transmission.

[0101] In operation S160, the media I / F device 930 may perform an operation of uninstalling from the host I / F device on the second command to generate a plurality of third commands. The description related to the operation of uninstalling may be as described above with reference to Figure 6 The operations of the FTL, ECC engine, and AES engine described above. In operation S170, the media I / F device 930 may transmit the third command to the plurality of NVM devices, respectively.

[0102] Fig.11 is a flowchart showing an operation method of the media I / F device according to the embodiment.

[0103] Reference Fig.11 , the media I / F device 930 can operate by performing a plurality of operations S210 to S240. Reference is omitted Fig.10 A redundant description of the operation of the media I / F device 930.

[0104] In operation S210, the media I / F device 930 may receive a first command obtained by serializing a plurality of host commands of an external host device from the host I / F device. In operation S220, the media I / F device 930 may generate a plurality of second commands by deserializing the first command. In operation S230, the media I / F device 930 may generate a plurality of third commands by performing an operation of uninstalling from the host I / F device on the second command. The description related to the operation of uninstalling may be as described above with reference to Figure 6 The operations of the FTL, ECC engine, and AES engine described above. In operation S240, the media I / F device 930 may transmit the third command to the plurality of NVM devices.

[0105] According to the above embodiment, by configuring the host I / F and the media I / F of the storage controller separately and connecting them using the SerDes method, the pad limitation can be solved and flexible circuit design can be achieved. In addition, according to the above embodiment, by reflecting the fineness of the process required for the host I / F device and the media I / F device respectively, the yield of circuit manufacturing can be improved and the production cost can be reduced.

[0106] Fig. 12A and Fig. 12B is a block diagram showing a packaging form of a media I / F device according to an embodiment.

[0107] For example, Fig. 12A and Fig. 12B A media I / F device is shown which is core-chipped and by which a storage device is formed. Redundant descriptions about the storage device, the host I / F device, and the media I / F device are omitted.

[0108] Reference Fig. 12A , the host I / F device substrate 500 and at least one media I / F device substrate 720 and 730 are core particles forming a single package 811, and the formed package 811 can be connected to the NVM device 812 to form a storage device 810.

[0109] In addition, refer to Fig. 12B , the first media I / F device substrate 720 may be connected to a plurality of NVM devices to form a first package 821, and the second media I / F device substrate 730 may be connected to a plurality of NVM devices to form a second package 822. The first package 821 and the second package 822 may be connected to the host I / F device substrate 500 to form a storage device 820.

[0110] Since the host I / F circuit board 500 processes commands from the host and executes the above reference Figure 2 The various operations described above may therefore often require relatively high-speed data processing, and for this purpose, the host I / F circuit substrate may need to be produced by an advanced process. In contrast, the media I / F circuit substrates 720 and 730 that mainly perform operations of exchanging data with the NVM device 812 may not require relatively high-speed data processing, and it may be effective to produce the media I / F circuit substrates 720 and 730 by a cost-effective mature process. Therefore, according to the above-mentioned embodiment, by reflecting the fineness of the processes required for the host I / F device and the media I / F device, respectively, the yield of circuit manufacturing can be improved and the production cost can be reduced.

[0111] Fig.13 is a block diagram showing a system 1000 to which a storage device according to an embodiment is applied.

[0112] Fig.13 The system 1000 may be a mobile system such as a portable communication terminal (or mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Fig.13 The system 1000 is not necessarily limited to a mobile system, but may include, for example, a personal computer, a laptop computer, a server, a media player, or an automotive device (such as a navigation system), etc.

[0113] Reference Fig.13, system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may additionally include an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0114] The main processor 1100 may control the overall operation of the system 1000, and in particular, control operations of other components forming the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0115] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may also include an accelerator block 1130, which is a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may also be implemented as a separate chip physically independent of other components of the main processor 1100.

[0116] Memories 1200a and 1200b may be used as main memory devices of system 1000 and may include volatile memory such as SRAM and / or DRAM, but may also include NVM such as flash memory, PRAM and / or RRAM. Memories 1200a and 1200b may also be implemented in the same package as main processor 1100.

[0117] The storage devices 1300a and 1300b may be used as non-volatile storage devices that store data regardless of whether power is supplied, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, and NVMs 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. The NVMs 1320a and 1320b may include a V-NAND flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) structure, or may also include other types of NVMs such as PRAM and / or RRAM.

[0118] The storage devices 1300a and 1300b may be included in the system 1000 in a state of being physically separated from the main processor 1100, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a form such as a solid state device (SSD) or a memory card, and may be connected to other components of the system 1000 through an I / F (such as a connection interface 1480 to be described below). Such storage devices (1300a, 1300b) may be devices applying a standard protocol, such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or NVM Express (NVMe), but are not necessarily limited thereto.

[0119] The image capture device 1410 may capture still images or moving images and may include a camera, a camcorder, and / or a webcam.

[0120] The user input device 1420 may receive various types of data input from a user of the system 1000 and may include a touch pad, a keyboard, a keypad, a mouse, and / or a microphone, etc.

[0121] The sensor 1430 may detect various types of physical quantities obtained from outside the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope.

[0122] The communication device 1440 may transmit and receive signals to and from other devices outside the system 1000 according to various communication protocols. The communication device 1440 may be implemented to include an antenna, a transceiver, and / or a modem.

[0123] Display 1450 and speaker 1460 may be used as output devices for outputting visual information and auditory information, respectively, to a user of system 1000 .

[0124] The power supply device 1470 may appropriately convert power supplied by a battery built into the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000 .

[0125] The connection interface 1480 may provide connection between the system 1000 and an external device connected to the system 1000 to exchange data with the system 1000. The connection interface 1480 may be implemented according to various I / F methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Mini I / F (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCle), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), Compact Flash (CF) card I / F, etc.

[0126] Fig.14 is a block diagram showing a data center 3000 to which a storage device according to an embodiment is applied.

[0127] Reference Fig.14 , the data center 3000 is a facility that collects various types of data and provides services, and may also be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, or may be a computing system used in a company such as a bank or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently according to the embodiment, and the number of application servers 3100 to 3100n may be different from the number of storage servers 3200 to 3200m.

[0128] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. Taking the storage server 3200 as an example, the processor 3210 may control the overall operation of the storage server 3200 and access the memory 3220 to execute instructions and / or data loaded into the memory 3220. The memory 3220 may include a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (NVMDIMM). According to an embodiment, the number of processors 3210 and memories 3220 included in the storage server 3200 may have multiple options. In an embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an embodiment, the number of processors 3210 may be different from the number of memories 3220. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 can be similarly applied to the application server 3100. According to an embodiment, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in the storage server 3200 may be selected differently according to the embodiment.

[0129] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be implemented using Fibre Channel (FC) or Ethernet. Here, FC is a medium for relatively high-speed data transmission, and an optical switch that provides high performance / high availability can be used. Depending on the access method of the network 3300, the storage servers 3200 to 3200m can be provided as file storage, block storage, or object storage.

[0130] In an embodiment, the network 1300 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to an FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to a SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In other embodiments, the network 1300 may be a general-purpose network, such as a TCP / IP network. For example, the network 1300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), NVMe over Fabrics (NVMe-oF), and the like.

[0131] Hereinafter, description is made based on the application server 3100 and the storage server 3200. The description of the application server 3100 may also be applicable to other application servers 3100n, and the description of the storage server 3200 may also be applicable to other storage servers 3200m.

[0132] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0133] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300, or may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute a command to move or copy data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. Here, data may be moved to storage 3120 to 3120n of application servers 3100 to 3100n through storage 3220 to 3220m of storage servers 3200 to 3200m or directly from storage devices 3250 to 3250m of storage servers 3200 to 3200m. Data moved through network 3300 may be encrypted data for security or privacy purposes.

[0134] Taking the storage server 3200 as an example, the I / F 3254 may provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the NIC 3240 and the controller 3251. For example, the I / F 3254 may be implemented according to a direct attached storage (DAS) method that directly connects the storage device 3250 to a dedicated cable. In addition, for example, the I / F 1254 may be implemented according to various interface methods, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB, SD card, MMC, eMMC, UFS, eUFS, CF card I / F, etc.

[0135] The storage server 3200 may further include a switch 3230 and a NIC 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or connect the NIC 3240 to the storage device 3250 under the control of the processor 3210.

[0136] In an embodiment, the NIC 3240 may include a network I / F card, a network adapter, etc. The NIC 3240 may be connected to the network 3300 through a wired I / F, a wireless I / F, a Bluetooth I / F, an optical I / F, etc. The NIC 3240 may include an internal memory, a digital signal processor (DSP), a host bus I / F, etc., and may be connected to the processor 3210 and / or the switch 3230 through the host bus I / F. The host bus I / F may be implemented as one of the examples of the above-mentioned I / F 3254. In an embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0137] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3130 to 3130n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m to program or read data. Here, the data may be data that has been error corrected by an ECC engine. The data may be data that has been processed by a data bus inversion (DBI) or a data mask (DM), and may include cyclic redundancy code (CRC) information. The data may be encrypted to ensure security or privacy.

[0138] The storage devices 3150 to 3150m and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, when reading data from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal and may be used to output data to the DQ bus. A data strobe (DQS) may be generated using the RE signal. The command and address signals may be latched to the page buffer according to the rising edge or falling edge of the write enable (WE) signal.

[0139] The controller 3251 may generally control the operation of the storage device 3250. In an embodiment, the controller 3251 may include a static random access memory (SRAM). The controller 3251 may write data to the NAND flash memory 3252 in response to a write command, or may read data from the NAND flash memory 3252 in response to a read command. For example, the write command and / or the read command may be provided by a processor 3210 in the storage server 3200, a processor 3210m in another storage server 3200m, or a processor 3110 or 3110n in an application server 3100 or 3100n. The DRAM 3253 may temporarily store (buffer) data to be written to the NAND flash memory 3252 or data read from the NAND flash memory 3252. In addition, the DRAM 3253 may store metadata. Here, the metadata is generated by the controller 3251 to manage user data or data of the NAND flash memory 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0140] Fig.15 is a cross-sectional view showing a BVNAND structure that may be applied to a memory device according to an embodiment.

[0141] Reference Fig.15 , the memory device 4000 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper chip to the lower chip by a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on a top metal layer of the upper chip to a bonding metal formed on a top metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also include aluminum or tungsten.

[0142] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 4000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0143] The peripheral circuit region PERI may include a first substrate 4110, an interlayer insulating layer 4115, a plurality of circuit elements 4120a, 4120b, and 4120c formed on the first substrate 4110, first metal layers 4130a, 4130b, and 4130c connected to the circuit elements 4120a, 4120b, and 4120c, respectively, and second metal layers 4140a, 4140b, and 4140c formed on the first metal layers 4130a, 4130b, and 4130c, respectively. In an embodiment, the first metal layers 4130a, 4130b, and 4130c may include tungsten having a relatively high resistance, and the second metal layers 4140a, 4140b, and 4140c may include copper having a relatively low resistance.

[0144] exist Fig.15 , only the first metal layers 4130a, 4130b, and 4130c and the second metal layers 4140a, 4140b, and 4140c are shown and described, but the embodiment is not limited thereto, and at least one metal layer may be further formed on the second metal layers 4140a, 4140b, and 4140c. At least some of the one or more metal layers formed on top of the second metal layers 4140a, 4140b, and 4140c may include aluminum or the like having a lower resistance than copper forming the second metal layers 4140a, 4140b, and 4140c.

[0145] The interlayer insulating layer 4115 may be disposed on the first substrate 4110 to cover the circuit elements 4120a, 4120b, and 4120c, the first metal layers 4130a, 4130b, and 4130c, and the second metal layers 4140a, 4140b, and 4140c, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0146] The lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL by a bonding method, and the lower bonding metals 4171b and 4172b and the upper bonding metals 4271b and 4272b may include, for example, aluminum, copper, or tungsten.

[0147] The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 4210 and a common source line 4220. On the second substrate 4210, a plurality of word lines 4231 to 4238 may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 4210; 4230. A string selection line and a ground selection line may be respectively provided above and below the word line 4230, and the word line 4230 may be located between the string selection line and the ground selection line.

[0148] In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the upper surface of the second substrate 4210 to penetrate the word line 4230, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 4250c and the second metal layer 4260c. For example, the first metal layer 4250c may be a bit line contact, and the second metal layer 4260c may be a bit line. In an embodiment, the bit line 4260c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 4210.

[0149] exist Fig.15 In the illustrated embodiment, the region where the channel structure CH and the bit line 4260c are located may be defined as a bit line bonding region BLBA. The bit line 4260c may be electrically connected to a circuit element 4120c providing a page buffer 4293 in a peripheral circuit region PERI of the bit line bonding region BLBA. For example, in the peripheral circuit region PERI, the bit line 4260c may be connected to upper bonding metals 4271c and 4272c, and the upper bonding metals 4271c and 4272c may be connected to lower bonding metals 4171c and 4172c connected to the circuit element 4120c of the page buffer 4293.

[0150] In the word line bonding area WLBA, the word line 4230 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 4210, and may be connected to a plurality of cell contact plugs 4241 to 4247; 4240. Since at least some of the word lines 4230 extend different lengths along the second direction, the word lines 4230 and the cell contact plugs 4240 may be connected to each other at the provided pads. The first metal layer 4250b and the second metal layer 4260b may be sequentially connected to the upper portion of the cell contact plug 4240 connected to the word line 4230. In the word line bonding area WLBA, the cell contact plug 4240 may be connected to the peripheral circuit area PERI through the upper bonding metals 4271b and 4272b of the cell area CELL and the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI.

[0151] The cell contact plug 4240 may be electrically connected to a circuit element 4120b providing a row decoder 4294 in the peripheral circuit region PERI. In an embodiment, an operating voltage of the circuit element 4120b providing the row decoder 4294 may be different from an operating voltage of the circuit element 4120c providing the page buffer 4293. For example, an operating voltage of the circuit element 4120c providing the page buffer 4293 may be greater than an operating voltage of the circuit element 4120b providing the row decoder 4294.

[0152] The common source line contact plug 4280 may be located in the external pad bonding area PA. The common source line contact plug 4280 may include a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line 4220. The first metal layer 4250a and the second metal layer 4260a may be sequentially stacked on the common source line contact plug 4280. For example, the area where the common source line contact plug 4280, the first metal layer 4250a, and the second metal layer 4260a are located may be defined as the external pad bonding area PA.

[0153] The input / output pads 4105 and 4205 may be located in the external pad bonding area PA. Fig.15 , a lower insulating film 4101 may be formed on a lower portion of the first substrate 4110 to cover a lower surface of the first substrate 4110, and a first input / output pad 4105 may be formed on the lower insulating film 4101. The first input / output pad 4105 may be connected to at least one of the circuit elements 4120a, 4120b, and 4120c located in the peripheral circuit region PERI through the first input / output contact plug 4103, and may be separated from the first substrate 4110 by the lower insulating film 4101. In addition, a side insulating film may be located between the first input / output contact plug 4103 and the first substrate 4110 to electrically separate the first input / output contact plug 4103 from the first substrate 4110.

[0154] Reference Fig.15 , an upper insulating film 4201 may be formed on the top of the second substrate 4210 to cover the upper surface of the second substrate 4210, and second input / output pads 4205 may be provided on the upper insulating film 4201. The second input / output pads 4205 may be connected to at least one of the circuit elements 4120a, 4120b, and 4120c located in the peripheral circuit region PERI through the second input / output contact plugs 4203.

[0155] According to an embodiment, the second substrate 4210 and the common source line 4220 may not be located in the region where the second input / output contact plug 4203 is located. In addition, the second input / output pad 4205 may not overlap with the word line 4230 in the third direction (Z-axis direction). Fig.15 , the second input / output contact plug 4203 may be separated from the second substrate 4210 in a direction parallel to the upper surface of the second substrate 4210 , and may be connected to the second input / output pad 4205 through the interlayer insulating layer 4215 of the cell region CELL.

[0156] According to an embodiment, the first input / output pad 4105 and the second input / output pad 4205 may be selectively formed. For example, the memory device 4000 may include only the first input / output pad 4105 disposed on top of the first substrate 4110, or only the second input / output pad 4205 disposed on top of the second substrate 4210. According to another embodiment, the memory device 4000 may include both the first input / output pad 4105 and the second input / output pad 4205.

[0157] The metal pattern of the uppermost metal layer may exist as a dummy pattern in the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell region CELL and the peripheral circuit region PERI, or the uppermost metal layer may be empty.

[0158] In the memory device 4000, in order to correspond to the upper metal pattern 4272a formed at the uppermost metal layer of the cell region CELL in the external pad bonding area PA, a lower metal pattern 4176a having the same shape as the upper metal pattern 4272a of the cell region CELL may be formed on the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 4176a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in order to correspond to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding area PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed on the uppermost metal layer of the cell region CELL.

[0159] Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL by a bonding method.

[0160] In addition, in the bit line bonding area BLBA, in order to correspond to the lower metal pattern 4152 formed on the uppermost metal layer of the peripheral circuit area PERI, an upper metal pattern 4292 having the same shape as the lower metal pattern 4152 of the peripheral circuit area PERI may be formed on the uppermost metal layer of the cell area CELL. No contact portion may be formed on the upper metal pattern 4292 formed on the uppermost metal layer of the cell area CELL.

[0161] According to an exemplary embodiment, at least one of the components, elements, modules or units (collectively referred to as "components" in this paragraph) represented by blocks in the accompanying drawings may be embodied as various numbers of hardware, software and / or firmware structures that perform the above-mentioned various functions. For example, at least one of these components may use a direct circuit structure, such as a memory, a processor, a logic circuit, a lookup table, etc., which can perform various functions by the control of one or more microprocessors or other control devices. In addition, at least one of these components may be specifically embodied as a module, a program or a portion of code, which contains one or more executable instructions for performing specific logical functions and is executed by one or more microprocessors or other control devices. In addition, at least one of these components may include a processor (such as a central processing unit (CPU)), a microprocessor, etc., that performs various functions, or is implemented by it. Two or more of these components may be combined into a single component that performs all operations or functions of the two or more components combined. In addition, at least part of the functions of at least one of these components may be performed by another of these components. In addition, although the bus is not shown in the above block diagram, communication between components may be performed through the bus. The functional aspects of the above exemplary embodiments may be implemented by algorithms executed on one or more processors. Furthermore, the components or processing steps represented by blocks may utilize any number of related technologies for electronics configuration, signal processing and / or control, data processing, and the like.

[0162] Although embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A storage device, comprising: a plurality of non-volatile memory devices; a host interface device configured to communicate with an external host device via an interface channel; as well as at least one media interface device connected between the host interface device and the plurality of non-volatile memory devices, the at least one media interface device being configured to control the plurality of non-volatile memory devices, The at least one media interface device is further configured to perform operations offloaded from the host interface device and to perform serial communications with the host interface device.

2. The storage device according to claim 1, wherein: The at least one media interface device comprises: a first interface circuit configured to perform serial communication with the host interface device; a second interface circuit configured to communicate with the plurality of non-volatile memory devices; and A processing circuit is configured to perform operations offloaded from the host interface device.

3. The storage device according to claim 2, wherein: The processing circuit includes an error correction code engine configured to generate parity bits for write data and correct errors for read data based on the parity bits.

4. The storage device according to claim 2, wherein: The processing circuit includes an advanced encryption standard engine configured to perform encryption operations on write data and decryption operations on read data based on an encryption key.

5. The storage device according to claim 2, wherein: The processing circuit includes a flash translation layer circuit configured to perform at least one of address mapping, wear leveling, and garbage collection.

6. The storage device according to claim 2, wherein: The media interface device also includes a buffer memory configured to temporarily store data.

7. The storage device according to claim 2, wherein: The first interface circuit is further configured to communicate with the plurality of non-volatile memory devices through a frequency boosting interface method.

8. The storage device according to claim 1, wherein: The at least one media interface device and the plurality of non-volatile memory devices are configured as a die included in a single package.

9. The storage device according to claim 1, wherein: The at least one media interface device and the host interface device are configured as a chip included in a single package.

10. A system comprising: a plurality of non-volatile memory devices; as well as Media interface devices, including: a first interface circuit configured to connect to an external host interface device to operate as a storage device; a second interface circuit configured to connect to the plurality of nonvolatile memory devices; and processing circuitry configured to perform operations offloaded from the host interface device, Wherein, the first interface circuit is further configured to perform serial communication with the host interface device.

11. The system according to claim 10, wherein: The processing circuit includes an error correction code engine configured to generate parity bits for write data and correct errors for read data based on the parity bits.

12. The system according to claim 10, wherein: The processing circuit includes an advanced encryption standard engine configured to perform encryption operations on write data and decryption operations on read data based on an encryption key.

13. The system according to claim 10, wherein: The processing circuit includes a flash translation layer circuit configured to perform at least one of address mapping, wear leveling, and garbage collection.

14. The system according to claim 10, wherein: The media interface device also includes a buffer memory configured to temporarily store data.

15. The system according to claim 10, wherein: The first interface circuit is further configured to communicate with the plurality of non-volatile memory devices through a frequency boosting interface method.

16. An operating method of a media interface device, the media interface device being connected between a host interface device and a plurality of non-volatile memory devices, the host interface device being configured to communicate with an external host device, and the media interface device being configured to control the plurality of non-volatile memory devices, the operating method comprising: receiving a first command from the host interface device, in which a plurality of host commands of the external host device are serialized; Deserializing the first command to generate a plurality of second commands; performing an operation offloaded from the host interface device on the plurality of second commands to generate a plurality of third commands; as well as The plurality of third commands are transmitted to the plurality of nonvolatile memory devices, respectively.

17. The operating method according to claim 16, wherein: Generating the plurality of third commands includes generating, by an error correction code engine, parity bits for data corresponding to the second command.

18. The operating method according to claim 16, wherein: Generating the plurality of third commands includes performing an encryption operation on data corresponding to the second command using an encryption key through an advanced encryption standard engine.

19. The operating method according to claim 16, wherein: The media interface device and the plurality of non-volatile memory devices are configured as a die included in a single package, and The single package is configured to be combined with the host interface device, and the host interface device is packaged separately from the single package.

20. The operating method according to claim 16, wherein: The media interface device and the host interface device are configured as chips included in a single package, and The single package is configured to be combined with the plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices are packaged separately from the single package.

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