Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); a plurality of sub-pixels (P) located on one side of the substrate (1), the plurality of sub-pixels (P) comprising: sub-pixel rows extending along a first direction and arranged along a second direction; at least one sub-pixel (P) comprising: a main pixel part (PA) distributed along the second direction, and an auxiliary pixel part (PB), wherein the brightness of the main pixel part (PA) is greater than the brightness of the auxiliary pixel part (PB), and in the sub-pixel row, the main pixel part (PA) and the auxiliary pixel part (PB) are arranged alternately.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light with the VA method of the LCD panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in utilizing a special polymer material as an alignment film to precisely control the tilt of liquid crystal molecules along the ultraviolet light direction. Its precision is measured in picometers (one trillionth of a meter). The advantage of UV2A is that the liquid crystal panel has a simple structure without protrusions or slits. This "dream of liquid crystal engineers" was explored as early as 30 years ago. Today, with the availability of new materials, production equipment, and a perfected processing procedure, this dream has been realized. The simple structure of the liquid crystal panel not only improves production efficiency but also offers many advantages in image quality.

[0004] High-resolution products, such as 8K and 16K displays, are the main direction for future products. However, current 8K products using vertically aligned liquid crystal (VA) have problems with low transmittance and poor color shift. Summary of the Invention

[0005] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0006] Substrate;

[0007] A plurality of sub-pixels are located on one side of the substrate. The plurality of sub-pixels include: a row of sub-pixels extending along a first direction and arranged along a second direction; at least one of the sub-pixels includes: a main pixel portion distributed along the second direction and an auxiliary pixel portion, wherein the brightness of the main pixel portion is greater than the brightness of the auxiliary pixel portion, and the main pixel portion and the auxiliary pixel portion are alternately arranged in the sub-pixel row.

[0008] In one possible implementation, the array substrate includes: a gate line extending along the first direction, a data line extending along the second direction, a first common trace distributed on one side of the gate line extending along the first direction, and a second common trace distributed on the other side of the gate line extending along the first direction.

[0009] The sub-pixel includes: a first sub-pixel electrode, a second sub-pixel electrode, a first transistor electrically connected to the first sub-pixel electrode, a second transistor electrically connected to the second sub-pixel electrode, and a third transistor electrically connected to one of the first transistor and the second transistor; the first sub-pixel electrode and the first common trace are located on the same side of the gate line, and the second sub-pixel electrode and the second common trace are located on the same side of the gate line.

[0010] On the sub-pixel row, the orthographic projections of the third transistors of the plurality of sub-pixels on the substrate are alternately distributed in a first region and a second region; wherein, the first region includes: the gate line, the first common trace, and the region between the gate line and the first common trace; the second region includes: the gate line, the second common trace, and the region between the gate line and the second common trace.

[0011] In one possible implementation, on the sub-pixel row, the third transistors of a plurality of the sub-pixels are alternately electrically connected to the first common trace and the second common trace.

[0012] In one possible implementation, the first transistor includes: a first transistor gate, a first transistor first terminal, and a first transistor second terminal; the second transistor includes: a second transistor gate, a second transistor first terminal, and a second transistor second terminal; and the third transistor includes: a third transistor gate, a third transistor first terminal, and a third transistor second terminal.

[0013] On the sub-pixel row, the second pole of the first transistor and the second pole of the second transistor of a plurality of sub-pixels are alternately multiplexed as the first pole of the third transistor.

[0014] In one possible implementation, the plurality of first transistor second electrodes include: a first type of second electrode and a second type of second electrode; the first type of second electrode includes: a first type of first portion extending along the first direction, a first type of second portion extending from one end of the first type of first portion toward the gate line, and a first type of third portion extending from the other end of the first type of first portion toward the gate line; the second type of second electrode includes: a second type of first portion extending along the first direction, and a second type of second portion extending from one end of the second type of first portion toward the gate line 2.

[0015] On the sub-pixel row, the first type of second pole and the second type of second pole are alternately distributed.

[0016] In one possible implementation, the second transistor's second electrode includes: a third type of second electrode and a fourth type of second electrode; the third type of second electrode includes: a third type of first portion extending along the first direction, a third type of second portion extending from one end of the third type of first portion toward the gate line, and a third type of third portion extending from the other end of the third type of first portion toward the gate line; the fourth type of second electrode includes: a fourth type of first portion extending along the first direction, and a fourth type of second portion extending from one end of the fourth type of first portion toward the gate line.

[0017] On the sub-pixel row, the third type of second pole and the fourth type of second pole are distributed alternately.

[0018] In one possible implementation, the first common trace has a first common protrusion facing the gate line side, and the orthographic projection of the second electrode of the third transistor on the substrate and the orthographic projection of the first common protrusion on the substrate have an overlapping area; the second common trace has a second common protrusion facing the gate line side, and the orthographic projection of the second electrode of the third transistor on the substrate and the orthographic projection of the second common protrusion on the substrate have an overlapping area.

[0019] On the sub-pixel row, there is a sub-pixel spaced between adjacent first common protrusions and a sub-pixel spaced between adjacent second common protrusions, and the first common protrusions and the second common protrusions are staggered.

[0020] In one possible implementation, the first sub-pixel electrode is an integral structure, and the second sub-pixel electrode is an integral structure.

[0021] In one possible implementation, the first sub-pixel electrode includes: a first electrode portion and a second electrode portion sequentially distributed along the second direction; the second sub-pixel electrode includes: a third electrode portion and a fourth electrode portion sequentially distributed along the second direction.

[0022] The first electrode portion has a plurality of first slits, the second electrode portion has a plurality of second slits, the third electrode portion has a plurality of third slits, and the fourth electrode portion has a plurality of fourth slits;

[0023] The first slit extends in the same direction as the second slit, the third slit extends in the same direction as the fourth slit, and the first slit extends in a different direction than the third slit.

[0024] In one possible implementation, a fifth slit is further provided between the first electrode portion and the second electrode portion, and the extension direction of the fifth slit is different from the extension direction of the first slit.

[0025] A sixth slit is also provided between the third electrode portion and the fourth electrode portion, and the extension direction of the sixth slit is different from the extension direction of the third slit.

[0026] In one possible implementation, the fifth slit extends along the second direction, and the sixth slit extends along the second direction.

[0027] In one possible implementation, the fifth slit extends in the same direction as the third slit, and the sixth slit extends in the same direction as the first slit.

[0028] In one possible implementation, the side of the first electrode portion facing the second electrode portion is a semi-closed structure, the side of the second electrode portion facing the first electrode portion is a semi-closed structure, and the closed position of the first electrode portion facing the second electrode portion is opposite to the open position of the second electrode portion facing the first electrode portion, and the open position of the first electrode portion facing the second electrode portion is opposite to the closed position of the second electrode portion facing the first electrode portion.

[0029] In one possible implementation, the first slit of the first electrode portion is integral with the second slit of the second electrode portion; the third slit of the third electrode portion is integral with the fourth slit of the fourth electrode portion.

[0030] In one possible implementation, the array substrate includes: a gate line extending along the first direction, a data line extending along the second direction, a first common trace distributed on one side of the gate line, and a second common trace distributed on the other side of the gate line.

[0031] The sub-pixel includes: a first transistor, a second transistor, a third transistor electrically connected to one of the first transistor and the second transistor, and a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion sequentially distributed along the second direction; the first electrode portion is electrically connected to one of the third electrode portion and the fourth electrode portion to form a first connecting sub-pixel electrode; the second electrode portion is electrically connected to the other of the third electrode portion and the fourth electrode portion to form a second connecting sub-pixel electrode;

[0032] In the sub-pixel row, the first connecting sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; the second connecting sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; and in the same sub-pixel, the first connecting sub-pixel electrode and the second connecting sub-pixel electrode are electrically connected to different transistors.

[0033] In one possible implementation, the first electrode portion is electrically connected to the fourth electrode portion, and the second electrode portion is electrically connected to the third electrode portion.

[0034] In one possible implementation, the array substrate further includes: a first connecting portion extending along the second direction, and a second connecting portion;

[0035] One end of the first connecting portion is electrically connected to the first electrode portion, and the other end is electrically connected to the fourth electrode portion; one end of the second connecting portion is electrically connected to the second electrode portion, and the other end is electrically connected to the third electrode portion.

[0036] In one possible implementation, the array substrate further includes: a first connection protrusion connected to the first connection portion and protruding toward the side of the third transistor;

[0037] On the sub-pixel row, the first connecting protrusion is alternately electrically connected to the first transistor and the second transistor.

[0038] In one possible implementation, on the sub-pixel row, the outer edge extensions of adjacent first connecting protrusions along the first direction do not coincide.

[0039] In one possible implementation, the first electrode portion is electrically connected to the third electrode portion, and the second electrode portion is electrically connected to the fourth electrode portion.

[0040] In one possible implementation, the array substrate further includes: a third connecting portion extending along the second direction, and a fourth connecting portion;

[0041] The third connection portion is projected onto the substrate on the same side as the first sub-pixel electrode on the substrate, and one end is electrically connected to the first electrode portion, while the other end is electrically connected to the side of the third electrode portion facing the second electrode portion.

[0042] One end of the fourth connecting part is electrically connected to the second electrode part, and the other end is electrically connected to the fourth electrode part.

[0043] In one possible implementation, the plurality of sub-pixels includes: a sub-pixel column extending along the second direction and arranged along the first direction; wherein the main pixel portion and the auxiliary pixel portion are arranged alternately in the sub-pixel column.

[0044] In one possible implementation, the plurality of sub-pixels includes: a sub-pixel column extending along the second direction and arranged along the first direction; wherein, two main pixel portions and two auxiliary pixel portions are alternately arranged in the sub-pixel column.

[0045] In one possible implementation, the array substrate further includes: a first electrode layer; the first electrode layer includes: a first electrode connection portion, a first cutout, and a second cutout;

[0046] The orthographic projection of the first cutout on the substrate at least partially overlaps with the orthographic projection of the first sub-pixel electrode on the substrate; the orthographic projection of the second cutout on the substrate at least partially overlaps with the orthographic projection of the second sub-pixel electrode on the substrate.

[0047] In one possible implementation, the orthographic projection of the first electrode connection onto the substrate covers the orthographic projection of the data line onto the substrate.

[0048] This disclosure also provides a display panel, which includes the array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate, wherein the counter substrate has a common electrode layer disposed on the side facing the array substrate.

[0049] In one possible implementation, the first electrode layer is loaded with the same signal as the common electrode layer.

[0050] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0051] Figure 1A This is one of the top views of the array substrate provided in the embodiments of this disclosure; Figure 1B for Figure 1A Schematic diagram of a single film layer of the middle gate line layer;

[0052] Figure 1C for Figure 1A A schematic diagram of a single-film layer with an active layer;

[0053] Figure 1D for Figure 1A A schematic diagram of a single film layer in the middle data line layer;

[0054] Figure 1E for Figure 1A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0055] Figure 1F for Figure 1A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0056] Figure 1G for Figure 1A A schematic diagram simulating the optical effect of the array substrate;

[0057] Figure 1H for Figure 1ASchematic diagram of the cross section at point EF;

[0058] Figure 2A This is a second top view of the array substrate provided in the embodiments of this disclosure; Figure 2B for Figure 2A Schematic diagram of a single film layer of the middle gate line layer;

[0059] Figure 2C for Figure 2A A schematic diagram of a single-film layer with an active layer;

[0060] Figure 2D for Figure 2A A schematic diagram of a single film layer in the middle data line layer;

[0061] Figure 2E for Figure 2A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0062] Figure 2F for Figure 2A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0063] Figure 2G for Figure 2A A schematic diagram simulating the optical effect of the array substrate;

[0064] Figure 3A This is the third top view schematic diagram of the array substrate provided in the embodiments of this disclosure; Figure 3B for Figure 3A Schematic diagram of a single film layer of the middle gate line layer;

[0065] Figure 3C for Figure 3A A schematic diagram of a single-film layer with an active layer;

[0066] Figure 3D for Figure 3A A schematic diagram of a single film layer in the middle data line layer;

[0067] Figure 3E for Figure 3A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0068] Figure 3F for Figure 3A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0069] Figure 3G for Figure 3A A schematic diagram simulating the optical effect of the array substrate;

[0070] Figure 4A This is the fourth top view schematic diagram of the array substrate provided in the embodiments of this disclosure; Figure 4B for Figure 4A Schematic diagram of a single film layer of the middle gate line layer;

[0071] Figure 4C for Figure 4A A schematic diagram of a single-film layer with an active layer;

[0072] Figure 4D for Figure 4A A schematic diagram of a single film layer in the middle data line layer;

[0073] Figure 4E for Figure 4A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0074] Figure 4F for Figure 4A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0075] Figure 4G for Figure 4A A schematic diagram simulating the optical effect of the array substrate;

[0076] Figure 5A Fifth top view of the array substrate provided in the embodiments of this disclosure; Figure 5B for Figure 5A Schematic diagram of a single film layer of the middle gate line layer;

[0077] Figure 5C for Figure 5A A schematic diagram of a single-film layer with an active layer;

[0078] Figure 5D for Figure 5A A schematic diagram of a single film layer in the middle data line layer;

[0079] Figure 5E for Figure 5A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0080] Figure 5F for Figure 5A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0081] Figure 5G for Figure 5A A schematic diagram simulating the optical effect of the array substrate;

[0082] Figure 6A This is the sixth top view schematic diagram of the array substrate provided in the embodiments of this disclosure; Figure 6B for Figure 6A Schematic diagram of a single film layer of the middle gate line layer;

[0083] Figure 6C for Figure 6A A schematic diagram of a single-film layer with an active layer;

[0084] Figure 6D for Figure 6A A schematic diagram of a single film layer in the middle data line layer;

[0085] Figure 6E for Figure 6A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0086] Figure 6F for Figure 6A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0087] Figure 7 This is the seventh top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0088] Figure 8 Eighth top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0089] Figure 9A This is the ninth top view of the array substrate provided in the embodiments of this disclosure; Figure 9B for Figure 9A Schematic diagram of a single film layer of the middle gate line layer;

[0090] Figure 9C for Figure 9A A schematic diagram of a single-film layer with an active layer;

[0091] Figure 9D for Figure 9A A schematic diagram of a single film layer in the middle data line layer;

[0092] Figure 9E for Figure 9A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0093] Figure 9F for Figure 9A A schematic diagram of a single film layer of the first electrode layer in the middle;

[0094] Figure 9G for Figure 9A A schematic diagram of a single-film layer of the second insulating layer;

[0095] Figure 9H for Figure 9A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0096] Figure 9I for Figure 9A A schematic diagram of the black matrix corresponding to the array substrate shown;

[0097] Figure 9J for Figure 9A A schematic diagram simulating the optical effect corresponding to the array substrate shown;

[0098] Figure 10 This is a schematic diagram of the sub-pixel equivalent circuit provided in an embodiment of the present disclosure;

[0099] Figure 11 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0100] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0101] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0102] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0103] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0104] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0105] See Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, Figures 5A-5F As shown, Figures 6A-6F As shown, where, Figure 1A This is one of the top views of the array substrate provided in the embodiments of this disclosure. Figure 1B for Figure 1A Schematic diagram of a single film layer of the middle gate line layer. Figure 1C for Figure 1A A schematic diagram of a single-film layer with an active layer. Figure 1D for Figure 1A A schematic diagram of a single film layer in the middle data line layer. Figure 1E for Figure 1A A schematic diagram of the single-film layer of the first insulating layer. Figure 1F for Figure 1A A schematic diagram of a single film layer of the middle pixel electrode layer. Figure 2A This is a second top view schematic diagram of the array substrate provided in an embodiment of this disclosure. Figure 2B for Figure 2A Schematic diagram of a single film layer of the middle gate line layer. Figure 2C for Figure 2A A schematic diagram of a single-film layer with an active layer. Figure 2D for Figure 2A A schematic diagram of a single film layer in the middle data line layer. Figure 2E for Figure 2A A schematic diagram of the single-film layer of the first insulating layer. Figure 2F for Figure 2A A schematic diagram of a single film layer of the middle pixel electrode layer. Figure 3A This is the third top view schematic diagram of the array substrate provided in the embodiments of this disclosure. Figure 3B for Figure 3A Schematic diagram of a single film layer of the middle gate line layer. Figure 3C for Figure 3A A schematic diagram of a single-film layer with an active layer. Figure 3D for Figure 3A A schematic diagram of a single film layer in the middle data line layer. Figure 3E for Figure 3A A schematic diagram of the single-film layer of the first insulating layer. Figure 3F for Figure 3A A schematic diagram of a single film layer of the middle pixel electrode layer. Figure 4A This is the fourth top view schematic diagram of the array substrate provided in the embodiments of this disclosure. Figure 4B for Figure 4A Schematic diagram of a single film layer of the middle gate line layer. Figure 4C for Figure 4A A schematic diagram of a single-film layer with an active layer. Figure 4D for Figure 4A A schematic diagram of a single film layer in the middle data line layer. Figure 4E for Figure 4A A schematic diagram of the single-film layer of the first insulating layer. Figure 4F for Figure 4A A schematic diagram of a single film layer of the middle pixel electrode layer. Figure 5A This is the fifth top view schematic diagram of the array substrate provided in the embodiments of this disclosure. Figure 5B for Figure 5A Schematic diagram of a single film layer of the middle gate line layer. Figure 5C for Figure 5A A schematic diagram of a single-film layer with an active layer. Figure 5D for Figure 5A A schematic diagram of a single film layer in the middle data line layer. Figure 5E for Figure 5A A schematic diagram of the single-film layer of the first insulating layer. Figure 5F for Figure 5A A schematic diagram of a single film layer of the middle pixel electrode layer. Figure 6A This is the sixth top view schematic diagram of the array substrate provided in the embodiments of this disclosure. Figure 6B for Figure 6A Schematic diagram of a single film layer of the middle gate line layer. Figure 6C for Figure 6A A schematic diagram of a single-film layer with an active layer. Figure 6D for Figure 6A A schematic diagram of a single film layer in the middle data line layer. Figure 6E for Figure 6A A schematic diagram of the single-film layer of the first insulating layer. Figure 6F for Figure 6A A schematic diagram of a single film layer of the middle pixel electrode layer. This disclosure provides an array substrate, including:

[0106] Substrate 1;

[0107] Multiple sub-pixels P are located on one side of substrate 1. The multiple sub-pixels P include: a row of sub-pixels extending along a first direction X and arranged along a second direction Y; at least one sub-pixel P includes: a main pixel portion PA distributed along the second direction Y and an auxiliary pixel portion PB, wherein the brightness of the main pixel portion PA is greater than the brightness of the auxiliary pixel portion PB, and the main pixel portion PA and the auxiliary pixel portion PB are arranged alternately in the sub-pixel row.

[0108] In this embodiment of the present disclosure, at least one sub-pixel P includes: a main pixel portion PA distributed along the second direction Y, and an auxiliary pixel portion PB, wherein the brightness of the main pixel portion PA is greater than the brightness of the auxiliary pixel portion PB, and in the sub-pixel row, the main pixel portion PA and the auxiliary pixel portion PB are arranged alternately, that is, the main pixel portion PA and the auxiliary pixel portion PB are vertically divided and staggered. The two sub-pixels in the first direction X can form a 2P8D (2 sub-pixels and 8 planning areas) effect of mutual brightness and darkness compensation, and the second direction Y can also form a mutual brightness and darkness compensation effect. Moreover, the two sub-pixels in the first direction X can also form a mutual viewing angle compensation effect, and the second direction Y can also form a mutual viewing angle compensation effect. This 2P8D design can achieve the effect of both improving transmittance and improving color shift.

[0109] It is understandable that the brightness of the main pixel PA is greater than the brightness of the auxiliary pixel PB, which refers to the brightness comparison within a sub-pixel P when the display panel is powered on and lit.

[0110] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, the array substrate includes: a gate line 2 extending along a first direction X, a data line 3 extending along a second direction Y, and a first common trace 25 distributed on one side of the gate line 2 extending along the first direction X, and a second common trace 26 distributed on the other side of the gate line 2 extending along the first direction X; the sub-pixel includes: a first sub-pixel electrode 41, a second sub-pixel electrode 42, a first transistor T1 electrically connected to the first sub-pixel electrode 41, a second transistor T2 electrically connected to the second sub-pixel electrode, and a third transistor T3 electrically connected to one of the first transistor T1 and the second transistor T2; the first sub-pixel electrode 41 and the first common trace 25 are located on the same side of the gate line 2, and the second sub-pixel electrode 41 is electrically connected to the first common trace 25 extending along the first direction X, and the second common trace 26 is electrically connected to the second common trace 26 extending along the first direction X. Electrode 42 and the second common trace 26 are located on the same side of gate line 2. For example, as in 1A, the first sub-pixel electrode 41 and the first common trace 25 are both located on the upper side of gate line 2, and the second sub-pixel electrode 42 and the second common trace 26 are both located on the lower side of gate line 2. In the sub-pixel row, the orthogonal projections of the third transistors T3 of multiple sub-pixels P onto the substrate 1 are alternately distributed in the first region S1 and the second region S2. The first region S1 includes: gate line 2, the first common trace 25, and the region between gate line 2 and the first common trace 25. The second region S2 includes: gate line 2, the second common trace 26, and the region between gate line 2 and the second common trace 26.

[0111] In this embodiment of the present disclosure, the third transistors T3 of the multiple sub-pixels P are alternately distributed in the first region S1 and the second region S2 on the orthogonal projection of the substrate 1. In this way, the third transistors T3 are alternately electrically connected to the first common line 25 and the second common line 26, thereby realizing the alternating arrangement of the main pixel part PA and the auxiliary pixel part PB.

[0112] Specifically, the orthographic projection of the first transistor T1 onto the substrate 1 can be distributed in the first region S1 (the first region S1 may include: gate line 2, first common trace 25, and the region between gate line 2 and first common trace 25). That is, the orthographic projection of the first transistor T1 onto the substrate 1 may overlap with the orthographic projection of the gate line 2 onto the substrate 1, overlap with the orthographic projection of the first common trace 25 onto the substrate 1, and overlap with the orthographic projection of the region between gate line 2 and first common trace 25 onto the substrate 1. The orthographic projection of the second transistor T2 onto the substrate 1 can be distributed in the second region S2 (the second region S2 may include: gate line 2, second common trace 26, and the region between gate line 2 and second common trace 26). That is, the orthographic projection of the first transistor T1 onto the substrate 1 may overlap with the orthographic projection of the gate line 2 onto the substrate 1, overlap with the orthographic projection of the second common trace 26 onto the substrate 1, and overlap with the orthographic projection of the region between gate line 2 and second common trace 26 onto the substrate 1.

[0113] It is understandable that, along the first direction X, the first sub-pixel electrode 41 of each sub-pixel P is a sub-pixel electrode located on one side of the gate line 2, for example, all of them are located on the upper side of the gate line 2, and the second sub-pixel electrode 42 is a sub-pixel electrode located on the other side of the gate line 2, for example, all of them are located on the lower side of the gate line 2; and along the first direction X, the positions of the main pixel portion PA of the sub-pixel P are alternately distributed, that is, for two adjacent main pixel portions PA of the sub-pixel P along the first direction X, one is located on the upper side of the gate line 2 and the other is located on the lower side of the gate line 2. Similarly, along the first direction X, the positions of the auxiliary pixel portions PB of the sub-pixel P are also alternately distributed, that is, for two adjacent auxiliary pixel portions PB of the sub-pixel P along the first direction X, one is located on the upper side of the gate line 2 and the other is located on the lower side of the gate line 2.

[0114] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, on the sub-pixel row, the third transistor T3 of multiple sub-pixels P is alternately electrically connected to the first common trace 25 and the second common trace 26. This achieves an alternating arrangement of the main pixel section PA and the auxiliary pixel section PB. Specifically, the third transistor T3 can be electrically connected to the first common trace 25 or the second common trace 26 through a third via K3.

[0115] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, the first transistor T1 includes: a first transistor gate (not shown in the figure, but may specifically be a portion of multiplexed gate line 2), a first transistor terminal T1a, and a first transistor terminal T1b; the second transistor T2 includes: a second transistor gate (not shown in the figure, but may specifically be a portion of multiplexed gate line 2), a second transistor terminal T2a, and a second transistor terminal T2b; the third transistor T3 includes: a third transistor gate (not shown in the figure, but may specifically be a portion of multiplexed gate line 2), a third transistor terminal T3a, and a third transistor terminal T3b; in the sub-pixel row, the first transistor terminal T1b and the second transistor terminal T2b of multiple sub-pixels P are alternately multiplexed as the third transistor terminal T3a.

[0116] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, the plurality of first transistor second electrodes T1b include: a first type of second electrode T1bX and a second type of second electrode T1bY; the first type of second electrode T1bX includes: a first type of first portion T1bX1 extending along the first direction X, a first type of second portion T1bX2 extending from one end of the first type of first portion T1bX toward the gate line 2, and a first type of third portion T1bX3 extending from the other end of the first type of first portion T1bX toward the gate line 2; the second type of second electrode T1bY includes: a second type of first portion T1bY1 extending along the first direction X, and a second type of second portion T1bY2 extending from one end of the second type of first portion T1bY1 toward the gate line; the first type of second electrode and the second type of second electrode are alternately distributed on the sub-pixel row.

[0117] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4FAs shown, the second transistor T2b includes: a third type second electrode T2bX and a fourth type second electrode T2bY; the third type second electrode T2bX includes: a third type first part T2bX1 extending along the first direction X, a third type second part T2bX2 extending from one end of the third type first part T2bX1 toward the gate line 2, and a third type third part T2bX3 extending from the other end of the third type first part T2bX1 toward the gate line 2; the fourth type second electrode T2bY includes: a fourth type first part T2bY1 extending along the first direction X, and a fourth type second part T2bY2 extending from one end of the fourth type first part T2bY1 toward the gate line 2; the third type second electrode and the fourth type second electrode are alternately distributed on the sub-pixel row.

[0118] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, the first common trace 25 has a first common protrusion 25a facing the gate line 2. The orthographic projection of the second electrode T3b of the third transistor on the substrate 1 overlaps with the orthographic projection of the first common protrusion 25a on the substrate 1. The first common trace 25 can be connected to the second electrode T3b of the third transistor through the third via K3. The second common trace 26 has a second common protrusion 26a facing the gate line 2. The orthographic projection of the second electrode T3b of the third transistor on the substrate 1 overlaps with the orthographic projection of the second common protrusion 26a on the substrate. In the overlapping area, the second common trace 26 can be connected to the second electrode T3b of another third transistor through another third via K3 via the second common protrusion 26a; on the sub-pixel row, there is a sub-pixel P between adjacent first common protrusions 25a, that is, a first common protrusion 25a can be set every other sub-pixel P; there is a sub-pixel between adjacent second common protrusions 26a, that is, a second common protrusion 26a can be set every other sub-pixel P. The first common protrusions 25a and the second common protrusions 26a are staggered, specifically, as follows: Figure 1B In the middle, the first straight line k1 extending along the second direction Y and passing through the center of the first common convex part 25a does not coincide with the second straight line k2 extending along the second direction Y and passing through the center of the first common convex part 25a.

[0119] In one possible implementation, see Figure 1F and Figure 1H As shown, Figure 1H for Figure 1AThe cross-sectional diagram along the dashed line EF shows that the array substrate may also include a lap electrode 43. Optionally, the lap electrode 43 can be disposed on the same layer and made of the same material as the pixel electrode. The third via K3 can be a half-via, partially exposing the first common trace 25 (or the second common trace 26) and partially exposing the second electrode T3b of the third transistor. The lap electrode 43 is partially in contact with the first common trace 25 (or the second common trace 26) and partially with the second electrode T3b of the third transistor at the third via K3, thereby electrically connecting the first common trace 25 (or the second common trace 26) and the second electrode T3b of the third transistor through the lap electrode 43. Specifically, the design of the third via K3 as a half-via allows the third via K3 to form a stepped structure inside, which plays a role in guiding the alignment liquid and avoiding the moiré effect on the screen.

[0120] For details, see Figure 10 As shown, Figure 10 It can be Figure 1AEquivalent circuit diagram at the second sub-pixel P from the left in the middle. Here, S is the data line on the left side of the pixel, that is, the signal line that transmits the data signal to the current sub-pixel P, that is, the data line electrically connected to the current sub-pixel P. S_other is the data line on the right side of the pixel and also the data line of the horizontally adjacent pixel. Pixel circuit: It may include the first transistor T1, the second transistor T2, the third transistor T3, the first capacitor Cpd_bright, the second capacitor Cgp_bright, the third capacitor Cst_bright, the fourth capacitor Clc_bright, the fifth capacitor Cpp(n + 1), the sixth capacitor Cpd_other_bright, the seventh capacitor Cpd_dark, the eighth capacitor Cgp_dark, the ninth capacitor Cst_dark, the tenth capacitor Clc_dark, the eleventh capacitor Cpp(n - 1), the twelfth capacitor Cpd_other_dark, and the thirteenth capacitor Cgcs. Among them, a first capacitor Cpd_bright is formed between the first sub-pixel electrode 41 and the data line 3, a second capacitor Cgp_bright is formed between the first sub-pixel electrode 41 and the gate line 2, a third capacitor Cst_bright can be formed in the overlapping area between the first sub-pixel electrode 41 and the first common trace 25, a fourth capacitor Clc_bright can be formed between the first sub-pixel electrode 41 and the common electrode on the opposite substrate side, a fifth capacitor Cpp(n + 1) can be formed between the first sub-pixel electrode 41 of the current sub-pixel P and the second sub-pixel electrode 42 of the previous sub-pixel P, and a sixth capacitor Cpd_other_bright can be formed between the first sub-pixel electrode 41 and the adjacent data line 3. A seventh capacitor Cpd_dark is formed between the second sub-pixel electrode 42 and the data line 3, an eighth capacitor Cgp_dark is formed between the second sub-pixel electrode 42 and the gate line 2, a ninth capacitor Cst_dark can be formed in the overlapping area between the second sub-pixel electrode 42 and the second common trace 26, a tenth capacitor Clc_dark can be formed between the second sub-pixel electrode 42 and the common electrode on the opposite substrate side, an eleventh capacitor Cpp(n - 1) can be formed between the second sub-pixel electrode 42 of the current sub-pixel P and the first sub-pixel electrode 41 of the next sub-pixel P, and a twelfth capacitor Cpd_other_dark can be formed between the second sub-pixel electrode 42 and the adjacent data line 3. A thirteenth capacitor Cgcs can be formed in the overlapping area between the gate line 2 and the second pole T3b of the third transistor. Specifically, as shown in Figure 1A and Figure 11 Since the third transistor T3 is connected to the second transistor T2, the voltage applied to the second sub-pixel electrode 42 will be partially divided into the thirteenth capacitor Cgcs through the third transistor T3, and / or on the transmitted common trace (the first common trace 25 or the second common trace 26), so that the voltage obtained by the second sub-pixel electrode 42 is lower than the voltage obtained by the first sub-pixel electrode 41. As a result, the light emission brightness of the second sub-pixel electrode 42 is less than the light emission brightness of the first sub-pixel electrode 41. The second sub-pixel electrode 42 serves as the auxiliary pixel portion PB, and the first sub-pixel electrode 41 serves as the main pixel portion PA. For adjacent sub-pixels P (such as Figure 1AThe first sub-pixel P from the left in the middle, because the third transistor T3 is connected to the first transistor T1, the voltage applied to the first sub-pixel electrode 41 will be distributed through the third transistor T3 to the gate line 2 and the second electrode T3b of the third transistor to form the fourteenth capacitor ( Figure 11 (not shown in the image) This causes the voltage received by the first sub-pixel electrode 41 to be lower than the voltage received by the second sub-pixel electrode 42, and thus the light emission brightness of the first sub-pixel electrode 41 is less than the light emission brightness of the second sub-pixel electrode 42. The first sub-pixel electrode 41 serves as the auxiliary pixel part PB, and the second sub-pixel electrode 42 serves as the main pixel part PA, thereby forming an alternating light and dark distribution effect on the sub-pixel row.

[0121] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, the array substrate may also include a third common line 27 that electrically connects the first common line 25 and the second common line 26. The orthographic projection of the third common line 27 onto the substrate 1 is located on both sides of the orthographic projection of the data line 3 onto the substrate 1, which can improve the coupling capacitance between the data line 3 and the first sub-pixel electrode 41 (or the second sub-pixel electrode 42).

[0122] In one possible implementation, see Figures 1A-1F As shown, Figures 2A-2F As shown, Figures 3A-3F As shown, Figures 4A-4F As shown, the first sub-pixel electrode 41 is an integral structure, and the second sub-pixel electrode 42 is an integral structure.

[0123] In one possible implementation, see Figure 1F As shown, Figure 2F As shown, Figure 3F As shown, Figures 5A-5F As shown, the first sub-pixel electrode 41 includes a first electrode portion P1 and a second electrode portion P2 sequentially distributed along the second direction Y; the second sub-pixel electrode 42 includes a third electrode portion P3 and a fourth electrode portion P4 sequentially distributed along the second direction Y; the first electrode portion P1 has a plurality of first slits F1, the second electrode portion P2 has a plurality of second slits F2, the third electrode portion P3 has a plurality of third slits F3, and the fourth electrode portion P4 has a plurality of fourth slits F4; in one possible embodiment, see [reference needed]. Figure 1F As shown, Figure 2F As shown, Figure 3F As shown, the extension direction of the first slit F1 is the same as that of the second slit F2, and the extension direction of the third slit F3 is the same as that of the fourth slit F4. The extension direction of the first slit F1 is different from that of the third slit F3. In one possible implementation, see [link to implementation details]. Figure 5FAs shown, the extension direction of the first slit F1 is the same as that of the fourth slit F4, the extension direction of the second slit F2 is the same as that of the third slit F3, and the extension direction of the first slit F1 is different from that of the second slit F2.

[0124] For details, see Figure 1F As shown, Figure 2F As shown, Figure 3F As shown, the angle formed between the extension direction of the first slit F1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed between the extension direction of the second slit F2 and the first direction X can be 40° to 50°, for example, 45°; the angle formed between the extension direction of the third slit F3 and the first direction X can be 130° to 140°, for example, 135°; the angle formed between the extension direction of the fourth slit F4 and the first direction X can be 130° to 140°, for example, 135°.

[0125] For details, see Figure 5F As shown, the angle formed between the extension direction of the first slit F1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed between the extension direction of the second slit F2 and the first direction X can be 130° to 140°, for example, 135°; the angle formed between the extension direction of the third slit F3 and the first direction X can be 130° to 140°, for example, 135°; and the angle formed between the extension direction of the fourth slit F4 and the first direction X can be 40° to 50°, for example, 45°.

[0126] In one possible implementation, see Figure 1F As shown, Figure 2F As shown, a fifth slit F5 is provided between the first electrode portion P1 and the second electrode portion P2, and the extension direction of the fifth slit F5 is different from the extension direction of the first slit F1; a sixth slit F6 is provided between the third electrode portion P3 and the fourth electrode portion P4, and the extension direction of the sixth slit F6 is different from the extension direction of the third slit F3. In this embodiment of the present disclosure, the fifth slit F5 between the first electrode portion P1 and the second electrode portion P2 can improve the horizontal dark lines in the center of the first sub-pixel electrode 41; the sixth slit F6 between the third electrode portion P3 and the fourth electrode portion P4 can improve the horizontal dark lines in the center of the second sub-pixel electrode 42, thereby improving the aperture ratio of the display panel.

[0127] In one possible implementation, see Figure 1F As shown, the fifth slit F5 extends along the second direction Y, and the sixth slit F6 extends along the second direction Y.

[0128] In one possible implementation, see Figure 2FAs shown, the fifth slit F5 extends in the same direction as the third slit F3, and the sixth slit F6 extends in the same direction as the first slit F1.

[0129] In one possible implementation, see Figure 3F As shown, the side of the first electrode portion P1 facing the second electrode portion P2 is a semi-closed structure, and the side of the second electrode portion P2 facing the first electrode portion P1 is also a semi-closed structure. The closed position of the first electrode portion P1 facing the second electrode portion P2 is opposite to the open position of the second electrode portion P2 facing the first electrode portion P1, and the open position of the first electrode portion P1 facing the second electrode portion P2 is opposite to the closed position of the second electrode portion P2 facing the first electrode portion P1. The closed position of the second electrode portion P2 facing the first electrode portion P1 connects with the closed position of the first electrode portion P1 facing the second electrode portion P2, and this connection point is located in the middle region of the first electrode portion P1 (or the second electrode portion P2) in the first direction X.

[0130] In one possible implementation, see Figures 4A-4F As shown, the first slit F1 of the first electrode part P1 and the second slit F2 of the second electrode part P2 are integrally formed; the third slit F3 of the third electrode part P3 and the fourth slit F4 of the fourth electrode part P4 are integrally formed.

[0131] In one possible implementation, see Figures 5A-5F As shown, the array substrate includes: a gate line 2 extending along a first direction X, a data line 3 extending along a second direction Y, and a first common trace 25 distributed on one side of the gate line 2, and a second common trace 26 distributed on the other side of the gate line 2; the sub-pixel P includes: a first transistor T1, a second transistor T2, a third transistor T3 electrically connected to one of the first transistor T1 and the second transistor T2, and a first electrode portion P1, a second electrode portion P2, a third electrode portion P3, and a fourth electrode portion P4 sequentially distributed along the second direction Y; the first electrode portion P1 is electrically connected to one of the third electrode portion P3 and the fourth electrode portion P4 to form a first connecting sub-pixel electrode P11, for example, as Figure 5A In this configuration, the first electrode portion P1 is electrically connected to the fourth electrode portion P4 to form the first connecting sub-pixel electrode P11; the second electrode portion P2 is electrically connected to another of the third electrode portion P3 and the fourth electrode portion P4 to form the second connecting sub-pixel electrode P12, for example, as shown below. Figure 5AIn the process, the second electrode portion P2 and the third electrode portion P3 are electrically connected to form the second connecting sub-pixel electrode P12; wherein, in the sub-pixel row, the first connecting sub-pixel electrodes P11 of multiple sub-pixels P are alternately electrically connected to the first transistor T1 and the second transistor T2; the second connecting sub-pixel electrodes P12 of multiple sub-pixels P are alternately electrically connected to the first transistor T1 and the second transistor T2; and in the same sub-pixel, the first connecting sub-pixel electrode P11 and the second connecting sub-pixel electrode P12 are electrically connected to different transistors.

[0132] In this embodiment, the connection position of the third transistor T3 is fixed. By adjusting the connection relationship between the first connecting sub-pixel electrode P11 and the first transistor T1 and the second transistor T2, and the connection relationship between the second connecting sub-pixel electrode P1 and the first transistor T1 and the second transistor T2, the first connecting sub-pixel electrode P11 can be made to be the main pixel part PA or the auxiliary pixel part PB, and the second connecting sub-pixel electrode P12 can be made to be the main pixel part PA or the auxiliary pixel part PB. Furthermore, the first connecting sub-pixel electrode P11 is alternately electrically connected to the first transistor T1 and the second transistor T2, and the second connecting sub-pixel electrodes P12 of the multiple sub-pixels P are alternately electrically connected to the first transistor T1 and the second transistor T2, so that the main pixel part PA and the auxiliary pixel part PB can be arranged alternately, thereby achieving the effect of both improving transmittance and improving color shift.

[0133] Specifically, the orthographic projection of the first transistor T1 onto the substrate 1 can be distributed in the first region S1 (the first region S1 may include: gate line 2, first common trace 25, and the region between gate line 2 and first common trace 25). That is, the orthographic projection of the first transistor T1 onto the substrate 1 may overlap with the orthographic projection of the gate line 2 onto the substrate 1, overlap with the orthographic projection of the first common trace 25 onto the substrate 1, and overlap with the orthographic projection of the region between gate line 2 and first common trace 25 onto the substrate 1. The orthographic projection of the second transistor T2 onto the substrate 1 can be distributed in the second region S2 (the second region S2 may include: gate line 2, second common trace 26, and the region between gate line 2 and second common trace 26). That is, the orthographic projection of the first transistor T1 onto the substrate 1 may overlap with the orthographic projection of the gate line 2 onto the substrate 1, overlap with the orthographic projection of the second common trace 26 onto the substrate 1, and overlap with the orthographic projection of the region between gate line 2 and second common trace 26 onto the substrate 1.

[0134] Specifically, in a sub-pixel row, the third transistor T3 can be electrically connected only to the second transistor T2, such as... Figure 5A As shown; in another possible implementation, the third transistor T3 may also be electrically connected only to the first transistor T1.

[0135] In one possible implementation, see Figures 5A-5FAs shown, the first electrode portion P1 is electrically connected to the fourth electrode portion P4, and the second electrode portion P2 is electrically connected to the third electrode portion P3. In another possible embodiment, see... Figures 6A-6F As shown, the first electrode part P1 is electrically connected to the third electrode part P3, and the second electrode part P2 is electrically connected to the fourth electrode part P4.

[0136] In one possible implementation, see Figures 5A-5F As shown, the array substrate further includes a first connecting portion P5 extending along the second direction Y, and a second connecting portion P6; one end of the first connecting portion P5 is electrically connected to the first electrode portion P1, and the other end is electrically connected to the fourth electrode portion P4; one end of the second connecting portion P6 is electrically connected to the second electrode portion P2, and the other end is electrically connected to the third electrode portion P3. This achieves the electrical connection between the first electrode portion P1 and the fourth electrode portion P4, and the electrical connection between the second electrode portion P2 and the third electrode portion P3.

[0137] For details, see Figures 5A-5F As shown, the first connection portion P5 extends along the second direction Y, and its orthographic projection on the substrate 1 is located on the side of the second electrode portion P2 and the third electrode portion P3; the second connection portion P5 extends along the second direction Y, and its orthographic projection on the substrate 1 is located in the region between the first common trace 25 and the second common trace 26.

[0138] In one possible implementation, see Figures 5A-5F As shown, the array substrate also includes: a first connection protrusion P7 connected to the first connection portion P5 and protruding toward the third transistor T3.

[0139] On the sub-pixel row, the first connecting protrusion P7 is alternately electrically connected to the first transistor T1 and the second transistor T2. This achieves the alternating electrical connection of the first connecting sub-pixel electrode P11 and the second connecting sub-pixel electrode P12 to the first transistor T1 and the second transistor T2.

[0140] In one possible implementation, see Figures 5A-5F As shown, on the sub-pixel row, the outer edge extensions of adjacent first connecting protrusions P7 along the first direction X do not coincide.

[0141] In one possible implementation, see Figures 6A-6F As shown, the first electrode portion P1 is electrically connected to the third electrode portion P3 to form the first connecting sub-pixel electrode P11; the second electrode portion P2 is electrically connected to the fourth electrode portion P4 to form the second connecting sub-pixel electrode P12.

[0142] In one possible implementation, see Figures 6A-6FAs shown, the array substrate further includes: a third connecting portion P8 extending along the second direction Y, and a fourth connecting portion P9; one end of the third connecting portion P8 is electrically connected to the first electrode portion P1, and the other end is electrically connected to the side of the third electrode portion P3 facing the second electrode portion P2; one end of the fourth connecting portion P9 is electrically connected to the second electrode portion P2, and the other end is electrically connected to the fourth electrode portion P4. Optionally, combined with Figure 6A Figure 6D ,and Figure 6F As shown, the orthographic projection of the fourth connection P9 onto the substrate 1 overlaps with the second electrode T2b of the second transistor; the orthographic projection of the fourth connection P9 onto the substrate 1 at least partially overlaps with the orthographic projection of the third common trace 27 onto the substrate 1; and the orthographic projection of the third connection P8 onto the substrate 1 overlaps with the orthographic projection of the third common trace 27 onto the substrate 1.

[0143] In one possible implementation, combining Figure 6A Figure 6D ,and Figure 6F As shown, in a sub-pixel P (such as...) Figure 6F In the left sub-pixel P), one end of the third connecting portion P8 is electrically connected to the end of the first electrode portion P1 facing the second electrode portion P2, and it passes around one side of the second electrode portion P2 and is electrically connected to the end of the third electrode portion P3 facing the second electrode portion P2. That is, the third connecting portion P8 is located on the right edge of the sub-pixel P; in another adjacent sub-pixel P (such as... Figure 6F In the middle sub-pixel P), one end of the third connecting part P8 is electrically connected to the end of the first electrode part P1 facing the second electrode part P2, and passes through the area between the first transistor T1 and the third transistor T3, and passes around one side of the second electrode part P2 to be electrically connected to the third electrode part P3. That is, the third connecting part P8 is located on the left edge of the sub-pixel P.

[0144] In one possible implementation, combining Figure 6A Figure 6D ,and Figure 6F As shown, in a sub-pixel P (such as...) Figure 6F In the left sub-pixel P), one end of the fourth connecting part P9 is electrically connected to the end of the second electrode part P2 facing the third electrode part P3, and passes through the area between the first transistor T1 and the third transistor T3, and around one side of the third electrode part P3 to be electrically connected to the fourth electrode part P4. That is, the fourth connecting part P9 is located on the left edge of the sub-pixel P; in another adjacent sub-pixel P (such as... Figure 6F In the middle sub-pixel P, one end of the fourth connecting part P9 is electrically connected to the end of the second electrode part P2 facing the third electrode part P3, and is electrically connected to the end of the fourth electrode part P4 facing the third electrode part P3 around one side of the third electrode part P3. That is, the fourth connecting part P9 is located on the right edge of the sub-pixel P.

[0145] For details, see Figures 6A-6F As shown, the third connection portion P8 extends along the second direction Y, and its orthographic projection on the substrate 1 is located on the side of the second electrode portion P2; the fourth connection portion P9, its orthographic projection on the substrate 1, is partially located in the region between the first common trace 25 and the second common trace 26, and partially located on the side of the third electrode portion P3.

[0146] In one possible implementation, see Figure 7 As shown, the plurality of sub-pixels includes: a sub-pixel column extending along the second direction Y and arranged along the first direction X; in the sub-pixel column, the main pixel portion PA and the auxiliary pixel portion PB are arranged alternately. In this embodiment of the present disclosure, the alternating arrangement of the main pixel portion PA and the auxiliary pixel portion PB in the sub-pixel column can form a 2P8D effect of mutual compensation of brightness and darkness in two sub-pixels in the first direction X, and at the same time, a mutual compensation of brightness and darkness effect can also be formed in the second direction Y, thereby achieving the effect of both improving transmittance and improving color shift.

[0147] In one possible implementation, see Figure 8 As shown, the plurality of sub-pixels includes: a sub-pixel column extending along the second direction Y and arranged along the first direction; in the sub-pixel column, two main pixel portions PA and two auxiliary pixel portions PB are arranged alternately. In this embodiment of the present disclosure, the alternating arrangement of two main pixel portions PA and two auxiliary pixel portions PB in the sub-pixel column can also form a 2P8D effect of mutual brightness and darkness compensation in the two sub-pixels in the first direction X, while the second direction Y can also form a brightness and darkness compensation effect, thereby achieving the effect of both improving transmittance and improving color shift.

[0148] In one possible implementation, see Figures 9A-9H As shown, the array substrate further includes: a first electrode layer 7; the first electrode layer 7 includes: a first electrode connection portion 71, a first cutout 72, and a second cutout 73; the orthographic projection of the first cutout 72 onto the substrate 1 at least partially overlaps with the orthographic projection of the first sub-pixel electrode 41 onto the substrate 1; the orthographic projection of the second cutout 73 onto the substrate 1 at least partially overlaps with the orthographic projection of the second sub-pixel electrode 42 onto the substrate 1. In this embodiment of the present disclosure, for a VA display panel with a pixel electrode layer on the array substrate and a common electrode layer on the opposing substrate, the pressure difference at the locations with the first cutout 72 and the second cutout 73 within the same pixel electrode is different from that at the locations without the first cutout 72 and the second cutout 73, which allows for more uniform liquid crystal twisting, reduces dark lines corresponding to the pixel electrode, reduces the width of the black matrix, and improves the transmittance of the display panel; in addition, besides the vertical electric field formed by the pixel electrode and the common electrode, the pixel electrode and the first electrode layer 7 form a lateral electric field within the array substrate, which can increase the deflection direction of the liquid crystal and improve the color shift problem of the display panel.

[0149] In one possible implementation, see Figures 9A-9H As shown, the first electrode layer 7 further includes a third cutout 74, so that the first sub-pixel electrode 41 (or the second sub-pixel electrode 42, or the first electrode portion P1, or the second electrode portion P2, or the third electrode portion P3, or the fourth electrode portion P4) above the first electrode layer 7 is connected to the second electrode of the first transistor T1b or the second electrode of the second transistor T2b below the first electrode layer 7 at the third cutout 74.

[0150] Specifically, the first electrode layer 7 can be located between the substrate 1 and the pixel electrode layer. Specifically, the first electrode layer 7 can have the same signal applied as the common electrode layer of the opposing substrate. The first electrode layer 7 can specifically be a transparent electrode layer, and the material of the first electrode layer 7 can specifically be indium tin oxide.

[0151] In one possible implementation, see Figures 9A-9G As shown, the orthographic projection of the first electrode connection portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1. In this embodiment of the present disclosure, the orthographic projection of the first electrode connection portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1. The coupling capacitance between the pixel electrode and the data line 3 can be shielded by the first electrode connection portion 71, which can avoid setting the third common trace 27, thereby increasing the transmittance of the display panel.

[0152] In one possible implementation, it could also be in Figure 5A , Figure 6A The array substrate structure shown has a first electrode layer 7. The orthographic projection of the first cutout 72 of the first electrode layer 7 onto the substrate can overlap with the orthographic projections of the first electrode portion P1 and the second electrode portion P2 onto the substrate 1. The orthographic projection of the second cutout 73 of the first electrode layer 7 onto the substrate can overlap with the orthographic projections of the third electrode portion P3 and the fourth electrode portion P4 onto the substrate 1.

[0153] Combination Figure 1G , Figure 2G , Figure 3G , Figure 4G , Figure 5G and Figure 9J As shown, this disclosure embodiment performed optical simulations on different array substrate structures. By comparing the horizontal dark fringes in the center of the sub-pixels, it can be clearly seen that for those without the first electrode layer 7... Figure 1G , Figure 2G , Figure 3G , Figure 4G , Figure 5G The corresponding array substrate structure, wherein, Figure 1A The structure corresponding to this type of structure has the highest transmittance, with a simulated value of 6.34%; while for the corresponding array substrate structure with the first electrode layer 7 added, such as Figure 9JAs shown, the transmittance is higher, with a simulated value of 6.95%.

[0154] Based on the same inventive concept, this disclosure also provides a display panel, see [link to relevant documentation]. Figure 11 As shown, the array includes an array substrate as provided in the embodiments of this disclosure, and also includes a counter substrate disposed opposite to the array substrate, wherein a common electrode layer 8 is disposed on the side of the counter substrate facing the array substrate.

[0155] Specifically, the first common trace 25, the second common trace 26, the third common trace 27, and the first electrode layer 7 can be the same signal loaded as the common electrode layer 8 of the opposing substrate.

[0156] In one possible implementation, combining Figures 9A-9G as well as Figure 11 As shown, the data line 3 can be located on the side of the gate line 2 away from the substrate 1, the first electrode layer 7 can be located on the side of the data line 3 away from the gate line 2, and the pixel electrode (including the first electrode portion P1, the second electrode portion P2, the third electrode portion P3, and the fourth electrode portion P4) can be located on the side of the first electrode layer 7 away from the data line 3. A gate insulating layer can also be provided between the layer where the gate line 2 is located and the layer where the data line 3 is located. An active layer can also be provided between the gate insulating layer and the data line 3 (the active layer can include an active pattern 5, and the active layer material can be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which are not limited here). A first insulating layer 91 can also be provided between the data line 3 and the first electrode layer 7, and a second insulating layer 92 can be provided between the first electrode layer 7 and the pixel electrode.

[0157] In one possible implementation, combining Figures 9A-9I as well as Figure 11 As shown, the display panel can also be provided with a black matrix 6. The orthogonal projection of the black matrix 6 onto the substrate 1 can cover the orthogonal projection of the gate line 2 onto the substrate 1, and also cover the orthogonal projection of the data line 3 onto the substrate 1. Specifically, the opposing substrate can include an opposing substrate 80, and the black matrix 6 can be located between the opposing substrate 80 and the common electrode layer 8. Figure 11 (Not shown in the image).

[0158] In one possible implementation, combining Figure 11As shown, the first electrode layer 7 is located on the side of the pixel electrode (including the first electrode portion P1, the second electrode portion P2, the third electrode portion P3, and the fourth electrode portion P4) away from the opposing substrate. In this common embodiment, the first electrode layer 7, located on the side of the pixel electrode away from the opposing substrate, can isolate (or shield) the first overlap capacitance between the pixel electrode and the gate line 2 and the second overlap capacitance between the pixel electrode and the data line 3, greatly reducing the risk of crosstalk. Simultaneously, the presence of the first electrode layer 7 reduces the distance between the pixel electrodes, causing overlap between the pixel electrode and the gate line 2, and overlap between the pixel electrode and the data line 3, reducing the risk of liquid crystal leakage. This reduces the width of the black matrix, increases the pixel aperture ratio, and improves the pixel transmittance.

[0159] Based on the same inventive concept, this disclosure also provides a display device, which includes a display panel as provided in the embodiments of this disclosure. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.

[0160] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0161] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0162] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; A plurality of sub-pixels are located on one side of the substrate. The plurality of sub-pixels include: a row of sub-pixels extending along a first direction and arranged along a second direction; at least one of the sub-pixels includes: a main pixel portion and an auxiliary pixel portion distributed along the second direction, wherein the brightness of the main pixel portion is greater than the brightness of the auxiliary pixel portion, and the main pixel portion and the auxiliary pixel portion are alternately arranged in the sub-pixel row; the sub-pixel includes: a first sub-pixel electrode, a second sub-pixel electrode, a first transistor, a second transistor, and a third transistor; A grid line extending along the first direction; A data cable extending along the second direction; The first common trace is distributed on one side of the gate line; The second common trace is distributed on the other side of the gate line; The first transistor includes: a first transistor gate, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor gate, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor gate, a third transistor first electrode, and a third transistor second electrode; on the sub-pixel row, the first transistor second electrode and the second transistor second electrode of a plurality of sub-pixels are alternately multiplexed as the third transistor first electrode; The plurality of first transistor second electrodes include: a first type of second electrode and a second type of second electrode; the first type of second electrode includes: a first type of first portion extending along the first direction, a first type of second portion extending from one end of the first type of first portion toward the gate line, and a first type of third portion extending from the other end of the first type of first portion toward the gate line; the second type of second electrode includes: a second type of first portion extending along the first direction, and a second type of second portion extending from one end of the second type of first portion toward the gate line; the first type of second electrode and the second type of second electrode are alternately distributed on the sub-pixel row; The second transistor's second electrode includes: a third type of second electrode and a fourth type of second electrode; the third type of second electrode includes: a third type of first portion extending along the first direction, a third type of second portion extending from one end of the third type of first portion toward the gate line, and a third type of third portion extending from the other end of the third type of first portion toward the gate line; the fourth type of second electrode includes: a fourth type of first portion extending along the first direction, and a fourth type of second portion extending from one end of the fourth type of first portion toward the gate line; the third type of second electrode and the fourth type of second electrode are alternately distributed on the sub-pixel row.

2. The array substrate as claimed in claim 1, wherein, The first transistor is electrically connected to the first sub-pixel electrode, the second transistor is electrically connected to the second sub-pixel electrode, and one of the first transistor and the second transistor is electrically connected to the third transistor; the first sub-pixel electrode and the first common trace are located on the same side of the gate line, and the second sub-pixel electrode and the second common trace are located on the same side of the gate line. On the sub-pixel row, the orthographic projections of the third transistors of the plurality of sub-pixels on the substrate are alternately distributed in a first region and a second region; wherein, the first region includes: the gate line, the first common trace, and the region between the gate line and the first common trace; the second region includes: the gate line, the second common trace, and the region between the gate line and the second common trace.

3. The array substrate as described in claim 1 or 2, wherein, On the sub-pixel row, the third transistors of a plurality of the sub-pixels are alternately electrically connected to the first common trace and the second common trace.

4. The array substrate as claimed in claim 1, wherein, The first common trace has a first common protrusion facing the gate line side, and the orthographic projection of the second electrode of the third transistor on the substrate and the orthographic projection of the first common protrusion on the substrate have an overlapping area; the second common trace has a second common protrusion facing the gate line side, and the orthographic projection of the second electrode of the third transistor on the substrate and the orthographic projection of the second common protrusion on the substrate have an overlapping area. On the sub-pixel row, there is a sub-pixel spaced between adjacent first common protrusions and a sub-pixel spaced between adjacent second common protrusions, and the first common protrusions and the second common protrusions are staggered.

5. The array substrate as claimed in claim 2, wherein, The first sub-pixel electrode is a single-piece structure, and the second sub-pixel electrode is a single-piece structure.

6. The array substrate as claimed in claim 5, wherein, The first sub-pixel electrode includes: a first electrode portion and a second electrode portion sequentially distributed along the second direction; the second sub-pixel electrode includes: a third electrode portion and a fourth electrode portion sequentially distributed along the second direction. The first electrode portion has a plurality of first slits, the second electrode portion has a plurality of second slits, the third electrode portion has a plurality of third slits, and the fourth electrode portion has a plurality of fourth slits; The first slit extends in the same direction as the second slit, the third slit extends in the same direction as the fourth slit, and the first slit extends in a different direction than the third slit.

7. The array substrate as claimed in claim 6, wherein, A fifth slit is also provided between the first electrode portion and the second electrode portion, and the extension direction of the fifth slit is different from the extension direction of the first slit; A sixth slit is also provided between the third electrode portion and the fourth electrode portion, and the extension direction of the sixth slit is different from the extension direction of the third slit.

8. The array substrate as claimed in claim 7, wherein, The fifth slit extends along the second direction, and the sixth slit extends along the second direction.

9. The array substrate as claimed in claim 7, wherein, The fifth slit extends in the same direction as the third slit, and the sixth slit extends in the same direction as the first slit.

10. The array substrate as claimed in claim 6, wherein, The side of the first electrode portion facing the second electrode portion is a semi-closed structure, and the side of the second electrode portion facing the first electrode portion is a semi-closed structure. The closed position of the first electrode portion facing the second electrode portion is opposite to the open position of the second electrode portion facing the first electrode portion, and the open position of the first electrode portion facing the second electrode portion is opposite to the closed position of the second electrode portion facing the first electrode portion.

11. The array substrate as claimed in claim 6, wherein, The first slit of the first electrode portion is integral with the second slit of the second electrode portion; the third slit of the third electrode portion is integral with the fourth slit of the fourth electrode portion.

12. The array substrate as claimed in claim 1, wherein, One of the first transistor and the second transistor is electrically connected to the third transistor; the sub-pixel includes: a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion distributed sequentially along the second direction; the first electrode portion is electrically connected to one of the third electrode portion and the fourth electrode portion to form a first connecting sub-pixel electrode; the second electrode portion is electrically connected to the other of the third electrode portion and the fourth electrode portion to form a second connecting sub-pixel electrode; In the sub-pixel row, the first connecting sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; the second connecting sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; and in the same sub-pixel, the first connecting sub-pixel electrode and the second connecting sub-pixel electrode are electrically connected to different transistors.

13. The array substrate as claimed in claim 12, wherein, The first electrode portion is electrically connected to the fourth electrode portion, and the second electrode portion is electrically connected to the third electrode portion.

14. The array substrate as claimed in claim 13, wherein, The array substrate further includes: a first connecting portion extending along the second direction, and a second connecting portion; One end of the first connecting portion is electrically connected to the first electrode portion, and the other end is electrically connected to the fourth electrode portion; one end of the second connecting portion is electrically connected to the second electrode portion, and the other end is electrically connected to the third electrode portion.

15. The array substrate as claimed in claim 14, wherein, The array substrate further includes: a first connection protrusion connected to the first connection portion and protruding toward the side of the third transistor; On the sub-pixel row, the first connecting protrusion is alternately electrically connected to the first transistor and the second transistor.

16. The array substrate as claimed in claim 15, wherein, On the sub-pixel row, the outer edge extensions of adjacent first connecting protrusions along the first direction do not coincide.

17. The array substrate as claimed in claim 12, wherein, The first electrode portion is electrically connected to the third electrode portion, and the second electrode portion is electrically connected to the fourth electrode portion.

18. The array substrate as claimed in claim 17, wherein, The array substrate further includes: a third connecting portion extending along the second direction, and a fourth connecting portion; The third connection portion is projected onto the substrate on the same side as the first sub-pixel electrode on the substrate, and one end is electrically connected to the first electrode portion, while the other end is electrically connected to the side of the third electrode portion facing the second electrode portion. One end of the fourth connecting part is electrically connected to the second electrode part, and the other end is electrically connected to the fourth electrode part.

19. The array substrate as claimed in claim 1, wherein, The plurality of sub-pixels includes: a sub-pixel column extending along the second direction and arranged along the first direction; in the sub-pixel column, the main pixel portion and the auxiliary pixel portion are arranged alternately.

20. The array substrate as claimed in claim 1, wherein, The plurality of sub-pixels includes: a sub-pixel column extending along the second direction and arranged along the first direction; in the sub-pixel column, two main pixel portions and two auxiliary pixel portions are arranged alternately.

21. The array substrate as claimed in claim 2, wherein, The array substrate further includes: a first electrode layer; the first electrode layer includes: a first electrode connection portion, a first cutout, and a second cutout; The orthographic projection of the first cutout on the substrate at least partially overlaps with the orthographic projection of the first sub-pixel electrode on the substrate; the orthographic projection of the second cutout on the substrate at least partially overlaps with the orthographic projection of the second sub-pixel electrode on the substrate.

22. The array substrate as claimed in claim 21, wherein, The orthographic projection of the first electrode connection portion onto the substrate covers the orthographic projection of the data line onto the substrate.

23. A display panel, wherein, The array substrate includes the array substrate as described in any one of claims 1-22, and further includes a counter substrate disposed opposite to the array substrate, wherein the counter substrate has a common electrode layer disposed on the side facing the array substrate.

24. The display panel as claimed in claim 23, wherein, The array substrate further includes a first electrode layer; the first electrode layer and the common electrode layer are loaded with the same signal.

25. A display device, wherein, Includes the display panel as described in claim 23 or 24.

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