Chip data checking method

Abstract

The invention provides a chip data checking method. The chip data checking method comprises the following steps: testing a chip to be tested through a first test site to an Nth test site in sequence; uploading test records and test data of the to-be-tested chip at each test site to a server; the server is in interactive communication connection with the MES system; automatically acquiring data of the server according to a material test program and a test machine recorded by the MES system; the integrity of the test data is ensured by comparing the test number record of the to-be-tested chip with the test data; and comparing the one-time passwords, the identity information and the uniqueness information of the batch identification codes of the plurality of test sites, and managing and controlling the to-be-tested chip through the MES system if a difference exists. According to the invention, through comparative analysis of test records and test data and material management and control through the MES, integrity and reliability of chip data are ensured; and the shipment chips are ensured to be good products with electrical properties and images of multiple tests, the customer complaint risk is reduced, and the reliability of the products is further enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of chip testing, and in particular relates to a chip data checking method. Background Art

[0002] As a core component of modern electronic devices, semiconductor chip quality management is particularly important. Reliable semiconductor chip quality can not only ensure the performance and stability of the equipment, but also help protect the interests of users. Automotive chips have more stringent quality requirements. Each automotive chip has unique identity information. Chips go through many links from production to shipment. There is a possibility of human or machine operation errors in each link. Problems in any link of the chip will affect the user experience. Hardware connection and hardware operation are prone to problems, such as hardware connection errors, incorrect result feedback, incorrect classification of good and defective chips; and hardware operation problems put the actual good chip into the defective area, or put the actual defective chip into the good area, resulting in incorrect chip classification; therefore, the entire chip link needs strict and reasonable inspection. Summary of the invention

[0003] The purpose of the present invention is to provide a chip data inspection method, which ensures the integrity and reliability of chip data through test records and test data comparison analysis, and material control through MES; ensures that the shipped chips are all good electrical performance and image products that have passed multiple tests, reduces the risk of customer complaints, and thereby enhances the reliability of the product.

[0004] The present invention provides a chip data checking method, comprising:

[0005] Testing the chip to be tested sequentially through the first test site to the Nth test site;

[0006] The test records and test data of the chip under test at each test site are uploaded to the server, and the server monitors the test status of the chip under test online; the server is connected to the MES system for interactive communication;

[0007] According to the material test program and test machine recorded by the MES system, the data of the server is automatically obtained; the integrity of the test data is ensured by comparing the test quantity record and test data of the chip to be tested; the one-time passwords, identity information and unique information of batch identification codes of multiple test sites are compared. If there are differences, the chip to be tested is controlled through the MES system.

[0008] Furthermore, the testing process in any one of the N testing sites includes: placing the chip to be tested into an input tray of the testing site, and the testing machine performs image testing and electrical performance testing on the chip to be tested distributed in multiple testing stations; the testing machine includes an image testing machine and an electrical performance testing machine;

[0009] The hardware abnormality of the test site will lead to test data errors; the hardware includes: the test circuits of the sorting machine and the test station, and the test circuits of the test machine and the test station.

[0010] Furthermore, the sorting machine is connected to the test station, and the tester is also connected to the test station. The sorting machine sends instructions to the test station, and the test station starts a test signal to the tester. The tester tests the chip to be tested and feeds back the test results to the sorting machine. The tester and the sorting machine each save test data and test results, and the tester has more detailed test results than the sorting machine.

[0011] Furthermore, the self-checking of the sorting machine and the testing machine in the same testing site specifically includes:

[0012] The sorting machine records the number of the chips to be tested actually tested by each test station and the number of good chips and the number of defective chips among the chips to be tested;

[0013] The testing machine also records the number of the chips to be tested actually tested by each of the testing stations and the number of good chips and the number of defective chips among the chips to be tested;

[0014] The test data and test quantity of the two data sources, the sorting machine and the testing machine, in the same test site are compared and verified. If they match, the hardware is normal; if they do not match, the hardware is abnormal.

[0015] Furthermore, the aforementioned test sites are cross-checked, including:

[0016] Obtain the identity information and test result data of the chip to be tested in the test machines of different test sites; perform a comparison before and after; if the chip to be tested has a good test result at the latter test site, there must be a good result at the former test site; if not, there is an abnormality in the hardware or a human operation error.

[0017] Further, checking whether the image tester and the test station are electrically connected correctly, and checking whether the electrical performance tester and the test station are electrically connected correctly;

[0018] The same test station is connected to the image testing machine and the electrical performance testing machine; the electrical performance testing machine can provide multiple test resources at the same time and connect multiple test stations at a time, and its test station numbers are accumulated in sequence; the image testing machine can only provide one test supply at a time and can only connect one test station at a time, and its test station number is set according to the line connection data line interface address.

[0019] Furthermore, during normal testing, the data of the electrical performance tester are stored in sequence according to the station order, and the data of the image tester are stored according to the data line interface address number; when the same test station tests the same chip to be tested, the electrical performance data are stored in sequence, and the image test data are stored in sequence according to the connected data lines;

[0020] If the connection is wrong, the result corresponding to the test station will record an error, and the error result will be fed back to the sorting machine, and the sorting machine will classify the error chip.

[0021] Furthermore, the first test site to the Nth test site perform tests in series, and the good chips tested by the previous test site flow into the next test site for testing, and the defective chips tested by the previous test site no longer flow into the next test site.

[0022] Furthermore, the first test site to the Nth test site are respectively set at different temperatures to test the chip to be tested.

[0023] Furthermore, the same test site includes a plurality of test stations; the test items of the plurality of test stations are the same; one test station tests one chip to be tested, and the plurality of test stations perform tests simultaneously.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention provides a chip data inspection method, including: testing the chip to be tested sequentially through the first test site to the Nth test site; uploading the test records and test data of the chip to be tested at each test site to the server, and the server monitors the test status of the chip to be tested online; the server is connected to the MES system for interactive communication; according to the material test program and test machine recorded by the MES system, the server data is automatically obtained; by comparing the test quantity record and test data of the chip to be tested, the integrity of the test data is ensured; comparing the one-time passwords, identity information and unique information of batch identification codes of multiple test sites, if there are differences, the chip to be tested is controlled by the MES system. The present invention ensures the integrity and reliability of chip data through comparative analysis of test records and test data, and performs material control through MES; ensures that the shipped chips are all good electrical performance and image products with multiple tests, reduces the risk of customer complaints, and thus enhances the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The figure is a flow chart of a chip data checking method according to an embodiment of the present invention.

[0027] Figure 2 The figure is a principle block diagram of a chip data checking method according to an embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram of test quantity recording and test value data checking in the chip data checking method according to an embodiment of the present invention.

[0029] Figure 4 It is a schematic diagram of checking the electrical performance test channel data and the image performance test channel data in the chip data checking method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0032] The embodiment of the present invention provides a chip data checking method, such as Figure 1 As shown, including:

[0033] Step S1, testing the chip to be tested at the first test site to the Nth test site in sequence;

[0034] Step S2: Upload the test records and test data of the chip under test at each test site to the server, and the server monitors the test status of the chip under test online; the server is connected to the MES system for interactive communication;

[0035] Step S3: Automatically obtain the data from the server according to the material test program and test machine recorded in the MES system; ensure the integrity of the test data by comparing the test quantity record and test data of the chip to be tested; compare the one-time passwords, identity information and unique information of batch identification codes of multiple test sites. If there are differences, control the chip to be tested through the MES system.

[0036] The steps of the chip data checking method according to the embodiment of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Step S1: Figure 2As shown, the chip to be tested is tested in sequence at the first test site to the Nth test site. Due to the needs of the testing process and flow, the chip testing is divided into several test sites. Each test site generates test data in the process of testing the chip. The first test site to the Nth test site are tested in series, and the good chips measured by the previous test site flow into the next test site for testing, and the defective chips measured by the previous test site no longer flow into the next test site. The test conditions and test contents of the first test site to the Nth test site can be set according to actual needs without limitation. Exemplarily, different temperatures can be set for the chip to be tested at the first test site to the Nth test site, for example, the first test site performs a high temperature preset temperature test, the second test site performs a normal temperature preset temperature test, and the third test site performs a low temperature preset temperature test.

[0038] The same test site includes several test stations. For example, the same test site includes: test station 1, test station 2 to test station n. The test items of the n test stations are the same. For example, one test station tests one chip, and n test stations can test at the same time.

[0039] Take any one of the test sites as an example for explanation; the test process in a test site includes: placing the chip to be tested into the input tray of the test site, and the test machine performs image test and electrical performance test on the chips to be tested scattered in multiple test stations. The chip test of the present invention includes electrical performance test and image test, and the electrical performance test includes open circuit and short circuit test of the chip; the image test includes testing whether the image of the chip is displayed normally, and whether the image has abnormal points, such as black spots, spots and other abnormal images. Specifically, the image tester performs image test on the chips scattered in multiple test stations, and the electrical performance tester performs electrical performance test on the chips scattered in multiple test stations. The same batch of chips (for example, hundreds or thousands of chips) can be image tested first, and then all electrical performance tests; or all electrical performance tests can be performed first, and then all image tests. Abnormal hardware at the test site will lead to test data errors; the hardware includes: test circuits between the sorting machine and the test station, and test circuits between the test machine and the test station.

[0040] The sorting machine screens and classifies the chips according to the chip test results. The sorting machine is responsible for transporting the input chips to the test module to complete the circuit stress test according to the pick-and-place method designed by the system. The sorting machine selects and classifies the circuits according to the test results. The sorting machine puts the qualified chips of the test station into the output tray of the test station. After the chip to be tested completes the test at the previous test station, it is transferred from the output tray of the previous test station to the input tray of the next test station for further testing.

[0041] Step S2, upload the test records and test data of the chip to be tested at each test site to the server, and the server monitors the test status of the chip to be tested online; the server is connected to the MES system in interactive communication. The server is a device that provides computing services. The server is composed of a processor, a hard disk, a memory, a system bus, etc. The server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has high requirements in terms of processing power, stability, reliability, security, scalability, manageability, etc. The server is connected to the MES system in interactive communication. MES (Manufacturing Execution System) is a production execution system, which is a production information management system for the workshop execution layer of a manufacturing enterprise. MES can provide enterprises with management modules including manufacturing data management, planning and scheduling management, production scheduling management, inventory management, and quality management, and create a solid, reliable, comprehensive, and feasible manufacturing collaborative management platform for enterprises. The MES system has functions such as process management, unit management, production tracking, performance analysis, document management, process management, quality management, and data collection. Provide operators and managers with information on the execution and tracking of plans and the current status of all resources.

[0042] Step S3: Automatically obtain the data from the server according to the material test program and test machine recorded in the MES system; ensure the integrity of the test data by comparing the test quantity record and test data of the chip to be tested; compare the one-time passwords, identity information and unique information of batch identification codes of multiple test sites. If there are differences, control the chip to be tested through the MES system.

[0043] Figure 3 FIG. 1 is a schematic diagram of a test quantity record and a test value data check in a chip data check method according to an embodiment of the present invention. Figure 2 and Figure 3 As shown, the sorter is connected to the test station, and the tester is also connected to the test station. The sorter sends instructions to the test station, and the test station starts the test signal to the tester. The tester tests the chip to be tested and feeds back the test results to the sorter. The tester and the sorter each save the test data and test results, and the tester has more detailed test results than the sorter.

[0044] Self-check the sorting machine and testing machine in the same test site, including:

[0045] The sorting machine records the number of chips actually tested at each test station, as well as the number of good and bad chips. The test machine also records the number of chips actually tested at each test station, as well as the number of good and bad chips. Specifically, the test machine records the chip test results and which test station actually tested the chip, and counts the number of chips actually tested at each station, as well as the number of good and bad chips. Compare and verify the test data and test quantities of the two data sources, the sorting machine and the test machine, in the same test site. If they match, the hardware is normal; if they do not match, then there is an abnormality in the hardware.

[0046] Cross-check the previous and next test sites, specifically including: obtaining the chip identity information and test result data in the test machines of different test sites. Compare the previous and next test sites. The chip with a good test result at the next test site must have a good result at the previous test site. If not, there is an abnormality in the hardware or a human error.

[0047] like Figure 3 As shown, the first inspection module is a first program compiled based on the inspection logic of the sorting machine and test machine self-inspection and the cross-inspection of the front and rear test sites in the same test site. The first program is installed on the server to constitute the first inspection module. The test quantity record and test value data are input into the first inspection module; if the inspection is successful, the material is released; if the inspection fails, the material is controlled by the MES system. Inspection rules: (1) The test quantity record of good products must match the number of good products in the test value; (2) The uniqueness information of the good products in the last test site must match the information of all previous test sites. The hardware is correctly connected and runs correctly, and the good products are placed normally on the final output tray. If there is an abnormality, the final output tray of good products will be mixed with defective products. Through comparative analysis of test records and test data, and material control through the MES system, the integrity and reliability of the data are ensured.

[0048] Figure 4 FIG. 1 is a schematic diagram of checking the electrical performance test channel data and the image performance test channel data in the chip data checking method according to an embodiment of the present invention. Figure 2 and Figure 4 As shown, check whether the electrical connection between the image tester and the test station is correct, and check whether the electrical connection between the electrical performance tester and the test station is correct; the same test station is connected to the image tester and the electrical performance tester; the electrical performance tester can provide multiple test resources at the same time, connect multiple test stations at a time, and its test station numbers are accumulated in sequence; the image tester can only provide one test supply at a time, and can only connect to one test station at a time, and its test station number is set according to the line connection data line interface address.

[0049] During normal testing, the data of the electrical performance tester is stored in the order of the stations, and the image tester is stored according to the data line interface address number; when the same test station tests the same chip to be tested, the electrical performance data is stored in order, and the image test data is stored in the order of the connected data lines. If the connection is wrong, the result corresponding to the test station will be recorded incorrectly. For example, if the data line of station 2 is connected to the interface of the tester numbered 1, then the tester will think that the chip at station 2 is from station 1, and the image tester will record the measured data as the result of test station 1. In this way, the chip with qualified electrical performance results at station 1 will be displayed in the image result station 2; at this time, the connection is abnormal, and the error result is fed back to the sorting machine, and the sorting machine will classify the wrong chip.

[0050] The second inspection module is a second program compiled based on the inspection logic for checking whether the electrical connection between the image tester and the test station is correct, and whether the electrical connection between the electrical performance tester and the test station is correct. The second program is installed on the server to form the second inspection module.

[0051] like Figure 4 As shown, the electrical performance test channel data and the image performance test channel data are input into the second inspection module; if the inspection is successful, the material is released; if the inspection fails, the material is controlled by the MES system. Inspection rules of the second inspection module: the test channels of the same chip must be consistent. The data of different testers at the same test site and the same test station are cross-validated. The inspection logic is: the same test station and the same test station are connected to different testers. Select the chip data measured by different testers, filter the data to obtain the test station containing identity information and test results. Exclude the identity information of defective products. Compare whether the test stations of the same good chip are the same. If they are the same, the hardware is normal; if they are different, the hardware connection is abnormal.

[0052] In summary, the present invention provides a chip data inspection method, including: testing the chip to be tested from the first test site to the Nth test site in sequence; uploading the test records and test data of the chip to be tested at each test site to the server, and the server monitors the test status of the chip to be tested online; the server is connected to the MES system for interactive communication; according to the material test program and test machine recorded by the MES system, the server data is automatically obtained; by comparing the test quantity record and test data of the chip to be tested, the integrity of the test data is ensured; comparing the one-time passwords, identity information and unique information of batch identification codes of multiple test sites, if there are differences, the chip to be tested is controlled by the MES system. The present invention ensures the integrity and reliability of chip data through comparative analysis of test records and test data, and performs material control through MES; ensures that the shipped chips are all good products with electrical performance and images tested by multiple channels, reduces the risk of customer complaints, and thus enhances the reliability of the product.

[0053] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0054] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A chip data inspection method, characterized in that: include: Testing the chip to be tested sequentially through the first test site to the Nth test site; The test records and test data of the chip under test at each test site are uploaded to the server, and the server monitors the test status of the chip under test online; the server is connected to the MES system for interactive communication; According to the material test program and test machine recorded by the MES system, the data of the server is automatically obtained; the integrity of the test data is ensured by comparing the test quantity record and test data of the chip to be tested; the one-time passwords, identity information and unique information of batch identification codes of multiple test sites are compared. If there are differences, the chip to be tested is controlled through the MES system.

2. The chip data checking method according to claim 1, characterized in that: The testing process in any one of the N testing sites includes: placing the chip to be tested into the input tray of the testing site, and the testing machine performs image testing and electrical performance testing on the chip to be tested distributed in multiple testing stations; the testing machine includes an image testing machine and an electrical performance testing machine; The hardware abnormality of the test site will lead to test data errors; the hardware includes: the test circuits of the sorting machine and the test station, and the test circuits of the test machine and the test station.

3. The chip data checking method according to claim 2, characterized in that: The sorting machine is connected to the test station, and the tester is also connected to the test station. The sorting machine sends instructions to the test station, and the test station starts a test signal to the tester. The tester tests the chip to be tested and feeds back the test result to the sorting machine. The tester and the sorting machine each save the test data and test results, and the tester has more detailed test results than the sorting machine.

4. The chip data checking method according to claim 3, characterized in that: The self-inspection of the sorting machine and the testing machine in the same testing site specifically includes: The sorting machine records the number of the chips to be tested actually tested by each test station and the number of good chips and the number of defective chips among the chips to be tested; The testing machine also records the number of the chips to be tested actually tested by each of the testing stations and the number of good chips and the number of defective chips among the chips to be tested; The test data and test quantity of the two data sources, the sorting machine and the testing machine, in the same test site are compared and verified. If they match, the hardware is normal; if they do not match, the hardware is abnormal.

5. The chip data checking method according to claim 2, characterized in that: Cross-check the previous and subsequent test sites, including: Obtain the identity information and test result data of the chip to be tested in the test machines of different test sites; perform a comparison before and after; if the chip to be tested has a good test result at the latter test site, there must be a good result at the former test site; if not, there is an abnormality in the hardware or a human operation error.

6. The chip data checking method according to claim 2, characterized in that: Check whether the image tester and the test station are electrically connected correctly, and check whether the electrical performance tester and the test station are electrically connected correctly; The same test station is connected to the image testing machine and the electrical performance testing machine; the electrical performance testing machine can provide multiple test resources at the same time and connect multiple test stations at a time, and its test station numbers are accumulated in sequence; the image testing machine can only provide one test supply at a time and can only connect one test station at a time, and its test station number is set according to the line connection data line interface address.

7. The chip data checking method according to claim 6, characterized in that: During normal testing, the data of the electrical performance tester is stored in the order of the stations, and the data of the image tester is stored in the order of the data line interface address number; when the same test station tests the same chip to be tested, the electrical performance data is stored in order, and the image test data is stored in the order of the connected data lines; If the connection is wrong, the result corresponding to the test station will record an error, and the error result will be fed back to the sorting machine, and the sorting machine will classify the error chip.

8. The chip data checking method according to claim 1, characterized in that: The first test site to the Nth test site perform tests in series, and the good chips tested by the previous test site flow into the next test site for testing, and the bad chips tested by the previous test site no longer flow into the next test site.

9. The chip data checking method according to claim 1, characterized in that: The first test site to the Nth test site are respectively set at different temperatures to test the chip to be tested.

10. The chip data checking method according to claim 2, characterized in that: The same test site includes a plurality of test stations; the test items of the plurality of test stations are the same; one test station tests one chip to be tested, and the plurality of test stations perform tests simultaneously.

Images