Method for remotely upgrading 7-series FPGA programs of Xilinx through serial port
Through the serial port remote upgrade method, the functional modules are used to realize the writing and verification of FPGA programs, solving the problems of cumbersome and easy-to-break equipment upgrades in traditional methods, and achieving flexible and secure FPGA program upgrades.
Patent Information
- Application Number
- CN202411983804.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-06
AI Technical Summary
Traditional methods to upgrade Xilinx's 7 series FPGA programs require emulators, which leads to cumbersome operation in equipment that requires airtight and watertight and is prone to damage the equipment.
Through the serial port remote upgrade method, functional modules include serial port transceiver module, ICAP control module, DDR data cache module, etc., to realize the writing and verification of FPGA programs, avoiding physical disassembly of the device.
It realizes flexible and secure upgrades of FPGA programs, avoids equipment damage, and does not require professional development software and emulators, and is easy to operate.
Smart Images
Figure CN119938109A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of data communication, and in particular to a method for remotely upgrading a Xilinx 7 series FPGA program via a serial port. Background Art
[0002] As Xilinx's 7 series FPGAs are widely used in various fields of equipment, the traditional method of upgrading FPGA programs requires hanging an emulator. This method of updating the program is very cumbersome when operating in some equipment that requires airtightness and watertightness.
[0003] In the prior art, when using an emulator to update the FPGA program, for some devices that require watertightness and airtightness, the device must be disassembled and the emulator must be inserted when updating the program, which will destroy the airtightness or watertightness of the device, and requires Xilinx's professional development software and emulator. This operation is not only inflexible, but also may damage the device during the upgrade process. Therefore, this solution proposes a method for remotely upgrading Xilinx's 7 series FPGA program via a serial port to solve the above problems. Summary of the invention
[0004] The purpose of the present invention is to provide a method for remotely upgrading Xilinx 7 series FPGA programs via a serial port, so as to solve the problems raised in the above background technology.
[0005] To achieve the above object, the present invention provides the following technical solution: a method for remotely upgrading Xilinx 7 series FPGA programs via a serial port, the upgrading method comprising the following steps:
[0006] The first step is to set up the functional module first, and then send the bin file of the FPGA to be burned to the FPGA through the serial port;
[0007] In the second step, after receiving the bin file from the serial port, the FPGA first stores it in the DDR cache unit;
[0008] The third step is to write the data cached in the DDR cache unit into the boot Flash;
[0009] The fourth step is to read the data written into the Flash and the data in the DDR after the writing is completed, and compare and verify the two sets of data read out;
[0010] Step 5: If the data is wrong after comparison and verification, it will prompt that the programming failed;
[0011] Step 6. Finally, write all the bin files into the startup Flash and after verification, it will prompt that the burning is completed, and at the same time send instructions and power off to restart the FPGA program.
[0012] Preferably, the bin file includes a G image and an M image, the G image is a non-updated image, and the M image is an updated image.
[0013] Preferably, the G image is provided with a serial port for updating the M image, and the M image is provided with a serial port for self-update.
[0014] Preferably, when the M image fails to be updated through the serial port during operation, the G image will be started after the FPGA is restarted, and the FPGA will re-update the M image through the serial port set by the G image.
[0015] Preferably, the functional modules include a startup SPI Flash control module, a serial port transceiver module, a soft core data processing module, an ICAP control module and a DDR data cache module.
[0016] Preferably, the serial port transceiver module receives control instructions and the bin file of the burned FPGA, the ICAP control module restarts the FPGA without powering on and controls the FPGA startup image sequence, and the DDR data storage module caches the bin file data received by the serial port into the DDR after the soft-core data processing module receives the instruction to upgrade the FPGA program, and the soft-core data processing module processes the control instructions and simultaneously controls the operation of the FPAG bin file fixed-line process.
[0017] Preferably, the serial port transceiver module communicates with the soft core via the AXI bus, converts the serial port data sent externally according to the serial port protocol, and converts the data sent by the soft core into the serial port format and sends it out, and the serial port sends instructions through the soft core to modify the baud rate configuration.
[0018] Preferably, the ICAP control module sends IPROG via ICAP primitive.
[0019] Preferably, the FPGA starts by first reading the G image from address 0, and then reads the M image according to the trigger set by the G image. If the M image fails to start, it will jump back to start the G image. If the M image starts normally, the M image will run.
[0020] Preferably, the workflow of the soft core data processing module is, after completing hardware initialization, waiting to receive an upgrade instruction, entering the upgrade process after receiving the upgrade instruction, and after entering the upgrade process, sending an erase instruction to ensure that the Flash is erased after entering the upgrade process abnormally;
[0021] If the erase command is received, the Flash at the set address will be erased and the erase progress will be reported. If the upgrade process is entered abnormally and no erase Flash command is received, the upgrade process will be exited;
[0022] After erasing is completed, the system waits for the user to transfer the bin file. The received bin file is written into the Flash and cached into the DDR. After the Bin file is transferred, the verification is started, and the data in the Flash is read out and compared with the data in the DDR.
[0023] If the verification passes, the upload verification passes, and the user sends a command to restart the FPGA. If the verification fails, the upload fails and exits the upgrade state.
[0024] Technical effects and advantages of the present invention:
[0025] The FPGA part of the serial port burning program provided by the present invention only needs to modify the bin file of the corresponding burned FPGA when porting to different Xilinx 7 series FPGA platforms. Such an upgrade method has high versatility and simple porting, and can be done by using a USB to serial port tool and a serial port debugging assistant without the need for professional development software and emulators. Therefore, the update can be completed without disassembling the device, and the device will not be damaged when the device program is upgraded. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 The figure is a schematic diagram of the data processing flow of the present invention.
[0027] Figure 2 This is a schematic diagram of the functional modules of the serial port remote upgrade FPGA program of the present invention.
[0028] Figure 3 It is a schematic diagram of the FPGA startup process of the present invention.
[0029] Figure 4 This is a schematic diagram of starting the Flash control address allocation of the present invention.
[0030] Figure 5 It is a functional schematic diagram of the serial port control module of the present invention. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0032] The present invention provides Figure 1 The method shown in the figure is to remotely upgrade the Xilinx 7 series FPGA program through a serial port, including the following steps:
[0033] The first step is to set up the functional module first, and then send the bin file of the FPGA to be burned to the FPGA through the serial port;
[0034] Specifically, the bin file includes a G image and an M image, the G image is a non-updated image, and the M image is an updated image.
[0035] Further, the G image is provided with a serial port for updating the M image, and the M image is provided with a serial port for self-update;
[0036] If the M image fails to be updated through the serial port when it is running, the G image will be started after the FPGA is restarted, and the FPGA will update the M image again through the serial port set by the G image.
[0037] It should be noted that in order to prevent the failure of updating the program through the serial port, a method for starting the Multiboot bin file (referring to the executable file used for the multi-boot system) of the FPGA is provided. The bin file contains a G image (GoldenImage) and an M image (Multi Image). The Golden Image is a stable image that does not need to be updated. The image needs to have the serial port update Multi Image function. The Multi Image is the image that needs to be updated. Under normal circumstances, the FPGA will start the MultiImage, and the Multi Image also has the serial port update function. If the MultiImage fails to be updated through the serial port when the Multi Image is running, the FPGA will start the Golden Image after restarting. In this way, the FPGA will re-update the MultiImage through the serial port, which will not cause the FPGA to fail to start after the Multi Image update fails.
[0038] In the second step, after receiving the bin file from the serial port, the FPGA first stores it in the DDR cache unit;
[0039] The third step is to write the data cached in the DDR cache unit into the boot Flash;
[0040] The fourth step is to read the data written in the Flash and the data in the DDR after writing is completed, and compare and verify the two sets of data read out to ensure the correctness of the data;
[0041] Step 5: If the data is wrong after comparison and verification, it will prompt that the programming failed;
[0042] Step 6. Finally, write all the bin files into the startup Flash and after verification, it will prompt that the burning is completed, and at the same time send instructions and power off to restart the FPGA program.
[0043] Specifically, refer to Figure 2As shown in the figure, the functional modules include the startup SPI Flash control module, the serial port transceiver module, the soft core data processing module, the ICAP control module and the DDR data cache module. The serial port supports different baud rates. The default baud rate is 921600bps and the highest baud rate is 6Mbps. You can send commands to switch to other baud rates through the serial port debugging assistant.
[0044] It should be noted that the startup SPI Flash control module mainly realizes and starts the Flash communication, and can read and write the data in the startup Flash. Due to the particularity of FPGA startup Flash, it is not possible to directly operate the startup Flash under normal circumstances. It is necessary to use the Xilinx official axi quad spi IP, which supports single-line, dual-line and 4-line SPI modes. After checking Enable STARTUP Primitive in the IP, it can directly communicate with the FPGA startup Flash. The IP communicates with the soft core through the AXI Lite bus, and can convert the data sent by the soft core through the AXILite bus into SPI format and transmit it to Flash.
[0045] Baud rate refers to the number of symbols (signal changes) transmitted per second. In data communications, baud rate directly affects the speed of data transmission. For example, if the baud rate of a communication system is 9600 baud, it means that 9600 signal changes can be transmitted per second. For some modulation methods, a symbol may contain multiple bits, so the baud rate and bit rate are not always the same. Bit rate refers to the number of bits transmitted per second.
[0046] Furthermore, the serial port transceiver module receives control instructions and the bin file of the burned FPGA, the ICAP control module restarts the FPGA without powering on and controls the FPGA startup image sequence, and the DDR data storage module caches the bin file data received by the serial port into the DDR after the soft-core data processing module receives the upgrade FPGA program instruction, and the soft-core data processing module processes the control instructions and controls the operation of the FPAG bin file fixed-line process at the same time.
[0047] refer to Figure 5 As shown, the serial port transceiver module communicates with the soft core through the AXI bus, converts the serial port data sent from the outside according to the serial port protocol, and converts the data sent by the soft core into the serial port format and sends it out. The serial port sends instructions through the soft core to modify the baud rate configuration.
[0048] The ICAP control module sends IPROG through the ICAP primitive. ICAP is an internal configuration access port in the FPGA (field programmable gate array), which allows the user to dynamically update the configuration of the FPGA at runtime.
[0049] It should be noted that the core part of the ICAP control module is composed of ICAP primitives. Through ICAP primitives, users can directly read and write the internal registers of the FPGA in the FPGA code. The functions of ICAP include: dynamic reconfiguration, ICAP allows partial or complete reconfiguration of the design while the FPGA is running, and can update the configuration of certain logic blocks without stopping the FPGA operation without affecting the functions of other parts; online changes, using ICAP, you can load new functions into the FPGA or fix errors in existing designs without physically reprogramming or restarting the device; improve flexibility, ICAP provides greater flexibility, and can dynamically change the functions of the FPGA at runtime according to different application requirements; support for multiple configuration formats, ICAP supports multiple configuration file formats, including .bit and .bin files, so as to easily load different designs.
[0050] In this design, ICAP primitive is used to send IPROG to implement Multiboot. The ICAP user instructions are shown in Table 1. According to the instructions, users can control the FPGA to read the image file from the specified address of Flash when starting.
[0051] Table 1 ICAP user command table
[0052]
[0053] refer to Figure 3 As shown, FPGA starts by reading the G image from address 0, and then reads the M image according to the trigger set by the G image. If the M image fails to start, it will jump back to start the G image. If the M image starts normally, the M image will run.
[0054] It should be noted that when FPGA is started, it first reads the Golden Image from address 0, and then reads the Multi Image according to the trigger set by the Golden Image. If the Multi Image fails to start, it will jump back to start the Golden Image. If the Multi Image starts normally, it will run the Multi Image according to Figure 3 It can be seen that the Flash address allocation follows Figure 4Golden uses 0 as the starting address to ensure that Golden Image can be started normally during startup. Multi Image is at a high address. In order to avoid storage address conflicts between the two image files, the addresses are allocated in half in the design. Taking Micron's N25Q256 Flash as an example, its size is 256Mbit, and the allocated Flash address is 0~0x00FFFFFF for Golden Image storage space, and 0x01000000~0x01FFFFFF for Multi Image storage space.
[0055] Specifically, the workflow of the soft core data processing module is as follows: after completing hardware initialization, it waits to receive an upgrade instruction, enters the upgrade process after receiving the upgrade instruction, and after entering the upgrade process, sends an erase instruction to ensure that the Flash is erased after entering the upgrade process abnormally;
[0056] If the erase command is received, the Flash at the set address will be erased and the erase progress will be reported. If the upgrade process is entered abnormally and no erase Flash command is received, the upgrade process will be exited;
[0057] After erasing is completed, the system waits for the user to transfer the bin file. The received bin file is written into the Flash and cached into the DDR. After the Bin file is transferred, the verification is started, and the data in the Flash is read out and compared with the data in the DDR.
[0058] If the verification passes, the upload verification passes, and the user sends a command to restart the FPGA. If the verification fails, the upload fails and exits the upgrade state.
[0059] It should be noted that after completing the hardware initialization, it waits to receive the upgrade command, and enters the upgrade process after receiving the upgrade command. After entering the upgrade process, it will not actively erase the Flash. It will first send an erase command to ensure that the Flash is erased after entering the upgrade process abnormally. If the erase command is received, the Flash at the set address will be erased and the erase progress will be reported. If the upgrade process is entered abnormally, after not receiving the erase Flash command, it will wait for a certain period of time before exiting the upgrade process. After the erasure is completed, it waits for the user to transfer the bin file;
[0060] Since the minimum area of Flash is 256 bytes, each time data is written, it does not cross the area. Writing too long data will cause writing failure. When the serial port debugging assistant sends files, you can set the file to be sent once according to 256Byte. There will be an interval of 1ms between each sending. The received bin file is written to Flash and cached in DDR. After the Bin file is transferred, the verification is started. The data in Flash is read out and compared with the data in DDR. If the verification passes, the upload verification passes, and the user is asked to send a command to restart the FPGA. If the verification fails, the upload fails and the upgrade state is exited. The user does not restart the device at this time and resends the startup upgrade program command to restart the upgrade process. If the user accidentally restarts the device at this time, the FPGA will start from Golden Image. At this time, you can re-upgrade the program according to the above operations.
[0061] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for remotely upgrading Xilinx 7 series FPGA programs via a serial port, characterized in that: The upgrade method includes the following steps: The first step is to set up the functional module first, and then send the bin file of the FPGA to be burned to the FPGA through the serial port; In the second step, after receiving the bin file from the serial port, the FPGA first stores it in the DDR cache unit; The third step is to write the data cached in the DDR cache unit into the boot Flash; The fourth step is to read the data written into the Flash and the data in the DDR after the writing is completed, and compare and verify the two sets of data read out; Step 5: If the data is wrong after comparison and verification, it will prompt that the programming failed; Step 6. Finally, write all the bin files into the startup Flash and after verification, it will prompt that the burning is completed, and at the same time send instructions and power off to restart the FPGA program.
2. The method for remotely upgrading Xilinx 7 series FPGA programs via serial port according to claim 1, characterized in that: The bin file includes a G image and an M image, wherein the G image is a non-updated image and the M image is an updated image.
3. The method for remotely upgrading Xilinx 7 series FPGA programs via serial port according to claim 2, characterized in that: The G image is provided with a serial port for updating the M image, and the M image is provided with a serial port for self-update.
4. The method for remotely upgrading Xilinx 7 series FPGA programs via a serial port according to claim 3, characterized in that: When the M image fails to be updated through the serial port during operation, the G image will be started after the FPGA is restarted, and the FPGA will update the M image again through the serial port set by the G image.
5. The method for remotely upgrading Xilinx 7 series FPGA programs via serial port according to claim 1, characterized in that: The functional modules include a startup SPI Flash control module, a serial port transceiver module, a soft core data processing module, an ICAP control module and a DDR data cache module.
6. A method for remotely upgrading Xilinx 7 series FPGA programs via a serial port according to claim 5, characterized in that: The serial port transceiver module receives control instructions and the bin file of the burned FPGA, the ICAP control module restarts the FPGA without powering on and controls the FPGA startup image sequence, and the DDR data storage module stores the bin file data received by the serial port into the DDR cache after the soft core data processing module receives the upgrade FPGA program instruction, and the soft core data processing module processes the control instructions and controls the operation of the FPAG bin file fixed call process at the same time.
7. The method for remotely upgrading Xilinx 7 series FPGA programs via a serial port according to claim 6, characterized in that: The serial port transceiver module communicates with the soft core via the AXI bus, converts the serial port data sent externally according to the serial port protocol, and converts the data sent by the soft core into the serial port format and sends it out. The serial port sends instructions to modify the baud rate configuration through the soft core.
8. The method for remotely upgrading Xilinx 7 series FPGA programs via a serial port according to claim 6, characterized in that: The ICAP control module sends IPROG through the ICAP primitive.
9. The method for remotely upgrading Xilinx 7 series FPGA programs via a serial port according to claim 6, characterized in that: The FPGA starts by first reading the G image from address 0, and then reads the M image according to the trigger set by the G image. If the M image fails to start, it will jump back to start the G image. If the M image starts normally, the M image will run.
10. The method for remotely upgrading Xilinx 7 series FPGA programs via a serial port according to claim 5, characterized in that: The working process of the soft core data processing module is as follows: after completing hardware initialization, it waits to receive an upgrade instruction, enters the upgrade process after receiving the upgrade instruction, and after entering the upgrade process, sends an erase instruction to ensure that the Flash is erased after entering the upgrade process abnormally; If the erase command is received, the Flash at the set address will be erased and the erase progress will be reported. If the upgrade process is entered abnormally and no erase Flash command is received, the upgrade process will be exited; After erasing is completed, the system waits for the user to transfer the bin file. The received bin file is written into the Flash and cached into the DDR. After the Bin file is transferred, the verification is started, and the data in the Flash is read out and compared with the data in the DDR. If the verification passes, the upload verification passes, and the user sends a command to restart the FPGA. If the verification fails, the upload fails and exits the upgrade state.