Memory recovery method and device, electronic equipment and storage medium

Abstract

The invention relates to a memory recovery method and device, electronic equipment and a storage medium. The method comprises the following steps: detecting an idle memory amount; if the idle memory amount is smaller than a first memory water level, executing memory recovery operation by utilizing N target threads according to the priority of the target threads, wherein in the N target threads, the priorities of P target threads are higher than the target priority; the priority of the N-P target threads is lower than the target priority; n and P are positive integers, and N-P is greater than or equal to 1. According to the method, the memory recovery rate and the relation that the memory recovery thread competes for CPU resources with other tasks can be balanced, and the purpose of reasonably managing the memory is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a memory recovery method, device, electronic device and storage medium. Background Art

[0002] Virtual reality (VR) and mixed reality (MR) devices have made rapid progress in recent years, but they also face many challenges, one of which is the limitation of hardware resources. Since these devices need to process a large amount of three-dimensional image and sound data, they usually have more powerful CPUs (central processing units) and graphics processors than mobile phones and tablets. However, this does not mean that these devices will not encounter problems when handling tasks. Since VR / MR applications need to execute many algorithms, the threads executing these algorithms will occupy a lot of CPU resources, resulting in insufficient memory. How to reasonably manage memory is an urgent problem to be solved. Summary of the invention

[0003] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a memory recycling method, device, electronic device and storage medium.

[0004] In a first aspect, the present disclosure provides a memory recovery method, comprising:

[0005] Check the amount of free memory;

[0006] If the amount of free memory is less than the first memory water level, memory recovery operations are performed using N target threads according to the priority of the target thread; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; the priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP≥1.

[0007] In a second aspect, the present disclosure further provides a memory recovery device, comprising:

[0008] A detection module, used to detect the amount of free memory;

[0009] A recycling module is used to perform a memory recycling operation using N target threads according to the priority of the target thread if the amount of free memory is less than a first memory water level; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; the priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP≥1.

[0010] In a third aspect, the present disclosure further provides an electronic device, the electronic device comprising:

[0011] one or more processors;

[0012] A storage device for storing one or more programs;

[0013] When the one or more programs are executed by the one or more processors, the one or more processors implement the memory recycling method as described above.

[0014] In a fourth aspect, the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the memory recovery method as described above.

[0015] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0016] The technical solution provided by the embodiment of the present disclosure is set to perform memory recovery operations using N target threads according to the priority of the target thread if the amount of free memory is less than the first memory water level; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; and the priorities of NP target threads are lower than the target priority. In essence, some threads are in a state of high-speed memory recovery, while other threads are in a state of low-speed memory recovery. This can ensure that memory recovery can be performed in time when the memory usage of the device is too high. On the other hand, since it does not make all memory recovery threads in a state of high-speed memory recovery, it can avoid too many memory recovery threads competing with other tasks for CPU resources during execution, resulting in the occurrence of undesirable conditions such as slow execution or delay of other tasks. It can achieve a balanced memory recovery rate and the relationship between the memory recovery thread and other tasks competing for CPU resources, so as to achieve the purpose of reasonable memory management. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 A flowchart of a memory recovery method provided by an embodiment of the present disclosure;

[0020] Figure 2-Figure 4 A schematic diagram of a memory recycling method provided in an embodiment of the present disclosure;

[0021] Figure 5 is a structural schematic diagram of a memory recycling device in an embodiment of the present disclosure;

[0022] Figure 6 It is a structural schematic diagram of an electronic device in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0025] Figure 1 This is a flowchart of a memory recycling method provided in an embodiment of the present disclosure. This embodiment is applicable to the case of memory recycling in a client. The method can be executed by a memory recycling device, which can be implemented in software and / or hardware. The device can be configured in an electronic device, such as a terminal, specifically including but not limited to smart phones, PDAs, tablet computers, wearable devices with display screens, desktop computers, laptop computers, all-in-one machines, smart home devices, etc. Among them, wearable devices include but are not limited to virtual reality devices, augmented reality devices, mixed reality devices, and augmented virtual devices.

[0026] like Figure 1 As shown, the method may specifically include:

[0027] S110, detecting the amount of free memory.

[0028] Free memory refers to the amount of physical memory in the computer that is not being used.

[0029] S120. If the amount of free memory is less than the first memory water level, use N target threads to perform memory recovery operations according to the priority of the target thread; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; the priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP≥1.

[0030] The memory water level refers to the threshold set by the system when allocating memory to threads. The system can determine the memory allocation strategy based on the relationship between the free memory amount and the memory water level. If the free memory amount is less than the first memory water level, it means that the amount of unused physical memory in the current computer is seriously insufficient, and memory recovery is urgently needed.

[0031] The target thread may be, for example, a thread for memory recycling. Exemplarily, the target thread may be a kswapd thread. The kswapd thread is a thread for recycling memory belonging to a CPU core. The target thread may, for example, recycle anonymous pages and file pages to increase the amount of free memory.

[0032] The target priority is a pre-specified priority, and the present application does not limit the level to which the target priority specifically refers. For example, it is assumed that the thread priority is defined as an integer ranging from 1 to 10, where 1 is the lowest priority and 10 is the highest priority. The target priority can be level 5, level 6, or level 7.

[0033] When scheduling threads, the CPU core will give certain preferential treatment according to the thread's priority. For example, the preferential treatment may be that threads with high priority are scheduled first, or that threads with high priority are allocated a longer execution time.

[0034] Since the priority of the P target threads is higher than the target priority, it means that during the memory recovery process, the P target threads are favored and can quickly recycle memory, and they are the main memory recovery threads. The priority of the NP target threads is lower than the target priority, which means that during the memory recovery process, the NP target threads are not favored and can slowly recycle memory, and they are auxiliary memory recovery threads.

[0035] There are many specific implementation methods for this step, and this application does not limit this. In one embodiment, the specific implementation method of this step includes: allocating time slices to the target thread and the candidate thread respectively according to the priorities of the target thread and the candidate thread; and controlling the target thread and the candidate thread to run in turn according to the time slice of the target thread and the time slice of the candidate thread.

[0036] The candidate thread is a thread that does not perform memory recovery operations. Exemplarily, the candidate thread is a thread in the foreground application or a thread in the background application. The foreground application means that the display interface of the application will be directly displayed on the screen of the electronic device and can directly receive user operations. The background application means that although the application has been started, its display interface is not visible to the user.

[0037] In practice, a single application may have one or more threads. If a single application has multiple threads, the priority of some threads in the same application may be higher than the target priority, equal to the target priority, or lower than the target priority.

[0038] Optionally, the duration of the time slice of the target thread and the duration of the time slice of the candidate thread are both in direct proportion to the priority, that is, whether it is the target thread or the candidate thread, the higher the priority of the thread, the longer the duration of the time slice allocated to it.

[0039] Exemplarily, assume that the thread priority is defined as an integer ranging from 1 to 10, where 1 is the lowest priority and 10 is the highest priority. There are 2 target threads and 2 candidate threads. Among them, the priority of one target thread is 1, the priority of the other target thread is 8, the priority of one candidate thread is 9, and the priority of the other candidate thread is 6. When allocating time slices to each target thread and each candidate thread, the length of the time slice of the target thread with a priority of 1 is t1, the length of the time slice of the target thread with a priority of 8 is t2, the length of the time slice of the candidate thread with a priority of 9 is t3, and the length of the time slice of the candidate thread with a priority of 6 is t4, then t3>t2>t4>t1.

[0040] The longer the time slice of a thread is, the longer the execution time of the thread is. Since the priority of the P target threads is higher than the target priority, it means that during the memory recovery process, the running time of the P target threads is longer and more memory can be recovered, and they are the main memory recovery threads. The priority of the NP target threads is lower than the target priority, which means that during the memory recovery process, the running time of the NP target threads is shorter and less memory can be recovered, and they are auxiliary memory recovery threads.

[0041] The above technical solution is set to use N target threads to perform memory recovery operations according to the priority of the target thread if the amount of free memory is less than the first memory water level; wherein, among the N target threads, the priority of P target threads is higher than the target priority; and the priority of NP target threads is lower than the target priority. The essence of the above technical solution is to make some threads in a state of high-speed memory recovery, and other threads in a state of low-speed memory recovery. On the one hand, this can ensure that memory recovery can be performed in time when the memory usage of the device is too high. On the other hand, since it does not make all memory recovery threads in a state of high-speed memory recovery, it can avoid too many memory recovery threads competing with other tasks for CPU resources during execution, resulting in the occurrence of undesirable conditions such as slow execution or delay of other tasks. It can achieve a balanced relationship between the memory recovery rate and the memory recovery thread competing with other tasks for CPU resources, so as to achieve the purpose of reasonable memory management.

[0042] It should be noted that, in practice, this application does not restrict the size relationship between P and NP. By reasonably setting the values ​​of P and NP, it is helpful to further achieve a balance between the memory recycling rate and the relationship between the memory recycling thread and other tasks competing for CPU resources. Optionally, P<NP.

[0043] Based on the above technical solution, in one embodiment, optionally, after S120, it also includes: if the amount of free memory is higher than the second memory water level, adjusting the priorities of the P target threads so that the priorities of the P target threads after adjustment are lower than the target priority, and the second memory water level is higher than the first memory water level.

[0044] The free memory amount is higher than the second memory water mark, which means that the amount of unused physical memory in the current computer is still insufficient and memory reclamation is required, but the memory reclamation demand is not urgent.

[0045] By setting and adjusting the priorities of the P target threads so that the priorities of the P target threads after adjustment are lower than the target priority, its essence is to ensure that the competition for CPU resources among the P target threads is further reduced while still performing memory recycling, so as to further avoid the occurrence of undesirable conditions such as slow execution or delay of other task threads.

[0046] On the basis of the above technical solutions, optionally, if the amount of free memory is higher than a third memory water level, the N target threads are controlled to be in a dormant state, and the third memory water level is higher than the first memory water level.

[0047] The free memory amount is higher than the third memory watermark, which means that the amount of unused physical memory in the current computer is sufficient and memory recycling is not required.

[0048] For example, see Figure 2 , when the system starts, the CPU core will create N target threads. When the system starts, the amount of free memory is usually large, and there is no need to start N target threads for memory recovery. The N target threads are in a dormant state. As the system runs, the amount of free memory gradually decreases. When the amount of free memory is less than the first memory water level, the N target threads are awakened for memory recovery, where among the N target threads, the priority of P target threads is higher than the target priority; the priority of NP target threads is lower than the target priority. Thereafter, the P target threads are in a high-speed memory recovery state, and the NP target threads are in a low-speed memory recovery state. Then, as the N target threads continue to perform memory recovery operations and the system continues to run, the amount of free memory may decrease first and then increase, or the amount of free memory may gradually increase. When the amount of free memory increases to be higher than the third memory water level, it means that the current amount of free memory is sufficient and there is no need to recover the memory. The N target threads are controlled to be in a dormant state at the same time.

[0049] By setting that if the amount of free memory is higher than the third memory water level, the N target threads are controlled to be in a dormant state, it is possible to further avoid the occurrence of an undesirable state in which other tasks are executed slowly or delayed due to the running of the memory recovery thread.

[0050] In practice, if the memory water level includes the second memory water level mentioned above, optionally, the third memory water level is higher than the second memory water level.

[0051] On the basis of the above technical solution, in another embodiment, optionally, before S120, it also includes: if the amount of free memory is lower than the fourth memory water level, wake up N target threads; at the time of wake-up, the priorities of the N target threads are all lower than the target priority; according to the priorities of the N target threads at the time of wake-up, use the N target threads to perform memory recovery operations; S120 includes: if the amount of free memory is lower than the first memory water level, adjust the priorities of P target threads among the N target threads so that the priorities of the P target threads after adjustment are higher than the target priority; according to the priorities of the target threads after adjustment, use the N target threads to perform memory recovery operations. The fourth memory water level is higher than the first memory water level.

[0052] The amount of free memory is lower than the fourth memory watermark, which means that the amount of unused physical memory in the current computer is slightly insufficient and memory reclamation is required, but the demand for memory reclamation is not urgent.

[0053] For example, see Figure 3 , when the system starts, the kernel creates N target threads. When the system starts, the amount of free memory is usually large, and there is no need to start N target threads for memory recovery. The N target threads are in a dormant state. As the system runs, the amount of free memory gradually decreases. When the amount of free memory is less than the fourth memory water level, the N target threads are awakened for memory recovery. The priorities of the N target threads are all lower than the target priority, and the N target threads are all in a low-speed memory recovery state. Then, as the N target threads continue to perform memory recovery operations and the system continues to run, if the amount of free memory further decreases. When the amount of free memory is lower than the first memory water level, the priorities of P target threads among the N target threads are adjusted, and the priorities of the P target threads after adjustment are higher than the target priority. Thereafter, the P target threads are in a high-speed memory recovery state, and the NP target threads are in a low-speed memory recovery state.

[0054] Continue to see Figure 3 , then as the N target threads continue to perform memory recovery operations and the system continues to run, the amount of free memory may first decrease and then increase, or gradually increase. If the amount of free memory is higher than the second memory water level, the priorities of the P target threads are adjusted again so that the priorities of the P target threads after adjustment are lower than the target priority. In other words, at this time, the priorities of all target threads are lower than the target priority, and the N target threads are again in a low-speed memory recovery state until the amount of free memory is higher than the third memory water level, and the N target threads are controlled to be in a dormant state at the same time.

[0055] Furthermore, the first memory water level and the second memory water level may be set equal. Figure 4 , when the amount of free memory is less than the fourth memory water level, wake up N target threads for memory recovery. The priorities of the N target threads are all lower than the target priority, and the N target threads are all in a low-speed memory recovery state. Then, as the N target threads continue to perform memory recovery operations and the system continues to run, if the amount of free memory further decreases. When the amount of free memory is lower than the first memory water level, adjust the priorities of P target threads among the N target threads, and the priorities of the P target threads after adjustment are higher than the target priority. Thereafter, the P target threads are in a high-speed memory recovery state, and the NP target threads are in a low-speed memory recovery state. Then, as the N target threads continue to perform memory recovery operations and the system continues to run, the amount of free memory first decreases and then increases. If the amount of free memory is higher than the second memory water level (i.e., the first memory water level), adjust the priorities of the P target threads so that the priorities of the P target threads after adjustment are lower than the target priority, and the N target threads are again in a low-speed memory recovery state until the amount of free memory is higher than the third memory water level, and control the N target threads to be in a dormant state at the same time.

[0056] It should be noted that in the prior art, such as the Linux system, the initial memory water level is set when the kernel is initialized. There are usually three initial memory water levels: min, low, and high. When the amount of free memory is lower than low, the kswapd thread recycles memory until the amount of free memory reaches high and then stops recycling. Among them, the size of min is equal to the value of the kernel parameter min_free_kbytes. low = min*5 / 4, high = min*3 / 2.

[0057] In this application, optionally, see Figure 4 , set the fourth memory water level higher than low, the first memory water level lower than low, and the third memory water level higher than high. The purpose of this setting is to wake up N target threads in advance and perform low-speed memory recovery compared to the prior art. Only when the first memory water level lower than low is reached, some target threads are switched to the state of high-speed memory recovery. Memory recovery is stopped only when the third memory water level higher than high is reached. In this way, the duration of high-speed memory recovery can be fully shortened, and the competition for CPU resources by memory recovery threads can be further reduced.

[0058] On the basis of the above technical solutions, optionally, a central processing unit core with the largest idle computing power is used to run a sub-target thread, where the sub-target thread is a target thread with a priority lower than the target priority.

[0059] Exemplarily, when the priority of P target threads is lower than the target priority, the CPU core with the largest idle computing power is used to run all target threads (i.e., N target threads). When the priority of P target threads is higher than the target priority, the CPU core with the largest idle computing power is used to run at least NP target threads with a priority lower than the target priority. The reason for this setting is that in some systems, the Energy Aware Scheduling (EAS) function is enabled by default. When the energy-aware scheduling function is enabled, the task scheduling is based on the lowest power consumption as the standard to select the core for the thread, and the result is that, without exceeding the maximum load limit, the core with smaller idle computing power is preferentially selected to run the thread. By setting the use of the CPU core with the largest idle computing power to run the sub-target thread, the purpose is to limit the use of the CPU core with the largest idle computing power to run the sub-target thread regardless of whether the system turns on the energy-aware scheduling function, which can further improve the memory recovery efficiency and improve memory utilization.

[0060] Furthermore, before using the CPU core with the largest idle computing power to run at least part of the target thread, the method also includes: obtaining load data of each core in the CPU; and determining the CPU core with the largest idle computing power based on the load data of each core.

[0061] The load data of the kernel may be, for example, data reflecting the operation status of threads running on the kernel within a certain period of time. Optionally, the actual total operation time of all threads running on the kernel within a certain period of time and the actual frequency of the kernel are obtained; the actual total operation time is normalized to obtain the load data of the kernel. The load data of the kernel reflects the total operation time of all threads running on the kernel when the kernel frequency is the highest frequency. The smaller the load data of the kernel, the greater the idle computing power of the kernel.

[0062] In actual thread scheduling, there are usually multiple scheduling methods. For example, one scheduling method is to execute the tasks corresponding to the threads with lower priority after the tasks corresponding to the threads with higher priority are completed. Another scheduling method is to allocate time slices to threads, and control the threads to execute the corresponding tasks according to the time slices of the threads. If the tasks corresponding to a thread are not completed within the corresponding time slice, the thread is suspended, and the next thread is controlled to execute in the next time slice. Optionally, when determining the load data of the kernel, the "all threads" mentioned include threads scheduled using different scheduling methods. The purpose of this setting is to ensure that the CPU core with the largest idle computing power is accurately determined.

[0063] It should also be noted that the technical method provided by the present application belongs to a background memory recovery method. In the prior art, another method for memory recovery is direct memory recovery (DR). Direct memory recovery refers to directly starting the memory recovery operation when it is found that the amount of free memory is seriously insufficient when allocating memory to a process. At this time, the process applying for memory will wait until the memory is recovered to a certain amount before it can allocate memory. Obviously, direct memory recovery will cause the application to freeze or delay response, affecting the user experience. The use of the technical solution provided by the present application is conducive to eliminating the situation of direct memory recovery.

[0064] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0065] Figure 5 Schematic diagram of a memory recovery device in an embodiment of the present disclosure. The memory recovery device provided in the embodiment of the present disclosure can be configured in a client or in a server. Figure 5 , the memory recovery device specifically includes:

[0066] A detection module 210, used to detect the amount of free memory;

[0067] The recycling module 220 is used to perform a memory recycling operation using N target threads according to the priority of the target thread if the amount of free memory is less than the first memory water level; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; the priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP≥1.

[0068] Furthermore, the recovery module 220 is used to:

[0069] If the amount of free memory is less than the first memory water level, after performing a memory recovery operation using N target threads according to the priority of the target thread, if the amount of free memory is higher than the second memory water level, the priorities of the P target threads are adjusted so that the priorities of the P target threads after adjustment are lower than the target priority, and the second memory water level is higher than the first memory water level.

[0070] Furthermore, the recovery module 220 is used to:

[0071] If the amount of free memory is higher than a third memory water level, the N target threads are controlled to be in a dormant state, and the third memory water level is higher than the first memory water level.

[0072] Furthermore, the recovery module 220 is used to:

[0073] If the amount of free memory is less than the first memory water level, before using N target threads to perform memory recovery operations according to the priority of the target thread, if the amount of free memory is lower than the fourth memory water level, the N target threads are awakened; at the awakening time, the priorities of the N target threads are all lower than the target priority; according to the priorities of the N target threads at the awakening time, the memory recovery operations are performed using the N target threads;

[0074] If the amount of free memory is lower than the first memory water level, the priorities of P target threads among the N target threads are adjusted so that the priorities of the P target threads after adjustment are higher than the target priority, and the fourth memory water level is higher than the first memory water level.

[0075] Furthermore, the recovery module 220 is used to:

[0076] According to the priorities of the target thread and the candidate thread, time slices are allocated to the target thread and the candidate thread respectively; the candidate thread is a thread that does not perform a memory reclaim operation;

[0077] According to the time slice of the target thread and the time slice of the candidate thread, the target thread and the candidate thread are controlled to run in turn.

[0078] Furthermore, the duration of the time slice of the target thread and the duration of the time slice of the candidate thread are both in direct proportion to the priority.

[0079] Furthermore, the recovery module 220 is used to:

[0080] A central processing unit core with the largest idle computing power is used to run a sub-target thread, wherein the sub-target thread is the target thread having a priority lower than the target priority.

[0081] The memory recovery device provided in the embodiment of the present disclosure can execute the steps executed in the memory recovery method provided in the method embodiment of the present disclosure, and has the same or corresponding beneficial effects, which will not be repeated here.

[0082] Figure 6 Schematic diagram of the structure of an electronic device in the embodiment of the present disclosure. Figure 6, which shows a schematic diagram of the structure of an electronic device 1000 suitable for implementing the embodiment of the present disclosure. The electronic device 1000 in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), wearable electronic devices, etc., and fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 6 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0083] like Figure 6 As shown, the electronic device 1000 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 into a random access memory (RAM) 1003 to implement the memory recovery method of the embodiment described in the present disclosure. In the RAM 1003, various programs and information required for the operation of the electronic device 1000 are also stored. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0084] Typically, the following devices may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange information. Although Figure 6 The electronic device 1000 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0085] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart, thereby implementing the memory recovery method as described above. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 1009, or installed from a storage device 1008, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0086] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include an information signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated information signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0087] In some embodiments, the client and the server may communicate using any known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital information communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any known or future developed network.

[0088] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0089] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device:

[0090] Check the amount of free memory;

[0091] If the amount of free memory is less than the first memory water level, memory recovery operations are performed using N target threads according to the priority of the target thread; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; the priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP≥1.

[0092] Optionally, when the above one or more programs are executed by the electronic device, the electronic device may also execute other steps described in the above embodiments.

[0093] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0094] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0095] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0096] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0097] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0098] According to one or more embodiments of the present disclosure, the present disclosure provides an electronic device, including:

[0099] one or more processors;

[0100] A memory for storing one or more programs;

[0101] When the one or more programs are executed by the one or more processors, the one or more processors implement any memory recovery method provided in the present disclosure.

[0102] According to one or more embodiments of the present disclosure, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any memory reclaiming method provided by the present disclosure.

[0103] The embodiments of the present disclosure also provide a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, the memory recycling method described above is implemented.

[0104] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0105] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory recovery method, characterized in that: include: Check the amount of free memory; If the amount of free memory is less than the first memory watermark, N target threads are used to perform a memory reclaim operation according to the priority of the target thread; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; The priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP ≥ 1.

2. The method according to claim 1, characterized in that If the free memory amount is less than the first memory watermark, after using N target threads to perform the memory recycling operation according to the priority of the target thread, the method further includes: If the amount of free memory is higher than a second memory water level, the priorities of the P target threads are adjusted so that the priorities of the P target threads after adjustment are lower than the target priority, and the second memory water level is higher than the first memory water level.

3. The method according to claim 1, characterized in that Also includes: If the amount of free memory is higher than a third memory water level, the N target threads are controlled to be in a dormant state, and the third memory water level is higher than the first memory water level.

4. The method according to claim 1, characterized in that: If the free memory amount is less than the first memory watermark, before using N target threads to perform the memory reclaiming operation according to the priority of the target thread, the method further includes: If the amount of free memory is lower than the fourth memory water level, the N target threads are awakened; at the awakening time, the priorities of the N target threads are all lower than the target priority; according to the priorities of the N target threads at the awakening time, the memory recovery operation is performed using the N target threads; If the free memory amount is less than the first memory watermark, the memory reclaiming operation is performed using N target threads according to the priority of the target thread, including: If the amount of free memory is lower than the first memory water level, the priorities of P target threads among the N target threads are adjusted so that the priorities of the P target threads after adjustment are higher than the target priority, and the fourth memory water level is higher than the first memory water level.

5. The method according to any one of claims 1 to 4, characterized in that: The memory recycling operation is performed using N target threads according to the priority of the target thread, including: According to the priorities of the target thread and the candidate thread, time slices are allocated to the target thread and the candidate thread respectively; the candidate thread is a thread that does not perform a memory reclaim operation; According to the time slice of the target thread and the time slice of the candidate thread, the target thread and the candidate thread are controlled to run in turn.

6. The method according to claim 5, characterized in that The duration of the time slice of the target thread and the duration of the time slice of the candidate thread are both in direct proportion to the priority.

7. The method according to any one of claims 1 to 4, characterized in that: Also includes: A central processing unit core with the largest idle computing power is used to run a sub-target thread, wherein the sub-target thread is the target thread having a priority lower than the target priority.

8. A memory recovery device, characterized in that: include: A detection module, used to detect the amount of free memory; A recycling module, configured to, if the free memory amount is less than a first memory water level, use N target threads to perform a memory recycling operation according to the priority of the target thread; wherein, among the N target threads, the priorities of P target threads are higher than the target priority; The priorities of NP target threads are lower than the target priority; N and P are both positive integers, and NP ≥ 1.

9. An electronic device, characterized in that: The electronic device comprises: one or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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