Host memory buffer access method, storage device and storage medium

Abstract

The invention discloses a host memory buffer access method, a storage device and a storage medium, and relates to the technical field of memorizers, the method comprises the following steps: monitoring the running state of a bus, and confirming the busy and idle state of the bus, the busy and idle state comprising an idle state and a busy state; if the read-write request is received, acquiring and judging whether to start a transmission process or not according to the busy / idle state; if the bus is in an idle state, starting a transmission process according to the read-write request; and obtaining a to-be-transmitted data packet corresponding to the read-write request, and sending the to-be-transmitted data packet to a bus for transmission. According to the method and the device, the transmission time point of the data packet corresponding to the access request of the hmb can be dynamically adjusted according to the busy / idle state of the bus, so that rapid data transmission can be ensured, and transmission delay caused by data packet blockage is avoided.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a host memory buffer access method, a storage device and a storage medium. Background Art

[0002] HMB (Host Memory Buffer) is a specific area in the host memory. Since the data access speed of the memory is much faster than that of traditional slow storage devices such as hard disks or network storage devices, by utilizing the host's memory resources, HMB technology can significantly improve the performance of SSDs when processing large amounts of data transfer.

[0003] When the Host accesses the HMB intensively, data is frequently read or written from the system memory because each data access involves data transfer between the processor and the memory. These operations require a large amount of memory bandwidth, especially when processing large amounts of data or complex computing tasks, the access frequency of the HMB will increase significantly, further exacerbating the occupation of memory bandwidth. Due to the limited memory bandwidth, when HMB access occupies a large amount of bandwidth, other normal Host read and write commands will be subject to bandwidth limitations when accessing memory, and will need to wait longer to complete data transfer, resulting in increased latency.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a host memory buffer access method, a storage device and a storage medium, aiming to solve the technical problem of how to reduce the transmission delay caused by a busy bus.

[0006] To achieve the above object, the present application proposes a host memory buffer access method, the method comprising:

[0007] Monitor the running status of the bus and confirm the busy and idle status of the bus, which includes idle state and busy state;

[0008] If a read / write request is received, the data is obtained and the busy / idle status is determined to determine whether to start the transmission process. The busy / idle status includes the idle state and the busy state.

[0009] If the bus is in idle state, the transmission process is started according to the read and write request.

[0010] Get the data packet to be transmitted corresponding to the read / write request, and send the data to be transmitted to the bus for transmission.

[0011] In one embodiment, if a read / write request is received, the steps of obtaining and determining whether to start a transmission process according to a busy / idle state, wherein the busy / idle state includes an idle state and a busy state, include:

[0012] If a read / write request is received, an initial data packet corresponding to the read / write request is obtained, and the number of bytes in the initial data packet is determined;

[0013] Compare the number of bytes of the initial data packet with a preset byte number threshold;

[0014] If the number of bytes in the initial data packet is greater than the preset byte number threshold, it is determined whether the bus starts the transmission process according to the busy or idle state.

[0015] In one embodiment, the step of monitoring the running state of the bus and confirming the busy or idle state of the bus includes:

[0016] Acquire the real-time data transmission speed, and compare the real-time data transmission speed with a preset transmission speed threshold;

[0017] If the real-time data transmission speed is less than a preset transmission speed threshold, it is confirmed that the bus is in an idle state.

[0018] In one embodiment, if the bus is in an idle state, the steps after starting the transmission process according to the read / write request may include:

[0019] Determining whether the number of bytes of the initial data packet is greater than a preset bus maximum payload threshold;

[0020] If it is greater, the initial data packet is split according to a preset maximum payload threshold to obtain multiple data packets to be transmitted.

[0021] In one embodiment, the step of sending the data to be transmitted to the bus for transmission includes:

[0022] Sending the data packet to be transmitted to the bus, and transmitting the data packet to be transmitted at a preset first transmission speed;

[0023] The first transmission speed is adjusted according to the change of the unidirectional bandwidth of the bus.

[0024] In one embodiment, after the step of sending the data to be transmitted to the bus for transmission, the method includes:

[0025] After a preset time threshold, confirm whether all the data packets to be transmitted have been transmitted;

[0026] If the transmission is not completed, skip the step of determining whether to start the transmission process according to the busy / idle status and start the transmission process;

[0027] Transmit the untransmitted data packets to be transmitted.

[0028] In one embodiment, after the step of obtaining a data packet to be transmitted and sending the data to be transmitted to a bus for transmission, the following steps are included:

[0029] After the data packet to be transmitted is transferred to the host memory buffer, a completion status mark is generated;

[0030] Generate report information based on completion status flag.

[0031] In one embodiment, the host memory buffer access method further includes:

[0032] Get the remaining capacity of the host memory buffer;

[0033] If the remaining capacity is greater than or equal to the preset capacity alarm value, an alarm message is issued;

[0034] Data is cleaned up according to the preset cache elimination strategy.

[0035] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage device, which includes: a memory, a processor, and a computer program stored in the above-mentioned memory and executable on the above-mentioned processor, and the above-mentioned computer program is configured to implement the steps of the host memory buffer access method as described above.

[0036] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium. A computer program is stored on the storage medium, and when the computer program is executed by the processor, the steps of the host memory buffer access method as mentioned above are implemented.

[0037] The present application provides a host memory buffer access method, which monitors the operating status of the front-end bus to determine whether the bus is busy. When a read or write request is received, the busy or idle status of the bus is first obtained, and whether the read or write request will be processed immediately is determined based on the busy or idle status. If the bus is in an idle state, the data packet to be transmitted in the read or write request is obtained, and the data packet to be transmitted is transmitted. If the bus is in a busy state, it waits until the bus is in an idle state.

[0038] In the present application, when a read or write request is received, whether to perform data transmission is determined based on the busy or idle state of the bus, thereby dynamically adjusting the time point for transmitting the data packet corresponding to the HMB access request based on the busy or idle state of the bus, thereby ensuring that data transmission can be performed quickly and avoiding transmission delays caused by data packet blocking. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 A flowchart diagram of the first embodiment of the host memory buffer access method of the present application is provided;

[0042] Figure 2 A detailed flow chart of the first embodiment of the host memory buffer access method of the present application is provided;

[0043] Figure 3 A flowchart diagram of the second embodiment of the host memory buffer access method of the present application is provided;

[0044] Figure 4 A flowchart diagram of the host memory buffer access method embodiment 3 and embodiment 4 of the present application;

[0045] Figure 5 Schematic diagram of the device structure of the hardware operating environment involved in the host memory buffer access method in the embodiment of the present application. DETAILED DESCRIPTION

[0046] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0047] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0048] The main solution of the embodiment of the present application is: monitor the operating status of the bus, confirm the busy and idle status of the bus, and the busy and idle status includes idle status and busy status; if a read or write request is received, obtain it and determine whether to start the transmission process based on the busy or idle status; if the bus is in an idle state, start the transmission process based on the read or write request; obtain the data packet to be transmitted corresponding to the read or write request, and send the data packet to be transmitted to the bus for transmission.

[0049] HMB (Host Memory Buffer) is a specific area in the host memory. Since the data access speed of the memory is much faster than that of traditional slow storage devices such as hard disks or network storage devices, by utilizing the host's memory resources, HMB technology can significantly improve the performance of SSDs when processing large amounts of data transfer.

[0050] When the host accesses the HMB intensively, data is frequently read or written from the system memory because each data access involves data transfer between the processor and the memory. These operations require a large amount of memory bandwidth, especially when processing large amounts of data or complex computing tasks, the access frequency of the HMB will increase significantly, further exacerbating the occupation of memory bandwidth. Due to the limited memory bandwidth, when HMB access occupies a large amount of bandwidth, other normal host read and write commands will be subject to bandwidth constraints when accessing memory, and it will take longer to complete data transfer, resulting in increased latency.

[0051] In order to solve the above problems, the present application provides a host memory buffer access method, which monitors the operating status of the front-end bus to determine whether the bus is busy. When a read or write request is received, the busy or idle status of the bus is first obtained, and whether the read or write request will be processed immediately is determined based on the busy or idle status. If the bus is in an idle state, the data packet to be transmitted in the read or write request is obtained, and the data packet to be transmitted is transmitted. If the bus is in a busy state, it waits until the bus is in an idle state.

[0052] In the present application, when a read or write request is received, whether to perform data transmission is determined based on the busy or idle state of the bus, thereby dynamically adjusting the time point for transmitting the data packet corresponding to the HMB access request based on the busy or idle state of the bus, thereby ensuring that data transmission can be performed quickly and avoiding transmission delays caused by data packet blocking.

[0053] It should be noted that the execution subject of this embodiment can be a computing service device with network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, Nandflash and its corresponding controller and SSD and its corresponding controller, etc., or an electronic device or device capable of realizing the above functions. The following takes a flash memory storage device as an example to illustrate this embodiment and the following embodiments.

[0054] Based on this, the present application embodiment provides a host memory buffer access method, referring to Figure 1 , Figure 1 This is a flowchart of the first embodiment of the host memory buffer access method of the present application.

[0055] In this embodiment, the host memory buffer access method includes steps S100 to S400:

[0056] Step S100, monitoring the running state of the bus to confirm the busy and idle states of the bus, where the busy and idle states include an idle state and a busy state.

[0057] Step S200: If a read / write request is received, the request is obtained and it is determined whether to start the transmission process according to the busy / idle status.

[0058] It should be noted that the bus (PCIe, Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard used to connect various devices in a computer system, such as graphics cards, solid-state drives (SSDs), network interface cards, etc.

[0059] In this embodiment, the operating status of the bus is monitored by a controller, a processor or other components that can directly access and monitor the status of the PCIe bus. The bus activity, transmitted data packets and related control signals are monitored. This helps the system manage resources more effectively and ensures that data can be smoothly transmitted between various devices.

[0060] In this embodiment, whether the bus is in an idle state can be confirmed by counting PCIe transaction layer packets (TLPs), measuring the transmission time window, and directly evaluating the bus occupancy.

[0061] When counting PCIe transaction layer packets (TLPs) to confirm whether the bus is idle, set a counter to monitor the traffic of TLPs on the PCIe bus. Record the total number of TLPs sent and received over a period of time, as well as the number of each type of TLP. If the number of TLPs is low or almost non-existent, it may indicate that the PCIe bus is idle. If the number of TLPs is continuously high, it indicates that the PCIe bus is busy with data transmission.

[0062] When confirming whether the bus is idle through transfer time window measurement, select an appropriate time window length for measuring the transfer activity of the PCIe bus. The length of the time window should be determined according to the actual application scenario and performance requirements. Record timestamps at the beginning and end of the time window. Calculate the transfer time of the PCIe bus within the time window based on the timestamps. The transfer time can be expressed as the proportion of time the bus is busy within the time window or as the absolute length of time. If the transfer time is short or almost zero, it may indicate that the PCIe bus is idle within the time window. If the transfer time is long, it indicates that the PCIe bus is performing data transfer within the time window.

[0063] When evaluating whether the bus is idle by bus occupancy, use hardware counters or software tools to monitor the activity of the PCIe bus. Calculate the bus occupancy based on the monitoring results, that is, the proportion of time the bus is busy. If the bus occupancy is very low or almost zero, it may indicate that the PCIe bus is idle most of the time. If the bus occupancy is continuously high, it indicates that the PCIe bus is being used frequently.

[0064] Optionally, the results of TLP count, transfer time window measurement, and bus occupancy evaluation can be combined for analysis. If the number of TLPs is small, the transfer time is short, and the bus occupancy is low, the PCIe bus can be judged to be idle. If any of the above indicators indicate that the PCIe bus is busy, the bus cannot be considered idle.

[0065] In one possible implementation, please refer to Figure 2 Step S100, monitoring the running state of the bus to confirm the busy or idle state of the bus, may include steps S110 to S120:

[0066] Step S110, obtaining the real-time data transmission speed, and comparing the real-time data transmission speed with a preset transmission speed threshold.

[0067] Step S120: If the real-time data transmission speed is less than a preset transmission speed threshold, it is confirmed that the bus is in an idle state.

[0068] In this embodiment, a transmission speed threshold S1 is preset according to system requirements and performance requirements. The uplink or downlink transmission speed of the data packet on the bus is obtained through a preset detection time interval or real-time monitoring, and the monitored data packet transmission speed is compared with the preset threshold S1. The uplink data packet transmission speed refers to the speed of transmitting data from a lower-level device (such as a peripheral or subsystem) to a higher-level device (such as a central processing unit or main memory); and the downlink data packet transmission speed refers to the speed of transmitting data from a higher-level device to a lower-level device. If the data packet speed is less than S1, it is considered that the PCIe bus is in an idle state, and this idle time window is used to transmit data. After determining that the bus is in an idle state, the start condition of data transmission is triggered and data transmission is started. During the data transmission process, the speed of the PCIe uplink or downlink data packet is continuously monitored. If the data packet speed suddenly increases and exceeds S1, the transmission is suspended to avoid overloading the PCIe bus.

[0069] In a feasible implementation, in addition to comparing the real-time data transmission speed with the preset speed threshold, the probe can be connected to the relevant signal line of the bus through an oscilloscope, a logic analyzer or a dedicated bus analysis tool to monitor the state signal of the bus to determine whether the bus is in an idle state. Exemplarily, if the FRAME# signal is high (inactive state), and the IRDY# and TRDY# signals are also high (inactive state), it means that the bus is currently in an idle state. If the FRAME# signal is pulled low (active state), it means that a new transaction is in progress. At this time, it is necessary to further check the status of the IRDY# and TRDY# signals, and whether there is data transmission on the data line to determine the busy and idle state of the bus.

[0070] In one possible implementation, please refer to Figure 2 , step S200, if a read / write request is received, then obtain and determine whether to start the transmission process according to the busy / idle status, the busy / idle status includes the idle state and the busy state, and can include steps S210 to S230:

[0071] Step S210: If a read / write request is received, an initial data packet corresponding to the read / write request is obtained, and the number of bytes of the initial data packet is determined.

[0072] Step S220, comparing the number of bytes of the initial data packet with a preset byte number threshold.

[0073] Step S230: If the number of bytes of the initial data packet is greater than a preset byte number threshold, it is determined whether the bus starts the transmission process according to the busy / idle state.

[0074] In this embodiment, after receiving a read / write request, the read / write request is parsed to obtain an initial data packet and its byte count. A preset byte count threshold is obtained from a configuration or parameter, and the byte count of the initial data packet is compared with the preset byte count threshold. If the byte count of the initial data packet is less than or equal to the preset byte count threshold, data transmission is performed directly. If the byte count of the initial data packet is greater than the preset byte count threshold, the step of determining the bus state is entered, and when the bus is in an idle state, the transmission is started. Exemplarily, the preset byte count threshold is 4KB. When the byte count of the initial data packet corresponding to the received write request is greater than 4KB, it cannot be directly transmitted, but the idle / busy state of the bus needs to be determined. If the bus is in an idle state, the data packet to be transmitted corresponding to the initial data packet is transmitted, and the data packet to be transmitted is written to the space allocated by the host.

[0075] In this implementation, since the large data packet occupies a longer time on the bus, this will cause the read and write commands of other hosts to wait longer to access the bus. This waiting will increase the latency of other commands. By setting transmission conditions for the large data packet, the large data packet is transmitted when the transmission conditions are met, which can prevent the large data packet from blocking other read and write commands.

[0076] In this embodiment, starting the transmission when the bus is idle can ensure that no other device is occupying the bus, thereby avoiding conflicts and errors in the data transmission process and improving the overall efficiency of data transmission. In addition, avoiding starting the transmission when the bus is busy can reduce the interference of other devices on data transmission and ensure the integrity and accuracy of the data.

[0077] Step S300: If the bus is in an idle state, the transmission process is started according to the read / write request.

[0078] Step S400, obtaining a data packet to be transmitted corresponding to a read / write request, and sending the data to be transmitted to a bus for transmission.

[0079] In this embodiment, the condition for starting the transmission process is that the bus is in an idle state. If the bus is not in an idle state, the data transmission is delayed until the bus becomes idle. When the bus is detected to be in an idle state, the next data packet to be transmitted is obtained from the queue to be transmitted until all data packets to be transmitted are transmitted.

[0080] In one possible implementation, please refer to Figure 2 , step S400, sending the data to be transmitted to the bus for transmission, may include steps S410 to S420:

[0081] Step S410, sending the data packet to be transmitted to the bus, and transmitting it at a first transmission speed;

[0082] Step S420: adjusting the first transmission speed according to the change of the unidirectional bandwidth of the bus.

[0083] It should be noted that the unidirectional bandwidth is the maximum data transfer rate that the PCIe bus can support in a single direction.

[0084] In this embodiment, after the transmission process is started, the data packet to be transmitted is transmitted at a preset first transmission speed. The first transmission speed is set based on the system configuration or previous transmission experience. During the data transmission process, the unidirectional bandwidth usage of the PCIe bus is continuously monitored. The first transmission speed is dynamically adjusted according to the actual bandwidth usage of the PCIe bus. If the bus bandwidth usage increases (that is, other devices begin to occupy more bandwidth), the first transmission speed is reduced to ensure that the total bandwidth usage does not exceed the preset unidirectional bandwidth S0. If the bus bandwidth usage decreases, the first transmission speed can be appropriately increased to improve the transmission efficiency. During the adjustment process, ensure that the sum of the transmission speed threshold S1 and the first transmission speed S2 is less than the preset unidirectional bandwidth S0.

[0085] In this implementation, by dynamically adjusting the first transmission speed, it is possible to ensure that the bandwidth usage of the PCIe bus remains within a reasonable range, thereby avoiding bus congestion and data transmission delays.

[0086] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 3 In step S300, if the bus is in an idle state, after starting the transmission process according to the read / write request, steps A100 to A200 may also be included:

[0087] Step A100, determining whether the number of bytes of the initial data packet is greater than a preset bus maximum effective load threshold.

[0088] Step A200: If it is greater than, the initial data packet is split according to a preset maximum effective load threshold to obtain multiple data packets to be transmitted.

[0089] It should be noted that the bus maximum effective load threshold refers to the limit on the maximum amount of data or information that can be transmitted on the bus.

[0090] In this embodiment, Fw (firmware) makes a read and write request to HMB. After receiving the read and write request, it traverses each byte of the data packet and counts to obtain the number of bytes of the initial data packet. The maximum payload threshold supported by the bus is obtained from the configuration or parameters, and the number of bytes of the initial data packet is compared with the maximum payload threshold. If the number of bytes of the initial data packet is greater than the maximum payload value, the initial data packet is split according to the preset maximum payload threshold to obtain multiple data packets to be transmitted. The size of the initial data packet is n, and the max pay load size configured by PCIe is m. The data packet is divided into n / m=k data packets with transmission, and k is rounded up. Exemplarily, the max pay load size configured by Pcie is 256B. The size of each split data packet does not exceed the maximum payload threshold. The split data packets are stored in the host memory buffer. By splitting the data packets, it can be ensured that each data packet can be correctly processed by the bus to avoid communication errors.

[0091] In the present embodiment, in the PCIe bus, TLP (Transaction Layer Packet) is the basic unit of data transmission. The maximum payload threshold (Max Payload Size) of the PCIe configuration defines the maximum length of the data payload in the TLP. When the size of the data packet sent exceeds the Max Payload Size, this data will be divided into multiple small data packets (i.e., data packets to be transmitted). Each transmission packet will contain the necessary header information to ensure that the receiving end can correctly identify and process it. In order to ensure the integrity and order of the data, the sending end may add a sequence number or checksum to each small data packet. After receiving all the small data packets, the receiving end will reorganize and verify the data according to the sequence number or checksum.

[0092] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 4 In step S300, after obtaining the data packet to be transmitted and sending the data to be transmitted to the bus for transmission, steps S500 to S700 may also be included:

[0093] Step S500: after a preset time threshold, confirm whether all the data packets to be transmitted have been transmitted.

[0094] Step S600: If the transmission is not completed, skip the step of determining whether to start the transmission process according to the busy / idle status and start the transmission process.

[0095] Step S700: Transmit the untransmitted data packets to be transmitted.

[0096] In this embodiment, if the transmission of all data packets cannot be completed within the set time threshold t, whether to continue the transmission is no longer determined based on whether the speed is less than S1. Even if the current PCIe uplink speed is greater than or equal to S1, the remaining data packets are continued to be transmitted to ensure that the data can be completely transmitted to the host.

[0097] In this embodiment, a time threshold t is set, and a list packets_to_transmit is initialized to store the data packets to be transmitted. A variable transmitted_packets is initialized to record the number of data packets that have been transmitted. The data packets to be transmitted are added to the packets_to_transmit list. A timer or a timer is used to check whether the preset time threshold t is reached. After the time threshold is reached, check whether transmitted_packets is equal to the length of packets_to_transmit. If transmitted_packets is equal to the length of packets_to_transmit, it means that all data packets have been transmitted and the process ends. If transmitted_packets is not equal to the length of packets_to_transmit, it means that there are still data packets that have not been transmitted. At this time, it is no longer determined whether the bus is idle, and the data packets that have not been transmitted in packets_to_transmit are directly transmitted. Traverse the packets_to_transmit list and start transmitting data packets from the next index of transmitted_packets. After each data packet is transmitted, update the value of transmitted_packets until all data packets have been transmitted and the process ends.

[0098] In this embodiment, by setting a time threshold, it is possible to wait for the transmission of a data packet within a reasonable time range. If the data packet is not transmitted within the preset time, it is possible to respond quickly and start the process of transmitting the remaining data packets, avoiding long waiting times, thereby improving the overall transmission efficiency. In addition, in the process of waiting for data packet transmission, if resources (such as CPU time, memory, etc.) are constantly occupied for bus status checking, it will lead to resource waste. By setting a time threshold and directly transmitting the remaining data packets after the timeout, it is possible to reduce resource waste.

[0099] Based on the first embodiment of the present application, in the fourth embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above description, and will not be described in detail later. Figure 4 , after step S400, steps S800 to S900 are also included:

[0100] Step S800: after the data packet to be transmitted is transmitted to the host memory buffer, a completion status mark is generated.

[0101] Step S900, generating reporting information according to the completion status mark.

[0102] In this embodiment, when the data packet is confirmed to have been completely transmitted to the host memory buffer, a completion status mark is generated. This mark can be a simple flag, a status code, or a structure containing more detailed information. The content of the mark includes information such as the data packet ID, the transmission timestamp, whether the transmission is successful, whether the transmission time exceeds the preset time threshold and triggers a forced transmission. The feedback information may include confirmation that the data packet has been received, the status of successful transmission, and any related error codes or warning information.

[0103] In this embodiment, after the transmission is completed, a report message is sent to the firmware to inform whether the transmission is successfully completed and whether a forced transmission caused by a timeout occurs. The firmware takes corresponding measures based on the information in the report message, such as recording a log, notifying the user, or retrying the transmission.

[0104] Based on the first embodiment of the present application, in the fifth embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above description, and will not be described in detail later. On this basis, the method further includes the following steps:

[0105] Get the remaining capacity of the host memory buffer.

[0106] If the remaining capacity is greater than or equal to the preset capacity alarm value, an alarm message is issued.

[0107] Data is cleaned up according to the preset cache elimination strategy.

[0108] In this embodiment, the remaining capacity of the host memory buffer is monitored. When it is detected that the remaining capacity is greater than or equal to the preset capacity alarm value, it means that the buffer capacity is insufficient to accommodate the upcoming data packets. An alarm message is issued, and data is cleaned according to the preset elimination strategy. Data packets that are not very critical or can tolerate a certain loss rate are selected and discarded. Then, when necessary (for example, when data loss or error is detected), request to retransmit these data packets. Optionally, when monitoring the usage of the buffer, data such as the cache hit rate, miss rate, cache size, and the number of data items in the cache can also be obtained. This is used to evaluate cache performance and adjust elimination strategies.

[0109] In this embodiment, data is cleaned up according to a preset cache elimination strategy. The cache elimination strategy determines which data items should be removed or replaced when the cache space is insufficient. The cache elimination strategy may include: Least Recently Used (LRU) strategy, which removes the least recently accessed data items. Least Frequently Used (LFU) strategy, which removes the data items with the lowest access frequency. First In First Out (FIFO) strategy, which removes the data items that entered the cache earliest. Size or weight-based elimination: determines which data items to eliminate based on the size or weight of the data items.

[0110] In this embodiment, when the cache space is insufficient, data items are selected and removed or replaced according to a preset elimination strategy. According to the elimination strategy, determine which data items should be removed, and delete the selected data items from the cache. And regularly evaluate the cache performance and the effectiveness of the elimination strategy. If the cache hit rate decreases or the miss rate increases, adjust the elimination strategy or increase the cache capacity. Dynamically adjust the size of the buffer according to the current data transmission requirements and system load. By continuously monitoring the cache usage and performing data elimination according to the preset cache elimination strategy, it can be ensured that the cache system always maintains good performance. While ensuring the stability of data transmission, the flexibility and response speed of the system are improved.

[0111] The present application provides a storage device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the host memory buffer access method in the above-mentioned embodiment one.

[0112] Reference below Figure 5 , which shows a schematic diagram of the structure of a storage device suitable for implementing the embodiments of the present application. The storage device in the embodiments of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The storage device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0113] like Figure 5As shown, the storage device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the storage device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the storage device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a storage device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0114] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0115] The storage device provided by the present application adopts the host memory buffer access method in the above embodiment, which can solve the technical problem of how to reduce the transmission delay caused by the busy bus. Compared with the prior art, the beneficial effects of the storage device provided by the present application are the same as the beneficial effects of the host memory buffer access method provided by the above embodiment, and other technical features in the storage device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0116] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0117] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the above claims.

[0118] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, wherein the computer-readable program instructions are used to execute the host memory buffer access method in the above-mentioned embodiment.

[0119] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0120] The computer-readable storage medium may be included in a storage device, or may exist independently without being installed in a storage device.

[0121] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the storage device, the flash memory storage device: monitors the operating status of the bus, confirms the busy and idle status of the bus, and the busy and idle status includes the idle state and the busy state; if a read or write request is received, obtains it and determines whether to start the transmission process according to the busy and idle state; if the bus is in the idle state, starts the transmission process according to the read or write request; obtains the data packet to be transmitted corresponding to the read or write request, and sends the data packet to be transmitted to the bus for transmission.

[0122] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0123] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0124] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0125] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned host memory buffer access method, and can solve the technical problem of how to reduce the transmission delay caused by the busy bus. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the host memory buffer access method provided by the above-mentioned embodiment, and will not be repeated here.

[0126] The above are only some embodiments of the present application, and do not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the technical concept of the present application, or directly / indirectly used in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A host memory buffer access method, characterized in that: The method comprises: Monitor the running state of the bus to confirm the busy and idle states of the bus, wherein the busy and idle states include an idle state and a busy state; If a read / write request is received, the request is obtained and judged whether to start the transmission process according to the busy / idle status; If the bus is in the idle state, starting a transmission process according to the read / write request; Acquire the data packet to be transmitted corresponding to the read / write request, and send the data packet to be transmitted to the bus for transmission.

2. The host memory buffer access method according to claim 1, wherein: The step of monitoring the running state of the bus and confirming the busy or idle state of the bus comprises: Acquire a real-time data transmission speed, and compare the real-time data transmission speed with a preset transmission speed threshold; If the real-time data transmission speed is less than the preset transmission speed threshold, the bus is in the idle state.

3. The host memory buffer access method according to claim 1, wherein: If a read / write request is received, the step of determining whether to start a transmission process according to the busy / idle status includes: If the read / write request is received, obtaining an initial data packet corresponding to the read / write request, and determining the number of bytes of the initial data packet; Compare the number of bytes of the initial data packet with a preset byte number threshold; If the number of bytes of the initial data packet is greater than the preset byte number threshold, whether to start the transmission process is determined according to the busy / idle state.

4. The host memory buffer access method according to claim 3, wherein: After the step of starting the transmission process according to the read / write request if the bus is in an idle state, the method further includes: Determining whether the number of bytes of the initial data packet is greater than a preset bus maximum effective load threshold; If it is greater, the initial data packet is split according to the preset bus maximum effective load threshold to obtain a plurality of data packets to be transmitted.

5. The host memory buffer access method according to claim 1, wherein: The step of sending the data packet to be transmitted to the bus for transmission comprises: Sending the data packet to be transmitted to the bus, and transmitting the data packet to be transmitted at a preset first transmission speed; The first transmission speed is adjusted according to a change in the unidirectional bandwidth of the bus.

6. The host memory buffer access method according to claim 1, wherein: After the step of sending the data packet to be transmitted to the bus for transmission, the method further comprises: After a preset time threshold, confirm whether all the data packets to be transmitted have been transmitted; If the transmission is not completed, skipping the step of judging whether to start the transmission process according to the busy / idle status, and starting the transmission process; The untransmitted data packets to be transmitted are transmitted.

7. The host memory buffer access method according to claim 1, wherein: After the step of obtaining the data packet to be transmitted and sending the data packet to be transmitted to the bus for transmission, the following steps are included: After the data packet to be transmitted is transmitted to the host memory buffer, generating a completion status mark; Generate reporting information according to the completion status mark.

8. The host memory buffer access method according to claim 1, wherein: The method further comprises: Obtaining the remaining capacity of the host memory buffer; If the remaining capacity is greater than or equal to the preset capacity alarm value, an alarm message is issued; Data is cleaned up according to the preset cache elimination strategy.

9. A storage device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the host memory buffer access method according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the host memory buffer access method according to any one of claims 1 to 8 are implemented.

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