Display device, timing controller and control method thereof
By detecting and adjusting the voltage of the IIC clock and data lines, the problem of IIC signals not meeting the protocol under different timing controllers and memory combinations was solved, thus achieving display stability and power consumption optimization.
Patent Information
- Application Number
- CN202510207976.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2045-02-25
AI Technical Summary
When different timing controllers and memories are used together, the IIC signal may not meet the protocol requirements, resulting in encoding and reading errors, affecting the display screen, and also causing high power consumption.
By detecting the voltage signal of the IIC clock line, adjusting the voltage of the IIC clock line and data line after a set delay, the voltage is ensured to meet the protocol requirements. If necessary, the voltage is adjusted through a pull-up resistor loop to meet the IIC protocol. The voltage supply is optimized by combining the parameters stored in the register.
By combining different timing controllers and memory, we can ensure that the IIC signal meets the protocol requirements, avoid encoding and reading errors, and achieve the effect of saving power consumption.
Smart Images
Figure CN119942955B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to a display device, a timing controller and a control method thereof. BACKGROUND
[0002] In the era of rapid development of electronic technology, consumers have higher and higher requirements for the stability and low power consumption of electronic devices. In the driving circuit of some display devices, at least a timing controller (TCON) and a memory are included, the memory stores the code required by the timing controller, and communication is established between the timing controller and the memory to obtain the required code.
[0003] However, there is an inter-chip difference between different timing controllers and different memories. Exemplarily, the timing controller and the memory communicate through IIC, and when different timing controllers and memories or different timing controllers and different memories work together to obtain the code, the inter-chip difference between them may cause the IIC signal to not meet the requirements of the IIC protocol, and thus the code reading error occurs, causing the display picture to be abnormal. SUMMARY
[0004] In view of the above problems, the purpose of the present application is to provide a display device, a timing controller and a control method thereof, which not only ensures that the voltage on the IIC clock line and the IIC data line meets the IIC protocol requirements when different timing controllers and different memories work together, but also saves power consumption.
[0005] According to an aspect of the present application, a timing controller is provided for obtaining a code from a memory through an IIC clock line and an IIC data line, comprising:
[0006] a detection unit for obtaining a voltage detection signal of the IIC clock line at different times;
[0007] a control unit for obtaining a first time when the voltage of the IIC clock line reaches a set voltage for the first time according to the voltage detection signal, and judging whether the voltage of the IIC clock line reaches the set voltage after the first time is delayed for a set time according to the voltage detection signal;
[0008] a voltage switching unit for adjusting the voltage provided to the IIC data line and the IIC clock line in the case that the voltage of the IIC clock line does not reach the set voltage after the first time is delayed for the set time; and
[0009] a register for storing the corresponding IIC set parameters in the case that the voltage of the IIC clock line reaches the set voltage after the first time is delayed for the set time,
[0010] The control unit continues to receive the voltage detection signal after adjusting the voltage provided to the IIC data line and the IIC clock line.
[0011] Optionally, the control unit also invokes the IIC setting parameters in the register and provides corresponding voltages to the IIC data line and the IIC clock line through the voltage switching unit during the timing controller power-on stage.
[0012] Optionally, the control unit generates n groups of first control signals and second control signals according to the IIC setting parameters or according to the IIC setting parameters and step values, n being an integer greater than 1,
[0013] The voltage switching unit includes n first pull-up resistance circuits and n second pull-up resistance circuits,
[0014] Each first pull-up resistance circuit includes a first pull-up resistance, a first switch tube, and a second switch tube, the control end of the first switch tube receiving a corresponding first control signal, the first end of the first switch tube being grounded, the second end of the first switch tube being connected to the control end of the second switch tube, the second end of the second switch tube being connected to the power supply line via the first pull-up resistance, and the first end of the second switch tube being connected to the IIC clock line to provide a corresponding voltage;
[0015] Each second pull-up resistance circuit includes a second pull-up resistance, a third switch tube, and a fourth switch tube, the control end of the third switch tube receiving a corresponding second control signal, the first end of the third switch tube being grounded, the second end of the third switch tube being connected to the control end of the fourth switch tube, the second end of the fourth switch tube being connected to the power supply line via the second pull-up resistance, and the first end of the fourth switch tube being connected to the IIC data line to provide a corresponding voltage.
[0016] Optionally, the IIC setting parameters include the resistance values of the first pull-up resistances in the first pull-up resistance circuits that are turned on and the resistance values of the second pull-up resistances in the second pull-up resistance circuits that are turned on,
[0017] or the IIC setting parameters include two n-bit binary numbers, one n-bit binary number being composed of the levels of each first control signal and the other n-bit binary number being composed of the levels of each second control signal.
[0018] Optionally, the detection unit includes:
[0019] a voltage dividing network connected between the power supply line and the ground;
[0020] an operational amplifier, the first input end of the operational amplifier being connected to the voltage dividing node of the voltage dividing network, the second input end of the operational amplifier being connected to the output end thereof, and the output end of the operational amplifier outputting a setting voltage; and
[0021] a comparator, a first input terminal of the comparator is connected to the IIC clock line to receive a voltage of the IIC clock line, a second input terminal of the comparator is connected to the output terminal of the operational amplifier to receive the set voltage, and an output terminal of the comparator outputs the voltage detection signal.
[0022] According to another aspect of the present application, a control method of a timing controller is provided, the timing controller obtains a code from a memory through an IIC clock line and an IIC data line, comprising:
[0023] a detection unit obtains voltage detection signals of the IIC clock line at different times;
[0024] a control unit obtains a first time when a voltage of the IIC clock line reaches a set voltage for the first time according to the voltage detection signals;
[0025] and determines whether the voltage of the IIC clock line reaches the set voltage after the first time is delayed by a set time according to the voltage detection signals;
[0026] a register stores a corresponding IIC set parameter in a case that the voltage of the IIC clock line reaches the set voltage after the first time is delayed by the set time; and
[0027] a voltage switching unit adjusts a voltage provided to the IIC data line and the IIC clock line in a case that the voltage of the IIC clock line does not reach the set voltage after the first time is delayed by the set time, and the control unit continues to obtain the voltage detection signals.
[0028] Optionally, before obtaining the voltage detection signals of the IIC clock line at different times, the method further comprises:
[0029] calling the stored IIC set parameter to provide a corresponding voltage to the IIC data line and the IIC clock line.
[0030] Optionally, adjusting the voltage provided to the IIC data line and the IIC clock line comprises:
[0031] generating n groups of first control signals and second control signals according to the IIC set parameter and a step value, n is an integer greater than 1;
[0032] turning on a corresponding first pull-up resistor circuit to output a corresponding voltage to the IIC clock line and turning on a corresponding second pull-up resistor circuit to output a corresponding voltage to the IIC data line based on the n groups of first control signals and second control signals.
[0033] Optionally, the IIC setting parameters include resistance values of the first pull-up resistors in the first pull-up resistor circuits and resistance values of the second pull-up resistors in the second pull-up resistor circuits, or the IIC setting parameters include two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal.
[0034] According to another aspect of the present application, a display device is provided, comprising an IIC clock line and an IIC data line; a memory storing a code; a timing controller as described above, providing corresponding voltages to the IIC clock line and the IIC data line, and obtaining the code from the memory through the IIC clock line and the IIC data line to configure the timing controller.
[0035] The display device, the timing controller and the control method thereof provided by the present application can obtain voltage detection signals of the IIC clock line at different times, delay a set time when the voltage of the IIC clock line reaches the set voltage for the first time, record the voltages provided to the IIC data line and the IIC clock line in the case that the voltage of the IIC clock line reaches the set voltage, adjust the voltages provided to the IIC data line and the IIC clock line in the case that the voltage of the IIC clock line does not reach the set voltage, and continue to obtain voltage detection signals of the IIC clock line at different times. Thus, the timing controller of the present application can provide appropriate voltages to the IIC clock line and the IIC data line, which can ensure that the voltages on the IIC clock line and the IIC data line meet the IIC protocol requirements when different timing controllers and different memories are matched to work, thereby avoiding the situation that the display screen is abnormal due to the encoding reading error, and can save power consumption. BRIEF DESCRIPTION OF DRAWINGS
[0036] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:
[0037] Figure 1 FIG. 1 shows a structure schematic diagram of a display device according to an embodiment of the present application;
[0038] Figure 2 FIG. 2 shows a circuit schematic diagram of a detection unit in a timing controller according to an embodiment of the present application;
[0039] Figure 3 FIG. 3 shows a waveform schematic diagram of voltage detection performed by a timing controller according to an embodiment of the present application;
[0040] Figure 4 FIG. 4 shows a circuit schematic diagram of a voltage switching unit in a timing controller according to an embodiment of the present application;
[0041] Figure 5 Fig. 1 shows a flow diagram of a control method of a timing controller according to an embodiment of the present application. DETAILED DESCRIPTION
[0042] Various embodiments of the present application will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals. For the purpose of clarity, not every component is drawn to scale.
[0043] At present, a pull-up resistor with a small resistance is generally configured on an IIC data line and an IIC clock line, so that the voltage on the IIC clock line and the IIC data line can meet the IIC protocol requirement when different timing controllers and different memories are matched to work. However, the above scheme will increase power consumption.
[0044] The specific embodiments of the present application will be further described in detail below with reference to the drawings and embodiments.
[0045] Figure 1 Fig. 1 shows a structural diagram of a display device according to an embodiment of the present application.
[0046] The display device at least includes a display panel and a driving circuit. The display panel for example includes a plurality of pixel units. The driving circuit is used to drive the plurality of pixel units in the display panel to realize picture display.
[0047] As shown in Fig. 1, the driving circuit at least includes a serial bidirectional bus, a timing controller 100 and a memory 200. Figure 1
[0048] The memory 200 is for example a programmable erasable memory (EEPROM) and is used to store the code required by the timing controller 100. The code for example includes initialization code.
[0049] The timing controller 100 and the memory 200 communicate through the serial bidirectional bus to read the code and at least perform initialization configuration. The serial bidirectional bus for example includes an IIC data line SDA and an IIC clock line SCL. Exemplarily, the timing controller 100 includes a control unit 110, which reads the code stored in the memory through the IIC data line SDA and the IIC clock line SCL and at least completes the initialization configuration of the timing controller 100.
[0050] Further, the timing controller 100 can also provide appropriate voltages to the IIC clock line and the IIC data line to ensure that the voltages on the IIC clock line and the IIC data line meet the IIC protocol requirements when different timing controllers and different memories are used together. For example, the timing controller 100 further includes a detection unit 120, a voltage switching unit 130, and a register 140. The detection unit 120 is connected to the IIC clock line SCL and is configured to obtain a voltage detection signal of the IIC clock line SCL at different times. The control unit 110 is connected to the detection unit 120 and is configured to obtain a first time T1 at which the voltage of the IIC clock line SCL reaches a set voltage for the first time according to the voltage detection signal, and determine whether the voltage of the IIC clock line SCL reaches the set voltage after the first time T1 is delayed by a set time t according to the voltage detection signal. The voltage switching unit 130 is connected to the control unit 110 and the IIC data line SDA and the IIC clock line SCL, and is configured to adjust the voltages provided to the IIC data line SDA and the IIC clock line SCL if the voltage of the IIC clock line SCL does not reach the set voltage after the first time T1 is delayed by the set time t. The register 140 is connected to the control unit 110 and is configured to store IIC setting parameters corresponding to the case where the voltage of the IIC clock line SCL reaches the set voltage after the first time T1 is delayed by the set time t. The control unit 110 is further configured to continue to receive the voltage detection signal from the detection unit 120 after adjusting the voltages provided to the IIC data line SDA and the IIC clock line SCL.
[0051] In other embodiments, during the timing controller power-on stage, the control unit 110 first calls the IIC setting parameters in the register 140, and then controls the voltage switching unit 130 to provide corresponding voltages to the IIC data line SDA and the IIC clock line SCL. The IIC setting parameters are values stored in the register 140 after being adjusted or initial values preset in advance.
[0052] Further, the timing controller 100 also receives data signals from the host system and provides corresponding data signals. For example, the timing controller 100 further includes a data receiving unit 150, a data processing unit 160, and a data output unit 170. The data receiving unit 150 receives data signals from the host system and transmits the data signals to the data processing unit 160 through the register 140 or directly, and then the data processing unit 160 transmits corresponding data to the data output unit 170, and the data output unit 170 outputs the data signals. For example, the data processing unit 160 can at least reorder the data signals. For example, the timing controller 100 transmits display data to a data driving circuit in a driving circuit, and the data output unit 170 of the timing controller 100 transmits the display data to a P2P (Point-to-Point) interface of the data driving circuit through the P2P interface. The display data output by the timing controller 100 is transmitted to the data driving circuit in the form of a Package. For example, one Package includes a plurality of UI (Unit Interval).
[0053] Further, the IIC data line SDA and the IIC clock line SCL are respectively connected to the power supply line VDD through resistors.
[0054] Figure 2 A circuit schematic diagram of a detection unit in a timing controller according to an embodiment of the present application is shown. Figure 3 A waveform schematic diagram of voltage detection performed by a timing controller according to an embodiment of the present application is shown.
[0055] As Figure 2As shown, the detection unit 120 includes a comparator U1, an operational amplifier U2, and a voltage divider network. The voltage divider network is connected between the power supply line VDD and ground. The first input terminal of the operational amplifier U2 is connected to the voltage divider node of the voltage divider network, and the second input terminal of the operational amplifier U2 is connected to its output terminal. The output terminal of the operational amplifier U2 outputs a set voltage Vref. The first power supply terminal of the operational amplifier U2 receives the voltage VLED, and the second power supply terminal of the operational amplifier U2 is grounded. The voltage divider network includes, for example, resistors R3 and R4, which are connected in series between the power supply line VDD and ground. The connection node of resistors R3 and R4 serves as the voltage divider node. The first input terminal of the comparator U1 is connected to the IIC clock line SCL to receive the voltage VSCL of the IIC clock line SCL. The second input terminal of the comparator U1 is connected to the output terminal of the operational amplifier U2 to receive the set voltage Vref. The output terminal of the comparator U1 outputs a voltage detection signal SCLC. The first power supply terminal of the comparator U1 receives the supply voltage Vdd, and the second power supply terminal of the comparator U1 is grounded. For example, the first input terminals of operational amplifier U2 and comparator U1 are, for example, non-inverting input terminals, and the second input terminals of operational amplifier U2 and comparator U1 are, for example, inverting input terminals. The voltage detection signal SCLC is high when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref; otherwise, it is low.
[0056] like Figure 3 As shown, the timing controller 100 powers on when the power-on voltage VOK becomes active (e.g., high level). The voltage VSCL of the IIC clock line SCL is the rising edge detection point A of the voltage detection signal SCLC when it first reaches the set voltage Vref, and the falling edge detection point B of the voltage detection signal SCLC when it decreases to the set voltage Vref. The set voltage Vref that meets the IIC protocol requirements is, for example, 1.98V-3.3V, with a set time t > 600ns. The time between the rising edge detection point A and the falling edge detection point B of the voltage detection signal SCLC must be greater than or equal to the set time t.
[0057] The control unit 110 firstly calls the IIC setting parameters in the register 140 in the timing controller power-on stage, and then provides the corresponding n groups of first control signals and second control signals to the control voltage switching unit 130 to provide the corresponding voltages to the IIC data line SDA and the IIC clock line SCL. The IIC setting parameters are the values stored in the register 140 after the previous power-on adjustment or the initial values preset. Then the control unit 110 receives the voltage detection signal, and for example, counts the time when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time by using an internal counter, and judges whether the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements according to the voltage detection signal after the set time.
[0058] Further, the control unit 110 provides the corresponding n groups of first control signals and second control signals to the voltage switching unit 130 to stepwise increase the voltages provided to the IIC data line SDA and the IIC clock line SCL until the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements in the case that the voltage VSCL of the IIC clock line SCL does not reach the set voltage Vref after the set time when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time. The control unit 110 stores the corresponding IIC parameters in the register 140 in the case that the voltage VSCL of the IIC clock line SCL still reaches the set voltage Vref after the set time when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time.
[0059] Figure 4 A circuit schematic diagram of a voltage switching unit in a timing controller according to an embodiment of the present application is shown.
[0060] As shown in Figure 4 The voltage switching unit 130 includes for example n first pull-up resistance loops and n second pull-up resistance loops, and n is an integer greater than 1.
[0061] Each first pull-up resistance loop includes a first pull-up resistance R1n, a first switch tube SCNn, and a second switch tube SCPn. The control end of the first switch tube SCNn is connected to the control unit 110 to receive the corresponding first control signal SCn. The first end of the first switch tube SCNn is grounded. The second end of the first switch tube SCNn is connected to the control end of the second switch tube SCPn. The second end of the second switch tube SCPn is connected to the power supply line VDD via the corresponding first pull-up resistance R1n. The first end of the second switch tube SCPn is connected to the IIC clock line SCL to provide the corresponding voltage VSCL. For example, a resistance is connected between the control end and the first end of the second switch tube SCPn.
[0062] Each second pull-up resistance circuit includes a second pull-up resistance R2n, a third switch tube SDNn, and a fourth switch tube SDPn. The control terminal of the third switch tube SDNn is connected to the control unit 110 to receive a corresponding second control signal SDn. The first terminal of the third switch tube SDNn is grounded. The second terminal of the third switch tube SDNn is connected to the control terminal of the fourth switch tube SDPn. The second terminal of the fourth switch tube SDPn is connected to the power supply line VDD via a corresponding second pull-up resistance R2i. The first terminal of the fourth switch tube SDPn is connected to the IIC data line SDA to provide a corresponding voltage VSDA. Exemplarily, a resistance is connected between the control terminal and the first terminal of the fourth switch tube SDPn.
[0063] In the formula, the first switch tube is one of an NMOS tube and a PMOS tube, and the second switch tube is the other of the NMOS tube and the PMOS tube. The third switch tube is one of an NMOS tube and a PMOS tube, and the fourth switch tube is the other of the NMOS tube and the PMOS tube. The control terminal of the switch tube is, for example, the gate of the MOS tube. The first terminal of the switch tube is, for example, the source of the MOS tube. The second terminal of the switch tube is, for example, the drain of the MOS tube. In other embodiments, the first terminal of the switch tube can also be the drain of the MOS tube, and the second terminal of the switch tube is the source of the MOS tube.
[0064] Further, the IIC setting parameter is the resistance value of the first pull-up resistance and the second pull-up resistance stored in the register 140 after being adjusted before the previous power-on or the initial value of the first pull-up resistance and the second pull-up resistance preset in advance. The step value is the resistance difference between two adjacent resistances. Preferably, the resistance difference between every two adjacent resistances is equal.
[0065] In other embodiments, the IIC setting parameter can also be two n-bit binary numbers. One n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal. The step value is, for example, 1.
[0066] Exemplarily, the resistance values of the first pull-up resistances R11, R12, …, R1n decrease in turn, and the resistance values of the second pull-up resistances R21, R22, …, R2n decrease in turn. Further, the difference between every two adjacent resistances of the first pull-up resistances R11, R12, …, R1n is, for example, equal, and the difference between every two adjacent resistances of the second pull-up resistances R21, R22, …, R1n is, for example, equal.
[0067] In the power-on stage of the timing controller 100, the IIC setting parameters stored in the register 140 are called, for example, the first pull-up resistor R11 and the second pull-up resistor R21. The corresponding control unit 110 generates a plurality of groups of first control signals and second control signals, only the first control signal SC1 and the second control signal SD1 are in the active state, and the rest of the groups of first control signals and second control signals are in the inactive state. Correspondingly, only the first pull-up resistor circuit where the first pull-up resistor R11 is located and the second pull-up circuit where the second pull-up resistor R21 is located are turned on to provide the corresponding voltages to the IIC clock line SCL and the IIC data line SDA. In the voltage detection stage of the timing controller 100, when it is detected that the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirement (the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time and still reaches the set voltage Vref after a delay of a set time), the control unit 110 continues to store the first pull-up resistor R11 and the second pull-up resistor R21 as the IIC setting parameters to the corresponding positions of the register 140. When it is detected that the voltage VSCL of the IIC clock line SCL does not meet the IIC protocol requirement (the voltage VSCL of the IIC clock line SCL does not reach the set voltage Vref after a delay of a set time when it reaches the set voltage Vref for the first time), the control unit 110 provides the corresponding n groups of first control signals and second control signals to the voltage switching unit 130 to stepwise increase the voltage provided to the IIC data line SDA and the IIC clock line SCL until the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirement. For example, in the first adjustment, only the first control signal SC2 and the second control signal SD2 are in the active state in the n groups of first control signals and second control signals provided, and the rest of the groups of first control signals and second control signals are in the inactive state. Correspondingly, only the first pull-up resistor circuit where the first pull-up resistor R12 is located and the second pull-up circuit where the second pull-up resistor R22 is located are turned on to provide the corresponding voltages to the IIC clock line SCL and the IIC data line SDA. If the first adjustment makes the voltage VSCL of the IIC clock line SCL meet the IIC protocol requirement, the control unit 110 stores the first pull-up resistor R12 and the second pull-up resistor R22 as the IIC setting parameters to the corresponding positions of the register 140. If the first adjustment does not make the voltage VSCL of the IIC clock line SCL meet the IIC protocol requirement, the next adjustment is continued until the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirement. Each time the adjustment is continued, for example, the next first pull-up resistor circuit and the next second pull-up resistor circuit are sequentially turned on.
[0068] Figure 5 A flowchart of a control method of a timing controller according to an embodiment of the present application is shown.
[0069] As Figure 5 illustrated, the control method of the timing controller of the display device provided by the present application comprises the following steps:
[0070] Step S310: obtaining voltage detection signals of the IIC clock line at different times.
[0071] Step S320: obtaining a first time when the voltage of the IIC clock line reaches a set voltage for the first time according to the voltage detection signals.
[0072] Step S330: judging whether the voltage of the IIC clock line reaches the set voltage after the first time is delayed for a set time according to the voltage detection signals.
[0073] In the case that the voltage of the IIC clock line reaches the set voltage after the first time is delayed for the set time, step S340 is performed: storing the corresponding IIC setting parameter.
[0074] In the case that the voltage of the IIC clock line does not reach the set voltage after the first time is delayed for the set time, step S350 is performed: adjusting the voltage provided to the IIC data line and the IIC clock line. Then, step S310 is continuously performed.
[0075] Further, step S350 comprises: generating n groups of first control signals and second control signals according to the IIC setting parameter and a step value, n being an integer greater than 1; and turning on the corresponding first pull-up resistor circuit to output the corresponding voltage to the IIC clock line and turning on the corresponding second pull-up resistor circuit to output the corresponding voltage to the IIC data line based on the n groups of first control signals and second control signals.
[0076] In other embodiments, before obtaining the voltage detection signals of the IIC clock line at different times, the control method further comprises: calling the stored IIC setting parameter to provide the corresponding voltage to the IIC data line and the IIC clock line.
[0077] Further, the IIC setting parameter comprises the resistance value of the first pull-up resistor in the turned-on first pull-up resistor circuit and the resistance value of the second pull-up resistor in the turned-on second pull-up resistor circuit, or the IIC setting parameter comprises two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal.
[0078] In other embodiments, the timing controller 100 may, for example, also perform the above-mentioned control method.
[0079] The display device, the timing controller and the control method thereof provided by the application, by acquiring the voltage detection signal of IIC clock line at different time, and when the voltage of IIC clock line reaches the set voltage for the first time, delaying for a set time, then recording the voltage provided to IIC data line and IIC clock line when the voltage of IIC clock line reaches the set voltage, adjusting the voltage provided to IIC data line and IIC clock line when the voltage of IIC clock line does not reach the set voltage, and continuing to acquire the voltage detection signal of IIC clock line at different time. So that the timing controller of the application can provide appropriate voltage to IIC clock line and IIC data line, which not only ensures that the voltage on IIC clock line and IIC data line meets the IIC protocol requirement when different timing controllers and different memories work together, thereby avoiding the situation that the display screen is abnormal caused by encoding reading error, but also can save power consumption.
[0080] While the application has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modifications and this application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended to cover and define the present application broadly with regard to the present description and to establish the scope of the application only as set forth in the following claims.
Claims
1. A timing controller, which acquires a code from a memory through an IIC clock line and an IIC data line, characterized in that, The application comprises: a detection unit for obtaining voltage detection signals of an IIC clock line at different times; a control unit for obtaining, according to the voltage detection signals, a first time when the voltage of the IIC clock line reaches a set voltage for the first time, and judging, according to the voltage detection signals, whether the voltage of the IIC clock line reaches the set voltage after the first time is delayed for a set time; a voltage switching unit for adjusting the voltage provided to the IIC data line and the IIC clock line in the case that the voltage of the IIC clock line does not reach the set voltage after the first time is delayed for the set time; and a register for storing the IIC set parameters corresponding to the case that the voltage of the IIC clock line reaches the set voltage after the first time is delayed for the set time, The control unit continues to receive the voltage detection signals after adjusting the voltage provided to the IIC data line and the IIC clock line. The control unit further calls the IIC set parameters in the register and provides corresponding voltages to the IIC data line and the IIC clock line through the voltage switching unit in the timing controller power-on stage.
2. The timing controller of claim 1, wherein, The control unit generates n groups of first control signals and second control signals according to the IIC set parameters or according to the IIC set parameters and step values, n being an integer greater than 1, 3. A timing controller as claimed in claim 1 or 2, c h a r a c t e r i z e d in that The voltage switching unit comprises n first pull-up resistance circuits and n second pull-up resistance circuits, Each first pull-up resistance circuit comprises a first pull-up resistance, a first switch tube and a second switch tube, the control end of the first switch tube receives a corresponding first control signal, the first end of the first switch tube is grounded, the second end of the first switch tube is connected with the control end of the second switch tube, the second end of the second switch tube is connected with the power supply line through the first pull-up resistance, and the first end of the second switch tube is connected with the IIC clock line to provide a corresponding voltage; Each second pull-up resistance circuit comprises a second pull-up resistance, a third switch tube and a fourth switch tube, the control end of the third switch tube receives a corresponding second control signal, the first end of the third switch tube is grounded, the second end of the third switch tube is connected with the control end of the fourth switch tube, the second end of the fourth switch tube is connected with the power supply line through the second pull-up resistance, and the first end of the fourth switch tube is connected with the IIC data line to provide a corresponding voltage. The IIC set parameters comprise the resistance values of the first pull-up resistances in the first pull-up resistance circuits turned on and the resistance values of the second pull-up resistances in the second pull-up resistance circuits turned on, 4. The timing controller of claim 3, wherein, Or the IIC set parameters comprise two n-bit binary numbers, one n-bit binary number is composed of the levels of each first control signal, and the other n-bit binary number is composed of the levels of each second control signal. The detection unit comprises:
5. The timing controller of claim 1, wherein, a voltage division network connected between the power supply line and the ground; an operational amplifier, the first input end of the operational amplifier is connected with the voltage division node of the voltage division network, the second input end of the operational amplifier is connected with the output end of itself, and the output end of the operational amplifier outputs the set voltage; and A comparator, a first input terminal of the comparator is connected to the IIC clock line to receive a voltage of the IIC clock line, a second input terminal of the comparator is connected to the output terminal of the operational amplifier to receive the set voltage, and an output terminal of the comparator outputs the voltage detection signal.
6. A control method of a timing controller, the timing controller acquiring a code from a memory through an IIC clock line and an IIC data line, characterized by, The method comprises: obtaining voltage detection signals of the IIC clock line at different times by a detection unit; obtaining a first time when the voltage of the IIC clock line reaches the set voltage for the first time according to the voltage detection signals by a control unit; judging whether the voltage of the IIC clock line reaches the set voltage after the first time is delayed for a set time according to the voltage detection signals by the control unit; storing the corresponding IIC set parameters in a register in the case that the voltage of the IIC clock line reaches the set voltage after the first time is delayed for the set time; and adjusting the voltage provided to the IIC data line and the IIC clock line in the case that the voltage of the IIC clock line does not reach the set voltage after the first time is delayed for the set time by a voltage switching unit, and the control unit continues to obtain the voltage detection signals. Before obtaining the voltage detection signals of the IIC clock line at different times, the method further comprises:
7. The control method of a timing controller according to claim 6, wherein calling the stored IIC set parameters to provide corresponding voltages to the IIC data line and the IIC clock line. The adjusting the voltage provided to the IIC data line and the IIC clock line comprises:
8. The control method of a timing controller according to claim 6 or 7, wherein generating n groups of first control signals and second control signals according to the IIC set parameters and a step value, n is an integer greater than 1; turning on corresponding first pull-up resistor circuits to output corresponding voltages to the IIC clock line and turning on corresponding second pull-up resistor circuits to output corresponding voltages to the IIC data line based on the n groups of first control signals and second control signals. The IIC set parameters comprise resistance values of first pull-up resistors in the turned-on first pull-up resistor circuits and resistance values of second pull-up resistors in the turned-on second pull-up resistor circuits, or the IIC set parameters comprise two n-bit binary numbers, one n-bit binary number is composed of the levels of each first control signal, and the other n-bit binary number is composed of the levels of each second control signal.
9. The control method of a timing controller according to claim 8, wherein The method comprises:
10. A display device, characterized by comprising: an IIC clock line and an IIC data line; a memory storing an encoding; and a timing controller according to any one of claims 1-5, which provides corresponding voltages to the IIC clock line and the IIC data line, and obtains the encoding from the memory through the IIC clock line and the IIC data line to configure the timing controller.
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