Method and apparatus for predicting yield rate of wafer in field and system for manufacturing wafer

Abstract

A method and apparatus for predicting yield of intra-field wafers and a system for manufacturing wafers are provided. A method for predicting yield of an intra-field wafer includes: generating at least one virtual process path with respect to remaining processes of the intra-field wafer; and predicting the yield of the virtual factory wafer corresponding to the at least one virtual process path by using the trained yield prediction model.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0151203 filed in the Korean Intellectual Property Office on November 3, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a method and apparatus for predicting the yield of wafers within a field and a system for manufacturing wafers. Background Art

[0003] In a wafer manufacturing process, yield-related factors (such as yield degradation factors and yield improvement factors of in-fab wafers) may be quantified based on the yield of a fab-out wafer. Previously, the yield of an in-fab wafer was predicted by adding or subtracting the quantified yield-related factors from existing yield information. The yield prediction of the in-fab wafer was performed in batch units, making it impossible to predict the yield of the wafer unit, and process data and measurement data of each wafer may not be considered in the yield prediction, so the accuracy of the yield prediction is low. Summary of the invention

[0004] The present disclosure has made an effort to provide a method for predicting the yield of in-field wafers based on process data and measurement data of outgoing wafers.

[0005] The present disclosure has made another effort to provide an apparatus for predicting the yield of in-field wafers based on process data and measurement data of outgoing wafers.

[0006] Embodiments of the present disclosure provide a wafer manufacturing system for optimizing future process paths of wafers within a field based on predicted yields of the wafers within the field.

[0007] According to an embodiment, a method for predicting the yield of in-field wafers is provided, the method comprising: generating at least one virtual process path for the remaining process of the in-field wafers; and predicting the yield of virtual outbound wafers corresponding to the at least one virtual process path by using a trained yield prediction model.

[0008] According to an embodiment, a device for predicting the yield of in-field wafers is provided. The device includes: a processor and a memory, wherein the processor executes a program stored in the memory to generate at least one virtual process path for the remaining process of the in-field wafers, and uses a trained yield prediction model to predict the yield of a virtual out-of-factory wafer corresponding to the at least one virtual process path.

[0009] According to an embodiment, a system for manufacturing wafers is provided. The system includes: a yield prediction device for collecting wafer data of shipped wafers from processing equipment and measurement equipment arranged in a process sequence, and predicting the yield of in-field wafers in the process based on the wafer data of shipped wafers; and a process scheduler for receiving virtual process paths and predicted yields of the virtual process paths for the remaining processes of the in-field wafers from the yield prediction device, and optimizing process scheduling for the remaining processes of the in-field wafers based on the virtual process paths and the predicted yields. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of an apparatus for predicting a yield of a wafer according to an embodiment is shown.

[0011] Figure 2 Wafer data of a wafer according to an embodiment is shown.

[0012] Figure 3 A flow chart of a method for predicting a yield of a wafer according to an embodiment is shown.

[0013] Figure 4 The structure of the yield prediction model according to the embodiment is shown.

[0014] Figure 5 A method for training a yield prediction model according to an embodiment is shown.

[0015] Figure 6 A flow chart of a method for generating a virtual process path according to an embodiment is shown.

[0016] Figure 7 A wafer process sequence according to an embodiment is shown.

[0017] Figure 8 A virtual process path of an ongoing process added to an in-field wafer is shown according to an embodiment.

[0018] Fig. 9 A method for generating a virtual process path according to another embodiment is shown.

[0019] Fig.10 The structure of a path generation model according to an embodiment is shown.

[0020] Fig.11 A method for training a path generation model according to an embodiment is shown.

[0021] Fig.12 A method for inferring a path generation model according to an embodiment is shown.

[0022] Fig.13 A wafer manufacturing system according to an embodiment is shown.

[0023] Fig.14 A block diagram of a yield prediction device according to another embodiment is shown. DETAILED DESCRIPTION

[0024] In the following detailed description, only specific embodiments of the present invention are shown and described simply by way of illustration. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and description are to be considered illustrative and not restrictive in nature. Throughout the specification, the same reference numerals represent the same elements.

[0025] Unless explicitly described to the contrary, the word “comprise” and variations such as “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0026] Unless the expressions "a", "an", "single", etc. are used, expressions recited in the singular may be construed as meaning in the singular or in the plural.

[0027] “And / or” includes all combinations of each and at least one of the mentioned constituent elements.

[0028] The terms including ordinal numbers (such as, first, second, etc.) will only be used to describe various components and should not be interpreted as limiting these components. These terms can only be used to distinguish one component from other components. For example, without departing from the claims according to the present invention, the first constituent element can be referred to as the second constituent element, and similarly, the second constituent element can be referred to as the first constituent element.

[0029] In the flowcharts described with reference to the drawings in this specification, the order of operations may be changed, various operations may be merged, specific operations may be divided, and specific operations may not be performed.

[0030] Figure 1 A block diagram showing an apparatus for predicting a yield of a wafer according to some embodiments, Figure 2 shows wafer data of a wafer according to some embodiments, and Figure 3 A flow chart illustrating a method for predicting the yield of a wafer according to some embodiments.

[0031] In some embodiments, the yield prediction device 100 can train a yield prediction model by using wafer data of shipped wafers ("shipped" wafers, i.e., wafers whose manufacturing process has been completed), and can predict the yield of in-field wafers ("in-field" wafers, i.e., wafers that are still undergoing the manufacturing process) by using the trained yield prediction model. The yield of a wafer can represent the ratio of normal chips among the chips designed on the wafer. For example, when it is estimated that one hundred chips are designed to be set on the wafer and ninety-five normal chips are included in the shipped wafers, the yield can be 95%.

[0032] Reference Figure 1 The yield prediction apparatus 100 may include a data preprocessor 110 , a model learner 120 , a path generator 130 , and a yield predictor 140 .

[0033] In some embodiments, the data pre-processor 110 may collect wafer data of shipped wafers, and may pre-process the collected wafer data.

[0034] The data preprocessor 110 may encode the wafer data of the shipped wafer into a digital string, and may transmit the encoded digital string to the model learner 120. The encoded digital string may be used in training a yield prediction model.

[0035] Optionally, the data preprocessor 110 may convert the wafer data of the shipped wafer into a natural language sentence, make the converted natural language sentence into a token, and generate an input embedding from the token of the natural language sentence. The data preprocessor 110 may perform position encoding on the token of the natural language sentence corresponding to the wafer data to generate position information. The input embedding and the position information of the wafer data may be used in a path generation model for training a virtual process path.

[0036] In some embodiments, a shipped wafer may represent a wafer whose yield is determined when a process is completed. An in-field wafer may indicate a wafer whose process is ongoing. For example, the yield of a shipped wafer may be determined in an electrical die sort (EDS) process. The yield information for a single shipped wafer may include an identifier and a yield of the corresponding shipped wafer.

[0037] In some embodiments, the model learner 120 may train a yield prediction model by using the preprocessed wafer data input from the data preprocessor 110. The trained yield prediction model may be used in predicting the yield of the wafer. For example, the model learner 120 may include a deep neural network (DNN) as an underlying structure of the yield prediction model.

[0038] The model learner 120 may train a path generation model for generating a virtual process path of a wafer in a field. The data preprocessor 110 may convert the wafer data into an input embedding, and may perform position encoding on a word unit of a natural language sentence corresponding to the wafer data to train the path generation model. The input embedding and the position information of the wafer data may be provided to the model learner 120. For example, the model learner 120 may further include a transformer network as a basic structure of the path generation model.

[0039] In some embodiments, the path generator 130 may generate a virtual process path for an in-field wafer whose process is not completed, and may generate wafer data (e.g., features) of the virtual process path based on a process simulation about the virtual process path. The path generator 130 may generate at least one virtual process path for an in-field wafer by using wafer data of a sampled out-of-factory wafer. In another way, the wafer (e.g., relative to previous training of a path generation model using wafer data or by directly using out-of-factory wafer data). For the predicted virtual path, as described above, the path generator 130 may generate at least one virtual process path for an in-field wafer by using a trained path generation model. In one embodiment, at least one virtual process path generated for an in-field wafer may correspond to a virtual out-of-factory wafer.

[0040] In some embodiments, the yield predictor 140 may predict the yield of the virtual shipped wafer by inputting the wafer data of the virtual shipped wafer into a trained yield prediction model.

[0041] When the path generator 130 generates y virtual process paths for each x in-site wafers, the yield predictor 140 may input wafer data of (x×y) virtual shipped wafers into the trained yield prediction model to simultaneously predict the yields of the virtual shipped wafers.

[0042] In some embodiments, when y yields are predicted for a wafer in a field, the problem of future process paths of the wafer in the field can be analyzed based on the distribution of the y yields. The predicted yield of the wafer in the field can be used to improve the process scheduling of the wafer in the field.

[0043] Reference Figure 2 , showing semiconductor manufacturing steps, model names of equipment used for each manufacturing step, equipment identifiers, and chamber identifiers in the equipment. Also shown is the critical dimension (CD) of a measurement process performed after a specific step is completed.

[0044] The semiconductor manufacturing process may include multiple process steps, including an oxidation step on a wafer, a photolithography step, an etching step, a deposition and ion implantation step, and a metal interconnection step. Depending on the type of semiconductor, the number of steps for manufacturing a wafer may range from hundreds to thousands. A wafer passing through each manufacturing step may be managed using a wafer identifier, and wafer data (classification data and measurement data of a process) may be generated when passing through each manufacturing step. Therefore, the number of features of the wafer data may range from thousands to tens of thousands.

[0045] The order of processes (such as oxidation, measurement, or photolithography) for each wafer may be the same, and each process may be performed by different processing equipment and / or measurement equipment. Figure 2 , process step 1 of wafer WF1 may be performed in chamber 1 of equipment of model 1 having identifier EQP21, and process step 1 of wafer WF2 may be performed in chamber 2 of equipment of model 2 having identifier EQP22. For example, wafer data of wafer WF1 may include category data of processes (such as model 1, EQP21, chamber 1 and model 12, EQP21, and chamber 1) and measurement data (such as 0.3 and 0.4).

[0046] The wafer data may include category data and measurement data for each step of a particular wafer. The category data for a step may include information in the equipment (equipment model name (EQP_MODEL), equipment identifier (EQP_ID) and chamber identifier (EQP_CHAMBER_ID) PPID, RETICLE, etc. of the processing equipment used in the corresponding step). The category data may also include, for example, the time when a particular wafer enters the processing equipment, the time when a particular wafer leaves the processing equipment, and information about abnormal things generated in the process. The measurement data may include measurement results about measurements performed on the wafer.

[0047] Reference Figure 3, the data preprocessor 110 of the yield prediction device 100 may collect wafer data of shipped wafers from processing equipment and measurement equipment (S110). The model learner 120 of the yield prediction device 100 may train a yield prediction model (S120) through supervised learning by using the wafer data of shipped wafers and the yield information of shipped wafers. The yield of shipped wafers may be used as ground truth data, and the trained yield prediction model may output a predicted yield for a given input of a process path (e.g., a process path of a virtual shipped wafer (i.e., a cascade of a partial process path of an in-field wafer and a virtual process path inferred from a partial process path of the in-field wafer)). In some embodiments, the data preprocessor 110 of the yield prediction device 100 may preprocess the collected wafer data, and may provide the preprocessed wafer data to the model learner 120. For example, the data preprocessor 110 may preprocess the wafer data by encoding the wafer data of the shipped wafer into numbers, feature vectors, etc.

[0048] Reference Figure 2 The model names of the processing equipment used in the oxidation step, the measurement step, and the photolithography step, the equipment identifiers of the processing equipment, and the chamber identifiers in the processing equipment may be encoded as digital strings by the data preprocessor 110. When the model names and identifiers of the equipment used in the same step are the same, the model names and identifiers of the corresponding equipment may be encoded as the same digital strings. However, even if the model names and identifiers of the equipment are the same, the equipment used for different processes is different, and thus the model names and identifiers of the equipment in different processes may be encoded as different digital strings. For example, referring to Figure 2 , the identifier of the processing equipment used in the oxidation process of WF1 and the identifier of the processing equipment used in the lithography process of WF1 are EQP21, but the processing equipment are used in different steps, so EQP21 of the oxidation process and EQP21 of the lithography process can be encoded as different digital strings.

[0049] In some embodiments, the model learner 120 of the yield prediction device 100 may train a yield prediction model through supervised learning using preprocessed wafer data and yield information of shipped wafers. The model learner 120 may input the preprocessed wafer data of a specific shipped wafer into the yield prediction model, and the yield prediction model may output a yield prediction value corresponding to the corresponding shipped wafer. The model learner 120 may compare the yield prediction value output from the yield prediction model with the yield information of the shipped wafer to calculate a loss or objective function, and may update the yield prediction model based on the calculation result of the loss function or the objective function.

[0050] In some embodiments, the yield prediction apparatus 100 may generate a virtual process path for an in-plant wafer, and may predict the yield of a virtual shipped wafer corresponding to the virtual process path by using a trained yield prediction model.

[0051] Reference Figure 3 , the path generator 130 of the yield prediction apparatus 100 may virtually generate at least one virtual process path for the remaining processes of the in-field wafer (S130). The path generator 130 may obtain wafer data of a virtual outgoing wafer corresponding to the virtual process path through process simulation on the virtual process path.

[0052] In some embodiments, the path generator 130 may generate at least one virtual process path based on wafer data of shipped wafers sampled from the shipped wafers. Alternatively, the path generator 130 may generate at least one virtual process path by using a path generation model trained based on wafer data of shipped wafers.

[0053] The yield predictor 140 of the yield prediction apparatus 100 may predict the yield of a virtual outgoing wafer corresponding to the virtual process path of the in-field wafer by using the trained yield prediction model (S140). To this end, the yield predictor 140 of the yield prediction apparatus 100 may input wafer data of the virtual outgoing wafer into the trained yield prediction model to predict the yield of the virtual outgoing wafer.

[0054] As described above, the yield prediction device can perform process simulation on various process paths of a wafer in a field by using a yield prediction model trained based on wafer data of a shipped wafer, and can obtain the predicted yield by the number of virtual process paths. The process path with high yield is expected to be optimized by the yield distribution of various predictions about the wafer in the field. In addition, the problem of the virtual process path predicted to have a low yield can be analyzed, and the process for manufacturing the wafer can be improved.

[0055] Figure 4 shows the structure of a yield prediction model according to some embodiments, and Figure 5 A method for training a yield prediction model according to some embodiments is shown.

[0056] Reference Figure 4 The yield prediction model may be operable on a deep neural network including an input layer 210 , a hidden layer 220 , and an output layer 230 .

[0057] In some embodiments, the wafer data of the shipped wafer may be encoded as a digital string and may be input to the input node (x 1 to x i). The category data or measurement data of one process may correspond to one input node, or the digital string of the category data or measurement data of one process may correspond to the same input node. The input layer 210 may have an appropriate structure for processing a large number of inputs.

[0058] Reference Figure 5 , the data preprocessor 110 of the yield prediction apparatus 100 may encode the wafer data of the shipped wafer so that the wafer data of the shipped wafer can be used as an input of the deep neural network 200 (S121). In one embodiment, the data preprocessor 110 may encode the category data of the wafer data of a specific shipped wafer into a digital string, and may send the encoded wafer data and the measurement data represented as a number together with the yield information of the corresponding shipped wafer to the model learner 120 (S122).

[0059] The chip data may be obtained by at least one hidden layer (220) of the hidden layer 220 of the deep neural network 200. 1 to 420 n ) processing, and a value corresponding to the yield (e.g., a yield prediction value) may be output from the output layer 230. The yield prediction value output by the output layer 230 and the actual yield of the corresponding shipped wafer may be compared with each other to update the yield prediction model to move the yield prediction value (e.g., the weight, bias, etc. of the yield prediction model) closer to the ground truth yield.

[0060] Reference Figure 5 , the model learner 120 may compare the yield prediction value output by the yield prediction model with the actual ground truth yield of the shipped wafer corresponding to the wafer data input to the yield prediction model to calculate the loss function of the yield prediction model (S123). The model learner 120 may update the yield prediction model based on the comparison result between the yield prediction value output from the yield prediction model and the actual yield (e.g., the result of calculating the loss function) (S124).

[0061] For example, when the wafer data of the shipped wafer having an actual yield (ground truth) of 98% is processed by at least one hidden layer 220 of the deep neural network 200, and the output layer 230 of the deep neural network 200 outputs a yield prediction value of 97%, the model learner 120 may calculate a predetermined loss function based on the difference between the actual yield of 98% of the corresponding shipped wafer and the yield prediction value of 97%. The model learner 120 may update the weight of the yield prediction model so that the yield prediction model may output a higher yield for the same wafer data based on the calculation result of the loss function.

[0062] Figure 6 A flowchart showing a method for generating a virtual process path according to some embodiments is shown. Figure 7shows a wafer process sequence according to some embodiments, and Figure 8 A virtual process path of an ongoing process added to an in-field wafer is shown in accordance with some embodiments.

[0063] In some embodiments, the yield prediction device 100 can generate a virtual process path for unperformed processes (remaining processes) of in-field wafers based on wafer data of shipped wafers, and can predict the yield of virtual shipped wafers by using wafer data of virtual shipped wafers corresponding to the virtual process path.

[0064] Reference Figure 6 , the path generator 130 of the yield prediction apparatus 100 may sample at least one of the shipped wafers ( S131 ).

[0065] In some embodiments, the path generator 130 may sample relatively recently manufactured shipped wafers to reflect information about newly added equipment or repaired equipment on the process. When the manufactured wafers are sampled after a predetermined time that is a relatively recent time, wafers that have passed processes performed by various types of equipment and / or improved processes may be sampled.

[0066] The path generator 130 may randomly sample at least one of the shipped wafers manufactured after a predetermined time. When the shipped wafers are randomly sampled, the diversity of the process paths of the shipped wafers may be increased. In another manner, the path generator 130 may sample at least one of the shipped wafers having a yield greater than a predetermined value. For example, the yield of the first 25% (Q3) of the shipped wafers from among the entire shipped wafers may be predetermined as the yield size for sampling the wafers.

[0067] Alternatively, the path generator 130 may sample outgoing wafers having a process path that is the same as / similar to the process path performed by the in-field wafers to which the virtual process path is assigned.

[0068] In some embodiments, when the process sequence of a wafer includes n process steps, a shipped wafer may be determined after performing n process steps on one wafer. Figure 7 , WF1, WF2, WF3, WF4, WF5, and WF6 are factory wafers. Each factory wafer may undergo the same process steps, but may have different model names, identifiers, and / or chamber identifiers of the equipment used to perform each process step on one wafer. That is, the process steps of each wafer may be performed by different equipment, so Figure 7 The arrows in FIG. 1 for indicating the process progress of WF1 to WF6 are shown to be different from each other. It is assumed that the path generator 130 samples WF4, WF5, and WF6 from among the shipped wafers.

[0069] Reference Figure 6 , the path generator 130 of the yield prediction apparatus 100 may generate at least one virtual process path for the remaining processes of the in-site wafers based on the sampled wafer data of the outgoing wafers ( S132 ).

[0070] Reference Figure 7 and Figure 8 , WF7 and WF8 are intra-field wafers, and the process status of each wafer is different from each other (the process of WF7 is faster than that of WF8). Figure 8 , the path generator 130 may generate a virtual process path for the remaining processes of the in-field wafers WF7 and WF8 based on the wafer data of the sampled outgoing wafers WF4, WF5, and WF6. 4 It can indicate the situation when the virtual process path based on the wafer data of the outgoing wafer WF4 is added to the remaining process of the in-field wafer WF7. 5 It may indicate a situation when a virtual process path based on the wafer data of the shipped wafer WF5 is added to the remaining processes of the in-site wafer WF8.

[0071] Fig. 9 A method for generating a virtual process path according to some embodiments is shown. Fig.10 shows the structure of a path generation model according to some embodiments, Fig.11 A method for training a path generation model according to some embodiments is shown, and Fig.12 A method for inferring a path generation model according to some embodiments is shown.

[0072] In some embodiments, the yield prediction apparatus 100 may train a path generation model of a virtual process path based on wafer data of shipped wafers, and may generate a virtual process path for remaining processes of in-plant wafers by using the trained path generation model.

[0073] Reference Fig. 9 , the data preprocessor 110 of the yield prediction device 100 may preprocess the wafer data of the shipped wafers to generate input embedding and position information used in training a path generation model for generating a virtual process path (S210). In one embodiment, the data preprocessor 110 may convert the wafer data of the shipped wafers into natural language sentences, and may make the natural language sentences into word units. Making the natural language sentences into word units may mean dividing the words or subwords in the natural language sentences into word units. For example, in Figure 2 In the case of WF1, the chip data can be converted into natural language sentences as follows.

[0074] Natural language sentence corresponding to the wafer data of WF1: "In the oxidation process of wafer ID WF1, model 1 is used as EQP_MODEL, EQP_ID is EQP21, EQP_CHAMBER_ID is chamber 1, the measurement value about CD1 is 0.3, and the measurement value about CD2 is 0.4. In the lithography process of wafer ID WF1, model 12 is used as EQP_MODEL, EQP_ID is EQP21, and EQP_CHAMBER_ID is chamber 1..." The data pre-processor 110 may generate input embeddings of wafer data based on natural language sentences formulated as word-grams.

[0075] The data preprocessor 110 may perform position encoding on the natural language sentence to generate position information about each word unit of the natural language sentence corresponding to the wafer data. The position information of the word unit in the sentence may be assigned to each word unit and the position information may indicate the position of the word unit to which the position information is assigned in the sentence. The input embedding and position information of the wafer data of the shipped wafer generated by the data preprocessor 110 may be sent to the model learner 120.

[0076] In some embodiments, the model learner 120 of the yield prediction apparatus 100 may train a path generation model of a virtual process path based on input embedding and position information of wafer data of shipped wafers ( S220 ).

[0077] In some embodiments, the path generation model of the virtual process path may be a transformer model, and the model learner 120 may train a decoder of the transformer model so that the path generation model may generate the virtual process path. For example, the transformer model used as the path generation model may be a generative pre-trained transformer (GPT).

[0078] Reference Fig.10 , the path generation model 300 may include m decoders 310. With respect to the m decoders 310, the output of the i-th decoder 310 may be used as the input of the (i+1)-th decoder 310. When the operation of the decoder 310 is repeated m times, the path generation model 300 may output a final text prediction result. In some embodiments, the m decoders 310 may perform m times of masked multi self-attention, layer normalization, and feed forward operations on the input embedding by using the position information of the word unit in the natural language sentence.

[0079] Reference Fig.10, when input embedding and position information of wafer data are input, each decoder 310 of the path generation model 300 may perform self-attention. In one embodiment, when performing masked multi-self-attention, the decoder 310 may mask the latter part of the input sentence, train attention among the text of the unmasked part, and predict the text immediately following the unmasked text. The sentence or text may be masked by setting the probability of the masked part to 0.

[0080] The decoder 310 may add the result of the (residual connection) masked multi-self-attention, the input embedding, and the position information of the sentence made into a word unit to perform layer normalization. Layer normalization may be performed to increase the training rate and increase the training stability.

[0081] The decoder 310 may perform feedforward based on the layer normalization result. The feedforward result may be connected to the feedforward input residual to be layer normalized. According to the above process, the path generation model 300 may be trained by using a natural language sentence corresponding to the wafer data of the shipped wafer. During this process, the path generation model 300 may learn the order of the process steps so that the virtual process path to be generated in the inference process may not differ from the order of the process steps.

[0082] In some embodiments, the model learner 120 may train the path generation model 300 by sequentially predicting the text of natural language sentences corresponding to the wafer data.

[0083] For example, in a particular stage of training, the path generation model 300 may predict the next text of the unmasked portion of the natural language sentence corresponding to the wafer data from WF1.

[0084] Reference Fig.11 , when the natural language sentence input to the decoder 310 is "In the oxidation process of the wafer ID WF1, model 1 is used as EQP_MODEL, and EQP_ID is", the model learner 120 may train the path generation model 300 so that the decoder 310 outputs 'EQP21'. That is, the path generation model 300 may be trained by predicting the next text of "EQP_ID" through the decoder 310, calculating the probability of the predicted text, and outputting the text with the highest probability.

[0085] Reference Fig.11 , the bars given on the right side of the outputs may indicate the probabilities of the respective outputs determined by the model learner 120. In the middle portion of the training, the path generation model 300 may generate 'EQP21' for the masking statement about the wafer data of WF1 with the highest probability.

[0086] The shipped wafers sampled to train the path generation model 300 may / may not be equal to the shipped wafers sampled to train the yield prediction model. For example, for a predetermined period of time (e.g., the last ten days), shipped wafers having a size greater than a predetermined yield (e.g., 99%) may be sampled to train the path generation model 300. A natural language sentence corresponding to the wafer data of the shipped wafers may be used as a correct answer to the intermediate prediction result of the training path generation model 300, and thus the shipped wafers may need to have a high yield as a relatively manufactured wafer.

[0087] The path generator 130 may use the trained path generation model 300 to generate at least one virtual process path for the remaining processes of the wafer in the field (S132'). Figure 7 When the next process step of WF7 is the measurement process of step 51, the path generator 130 may generate a model name, identifier, chamber identifier, etc. of equipment and / or measurement equipment to be used for steps 51 to n (that is, the final step) of WF7 as a virtual process path by using the trained path generation model 300. Figure 7 When the next process step of WF8 is the ion implantation process of step 36, the path generator 130 can generate a model name, identifier, chamber identifier, etc. of equipment and / or measurement equipment to be used for steps 36 to step n (final step) of WF8 as a virtual process path by using the trained path generation model 300.

[0088] Reference Fig.12 , the path generator 130 may input the position information of the word element of the input embedding and natural language sentence “0.7 and 0.8 are measured as the measurement result of step 50 …… of wafer ID WF7” to the trained path generation model 300, and may receive “Model 23 is used as EQP_MODEL in the lithography process of step, and EQP_ID is ……” from the path generation model 300. In one embodiment, the virtual process path from step 51 to step n (that is, the final step) may be output as a result of the inference by the path generation model 300.

[0089] In some embodiments, the path generator 130 may convert the virtual process path expressed in a natural language sentence into wafer data. The data preprocessor 100 of the yield prediction apparatus 100 may encode the wafer data of the virtual process path into a digital string to be input to the yield prediction model, or may encode the virtual process path into a digital string.

[0090] The yield predictor 140 of the yield prediction apparatus 100 may predict the yield of each virtual process path of the in-field wafer or the yield of the virtual out-of-factory wafer corresponding to the virtual process path. In one embodiment, when the encoded wafer data of the virtual process path is input to the trained yield prediction model, the trained yield prediction model may perform a neural network operation on the encoded wafer data of the input virtual process path to infer the yield of the virtual process path, or may predict the yield of the virtual out-of-factory wafer corresponding to the virtual process path.

[0091] In some embodiments, the yield predictor 140 can predict the yield of the virtual process paths simultaneously or in parallel by using the trained yield prediction model. For example, when the in-field wafers for which the yield is to be predicted are WF7 and WF8 and the path generator 130 generates three virtual process paths for each in-field wafer based on three shipped wafers WF4, WF5 and WF6, the yield predictor 140 can predict the yield of 6 (=2×3) virtual process paths in parallel.

[0092] Fig.13 A wafer fabrication system according to some embodiments is shown.

[0093] Reference Fig.13 The yield prediction device 100 may collect wafer data of shipped wafers from processing equipment, measurement equipment, etc. arranged in a process sequence, and may predict the yield of in-field wafers of an ongoing process based on the wafer data of shipped wafers. In one embodiment, the yield prediction device 100 may predict the yield of each virtual process path generated for the remaining processes of an in-field wafer, and may determine the predicted yield of each virtual shipped wafer corresponding to the virtual process path.

[0094] In some embodiments, the yield prediction apparatus 100 may send the virtual process paths and the predicted yields of the virtual process paths to the process scheduler 10 , or may recommend a virtual process path having the highest yield to the process scheduler 10 .

[0095] In some embodiments, the process scheduler 10 may optimize the process scheduling of the remaining processes of the corresponding in-field wafers based on the virtual process paths and the predicted yield or based on the recommended virtual process paths. Optionally, the process scheduler 10 may analyze the virtual process paths with relatively low predicted yields and may improve the wafer manufacturing process.

[0096] Fig.14 A block diagram of a yield prediction device according to another embodiment is shown.

[0097] The yield prediction apparatus according to another embodiment may be implemented by using a computer system (eg, a computer-readable medium).

[0098] For example, a non-transitory computer-readable medium may be used to store information that causes one or more processors to perform a process for determining a yield associated with an in-field wafer, the in-field wafer being manufactured using a manufacturing step of a manufacturing process. In one embodiment, the performed process may include receiving information of first manufacturing data of the in-field wafer, the first manufacturing data including information about a first step of the manufacturing process that has been completed for the in-field wafer, wherein a second step of the manufacturing process has not yet been completed for the in-field wafer; determining second manufacturing data of the in-field wafer, the second manufacturing data including information about the second step of the manufacturing process that has not yet been completed for the in-field wafer; and predicting a yield of the in-field wafer based on the first manufacturing data and the second manufacturing data.

[0099] In some embodiments, the second manufacturing data is generated by a first neural network trained using wafer data of a shipped wafer, the wafer data including information about completion of a first step and a second step of a manufacturing process for producing the shipped wafer. In some embodiments, the information about completion of the second step of the manufacturing process is included in the wafer data of the shipped wafer, the wafer data including information about completion of the first step and the second step of the manufacturing process for producing the shipped wafer.

[0100] In another embodiment, a first neural network may be trained using wafer data of shipped wafers, the wafer data including second manufacturing data and third manufacturing data, the third manufacturing data including information on completion of a first manufacturing step for manufacturing the shipped wafers; the second manufacturing data is predicted by the trained first neural network; a second neural network is trained using the wafer data using the yield of the shipped wafers; and the yield of in-field wafers is predicted through inference of the second neural network based on the first manufacturing data.

[0101] Reference Fig.14 , the computer system 1400 includes one or more processors 1410 and a memory 1420. The memory 1420 may be connected to the one or more processors 1410, and may store instructions or programs configured to cause the one or more processors 1410 to perform a process including the above-described method.

[0102] The one or more processors 1410 may implement the functions, stages or methods proposed in the embodiments. The operation of the computer system 1400 according to the embodiments may be implemented by the one or more processors 1410. The one or more processors 1410 may include a GPU and a CPU.

[0103] The memory 1420 may be provided inside / outside the processor and may be connected to the processor by various methods known to those skilled in the art. The memory represents various forms of volatile storage media or nonvolatile storage media, and for example, the memory may include a read-only memory (ROM) and a random access memory (RAM). In another manner, the memory may be a PIM (Processing in Memory) including a logic unit for performing self-operation.

[0104] In another embodiment, some functions of the yield prediction device (e.g., training the yield prediction model and / or the path generation model, inference of the yield prediction model and / or the path generation model) can be provided by a neuromorphic chip including neurons, synapses, and interneuron connection modules. A neuromorphic chip is a computer device that simulates the structure of a biological nervous system and can perform neural network operations.

[0105] It is implemented not only by the devices and / or methods described so far, but also by a program that implements the functions corresponding to the configuration of the embodiment or a recording medium on which the program is recorded, and such an implementation can be easily implemented by any technician in the field to which the present description belongs from the description provided above. Specifically, the method (for example, image preprocessing method, etc.) according to the embodiment of the present disclosure is implemented in the form of program instructions that can be executed by various computer methods, and the computer-readable program instructions can be recorded on the medium. The computer-readable medium may include program instructions, data files, data structures, etc., alone or in combination. The program instructions recorded on the computer-readable medium may be specifically designed and configured for the embodiment, or may be known and available to technicians in the field of computer software. The computer-readable recording medium may include a hardware device configured to store and execute program instructions. For example, the computer-readable recording medium includes magnetic media (such as hard disks, floppy disks, and tapes), optical recording media (such as CD-ROMs and DVDs), and optical disks (such as floppy disks). The computer-readable recording medium may be a magneto-optical medium, ROM, RAM, flash memory, etc. The program instructions may include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer through an interpreter, etc.

[0106] Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements in the art by ordinary technicians using the basic concept of the present disclosure defined in the appended claims also belong to the scope of the present disclosure.

Claims

1. A method for predicting the yield of wafers in a field, the method comprising: generating at least one virtual process path regarding a remaining process of the wafer in the field, wherein the remaining process is an unfinished portion of a process for manufacturing the wafer in the field; and The yield of the wafers in the field is predicted by using a yield prediction model, wherein the yield prediction model predicts the yield based on the virtual process path.

2. The method according to claim 1, wherein: The yield prediction model is trained according to supervised learning by using wafer data of shipped wafers as training data and using yield information of shipped wafers as ground truth data.

3. The method according to claim 2, wherein: The steps to train the yield prediction model include: The wafer data encoded as numbers is input into a yield prediction model.

4. The method according to claim 3, wherein: The steps to train the yield prediction model include: The yield prediction model is updated based on a result of comparing the yield information with a yield prediction value output by the yield prediction model.

5. The method according to claim 1, wherein: The step of generating the at least one virtual process path for the remaining process of the wafer in the field comprises: sampling at least one of the shipped wafers; and The at least one virtual process path is generated based on sampled wafer data of the at least one shipped wafer.

6. The method according to claim 5, wherein: The step of sampling the at least one shipped wafer among the shipped wafers comprises: After a predetermined time, the at least one shipped wafer from among the shipped wafers from the factory is sampled, or the at least one shipped wafer from among the shipped wafers having a yield higher than a predetermined value is sampled.

7. The method according to claim 1, wherein: The step of generating the at least one virtual process path for the remaining process of the wafer in the field comprises: The at least one virtual process path is generated by using a path generation model.

8. The method according to claim 7, wherein: The path generation model is trained to generate the at least one virtual process path by using wafer data of shipped wafers, the shipped wafers including wafers that have completed manufacturing.

9. The method according to claim 8, wherein: The steps to train a path generation model include: The path generation model is input with embedding generated by converting wafer data of shipped wafers into natural language sentences and position information generated by performing position encoding on the natural language sentences.

10. The method according to claim 9, wherein: The steps of training the path generation model also include: Self-attention, layer normalization, and feed-forward operations are performed multiple times on the input embedding using the position information.

11. The method according to claim 1, wherein: The step of predicting the yield of the virtual outgoing wafer corresponding to the at least one virtual process path by using the trained yield prediction model comprises: The yields of a plurality of virtual wafers respectively corresponding to the at least one virtual process path are predicted at the same time.

12. The method according to claim 1, wherein: The step of predicting the yield of the virtual outgoing wafer corresponding to the at least one virtual process path by using the trained yield prediction model comprises: encoding wafer data of the at least one virtual process path; and The encoded wafer data of the at least one virtual process path is input into a trained yield prediction model.

13. A device for predicting the yield of wafers in a field, the device comprising: one or more processors and memory, The memory stores instructions configured to cause the one or more processors to perform a process, the process comprising: generating at least one virtual process path for a remaining process of the wafer in the field, wherein the remaining path is an unfinished portion of a process for manufacturing the wafer in the field; and The yield of the wafers in the field is predicted by using a yield prediction model, wherein the yield prediction model predicts the yield based on the virtual process path.

14. The device according to claim 13, wherein: The at least one virtual process path is generated by a path generation model, and the path generation model is trained to generate the at least one virtual process path by using wafer data of shipped wafers.

15. The device according to claim 13, wherein: The steps of predicting the yield of a virtual outgoing wafer by using the trained yield prediction model include: encoding wafer data of the at least one virtual process path; and The encoded wafer data of the at least one virtual process path is input into a trained yield prediction model.

16. The device according to claim 13, wherein: The yield prediction model is trained according to supervised learning by using wafer data of shipped wafers and yield information of shipped wafers.

17. A non-transitory computer readable medium storing information configured to cause one or more processors to perform a process for determining a yield associated with a wafer within a field, the wafer within the field being manufactured using a manufacturing step of a manufacturing process, the process comprising: receiving first manufacturing data for an in-field wafer, the first manufacturing data comprising information about a first step of a manufacturing process that has been completed for the in-field wafer, wherein a second step of the manufacturing process has not yet been completed for the in-field wafer; determining second manufacturing data for the in-field wafer, the second manufacturing data comprising information about a second step of the manufacturing process that has not yet been completed for the in-field wafer; and The yield of wafers within the field is predicted based on the first manufacturing data and the second manufacturing data.

18. The non-transitory computer readable medium of claim 17, wherein: The second manufacturing data is generated by a first neural network trained using wafer data of shipped wafers, the wafer data including information on completion of a first step and a second step of a manufacturing process for producing the shipped wafers.

19. The non-transitory computer readable medium of claim 18, wherein: Information on the completion of the second step of the manufacturing process is included in wafer data of the shipped wafer, the wafer data including information on the completion of the first step and the second step of the manufacturing process used to produce the shipped wafer.

20. The non-transitory computer readable medium of claim 18, the processing further comprising: training a first neural network using wafer data of a shipped wafer, the wafer data comprising second manufacturing data and third manufacturing data, the third manufacturing data comprising information about completion of a first manufacturing step used to manufacture the shipped wafer; predicting second manufacturing data by using the trained first neural network; Using the wafer data to train a second neural network using the wafer yield; and The yield of the wafers within the field is predicted based on the first manufacturing data through inference of the second neural network.

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