Optical computing chip data communication method based on USB interface

Abstract

The invention discloses an optical computing chip data communication method based on a USB interface. The optical computing chip data communication method comprises the following steps that S1, a USB signal is converted into a TTL signal through a USB-to-TTL module; s2, the TTL signal is transmitted to an ESP32 microcontroller, and a standardized data packet is analyzed and generated; s3, distributing data packets in a multi-channel dynamic parallel transmission architecture of the ESP32; s4, processing the data through an optical computing chip, outputting an optical signal, and transmitting the optical signal to a PD array; s5, performing photoelectric conversion and amplification on the optical signal by using a PD array; s6, transmitting the amplified electric signal to target equipment; and S7, detecting and correcting error code data by using an enhanced data error correction mechanism. According to the invention, efficient integration of the optical computing chip and the USB interface is realized, and a stable and low-cost data transmission scheme is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of optical communication and high-speed data transmission, and in particular to a data communication method for an optical computing chip based on a USB interface. Background Art

[0002] As one of the core technologies in the field of modern communications, optical communication technology has the characteristics of high speed, large capacity, and low loss, and has been widely used in data centers, long-distance communications, and consumer electronics. However, traditional optical communication systems often use dedicated interfaces and high-performance control chips to achieve data transmission and processing, which makes optical communication equipment face many limitations in terms of cost, compatibility, and scalability. Especially in consumer electronics and the Internet of Things, users are increasingly in need of low-cost, highly compatible data transmission solutions, and traditional solutions are difficult to meet this requirement.

[0003] Current optical communication equipment mainly uses optical fiber as the transmission medium, and realizes high-speed transmission and processing of signals through high-performance optical computing chips and controllers. However, in the prior art, optical communication equipment usually relies on high-end control chips and proprietary communication protocols, and is difficult to be directly compatible with mainstream universal interfaces (such as USB interfaces). This design not only increases the hardware complexity of the equipment, but also increases the development and maintenance costs of the system. In addition, the diversity and non-uniformity of interface standards in the prior art cause optical communication equipment to face adaptability problems in cross-platform applications. For example, the connection between the device and consumer electronic products requires an additional interface conversion module, which increases the system delay and the complexity of data transmission.

[0004] In traditional optical communication solutions, signal processing and data transmission efficiency are still insufficient. On the one hand, optical signals are affected by noise, attenuation and distortion during transmission, and existing technologies mainly rely on fixed compensation and modulation mechanisms to handle signal deviations. However, this static mechanism is difficult to adapt to complex changes in the transmission environment in real time, resulting in a decrease in signal quality, especially in long-distance transmission and high-load conditions. On the other hand, existing data transmission architectures usually adopt single-channel or fixed-channel configurations, which cannot dynamically adjust channel loads and balance bandwidth usage. This leads to system bottlenecks in high data traffic scenarios, affecting overall transmission efficiency.

[0005] Regarding the reliability of data transmission, the error detection and correction capabilities of existing technologies are relatively limited. Although some technologies have introduced basic error checking mechanisms (such as CRC checking), these methods are often difficult to meet actual needs in high bit error rate environments. In response to complex interference environments, existing solutions mostly use simple retransmission mechanisms and lack effective support for intelligent error correction algorithms, resulting in insufficient reliability and integrity of data transmission. In addition, in terms of spectrum management, traditional solutions usually use fixed spectrum configurations and lack the ability to dynamically manage spectrum resources. This makes it difficult for the channel to maintain stable data transmission under high interference and high load conditions, further limiting the performance of the system.

[0006] In terms of interface design, most existing optical communication devices rely on proprietary interfaces to communicate with the host computer. This design not only limits the versatility of the device, but also increases the difficulty of interface adaptation. Although some optical communication devices that support USB interfaces have appeared on the market, these devices often achieve the connection between the USB interface and the optical computing chip by adding additional adapter modules or dedicated drivers, which increases the hardware cost and implementation complexity of the device. For some low-cost consumer electronics and IoT devices, this design is difficult to meet market demand, further limiting the application of optical communication technology in these fields.

[0007] Therefore, how to provide a data communication method for an optical computing chip based on a USB interface is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0008] One object of the present invention is to propose a data communication method for an optical computing chip based on a USB interface. The present invention makes full use of optical communication technology, embedded systems and dynamic optimization algorithms, and describes in detail the integration method of the optical computing chip with an ESP32-S3 microcontroller and a USB interface, as well as signal compensation, modulation and demodulation, spectrum management and error correction mechanisms in data transmission. The method has the advantages of high transmission rate, strong system compatibility, high reliability and low implementation cost.

[0009] According to an embodiment of the present invention, a method for optical computing chip data communication based on a USB interface comprises the following steps:

[0010] S1, convert the USB signal sent by the host computer into a TTL signal through the USB to TTL module, and use the FIFO buffer to temporarily store the TTL signal;

[0011] S2, transmit the temporarily stored TTL signal to the ESP32 microcontroller, use its communication protocol processing module to perform preliminary analysis and verification on the signal, and generate the standardized data packet required by the multi-channel parallel transmission architecture;

[0012] S3. In the multi-channel dynamic parallel transmission architecture of the ESP32 microcontroller, standardized data packets are distributed to multiple channels according to the dynamic load balancing mechanism to optimize the efficiency and stability of data transmission;

[0013] S4, delivering the allocated multi-channel data packets to the optical computing chip, processing the data through the optical computing chip and outputting optical signals, which are transmitted to the PD array;

[0014] S5, using the PD array to perform photoelectric conversion on the optical signal, generate a corresponding electrical signal, and amplify the electrical signal;

[0015] S6, transmitting the amplified electrical signal to the target device to complete data reception and processing;

[0016] S7. During the data transmission process, an enhanced data error correction mechanism is used to detect and correct the erroneous data in transmission, combined with the soft decoding and automatic retransmission technology of LDPC codes.

[0017] Optionally, the S3 specifically includes:

[0018] S31, initialize the multi-channel dynamic parallel transmission architecture of the ESP32 microcontroller, and detect the status information of all currently available channels, including the bandwidth and current load of each channel;

[0019] S32, defining and obtaining a sequence of data packets to be transmitted, including the size, priority and target channel requirements of each data packet;

[0020] S33. Calculate the comprehensive balance factor of each channel based on the current status information of the channel, evaluate the load of each channel, and sort the available channels from low to high according to the load:

[0021]

[0022] Among them, θ and ρ are weight factors, F j is the comprehensive balance factor, L j Indicates the amount of data allocated to the channel, B j Indicates the maximum data processing capability of the channel, D j Indicates the time delay caused by data transmission on this channel;

[0023] S34, sorting the data packet sequence according to the priority of the data packet, and processing the data packet with a high priority first;

[0024] S35, starting with the high priority data packets, select the available channels with the lowest loads for allocation, and update the channel status information to reflect the new load;

[0025] S36, generating a corresponding data transmission queue for each channel, and arranging the data packets in the queue in order of priority;

[0026] S37, start the multi-channel transmission module, transmit data in the order of each channel queue, monitor the channel status in real time, and dynamically adjust the data packet allocation strategy according to the load changes that occur during the transmission process.

[0027] Optionally, the S4 specifically includes:

[0028] S41, receiving a multi-channel standardized data packet allocated by the ESP32 microcontroller, and transmitting the data packet to the input end of the optical computing chip through the interface;

[0029] S42, parsing the received data packet inside the optical computing chip, where the parsed content includes the target format, wavelength, and modulation mode of the signal;

[0030] S43, converting the digital signal into an optical signal according to the analysis result, generating an optical signal having preset frequency, wavelength and phase characteristics;

[0031] S44, transmitting the generated optical signal to the input end of the PD array through the output interface of the optical computing chip;

[0032] S45. Receive an optical signal in the PD array.

[0033] Optionally, the S5 specifically includes:

[0034] S51, using photodiodes in the PD array to perform photoelectric conversion on the optical signal, absorbing photon energy through semiconductor materials to release electrons, thereby generating a current signal;

[0035] S52, performing current stabilization processing on the generated current signal, and adjusting the current fluctuation through the internal circuit;

[0036] S53, inputting the stabilized current signal into a current amplification module, and using the amplifier to increase the signal strength;

[0037] S54, converting the amplified current signal into a standardized voltage signal, and eliminating the nonlinear distortion generated in the conversion process by stabilizing the voltage signal;

[0038] S55: Output the final processed electrical signal and transmit it to the target device interface.

[0039] Optionally, the S6 specifically includes:

[0040] S61, receiving the amplified electrical signal and transmitting it to the interface adapter module;

[0041] S62, analyzing the electrical signal to extract the level amplitude, frequency range and data format;

[0042] S63, transmitting the electrical signal to the data verification module and confirming the integrity of the signal;

[0043] S64, transmitting the verified electrical signal to the communication interface of the target device through the protocol conversion module;

[0044] S65, the target device receives the electrical signal and performs analysis and processing;

[0045] S66: The target device completes the application or output of the data.

[0046] Optionally, the S7 specifically includes:

[0047] S71, receiving a digital signal sequence output from a signal demodulation module, performing error detection on the signal sequence, and identifying and marking erroneous bits;

[0048] S72, converting the received signal sequence into a log-likelihood ratio representation for soft decoding processing:

[0049]

[0050] Among them, LLR(b i ) represents the log-likelihood ratio of the i-th bit, P(b i =1|r) represents the conditional probability that the signal is logic "1", P(b i =0|r) represents the conditional probability that the signal is logic "0", and ln is the logarithmic function;

[0051] S73, according to the verification rule of the LDPC code, locate the bit error position in the signal sequence and mark the bit that fails the verification;

[0052] S74, using the error correction capability of the LDPC code to correct the marked error bits, and updating the error bits in the signal sequence:

[0053]

[0054] Among them, W i is the current bit b i The correction weight is, λ is the channel state factor, is the history correction weight, i represents the index of the bit in the signal sequence;

[0055] S75. If the verification still fails, the automatic retransmission mechanism is triggered, and a data retransmission request is sent to the sender to obtain a new data packet;

[0056] S76, integrating the re-received data packet with the error-corrected signal sequence to generate a complete signal sequence, and outputting the complete signal sequence to the target device.

[0057] The beneficial effects of the present invention are:

[0058] The present invention solves the problems of poor compatibility between optical communication and universal interface, limited signal processing capability and insufficient data transmission stability in the prior art by proposing a data communication method for an optical computing chip based on a USB interface. The present invention adopts a deep integration design of an optical computing chip and an ESP32-S3 microcontroller, and by seamlessly connecting optical communication with the USB interface, the hardware cost of the device is greatly reduced, the system architecture is simplified, and the compatibility and scalability of the system are improved. As an intermediate controller, ESP32-S3 is not only responsible for data analysis, signal compensation and load balancing, but also realizes efficient data distribution in a multi-channel parallel transmission architecture, significantly improving the transmission efficiency of the system.

[0059] By introducing an adaptive compensation module for optical wave signals, the present invention can detect and correct the phase, amplitude and frequency deviation of optical signals in real time under dynamic environments, effectively solving the limitation that traditional fixed compensation mechanisms cannot cope with complex channel problems. In addition, the present invention adopts an intelligent dynamic spectrum management algorithm to dynamically adjust the frequency and bandwidth allocation according to the real-time status of the channel, ensuring the stability of data transmission, especially in high-load and high-interference scenarios, the spectrum utilization of the system has been significantly improved.

[0060] In terms of data transmission reliability, the present invention combines the soft decoding and automatic retransmission technology of LDPC codes to significantly improve the ability of error detection and correction, and can ensure the integrity and reliability of data even in high noise and high error rate environments. By performing QPSK modulation on the optical signal through the USB interface signal modulation module, the system not only realizes efficient optical signal processing, but also optimizes the transmission efficiency between optical communication and USB interface, thereby meeting the needs of high-speed data transmission in multiple fields such as consumer electronics, Internet of Things and industrial control.

[0061] In summary, the present invention has successfully realized a low-cost, highly compatible and high-efficiency data communication solution through comprehensive innovations in hardware architecture, data transmission mechanism and signal processing technology. It not only overcomes many limitations in the existing technology, but also expands the possibilities of optical communication technology in consumer electronics and industrial applications, and provides a new direction for the design of the next generation of high-speed data transmission equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0063] Figure 1 This is a flow chart of a data communication method for an optical computing chip based on a USB interface proposed by the present invention;

[0064] Figure 2 The present invention provides a schematic diagram of the modulation process of a USB interface signal modulation module in a method for optical computing chip data communication based on a USB interface. DETAILED DESCRIPTION

[0065] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0066] refer to Figure 1-2 , a data communication method for an optical computing chip based on a USB interface, comprising the following steps:

[0067] S1, convert the USB signal sent by the host computer into a TTL signal through the USB to TTL module, and use the FIFO buffer to temporarily store the TTL signal;

[0068] S2, transmit the temporarily stored TTL signal to the ESP32 microcontroller, use its communication protocol processing module to perform preliminary analysis and verification on the signal, and generate the standardized data packet required by the multi-channel parallel transmission architecture;

[0069] S3. In the multi-channel dynamic parallel transmission architecture of the ESP32 microcontroller, standardized data packets are distributed to multiple channels according to the dynamic load balancing mechanism to optimize the efficiency and stability of data transmission;

[0070] S4, delivering the allocated multi-channel data packets to the optical computing chip, processing the data through the optical computing chip and outputting optical signals, which are transmitted to the PD array;

[0071] S5, using the PD array to perform photoelectric conversion on the optical signal, generate a corresponding electrical signal, and amplify the electrical signal;

[0072] S6, transmitting the amplified electrical signal to the target device to complete data reception and processing;

[0073] S7. During the data transmission process, an enhanced data error correction mechanism is used to detect and correct the erroneous data in transmission, combined with the soft decoding and automatic retransmission technology of LDPC codes.

[0074] In this implementation, S3 specifically includes:

[0075] S31, initialize the multi-channel dynamic parallel transmission architecture of the ESP32 microcontroller, and detect the status information of all currently available channels, including the bandwidth and current load of each channel;

[0076] S32, defining and obtaining a sequence of data packets to be transmitted, including the size, priority and target channel requirements of each data packet;

[0077] S33. Calculate the comprehensive balance factor of each channel based on the current status information of the channel, evaluate the load of each channel, and sort the available channels from low to high according to the load:

[0078]

[0079] Among them, θ and ρ are weight factors, F j is the comprehensive balance factor, L j Indicates the amount of data allocated to the channel, B j Indicates the maximum data processing capability of the channel, D j Indicates the time delay caused by data transmission on this channel;

[0080] S34, sorting the data packet sequence according to the priority of the data packet, and processing the data packet with a high priority first;

[0081] S35, starting with the high priority data packets, select the available channels with the lowest loads for allocation, and update the channel status information to reflect the new load;

[0082] S36, generating a corresponding data transmission queue for each channel, and arranging the data packets in the queue in order of priority;

[0083] S37, start the multi-channel transmission module, transmit data in the order of each channel queue, monitor the channel status in real time, and dynamically adjust the data packet allocation strategy according to the load changes that occur during the transmission process.

[0084] In this implementation, S4 specifically includes:

[0085] S41, receiving a multi-channel standardized data packet allocated by the ESP32 microcontroller, and transmitting the data packet to the input end of the optical computing chip through the interface;

[0086] S42, parsing the received data packet inside the optical computing chip, where the parsed content includes the target format, wavelength, and modulation mode of the signal;

[0087] S43, converting the digital signal into an optical signal according to the analysis result, generating an optical signal having preset frequency, wavelength and phase characteristics;

[0088] S44, transmitting the generated optical signal to the input end of the PD array through the output interface of the optical computing chip;

[0089] S45. Receive an optical signal in the PD array.

[0090] In this implementation manner, S5 specifically includes:

[0091] S51, using photodiodes in the PD array to perform photoelectric conversion on the optical signal, absorbing photon energy through semiconductor materials to release electrons, thereby generating a current signal;

[0092] S52, performing current stabilization processing on the generated current signal, and adjusting the current fluctuation through the internal circuit;

[0093] S53, inputting the stabilized current signal into a current amplification module, and using the amplifier to increase the signal strength;

[0094] S54, converting the amplified current signal into a standardized voltage signal, and eliminating the nonlinear distortion generated in the conversion process by stabilizing the voltage signal;

[0095] S55: Output the final processed electrical signal and transmit it to the target device interface.

[0096] In this implementation manner, S6 specifically includes:

[0097] S61, receiving the amplified electrical signal and transmitting it to the interface adapter module;

[0098] S62, analyzing the electrical signal to extract the level amplitude, frequency range and data format;

[0099] S63, transmitting the electrical signal to the data verification module and confirming the integrity of the signal;

[0100] S64, transmitting the verified electrical signal to the communication interface of the target device through the protocol conversion module;

[0101] S65, the target device receives the electrical signal and performs analysis and processing;

[0102] S66: The target device completes the application or output of the data.

[0103] In this implementation manner, the S7 specifically includes:

[0104] S71, receiving a digital signal sequence output from a signal demodulation module, performing error detection on the signal sequence, and identifying and marking erroneous bits;

[0105] S72, converting the received signal sequence into a log-likelihood ratio representation for soft decoding processing:

[0106]

[0107] Among them, LLR(b i ) represents the log-likelihood ratio of the i-th bit, P(b i =1|r) represents the conditional probability that the signal is logic "1", P(b i =0|r) represents the conditional probability that the signal is logic "0", and ln is the logarithmic function;

[0108] S73, according to the verification rule of the LDPC code, locate the bit error position in the signal sequence and mark the bit that fails the verification;

[0109] S74, using the error correction capability of the LDPC code to correct the marked error bits, and updating the error bits in the signal sequence:

[0110]

[0111] Among them, W i is the current bit b i The correction weight is λ, λ is the channel state factor, is the history correction weight, i represents the index of the bit in the signal sequence;

[0112] S75. If the verification still fails, the automatic retransmission mechanism is triggered, and a data retransmission request is sent to the sender to obtain a new data packet;

[0113] S76, integrating the re-received data packet with the error-corrected signal sequence to generate a complete signal sequence, and outputting the complete signal sequence to the target device.

[0114] Embodiment 1:

[0115] In order to verify the feasibility of the present invention in implementation, the present invention is applied to smart home devices. In modern smart home devices, the demand for communication between devices is increasing, especially in scenarios where high-definition video, large amounts of sensor data, and real-time audio streams need to be quickly transmitted. Traditional communication solutions usually use Wi-Fi, Bluetooth, or wired Ethernet, but these methods either have rate bottlenecks or require complex wiring. To this end, we propose a data communication method for an optical computing chip based on a USB interface, which is applied to data transmission between a home smart gateway and a multimedia terminal to solve the problems of insufficient transmission rate, poor stability, and poor compatibility in the prior art.

[0116] In the actual scenario, we connected the smart gateway to the home multimedia terminal through the USB interface, used the ESP32-S3 microcontroller as the core unit for data processing, and transmitted the high-speed data from the Internet in the gateway to the multimedia terminal through the optical computing chip. The system adopts a multi-channel dynamic parallel transmission architecture, an adaptive compensation module for light wave signals, an intelligent dynamic spectrum management algorithm, and an enhanced data error correction mechanism to achieve high-speed and stable transmission of large-scale data. The test scenario was selected in a typical three-bedroom and two-living room home environment, with a distance between devices ranging from 5 to 15 meters, including a variety of home appliances, such as HDTVs, smart speakers, and smart air conditioners.

[0117] In this scenario, the smart gateway is connected to the ESP32-S3 microcontroller via a USB interface, and the ESP32-S3 is responsible for receiving and parsing high-definition video streaming data from the Internet. The data is divided into multiple standardized data packets and distributed to multiple transmission channels through a dynamic load balancing mechanism. The light wave signal adaptive compensation module detects the phase, amplitude and frequency of the optical signal in real time and dynamically corrects the signal deviation. The compensated signal enters the USB interface signal modulation module, and uses QPSK modulation technology to generate a high-quality optical signal. The optical signal is transmitted to the multimedia terminal through the optical computing chip. At the multimedia terminal, after the optical signal is demodulated and the photoelectric conversion is completed, the data is sent to the HDTV for playback.

[0118] To verify the performance of the system, we conducted multiple tests on transmission rate, transmission delay, signal stability and bit error rate.

[0119] Table 1 Transmission rate and delay test results

[0120]

[0121]

[0122] Table 2 Performance test of light wave signal compensation module

[0123]

[0124] Table 1 shows the excellent performance of the method of the present invention under different load scenarios. Under low load (20%), the transmission rate of the method of the present invention is 4.8Gbps and the delay is 2.5ms. Compared with 2.3Gbps and 8.0ms of traditional Ethernet, the rate is increased by 108.7% and the delay is reduced by 68.8%. As the load increases, the present invention still maintains the advantages of transmission rate and low delay under medium load (50%) and high load (80%). Its dynamic load balancing mechanism effectively alleviates the bottleneck problem of data transmission and ensures efficient and stable performance.

[0125] Table 2 shows the performance of the optical signal compensation module of the present invention under different noise environments. Under normal conditions, the signal distortion rate is reduced from 5.0% to 0.5%, an improvement of 90%. Under high noise conditions, the signal distortion rate is reduced from 25.0% to 8.5%, an improvement of 66%. These results show that the dynamic compensation technology of the present invention performs particularly well in high interference scenarios, ensuring the reliability and stability of signal transmission quality.

[0126] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A data communication method for an optical computing chip based on a USB interface, characterized in that: The steps include: S1, convert the USB signal sent by the host computer into a TTL signal through the USB to TTL module, and use the FIFO buffer to temporarily store the TTL signal; S2, transmit the temporarily stored TTL signal to the ESP32 microcontroller, use its communication protocol processing module to perform preliminary analysis and verification on the signal, and generate the standardized data packet required by the multi-channel parallel transmission architecture; S3. In the multi-channel dynamic parallel transmission architecture of the ESP32 microcontroller, standardized data packets are distributed to multiple channels according to the dynamic load balancing mechanism to optimize the efficiency and stability of data transmission; S4, delivering the allocated multi-channel data packets to the optical computing chip, processing the data through the optical computing chip and outputting optical signals, which are transmitted to the PD array; S5, using the PD array to perform photoelectric conversion on the optical signal, generate a corresponding electrical signal, and amplify the electrical signal; S6, transmitting the amplified electrical signal to the target device to complete data reception and processing; S7. During the data transmission process, an enhanced data error correction mechanism is used to detect and correct the erroneous data in transmission, combined with the soft decoding and automatic retransmission technology of LDPC codes.

2. According to the method of data communication of an optical computing chip based on a USB interface as described in claim 1, it is characterized in that: The S3 specifically includes: S31, initialize the multi-channel dynamic parallel transmission architecture of the ESP32 microcontroller, and detect the status information of all currently available channels, including the bandwidth and current load of each channel; S32, defining and obtaining a sequence of data packets to be transmitted, including the size, priority and target channel requirements of each data packet; S33. Calculate the comprehensive balance factor of each channel based on the current status information of the channel, evaluate the load of each channel, and sort the available channels from low to high according to the load: Among them, θ and ρ are weight factors, F j is the comprehensive balance factor, L j Indicates the amount of data allocated to the channel, B j Indicates the maximum data processing capability of the channel, D j Indicates the time delay caused by data transmission on this channel; S34, sorting the data packet sequence according to the priority of the data packet, and processing the data packet with a high priority first; S35, starting with the high priority data packets, select the available channels with the lowest loads for allocation, and update the channel status information to reflect the new load; S36, generating a corresponding data transmission queue for each channel, and arranging the data packets in the queue in order of priority; S37, start the multi-channel transmission module, transmit data in the order of each channel queue, monitor the channel status in real time, and dynamically adjust the data packet allocation strategy according to the load changes that occur during the transmission process.

3. The method for optical computing chip data communication based on USB interface according to claim 1, characterized in that: The S4 specifically includes: S41, receiving a multi-channel standardized data packet allocated by the ESP32 microcontroller, and transmitting the data packet to the input end of the optical computing chip through the interface; S42, parsing the received data packet inside the optical computing chip, where the parsed content includes the target format, wavelength, and modulation mode of the signal; S43, converting the digital signal into an optical signal according to the analysis result, generating an optical signal having preset frequency, wavelength and phase characteristics; S44, transmitting the generated optical signal to the input end of the PD array through the output interface of the optical computing chip; S45. Receive an optical signal in the PD array.

4. The method for optical computing chip data communication based on USB interface according to claim 1, characterized in that: The S5 specifically includes: S51, using photodiodes in the PD array to perform photoelectric conversion on the optical signal, absorbing photon energy through semiconductor materials to release electrons, thereby generating a current signal; S52, performing current stabilization processing on the generated current signal, and adjusting the current fluctuation through the internal circuit; S53, inputting the stabilized current signal into a current amplification module, and using the amplifier to increase the signal strength; S54, converting the amplified current signal into a standardized voltage signal, and eliminating the nonlinear distortion generated in the conversion process by stabilizing the voltage signal; S55: Output the final processed electrical signal and transmit it to the target device interface.

5. The method for optical computing chip data communication based on USB interface according to claim 1, characterized in that: The S6 specifically includes: S61, receiving the amplified electrical signal and transmitting it to the interface adapter module; S62, analyzing the electrical signal to extract the level amplitude, frequency range and data format; S63, transmitting the electrical signal to the data verification module and confirming the integrity of the signal; S64, transmitting the verified electrical signal to the communication interface of the target device through the protocol conversion module; S65, the target device receives the electrical signal and performs analysis and processing; S66: The target device completes the application or output of the data.

6. The method for optical computing chip data communication based on USB interface according to claim 1, characterized in that: The S7 specifically includes: S71, receiving a digital signal sequence output from a signal demodulation module, performing error detection on the signal sequence, and identifying and marking erroneous bits; S72, converting the received signal sequence into a log-likelihood ratio representation for soft decoding processing: Among them, LLR(b i ) represents the log-likelihood ratio of the i-th bit, P(b i =1|r) represents the conditional probability that the signal is logic "1", P(b i =0|r) represents the conditional probability that the signal is logic "0", and ln is the logarithmic function; S73, according to the verification rule of the LDPC code, locate the bit error position in the signal sequence and mark the bit that fails the verification; S74, using the error correction capability of the LDPC code to correct the marked error bits, and updating the error bits in the signal sequence: Among them, W i is the current bit b i The correction weight is, λ is the channel state factor, is the history correction weight, i represents the index of the bit in the signal sequence; S75. If the verification still fails, the automatic retransmission mechanism is triggered, and a data retransmission request is sent to the sender to obtain a new data packet; S76, integrating the re-received data packet with the error-corrected signal sequence to generate a complete signal sequence, and outputting the complete signal sequence to the target device.

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